1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_device.h 19 * \brief Host Driver: This file defines the octeon device structure. 20 */ 21 22 #ifndef _OCTEON_DEVICE_H_ 23 #define _OCTEON_DEVICE_H_ 24 25 #include <linux/interrupt.h> 26 #include <net/devlink.h> 27 28 /** PCI VendorId Device Id */ 29 #define OCTEON_CN68XX_PCIID 0x91177d 30 #define OCTEON_CN66XX_PCIID 0x92177d 31 #define OCTEON_CN23XX_PCIID_PF 0x9702177d 32 /** Driver identifies chips by these Ids, created by clubbing together 33 * DeviceId+RevisionId; Where Revision Id is not used to distinguish 34 * between chips, a value of 0 is used for revision id. 35 */ 36 #define OCTEON_CN68XX 0x0091 37 #define OCTEON_CN66XX 0x0092 38 #define OCTEON_CN23XX_PF_VID 0x9702 39 #define OCTEON_CN23XX_VF_VID 0x9712 40 41 /**RevisionId for the chips */ 42 #define OCTEON_CN23XX_REV_1_0 0x00 43 #define OCTEON_CN23XX_REV_1_1 0x01 44 #define OCTEON_CN23XX_REV_2_0 0x80 45 46 /** Endian-swap modes supported by Octeon. */ 47 enum octeon_pci_swap_mode { 48 OCTEON_PCI_PASSTHROUGH = 0, 49 OCTEON_PCI_64BIT_SWAP = 1, 50 OCTEON_PCI_32BIT_BYTE_SWAP = 2, 51 OCTEON_PCI_32BIT_LW_SWAP = 3 52 }; 53 54 enum lio_fw_state { 55 FW_IS_PRELOADED = 0, 56 FW_NEEDS_TO_BE_LOADED = 1, 57 FW_IS_BEING_LOADED = 2, 58 FW_HAS_BEEN_LOADED = 3, 59 }; 60 61 enum { 62 OCTEON_CONFIG_TYPE_DEFAULT = 0, 63 NUM_OCTEON_CONFS, 64 }; 65 66 #define OCTEON_INPUT_INTR (1) 67 #define OCTEON_OUTPUT_INTR (2) 68 #define OCTEON_MBOX_INTR (4) 69 #define OCTEON_ALL_INTR 0xff 70 71 /*--------------- PCI BAR1 index registers -------------*/ 72 73 /* BAR1 Mask */ 74 #define PCI_BAR1_ENABLE_CA 1 75 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP 76 #define PCI_BAR1_ENTRY_VALID 1 77 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \ 78 | (PCI_BAR1_ENDIAN_MODE << 1) \ 79 | PCI_BAR1_ENTRY_VALID) 80 81 /** Octeon Device state. 82 * Each octeon device goes through each of these states 83 * as it is initialized. 84 */ 85 #define OCT_DEV_BEGIN_STATE 0x0 86 #define OCT_DEV_PCI_ENABLE_DONE 0x1 87 #define OCT_DEV_PCI_MAP_DONE 0x2 88 #define OCT_DEV_DISPATCH_INIT_DONE 0x3 89 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x4 90 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5 91 #define OCT_DEV_RESP_LIST_INIT_DONE 0x6 92 #define OCT_DEV_DROQ_INIT_DONE 0x7 93 #define OCT_DEV_MBOX_SETUP_DONE 0x8 94 #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9 95 #define OCT_DEV_INTR_SET_DONE 0xa 96 #define OCT_DEV_IO_QUEUES_DONE 0xb 97 #define OCT_DEV_CONSOLE_INIT_DONE 0xc 98 #define OCT_DEV_HOST_OK 0xd 99 #define OCT_DEV_CORE_OK 0xe 100 #define OCT_DEV_RUNNING 0xf 101 #define OCT_DEV_IN_RESET 0x10 102 #define OCT_DEV_STATE_INVALID 0x11 103 104 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID 105 106 /** Octeon Device interrupts 107 * These interrupt bits are set in int_status filed of 108 * octeon_device structure 109 */ 110 #define OCT_DEV_INTR_DMA0_FORCE 0x01 111 #define OCT_DEV_INTR_DMA1_FORCE 0x02 112 #define OCT_DEV_INTR_PKT_DATA 0x04 113 114 #define LIO_RESET_SECS (3) 115 116 /*---------------------------DISPATCH LIST-------------------------------*/ 117 118 /** The dispatch list entry. 119 * The driver keeps a record of functions registered for each 120 * response header opcode in this structure. Since the opcode is 121 * hashed to index into the driver's list, more than one opcode 122 * can hash to the same entry, in which case the list field points 123 * to a linked list with the other entries. 124 */ 125 struct octeon_dispatch { 126 /** List head for this entry */ 127 struct list_head list; 128 129 /** The opcode for which the dispatch function & arg should be used */ 130 u16 opcode; 131 132 /** The function to be called for a packet received by the driver */ 133 octeon_dispatch_fn_t dispatch_fn; 134 135 /* The application specified argument to be passed to the above 136 * function along with the received packet 137 */ 138 void *arg; 139 }; 140 141 /** The dispatch list structure. */ 142 struct octeon_dispatch_list { 143 /** access to dispatch list must be atomic */ 144 spinlock_t lock; 145 146 /** Count of dispatch functions currently registered */ 147 u32 count; 148 149 /** The list of dispatch functions */ 150 struct octeon_dispatch *dlist; 151 }; 152 153 /*----------------------- THE OCTEON DEVICE ---------------------------*/ 154 155 #define OCT_MEM_REGIONS 3 156 /** PCI address space mapping information. 157 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 158 * Octeon gets mapped to different physical address spaces in 159 * the kernel. 160 */ 161 struct octeon_mmio { 162 /** PCI address to which the BAR is mapped. */ 163 u64 start; 164 165 /** Length of this PCI address space. */ 166 u32 len; 167 168 /** Length that has been mapped to phys. address space. */ 169 u32 mapped_len; 170 171 /** The physical address to which the PCI address space is mapped. */ 172 u8 __iomem *hw_addr; 173 174 /** Flag indicating the mapping was successful. */ 175 u32 done; 176 }; 177 178 #define MAX_OCTEON_MAPS 32 179 180 struct octeon_io_enable { 181 u64 iq; 182 u64 oq; 183 u64 iq64B; 184 }; 185 186 struct octeon_reg_list { 187 u32 __iomem *pci_win_wr_addr_hi; 188 u32 __iomem *pci_win_wr_addr_lo; 189 u64 __iomem *pci_win_wr_addr; 190 191 u32 __iomem *pci_win_rd_addr_hi; 192 u32 __iomem *pci_win_rd_addr_lo; 193 u64 __iomem *pci_win_rd_addr; 194 195 u32 __iomem *pci_win_wr_data_hi; 196 u32 __iomem *pci_win_wr_data_lo; 197 u64 __iomem *pci_win_wr_data; 198 199 u32 __iomem *pci_win_rd_data_hi; 200 u32 __iomem *pci_win_rd_data_lo; 201 u64 __iomem *pci_win_rd_data; 202 }; 203 204 #define OCTEON_CONSOLE_MAX_READ_BYTES 512 205 typedef int (*octeon_console_print_fn)(struct octeon_device *oct, 206 u32 num, char *pre, char *suf); 207 struct octeon_console { 208 u32 active; 209 u32 waiting; 210 u64 addr; 211 u32 buffer_size; 212 u64 input_base_addr; 213 u64 output_base_addr; 214 octeon_console_print_fn print; 215 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES]; 216 }; 217 218 struct octeon_board_info { 219 char name[OCT_BOARD_NAME]; 220 char serial_number[OCT_SERIAL_LEN]; 221 u64 major; 222 u64 minor; 223 }; 224 225 struct octeon_fn_list { 226 void (*setup_iq_regs)(struct octeon_device *, u32); 227 void (*setup_oq_regs)(struct octeon_device *, u32); 228 229 irqreturn_t (*process_interrupt_regs)(void *); 230 u64 (*msix_interrupt_handler)(void *); 231 232 int (*setup_mbox)(struct octeon_device *); 233 int (*free_mbox)(struct octeon_device *); 234 235 int (*soft_reset)(struct octeon_device *); 236 int (*setup_device_regs)(struct octeon_device *); 237 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int); 238 void (*bar1_idx_write)(struct octeon_device *, u32, u32); 239 u32 (*bar1_idx_read)(struct octeon_device *, u32); 240 u32 (*update_iq_read_idx)(struct octeon_instr_queue *); 241 242 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32); 243 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32); 244 245 void (*enable_interrupt)(struct octeon_device *, u8); 246 void (*disable_interrupt)(struct octeon_device *, u8); 247 248 int (*enable_io_queues)(struct octeon_device *); 249 void (*disable_io_queues)(struct octeon_device *); 250 }; 251 252 /* Must be multiple of 8, changing breaks ABI */ 253 #define CVMX_BOOTMEM_NAME_LEN 128 254 255 /* Structure for named memory blocks 256 * Number of descriptors 257 * available can be changed without affecting compatibility, 258 * but name length changes require a bump in the bootmem 259 * descriptor version 260 * Note: This structure must be naturally 64 bit aligned, as a single 261 * memory image will be used by both 32 and 64 bit programs. 262 */ 263 struct cvmx_bootmem_named_block_desc { 264 /** Base address of named block */ 265 u64 base_addr; 266 267 /** Size actually allocated for named block */ 268 u64 size; 269 270 /** name of named block */ 271 char name[CVMX_BOOTMEM_NAME_LEN]; 272 }; 273 274 struct oct_fw_info { 275 u32 max_nic_ports; /** max nic ports for the device */ 276 u32 num_gmx_ports; /** num gmx ports */ 277 u64 app_cap_flags; /** firmware cap flags */ 278 279 /** The core application is running in this mode. 280 * See octeon-drv-opcodes.h for values. 281 */ 282 u32 app_mode; 283 char liquidio_firmware_version[32]; 284 }; 285 286 /* wrappers around work structs */ 287 struct cavium_wk { 288 struct delayed_work work; 289 void *ctxptr; 290 u64 ctxul; 291 }; 292 293 struct cavium_wq { 294 struct workqueue_struct *wq; 295 struct cavium_wk wk; 296 }; 297 298 struct octdev_props { 299 /* Each interface in the Octeon device has a network 300 * device pointer (used for OS specific calls). 301 */ 302 int rx_on; 303 int napi_enabled; 304 int gmxport; 305 struct net_device *netdev; 306 }; 307 308 #define LIO_FLAG_MSIX_ENABLED 0x1 309 #define MSIX_PO_INT 0x1 310 #define MSIX_PI_INT 0x2 311 #define MSIX_MBOX_INT 0x4 312 313 struct octeon_pf_vf_hs_word { 314 #ifdef __LITTLE_ENDIAN_BITFIELD 315 /** PKIND value assigned for the DPI interface */ 316 u64 pkind : 8; 317 318 /** OCTEON core clock multiplier */ 319 u64 core_tics_per_us : 16; 320 321 /** OCTEON coprocessor clock multiplier */ 322 u64 coproc_tics_per_us : 16; 323 324 /** app that currently running on OCTEON */ 325 u64 app_mode : 8; 326 327 /** RESERVED */ 328 u64 reserved : 16; 329 330 #else 331 332 /** RESERVED */ 333 u64 reserved : 16; 334 335 /** app that currently running on OCTEON */ 336 u64 app_mode : 8; 337 338 /** OCTEON coprocessor clock multiplier */ 339 u64 coproc_tics_per_us : 16; 340 341 /** OCTEON core clock multiplier */ 342 u64 core_tics_per_us : 16; 343 344 /** PKIND value assigned for the DPI interface */ 345 u64 pkind : 8; 346 #endif 347 }; 348 349 struct octeon_sriov_info { 350 /* Number of rings assigned to VF */ 351 u32 rings_per_vf; 352 353 /** Max Number of VF devices that can be enabled. This variable can 354 * specified during load time or it will be derived after allocating 355 * PF queues. When max_vfs is derived then each VF will get one queue 356 **/ 357 u32 max_vfs; 358 359 /** Number of VF devices enabled using sysfs. */ 360 u32 num_vfs_alloced; 361 362 /* Actual rings left for PF device */ 363 u32 num_pf_rings; 364 365 /* SRN of PF usable IO queues */ 366 u32 pf_srn; 367 368 /* total pf rings */ 369 u32 trs; 370 371 u32 sriov_enabled; 372 373 /*lookup table that maps DPI ring number to VF pci_dev struct pointer*/ 374 struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS]; 375 376 u64 vf_macaddr[MAX_POSSIBLE_VFS]; 377 378 u16 vf_vlantci[MAX_POSSIBLE_VFS]; 379 380 int vf_linkstate[MAX_POSSIBLE_VFS]; 381 382 u64 vf_drv_loaded_mask; 383 }; 384 385 struct octeon_ioq_vector { 386 struct octeon_device *oct_dev; 387 int iq_index; 388 int droq_index; 389 int vector; 390 struct octeon_mbox *mbox; 391 struct cpumask affinity_mask; 392 u32 ioq_num; 393 }; 394 395 struct lio_vf_rep_list { 396 int num_vfs; 397 struct net_device *ndev[CN23XX_MAX_VFS_PER_PF]; 398 }; 399 400 struct lio_devlink_priv { 401 struct octeon_device *oct; 402 }; 403 404 /** The Octeon device. 405 * Each Octeon device has this structure to represent all its 406 * components. 407 */ 408 struct octeon_device { 409 /** Lock for PCI window configuration accesses */ 410 spinlock_t pci_win_lock; 411 412 /** Lock for memory accesses */ 413 spinlock_t mem_access_lock; 414 415 /** PCI device pointer */ 416 struct pci_dev *pci_dev; 417 418 /** Chip specific information. */ 419 void *chip; 420 421 /** Number of interfaces detected in this octeon device. */ 422 u32 ifcount; 423 424 struct octdev_props props[MAX_OCTEON_LINKS]; 425 426 /** Octeon Chip type. */ 427 u16 chip_id; 428 429 u16 rev_id; 430 431 u16 pf_num; 432 433 u16 vf_num; 434 435 /** This device's id - set by the driver. */ 436 u32 octeon_id; 437 438 /** This device's PCIe port used for traffic. */ 439 u16 pcie_port; 440 441 u16 flags; 442 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1) 443 444 /** The state of this device */ 445 atomic_t status; 446 447 /** memory mapped io range */ 448 struct octeon_mmio mmio[OCT_MEM_REGIONS]; 449 450 struct octeon_reg_list reg_list; 451 452 struct octeon_fn_list fn_list; 453 454 struct octeon_board_info boardinfo; 455 456 u32 num_iqs; 457 458 /* The pool containing pre allocated buffers used for soft commands */ 459 struct octeon_sc_buffer_pool sc_buf_pool; 460 461 /** The input instruction queues */ 462 struct octeon_instr_queue *instr_queue 463 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 464 465 /** The doubly-linked list of instruction response */ 466 struct octeon_response_list response_list[MAX_RESPONSE_LISTS]; 467 468 u32 num_oqs; 469 470 /** The DROQ output queues */ 471 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES]; 472 473 struct octeon_io_enable io_qmask; 474 475 /** List of dispatch functions */ 476 struct octeon_dispatch_list dispatch; 477 478 u32 int_status; 479 480 u64 droq_intr; 481 482 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */ 483 u64 bootmem_desc_addr; 484 485 /** Placeholder memory for named blocks. 486 * Assumes single-threaded access 487 */ 488 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; 489 490 /** Address of consoles descriptor */ 491 u64 console_desc_addr; 492 493 /** Number of consoles available. 0 means they are inaccessible */ 494 u32 num_consoles; 495 496 /* Console caches */ 497 struct octeon_console console[MAX_OCTEON_MAPS]; 498 499 /* Console named block info */ 500 struct { 501 u64 dram_region_base; 502 int bar1_index; 503 } console_nb_info; 504 505 /* Coprocessor clock rate. */ 506 u64 coproc_clock_rate; 507 508 /** The core application is running in this mode. See liquidio_common.h 509 * for values. 510 */ 511 u32 app_mode; 512 513 struct oct_fw_info fw_info; 514 515 /** The name given to this device. */ 516 char device_name[32]; 517 518 /** Application Context */ 519 void *app_ctx; 520 521 struct cavium_wq dma_comp_wq; 522 523 /** Lock for dma response list */ 524 spinlock_t cmd_resp_wqlock; 525 u32 cmd_resp_state; 526 527 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 528 529 struct cavium_wk nic_poll_work; 530 531 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS]; 532 533 void *priv; 534 535 int num_msix_irqs; 536 537 void *msix_entries; 538 539 /* when requesting IRQs, the names are stored here */ 540 void *irq_name_storage; 541 542 struct octeon_sriov_info sriov_info; 543 544 struct octeon_pf_vf_hs_word pfvf_hsword; 545 546 int msix_on; 547 548 /** Mail Box details of each octeon queue. */ 549 struct octeon_mbox *mbox[MAX_POSSIBLE_VFS]; 550 551 /** IOq information of it's corresponding MSI-X interrupt. */ 552 struct octeon_ioq_vector *ioq_vector; 553 554 int rx_pause; 555 int tx_pause; 556 557 struct oct_link_stats link_stats; /*stastics from firmware*/ 558 559 /* private flags to control driver-specific features through ethtool */ 560 u32 priv_flags; 561 562 void *watchdog_task; 563 564 u32 rx_coalesce_usecs; 565 u32 rx_max_coalesced_frames; 566 u32 tx_max_coalesced_frames; 567 568 bool cores_crashed; 569 570 struct { 571 int bus; 572 int dev; 573 int func; 574 } loc; 575 576 atomic_t *adapter_refcount; /* reference count of adapter */ 577 578 atomic_t *adapter_fw_state; /* per-adapter, lio_fw_state */ 579 580 bool ptp_enable; 581 582 struct lio_vf_rep_list vf_rep_list; 583 struct devlink *devlink; 584 enum devlink_eswitch_mode eswitch_mode; 585 }; 586 587 #define OCT_DRV_ONLINE 1 588 #define OCT_DRV_OFFLINE 2 589 #define OCTEON_CN6XXX(oct) ({ \ 590 typeof(oct) _oct = (oct); \ 591 ((_oct->chip_id == OCTEON_CN66XX) || \ 592 (_oct->chip_id == OCTEON_CN68XX)); }) 593 #define OCTEON_CN23XX_PF(oct) ((oct)->chip_id == OCTEON_CN23XX_PF_VID) 594 #define OCTEON_CN23XX_VF(oct) ((oct)->chip_id == OCTEON_CN23XX_VF_VID) 595 #define CHIP_CONF(oct, TYPE) \ 596 (((struct octeon_ ## TYPE *)((oct)->chip))->conf) 597 598 #define MAX_IO_PENDING_PKT_COUNT 100 599 600 /*------------------ Function Prototypes ----------------------*/ 601 602 /** Initialize device list memory */ 603 void octeon_init_device_list(int conf_type); 604 605 /** Free memory for Input and Output queue structures for a octeon device */ 606 void octeon_free_device_mem(struct octeon_device *oct); 607 608 /* Look up a free entry in the octeon_device table and allocate resources 609 * for the octeon_device structure for an octeon device. Called at init 610 * time. 611 */ 612 struct octeon_device *octeon_allocate_device(u32 pci_id, 613 u32 priv_size); 614 615 /** Register a device's bus location at initialization time. 616 * @param octeon_dev - pointer to the octeon device structure. 617 * @param bus - PCIe bus # 618 * @param dev - PCIe device # 619 * @param func - PCIe function # 620 * @param is_pf - TRUE for PF, FALSE for VF 621 * @return reference count of device's adapter 622 */ 623 int octeon_register_device(struct octeon_device *oct, 624 int bus, int dev, int func, int is_pf); 625 626 /** Deregister a device at de-initialization time. 627 * @param octeon_dev - pointer to the octeon device structure. 628 * @return reference count of device's adapter 629 */ 630 int octeon_deregister_device(struct octeon_device *oct); 631 632 /** Initialize the driver's dispatch list which is a mix of a hash table 633 * and a linked list. This is done at driver load time. 634 * @param octeon_dev - pointer to the octeon device structure. 635 * @return 0 on success, else -ve error value 636 */ 637 int octeon_init_dispatch_list(struct octeon_device *octeon_dev); 638 639 /** Delete the driver's dispatch list and all registered entries. 640 * This is done at driver unload time. 641 * @param octeon_dev - pointer to the octeon device structure. 642 */ 643 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); 644 645 /** Initialize the core device fields with the info returned by the FW. 646 * @param recv_info - Receive info structure 647 * @param buf - Receive buffer 648 */ 649 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); 650 651 /** Gets the dispatch function registered to receive packets with a 652 * given opcode/subcode. 653 * @param octeon_dev - the octeon device pointer. 654 * @param opcode - the opcode for which the dispatch function 655 * is to checked. 656 * @param subcode - the subcode for which the dispatch function 657 * is to checked. 658 * 659 * @return Success: octeon_dispatch_fn_t (dispatch function pointer) 660 * @return Failure: NULL 661 * 662 * Looks up the dispatch list to get the dispatch function for a 663 * given opcode. 664 */ 665 octeon_dispatch_fn_t 666 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 667 u16 subcode); 668 669 /** Get the octeon device pointer. 670 * @param octeon_id - The id for which the octeon device pointer is required. 671 * @return Success: Octeon device pointer. 672 * @return Failure: NULL. 673 */ 674 struct octeon_device *lio_get_device(u32 octeon_id); 675 676 /** Get the octeon id assigned to the octeon device passed as argument. 677 * This function is exported to other modules. 678 * @param dev - octeon device pointer passed as a void *. 679 * @return octeon device id 680 */ 681 int lio_get_device_id(void *dev); 682 683 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct) 684 { 685 u16 rev = (oct->rev_id & 0xC) >> 2; 686 687 return (rev == 0) ? 1 : rev; 688 } 689 690 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct) 691 { 692 return oct->rev_id & 0x3; 693 } 694 695 /** Read windowed register. 696 * @param oct - pointer to the Octeon device. 697 * @param addr - Address of the register to read. 698 * 699 * This routine is called to read from the indirectly accessed 700 * Octeon registers that are visible through a PCI BAR0 mapped window 701 * register. 702 * @return - 64 bit value read from the register. 703 */ 704 705 u64 lio_pci_readq(struct octeon_device *oct, u64 addr); 706 707 /** Write windowed register. 708 * @param oct - pointer to the Octeon device. 709 * @param val - Value to write 710 * @param addr - Address of the register to write 711 * 712 * This routine is called to write to the indirectly accessed 713 * Octeon registers that are visible through a PCI BAR0 mapped window 714 * register. 715 * @return Nothing. 716 */ 717 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); 718 719 /* Routines for reading and writing CSRs */ 720 #define octeon_write_csr(oct_dev, reg_off, value) \ 721 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) 722 723 #define octeon_write_csr64(oct_dev, reg_off, val64) \ 724 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) 725 726 #define octeon_read_csr(oct_dev, reg_off) \ 727 readl((oct_dev)->mmio[0].hw_addr + (reg_off)) 728 729 #define octeon_read_csr64(oct_dev, reg_off) \ 730 readq((oct_dev)->mmio[0].hw_addr + (reg_off)) 731 732 /** 733 * Checks if memory access is okay 734 * 735 * @param oct which octeon to send to 736 * @return Zero on success, negative on failure. 737 */ 738 int octeon_mem_access_ok(struct octeon_device *oct); 739 740 /** 741 * Waits for DDR initialization. 742 * 743 * @param oct which octeon to send to 744 * @param timeout_in_ms pointer to how long to wait until DDR is initialized 745 * in ms. 746 * If contents are 0, it waits until contents are non-zero 747 * before starting to check. 748 * @return Zero on success, negative on failure. 749 */ 750 int octeon_wait_for_ddr_init(struct octeon_device *oct, 751 u32 *timeout_in_ms); 752 753 /** 754 * Wait for u-boot to boot and be waiting for a command. 755 * 756 * @param wait_time_hundredths 757 * Maximum time to wait 758 * 759 * @return Zero on success, negative on failure. 760 */ 761 int octeon_wait_for_bootloader(struct octeon_device *oct, 762 u32 wait_time_hundredths); 763 764 /** 765 * Initialize console access 766 * 767 * @param oct which octeon initialize 768 * @return Zero on success, negative on failure. 769 */ 770 int octeon_init_consoles(struct octeon_device *oct); 771 772 /** 773 * Adds access to a console to the device. 774 * 775 * @param oct: which octeon to add to 776 * @param console_num: which console 777 * @param dbg_enb: ptr to debug enablement string, one of: 778 * * NULL for no debug output (i.e. disabled) 779 * * empty string enables debug output (via default method) 780 * * specific string to enable debug console output 781 * 782 * @return Zero on success, negative on failure. 783 */ 784 int octeon_add_console(struct octeon_device *oct, u32 console_num, 785 char *dbg_enb); 786 787 /** write or read from a console */ 788 int octeon_console_write(struct octeon_device *oct, u32 console_num, 789 char *buffer, u32 write_request_size, u32 flags); 790 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); 791 792 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); 793 794 /** Removes all attached consoles. */ 795 void octeon_remove_consoles(struct octeon_device *oct); 796 797 /** 798 * Send a string to u-boot on console 0 as a command. 799 * 800 * @param oct which octeon to send to 801 * @param cmd_str String to send 802 * @param wait_hundredths Time to wait for u-boot to accept the command. 803 * 804 * @return Zero on success, negative on failure. 805 */ 806 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 807 u32 wait_hundredths); 808 809 /** Parses, validates, and downloads firmware, then boots associated cores. 810 * @param oct which octeon to download firmware to 811 * @param data - The complete firmware file image 812 * @param size - The size of the data 813 * 814 * @return 0 if success. 815 * -EINVAL if file is incompatible or badly formatted. 816 * -ENODEV if no handler was found for the application type or an 817 * invalid octeon id was passed. 818 */ 819 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 820 size_t size); 821 822 char *lio_get_state_string(atomic_t *state_ptr); 823 824 /** Sets up instruction queues for the device 825 * @param oct which octeon to setup 826 * 827 * @return 0 if success. 1 if fails 828 */ 829 int octeon_setup_instr_queues(struct octeon_device *oct); 830 831 /** Sets up output queues for the device 832 * @param oct which octeon to setup 833 * 834 * @return 0 if success. 1 if fails 835 */ 836 int octeon_setup_output_queues(struct octeon_device *oct); 837 838 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); 839 840 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); 841 842 /** Turns off the input and output queues for the device 843 * @param oct which octeon to disable 844 */ 845 int octeon_set_io_queues_off(struct octeon_device *oct); 846 847 /** Turns on or off the given output queue for the device 848 * @param oct which octeon to change 849 * @param q_no which queue 850 * @param enable 1 to enable, 0 to disable 851 */ 852 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); 853 854 /** Retrieve the config for the device 855 * @param oct which octeon 856 * @param card_type type of card 857 * 858 * @returns pointer to configuration 859 */ 860 void *oct_get_config_info(struct octeon_device *oct, u16 card_type); 861 862 /** Gets the octeon device configuration 863 * @return - pointer to the octeon configuration struture 864 */ 865 struct octeon_config *octeon_get_conf(struct octeon_device *oct); 866 867 void octeon_free_ioq_vector(struct octeon_device *oct); 868 int octeon_allocate_ioq_vector(struct octeon_device *oct); 869 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq); 870 871 /* LiquidIO driver pivate flags */ 872 enum { 873 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */ 874 }; 875 876 #define OCT_PRIV_FLAG_DEFAULT 0x0 877 878 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag) 879 { 880 return !!(octdev->priv_flags & (0x1 << flag)); 881 } 882 883 static inline void lio_set_priv_flag(struct octeon_device *octdev, 884 u32 flag, u32 val) 885 { 886 if (val) 887 octdev->priv_flags |= (0x1 << flag); 888 else 889 octdev->priv_flags &= ~(0x1 << flag); 890 } 891 #endif 892