1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_device.h 19 * \brief Host Driver: This file defines the octeon device structure. 20 */ 21 22 #ifndef _OCTEON_DEVICE_H_ 23 #define _OCTEON_DEVICE_H_ 24 25 #include <linux/interrupt.h> 26 #include <net/devlink.h> 27 28 /** PCI VendorId Device Id */ 29 #define OCTEON_CN68XX_PCIID 0x91177d 30 #define OCTEON_CN66XX_PCIID 0x92177d 31 #define OCTEON_CN23XX_PCIID_PF 0x9702177d 32 /** Driver identifies chips by these Ids, created by clubbing together 33 * DeviceId+RevisionId; Where Revision Id is not used to distinguish 34 * between chips, a value of 0 is used for revision id. 35 */ 36 #define OCTEON_CN68XX 0x0091 37 #define OCTEON_CN66XX 0x0092 38 #define OCTEON_CN23XX_PF_VID 0x9702 39 #define OCTEON_CN23XX_VF_VID 0x9712 40 41 /**RevisionId for the chips */ 42 #define OCTEON_CN23XX_REV_1_0 0x00 43 #define OCTEON_CN23XX_REV_1_1 0x01 44 #define OCTEON_CN23XX_REV_2_0 0x80 45 46 /** Endian-swap modes supported by Octeon. */ 47 enum octeon_pci_swap_mode { 48 OCTEON_PCI_PASSTHROUGH = 0, 49 OCTEON_PCI_64BIT_SWAP = 1, 50 OCTEON_PCI_32BIT_BYTE_SWAP = 2, 51 OCTEON_PCI_32BIT_LW_SWAP = 3 52 }; 53 54 enum lio_fw_state { 55 FW_IS_PRELOADED = 0, 56 FW_NEEDS_TO_BE_LOADED = 1, 57 FW_IS_BEING_LOADED = 2, 58 FW_HAS_BEEN_LOADED = 3, 59 }; 60 61 enum { 62 OCTEON_CONFIG_TYPE_DEFAULT = 0, 63 NUM_OCTEON_CONFS, 64 }; 65 66 #define OCTEON_INPUT_INTR (1) 67 #define OCTEON_OUTPUT_INTR (2) 68 #define OCTEON_MBOX_INTR (4) 69 #define OCTEON_ALL_INTR 0xff 70 71 /*--------------- PCI BAR1 index registers -------------*/ 72 73 /* BAR1 Mask */ 74 #define PCI_BAR1_ENABLE_CA 1 75 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP 76 #define PCI_BAR1_ENTRY_VALID 1 77 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \ 78 | (PCI_BAR1_ENDIAN_MODE << 1) \ 79 | PCI_BAR1_ENTRY_VALID) 80 81 /** Octeon Device state. 82 * Each octeon device goes through each of these states 83 * as it is initialized. 84 */ 85 #define OCT_DEV_BEGIN_STATE 0x0 86 #define OCT_DEV_PCI_ENABLE_DONE 0x1 87 #define OCT_DEV_PCI_MAP_DONE 0x2 88 #define OCT_DEV_DISPATCH_INIT_DONE 0x3 89 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x4 90 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5 91 #define OCT_DEV_RESP_LIST_INIT_DONE 0x6 92 #define OCT_DEV_DROQ_INIT_DONE 0x7 93 #define OCT_DEV_MBOX_SETUP_DONE 0x8 94 #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9 95 #define OCT_DEV_INTR_SET_DONE 0xa 96 #define OCT_DEV_IO_QUEUES_DONE 0xb 97 #define OCT_DEV_CONSOLE_INIT_DONE 0xc 98 #define OCT_DEV_HOST_OK 0xd 99 #define OCT_DEV_CORE_OK 0xe 100 #define OCT_DEV_RUNNING 0xf 101 #define OCT_DEV_IN_RESET 0x10 102 #define OCT_DEV_STATE_INVALID 0x11 103 104 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID 105 106 /** Octeon Device interrupts 107 * These interrupt bits are set in int_status filed of 108 * octeon_device structure 109 */ 110 #define OCT_DEV_INTR_DMA0_FORCE 0x01 111 #define OCT_DEV_INTR_DMA1_FORCE 0x02 112 #define OCT_DEV_INTR_PKT_DATA 0x04 113 114 #define LIO_RESET_SECS (3) 115 116 /*---------------------------DISPATCH LIST-------------------------------*/ 117 118 /** The dispatch list entry. 119 * The driver keeps a record of functions registered for each 120 * response header opcode in this structure. Since the opcode is 121 * hashed to index into the driver's list, more than one opcode 122 * can hash to the same entry, in which case the list field points 123 * to a linked list with the other entries. 124 */ 125 struct octeon_dispatch { 126 /** List head for this entry */ 127 struct list_head list; 128 129 /** The opcode for which the dispatch function & arg should be used */ 130 u16 opcode; 131 132 /** The function to be called for a packet received by the driver */ 133 octeon_dispatch_fn_t dispatch_fn; 134 135 /* The application specified argument to be passed to the above 136 * function along with the received packet 137 */ 138 void *arg; 139 }; 140 141 /** The dispatch list structure. */ 142 struct octeon_dispatch_list { 143 /** access to dispatch list must be atomic */ 144 spinlock_t lock; 145 146 /** Count of dispatch functions currently registered */ 147 u32 count; 148 149 /** The list of dispatch functions */ 150 struct octeon_dispatch *dlist; 151 }; 152 153 /*----------------------- THE OCTEON DEVICE ---------------------------*/ 154 155 #define OCT_MEM_REGIONS 3 156 /** PCI address space mapping information. 157 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 158 * Octeon gets mapped to different physical address spaces in 159 * the kernel. 160 */ 161 struct octeon_mmio { 162 /** PCI address to which the BAR is mapped. */ 163 u64 start; 164 165 /** Length of this PCI address space. */ 166 u32 len; 167 168 /** Length that has been mapped to phys. address space. */ 169 u32 mapped_len; 170 171 /** The physical address to which the PCI address space is mapped. */ 172 u8 __iomem *hw_addr; 173 174 /** Flag indicating the mapping was successful. */ 175 u32 done; 176 }; 177 178 #define MAX_OCTEON_MAPS 32 179 180 struct octeon_io_enable { 181 u64 iq; 182 u64 oq; 183 u64 iq64B; 184 }; 185 186 struct octeon_reg_list { 187 u32 __iomem *pci_win_wr_addr_hi; 188 u32 __iomem *pci_win_wr_addr_lo; 189 u64 __iomem *pci_win_wr_addr; 190 191 u32 __iomem *pci_win_rd_addr_hi; 192 u32 __iomem *pci_win_rd_addr_lo; 193 u64 __iomem *pci_win_rd_addr; 194 195 u32 __iomem *pci_win_wr_data_hi; 196 u32 __iomem *pci_win_wr_data_lo; 197 u64 __iomem *pci_win_wr_data; 198 199 u32 __iomem *pci_win_rd_data_hi; 200 u32 __iomem *pci_win_rd_data_lo; 201 u64 __iomem *pci_win_rd_data; 202 }; 203 204 #define OCTEON_CONSOLE_MAX_READ_BYTES 512 205 typedef int (*octeon_console_print_fn)(struct octeon_device *oct, 206 u32 num, char *pre, char *suf); 207 struct octeon_console { 208 u32 active; 209 u32 waiting; 210 u64 addr; 211 u32 buffer_size; 212 u64 input_base_addr; 213 u64 output_base_addr; 214 octeon_console_print_fn print; 215 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES]; 216 }; 217 218 struct octeon_board_info { 219 char name[OCT_BOARD_NAME]; 220 char serial_number[OCT_SERIAL_LEN]; 221 u64 major; 222 u64 minor; 223 }; 224 225 struct octeon_fn_list { 226 void (*setup_iq_regs)(struct octeon_device *, u32); 227 void (*setup_oq_regs)(struct octeon_device *, u32); 228 229 irqreturn_t (*process_interrupt_regs)(void *); 230 u64 (*msix_interrupt_handler)(void *); 231 232 int (*setup_mbox)(struct octeon_device *); 233 int (*free_mbox)(struct octeon_device *); 234 235 int (*soft_reset)(struct octeon_device *); 236 int (*setup_device_regs)(struct octeon_device *); 237 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int); 238 void (*bar1_idx_write)(struct octeon_device *, u32, u32); 239 u32 (*bar1_idx_read)(struct octeon_device *, u32); 240 u32 (*update_iq_read_idx)(struct octeon_instr_queue *); 241 242 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32); 243 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32); 244 245 void (*enable_interrupt)(struct octeon_device *, u8); 246 void (*disable_interrupt)(struct octeon_device *, u8); 247 248 int (*enable_io_queues)(struct octeon_device *); 249 void (*disable_io_queues)(struct octeon_device *); 250 }; 251 252 /* Must be multiple of 8, changing breaks ABI */ 253 #define CVMX_BOOTMEM_NAME_LEN 128 254 255 /* Structure for named memory blocks 256 * Number of descriptors 257 * available can be changed without affecting compatibility, 258 * but name length changes require a bump in the bootmem 259 * descriptor version 260 * Note: This structure must be naturally 64 bit aligned, as a single 261 * memory image will be used by both 32 and 64 bit programs. 262 */ 263 struct cvmx_bootmem_named_block_desc { 264 /** Base address of named block */ 265 u64 base_addr; 266 267 /** Size actually allocated for named block */ 268 u64 size; 269 270 /** name of named block */ 271 char name[CVMX_BOOTMEM_NAME_LEN]; 272 }; 273 274 struct oct_fw_info { 275 u32 max_nic_ports; /** max nic ports for the device */ 276 u32 num_gmx_ports; /** num gmx ports */ 277 u64 app_cap_flags; /** firmware cap flags */ 278 279 /** The core application is running in this mode. 280 * See octeon-drv-opcodes.h for values. 281 */ 282 u32 app_mode; 283 char liquidio_firmware_version[32]; 284 }; 285 286 /* wrappers around work structs */ 287 struct cavium_wk { 288 struct delayed_work work; 289 void *ctxptr; 290 u64 ctxul; 291 }; 292 293 struct cavium_wq { 294 struct workqueue_struct *wq; 295 struct cavium_wk wk; 296 }; 297 298 struct octdev_props { 299 /* Each interface in the Octeon device has a network 300 * device pointer (used for OS specific calls). 301 */ 302 int rx_on; 303 int napi_enabled; 304 int gmxport; 305 struct net_device *netdev; 306 }; 307 308 #define LIO_FLAG_MSIX_ENABLED 0x1 309 #define MSIX_PO_INT 0x1 310 #define MSIX_PI_INT 0x2 311 #define MSIX_MBOX_INT 0x4 312 313 struct octeon_pf_vf_hs_word { 314 #ifdef __LITTLE_ENDIAN_BITFIELD 315 /** PKIND value assigned for the DPI interface */ 316 u64 pkind : 8; 317 318 /** OCTEON core clock multiplier */ 319 u64 core_tics_per_us : 16; 320 321 /** OCTEON coprocessor clock multiplier */ 322 u64 coproc_tics_per_us : 16; 323 324 /** app that currently running on OCTEON */ 325 u64 app_mode : 8; 326 327 /** RESERVED */ 328 u64 reserved : 16; 329 330 #else 331 332 /** RESERVED */ 333 u64 reserved : 16; 334 335 /** app that currently running on OCTEON */ 336 u64 app_mode : 8; 337 338 /** OCTEON coprocessor clock multiplier */ 339 u64 coproc_tics_per_us : 16; 340 341 /** OCTEON core clock multiplier */ 342 u64 core_tics_per_us : 16; 343 344 /** PKIND value assigned for the DPI interface */ 345 u64 pkind : 8; 346 #endif 347 }; 348 349 struct octeon_sriov_info { 350 /* Number of rings assigned to VF */ 351 u32 rings_per_vf; 352 353 /** Max Number of VF devices that can be enabled. This variable can 354 * specified during load time or it will be derived after allocating 355 * PF queues. When max_vfs is derived then each VF will get one queue 356 **/ 357 u32 max_vfs; 358 359 /** Number of VF devices enabled using sysfs. */ 360 u32 num_vfs_alloced; 361 362 /* Actual rings left for PF device */ 363 u32 num_pf_rings; 364 365 /* SRN of PF usable IO queues */ 366 u32 pf_srn; 367 368 /* total pf rings */ 369 u32 trs; 370 371 u32 sriov_enabled; 372 373 struct lio_trusted_vf trusted_vf; 374 375 /*lookup table that maps DPI ring number to VF pci_dev struct pointer*/ 376 struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS]; 377 378 u64 vf_macaddr[MAX_POSSIBLE_VFS]; 379 380 u16 vf_vlantci[MAX_POSSIBLE_VFS]; 381 382 int vf_linkstate[MAX_POSSIBLE_VFS]; 383 384 u64 vf_drv_loaded_mask; 385 }; 386 387 struct octeon_ioq_vector { 388 struct octeon_device *oct_dev; 389 int iq_index; 390 int droq_index; 391 int vector; 392 struct octeon_mbox *mbox; 393 struct cpumask affinity_mask; 394 u32 ioq_num; 395 }; 396 397 struct lio_vf_rep_list { 398 int num_vfs; 399 struct net_device *ndev[CN23XX_MAX_VFS_PER_PF]; 400 }; 401 402 struct lio_devlink_priv { 403 struct octeon_device *oct; 404 }; 405 406 /** The Octeon device. 407 * Each Octeon device has this structure to represent all its 408 * components. 409 */ 410 struct octeon_device { 411 /** Lock for PCI window configuration accesses */ 412 spinlock_t pci_win_lock; 413 414 /** Lock for memory accesses */ 415 spinlock_t mem_access_lock; 416 417 /** PCI device pointer */ 418 struct pci_dev *pci_dev; 419 420 /** Chip specific information. */ 421 void *chip; 422 423 /** Number of interfaces detected in this octeon device. */ 424 u32 ifcount; 425 426 struct octdev_props props[MAX_OCTEON_LINKS]; 427 428 /** Octeon Chip type. */ 429 u16 chip_id; 430 431 u16 rev_id; 432 433 u16 pf_num; 434 435 u16 vf_num; 436 437 /** This device's id - set by the driver. */ 438 u32 octeon_id; 439 440 /** This device's PCIe port used for traffic. */ 441 u16 pcie_port; 442 443 u16 flags; 444 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1) 445 446 /** The state of this device */ 447 atomic_t status; 448 449 /** memory mapped io range */ 450 struct octeon_mmio mmio[OCT_MEM_REGIONS]; 451 452 struct octeon_reg_list reg_list; 453 454 struct octeon_fn_list fn_list; 455 456 struct octeon_board_info boardinfo; 457 458 u32 num_iqs; 459 460 /* The pool containing pre allocated buffers used for soft commands */ 461 struct octeon_sc_buffer_pool sc_buf_pool; 462 463 /** The input instruction queues */ 464 struct octeon_instr_queue *instr_queue 465 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 466 467 /** The doubly-linked list of instruction response */ 468 struct octeon_response_list response_list[MAX_RESPONSE_LISTS]; 469 470 u32 num_oqs; 471 472 /** The DROQ output queues */ 473 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES]; 474 475 struct octeon_io_enable io_qmask; 476 477 /** List of dispatch functions */ 478 struct octeon_dispatch_list dispatch; 479 480 u32 int_status; 481 482 u64 droq_intr; 483 484 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */ 485 u64 bootmem_desc_addr; 486 487 /** Placeholder memory for named blocks. 488 * Assumes single-threaded access 489 */ 490 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; 491 492 /** Address of consoles descriptor */ 493 u64 console_desc_addr; 494 495 /** Number of consoles available. 0 means they are inaccessible */ 496 u32 num_consoles; 497 498 /* Console caches */ 499 struct octeon_console console[MAX_OCTEON_MAPS]; 500 501 /* Console named block info */ 502 struct { 503 u64 dram_region_base; 504 int bar1_index; 505 } console_nb_info; 506 507 /* Coprocessor clock rate. */ 508 u64 coproc_clock_rate; 509 510 /** The core application is running in this mode. See liquidio_common.h 511 * for values. 512 */ 513 u32 app_mode; 514 515 struct oct_fw_info fw_info; 516 517 /** The name given to this device. */ 518 char device_name[32]; 519 520 /** Application Context */ 521 void *app_ctx; 522 523 struct cavium_wq dma_comp_wq; 524 525 /** Lock for dma response list */ 526 spinlock_t cmd_resp_wqlock; 527 u32 cmd_resp_state; 528 529 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 530 531 struct cavium_wk nic_poll_work; 532 533 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS]; 534 535 void *priv; 536 537 int num_msix_irqs; 538 539 void *msix_entries; 540 541 /* when requesting IRQs, the names are stored here */ 542 void *irq_name_storage; 543 544 struct octeon_sriov_info sriov_info; 545 546 struct octeon_pf_vf_hs_word pfvf_hsword; 547 548 int msix_on; 549 550 /** Mail Box details of each octeon queue. */ 551 struct octeon_mbox *mbox[MAX_POSSIBLE_VFS]; 552 553 /** IOq information of it's corresponding MSI-X interrupt. */ 554 struct octeon_ioq_vector *ioq_vector; 555 556 int rx_pause; 557 int tx_pause; 558 559 struct oct_link_stats link_stats; /*stastics from firmware*/ 560 561 /* private flags to control driver-specific features through ethtool */ 562 u32 priv_flags; 563 564 void *watchdog_task; 565 566 u32 rx_coalesce_usecs; 567 u32 rx_max_coalesced_frames; 568 u32 tx_max_coalesced_frames; 569 570 bool cores_crashed; 571 572 struct { 573 int bus; 574 int dev; 575 int func; 576 } loc; 577 578 atomic_t *adapter_refcount; /* reference count of adapter */ 579 580 atomic_t *adapter_fw_state; /* per-adapter, lio_fw_state */ 581 582 bool ptp_enable; 583 584 struct lio_vf_rep_list vf_rep_list; 585 struct devlink *devlink; 586 enum devlink_eswitch_mode eswitch_mode; 587 }; 588 589 #define OCT_DRV_ONLINE 1 590 #define OCT_DRV_OFFLINE 2 591 #define OCTEON_CN6XXX(oct) ({ \ 592 typeof(oct) _oct = (oct); \ 593 ((_oct->chip_id == OCTEON_CN66XX) || \ 594 (_oct->chip_id == OCTEON_CN68XX)); }) 595 #define OCTEON_CN23XX_PF(oct) ((oct)->chip_id == OCTEON_CN23XX_PF_VID) 596 #define OCTEON_CN23XX_VF(oct) ((oct)->chip_id == OCTEON_CN23XX_VF_VID) 597 #define CHIP_CONF(oct, TYPE) \ 598 (((struct octeon_ ## TYPE *)((oct)->chip))->conf) 599 600 #define MAX_IO_PENDING_PKT_COUNT 100 601 602 /*------------------ Function Prototypes ----------------------*/ 603 604 /** Initialize device list memory */ 605 void octeon_init_device_list(int conf_type); 606 607 /** Free memory for Input and Output queue structures for a octeon device */ 608 void octeon_free_device_mem(struct octeon_device *oct); 609 610 /* Look up a free entry in the octeon_device table and allocate resources 611 * for the octeon_device structure for an octeon device. Called at init 612 * time. 613 */ 614 struct octeon_device *octeon_allocate_device(u32 pci_id, 615 u32 priv_size); 616 617 /** Register a device's bus location at initialization time. 618 * @param octeon_dev - pointer to the octeon device structure. 619 * @param bus - PCIe bus # 620 * @param dev - PCIe device # 621 * @param func - PCIe function # 622 * @param is_pf - TRUE for PF, FALSE for VF 623 * @return reference count of device's adapter 624 */ 625 int octeon_register_device(struct octeon_device *oct, 626 int bus, int dev, int func, int is_pf); 627 628 /** Deregister a device at de-initialization time. 629 * @param octeon_dev - pointer to the octeon device structure. 630 * @return reference count of device's adapter 631 */ 632 int octeon_deregister_device(struct octeon_device *oct); 633 634 /** Initialize the driver's dispatch list which is a mix of a hash table 635 * and a linked list. This is done at driver load time. 636 * @param octeon_dev - pointer to the octeon device structure. 637 * @return 0 on success, else -ve error value 638 */ 639 int octeon_init_dispatch_list(struct octeon_device *octeon_dev); 640 641 /** Delete the driver's dispatch list and all registered entries. 642 * This is done at driver unload time. 643 * @param octeon_dev - pointer to the octeon device structure. 644 */ 645 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); 646 647 /** Initialize the core device fields with the info returned by the FW. 648 * @param recv_info - Receive info structure 649 * @param buf - Receive buffer 650 */ 651 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); 652 653 /** Gets the dispatch function registered to receive packets with a 654 * given opcode/subcode. 655 * @param octeon_dev - the octeon device pointer. 656 * @param opcode - the opcode for which the dispatch function 657 * is to checked. 658 * @param subcode - the subcode for which the dispatch function 659 * is to checked. 660 * 661 * @return Success: octeon_dispatch_fn_t (dispatch function pointer) 662 * @return Failure: NULL 663 * 664 * Looks up the dispatch list to get the dispatch function for a 665 * given opcode. 666 */ 667 octeon_dispatch_fn_t 668 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 669 u16 subcode); 670 671 /** Get the octeon device pointer. 672 * @param octeon_id - The id for which the octeon device pointer is required. 673 * @return Success: Octeon device pointer. 674 * @return Failure: NULL. 675 */ 676 struct octeon_device *lio_get_device(u32 octeon_id); 677 678 /** Get the octeon id assigned to the octeon device passed as argument. 679 * This function is exported to other modules. 680 * @param dev - octeon device pointer passed as a void *. 681 * @return octeon device id 682 */ 683 int lio_get_device_id(void *dev); 684 685 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct) 686 { 687 u16 rev = (oct->rev_id & 0xC) >> 2; 688 689 return (rev == 0) ? 1 : rev; 690 } 691 692 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct) 693 { 694 return oct->rev_id & 0x3; 695 } 696 697 /** Read windowed register. 698 * @param oct - pointer to the Octeon device. 699 * @param addr - Address of the register to read. 700 * 701 * This routine is called to read from the indirectly accessed 702 * Octeon registers that are visible through a PCI BAR0 mapped window 703 * register. 704 * @return - 64 bit value read from the register. 705 */ 706 707 u64 lio_pci_readq(struct octeon_device *oct, u64 addr); 708 709 /** Write windowed register. 710 * @param oct - pointer to the Octeon device. 711 * @param val - Value to write 712 * @param addr - Address of the register to write 713 * 714 * This routine is called to write to the indirectly accessed 715 * Octeon registers that are visible through a PCI BAR0 mapped window 716 * register. 717 * @return Nothing. 718 */ 719 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); 720 721 /* Routines for reading and writing CSRs */ 722 #define octeon_write_csr(oct_dev, reg_off, value) \ 723 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) 724 725 #define octeon_write_csr64(oct_dev, reg_off, val64) \ 726 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) 727 728 #define octeon_read_csr(oct_dev, reg_off) \ 729 readl((oct_dev)->mmio[0].hw_addr + (reg_off)) 730 731 #define octeon_read_csr64(oct_dev, reg_off) \ 732 readq((oct_dev)->mmio[0].hw_addr + (reg_off)) 733 734 /** 735 * Checks if memory access is okay 736 * 737 * @param oct which octeon to send to 738 * @return Zero on success, negative on failure. 739 */ 740 int octeon_mem_access_ok(struct octeon_device *oct); 741 742 /** 743 * Waits for DDR initialization. 744 * 745 * @param oct which octeon to send to 746 * @param timeout_in_ms pointer to how long to wait until DDR is initialized 747 * in ms. 748 * If contents are 0, it waits until contents are non-zero 749 * before starting to check. 750 * @return Zero on success, negative on failure. 751 */ 752 int octeon_wait_for_ddr_init(struct octeon_device *oct, 753 u32 *timeout_in_ms); 754 755 /** 756 * Wait for u-boot to boot and be waiting for a command. 757 * 758 * @param wait_time_hundredths 759 * Maximum time to wait 760 * 761 * @return Zero on success, negative on failure. 762 */ 763 int octeon_wait_for_bootloader(struct octeon_device *oct, 764 u32 wait_time_hundredths); 765 766 /** 767 * Initialize console access 768 * 769 * @param oct which octeon initialize 770 * @return Zero on success, negative on failure. 771 */ 772 int octeon_init_consoles(struct octeon_device *oct); 773 774 /** 775 * Adds access to a console to the device. 776 * 777 * @param oct: which octeon to add to 778 * @param console_num: which console 779 * @param dbg_enb: ptr to debug enablement string, one of: 780 * * NULL for no debug output (i.e. disabled) 781 * * empty string enables debug output (via default method) 782 * * specific string to enable debug console output 783 * 784 * @return Zero on success, negative on failure. 785 */ 786 int octeon_add_console(struct octeon_device *oct, u32 console_num, 787 char *dbg_enb); 788 789 /** write or read from a console */ 790 int octeon_console_write(struct octeon_device *oct, u32 console_num, 791 char *buffer, u32 write_request_size, u32 flags); 792 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); 793 794 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); 795 796 /** Removes all attached consoles. */ 797 void octeon_remove_consoles(struct octeon_device *oct); 798 799 /** 800 * Send a string to u-boot on console 0 as a command. 801 * 802 * @param oct which octeon to send to 803 * @param cmd_str String to send 804 * @param wait_hundredths Time to wait for u-boot to accept the command. 805 * 806 * @return Zero on success, negative on failure. 807 */ 808 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 809 u32 wait_hundredths); 810 811 /** Parses, validates, and downloads firmware, then boots associated cores. 812 * @param oct which octeon to download firmware to 813 * @param data - The complete firmware file image 814 * @param size - The size of the data 815 * 816 * @return 0 if success. 817 * -EINVAL if file is incompatible or badly formatted. 818 * -ENODEV if no handler was found for the application type or an 819 * invalid octeon id was passed. 820 */ 821 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 822 size_t size); 823 824 char *lio_get_state_string(atomic_t *state_ptr); 825 826 /** Sets up instruction queues for the device 827 * @param oct which octeon to setup 828 * 829 * @return 0 if success. 1 if fails 830 */ 831 int octeon_setup_instr_queues(struct octeon_device *oct); 832 833 /** Sets up output queues for the device 834 * @param oct which octeon to setup 835 * 836 * @return 0 if success. 1 if fails 837 */ 838 int octeon_setup_output_queues(struct octeon_device *oct); 839 840 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); 841 842 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); 843 844 /** Turns off the input and output queues for the device 845 * @param oct which octeon to disable 846 */ 847 int octeon_set_io_queues_off(struct octeon_device *oct); 848 849 /** Turns on or off the given output queue for the device 850 * @param oct which octeon to change 851 * @param q_no which queue 852 * @param enable 1 to enable, 0 to disable 853 */ 854 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); 855 856 /** Retrieve the config for the device 857 * @param oct which octeon 858 * @param card_type type of card 859 * 860 * @returns pointer to configuration 861 */ 862 void *oct_get_config_info(struct octeon_device *oct, u16 card_type); 863 864 /** Gets the octeon device configuration 865 * @return - pointer to the octeon configuration struture 866 */ 867 struct octeon_config *octeon_get_conf(struct octeon_device *oct); 868 869 void octeon_free_ioq_vector(struct octeon_device *oct); 870 int octeon_allocate_ioq_vector(struct octeon_device *oct); 871 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq); 872 873 /* LiquidIO driver pivate flags */ 874 enum { 875 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */ 876 }; 877 878 #define OCT_PRIV_FLAG_DEFAULT 0x0 879 880 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag) 881 { 882 return !!(octdev->priv_flags & (0x1 << flag)); 883 } 884 885 static inline void lio_set_priv_flag(struct octeon_device *octdev, 886 u32 flag, u32 val) 887 { 888 if (val) 889 octdev->priv_flags |= (0x1 << flag); 890 else 891 octdev->priv_flags &= ~(0x1 << flag); 892 } 893 #endif 894