1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_device.h 19 * \brief Host Driver: This file defines the octeon device structure. 20 */ 21 22 #ifndef _OCTEON_DEVICE_H_ 23 #define _OCTEON_DEVICE_H_ 24 25 /** PCI VendorId Device Id */ 26 #define OCTEON_CN68XX_PCIID 0x91177d 27 #define OCTEON_CN66XX_PCIID 0x92177d 28 #define OCTEON_CN23XX_PCIID_PF 0x9702177d 29 /** Driver identifies chips by these Ids, created by clubbing together 30 * DeviceId+RevisionId; Where Revision Id is not used to distinguish 31 * between chips, a value of 0 is used for revision id. 32 */ 33 #define OCTEON_CN68XX 0x0091 34 #define OCTEON_CN66XX 0x0092 35 #define OCTEON_CN23XX_PF_VID 0x9702 36 #define OCTEON_CN23XX_VF_VID 0x9712 37 38 /**RevisionId for the chips */ 39 #define OCTEON_CN23XX_REV_1_0 0x00 40 #define OCTEON_CN23XX_REV_1_1 0x01 41 #define OCTEON_CN23XX_REV_2_0 0x80 42 43 /** Endian-swap modes supported by Octeon. */ 44 enum octeon_pci_swap_mode { 45 OCTEON_PCI_PASSTHROUGH = 0, 46 OCTEON_PCI_64BIT_SWAP = 1, 47 OCTEON_PCI_32BIT_BYTE_SWAP = 2, 48 OCTEON_PCI_32BIT_LW_SWAP = 3 49 }; 50 51 enum { 52 OCTEON_CONFIG_TYPE_DEFAULT = 0, 53 NUM_OCTEON_CONFS, 54 }; 55 56 #define OCTEON_INPUT_INTR (1) 57 #define OCTEON_OUTPUT_INTR (2) 58 #define OCTEON_MBOX_INTR (4) 59 #define OCTEON_ALL_INTR 0xff 60 61 /*--------------- PCI BAR1 index registers -------------*/ 62 63 /* BAR1 Mask */ 64 #define PCI_BAR1_ENABLE_CA 1 65 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP 66 #define PCI_BAR1_ENTRY_VALID 1 67 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \ 68 | (PCI_BAR1_ENDIAN_MODE << 1) \ 69 | PCI_BAR1_ENTRY_VALID) 70 71 /** Octeon Device state. 72 * Each octeon device goes through each of these states 73 * as it is initialized. 74 */ 75 #define OCT_DEV_BEGIN_STATE 0x0 76 #define OCT_DEV_PCI_ENABLE_DONE 0x1 77 #define OCT_DEV_PCI_MAP_DONE 0x2 78 #define OCT_DEV_DISPATCH_INIT_DONE 0x3 79 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x4 80 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5 81 #define OCT_DEV_RESP_LIST_INIT_DONE 0x6 82 #define OCT_DEV_DROQ_INIT_DONE 0x7 83 #define OCT_DEV_MBOX_SETUP_DONE 0x8 84 #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9 85 #define OCT_DEV_INTR_SET_DONE 0xa 86 #define OCT_DEV_IO_QUEUES_DONE 0xb 87 #define OCT_DEV_CONSOLE_INIT_DONE 0xc 88 #define OCT_DEV_HOST_OK 0xd 89 #define OCT_DEV_CORE_OK 0xe 90 #define OCT_DEV_RUNNING 0xf 91 #define OCT_DEV_IN_RESET 0x10 92 #define OCT_DEV_STATE_INVALID 0x11 93 94 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID 95 96 /** Octeon Device interrupts 97 * These interrupt bits are set in int_status filed of 98 * octeon_device structure 99 */ 100 #define OCT_DEV_INTR_DMA0_FORCE 0x01 101 #define OCT_DEV_INTR_DMA1_FORCE 0x02 102 #define OCT_DEV_INTR_PKT_DATA 0x04 103 104 #define LIO_RESET_SECS (3) 105 106 /*---------------------------DISPATCH LIST-------------------------------*/ 107 108 /** The dispatch list entry. 109 * The driver keeps a record of functions registered for each 110 * response header opcode in this structure. Since the opcode is 111 * hashed to index into the driver's list, more than one opcode 112 * can hash to the same entry, in which case the list field points 113 * to a linked list with the other entries. 114 */ 115 struct octeon_dispatch { 116 /** List head for this entry */ 117 struct list_head list; 118 119 /** The opcode for which the dispatch function & arg should be used */ 120 u16 opcode; 121 122 /** The function to be called for a packet received by the driver */ 123 octeon_dispatch_fn_t dispatch_fn; 124 125 /* The application specified argument to be passed to the above 126 * function along with the received packet 127 */ 128 void *arg; 129 }; 130 131 /** The dispatch list structure. */ 132 struct octeon_dispatch_list { 133 /** access to dispatch list must be atomic */ 134 spinlock_t lock; 135 136 /** Count of dispatch functions currently registered */ 137 u32 count; 138 139 /** The list of dispatch functions */ 140 struct octeon_dispatch *dlist; 141 }; 142 143 /*----------------------- THE OCTEON DEVICE ---------------------------*/ 144 145 #define OCT_MEM_REGIONS 3 146 /** PCI address space mapping information. 147 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 148 * Octeon gets mapped to different physical address spaces in 149 * the kernel. 150 */ 151 struct octeon_mmio { 152 /** PCI address to which the BAR is mapped. */ 153 u64 start; 154 155 /** Length of this PCI address space. */ 156 u32 len; 157 158 /** Length that has been mapped to phys. address space. */ 159 u32 mapped_len; 160 161 /** The physical address to which the PCI address space is mapped. */ 162 u8 __iomem *hw_addr; 163 164 /** Flag indicating the mapping was successful. */ 165 u32 done; 166 }; 167 168 #define MAX_OCTEON_MAPS 32 169 170 struct octeon_io_enable { 171 u64 iq; 172 u64 oq; 173 u64 iq64B; 174 }; 175 176 struct octeon_reg_list { 177 u32 __iomem *pci_win_wr_addr_hi; 178 u32 __iomem *pci_win_wr_addr_lo; 179 u64 __iomem *pci_win_wr_addr; 180 181 u32 __iomem *pci_win_rd_addr_hi; 182 u32 __iomem *pci_win_rd_addr_lo; 183 u64 __iomem *pci_win_rd_addr; 184 185 u32 __iomem *pci_win_wr_data_hi; 186 u32 __iomem *pci_win_wr_data_lo; 187 u64 __iomem *pci_win_wr_data; 188 189 u32 __iomem *pci_win_rd_data_hi; 190 u32 __iomem *pci_win_rd_data_lo; 191 u64 __iomem *pci_win_rd_data; 192 }; 193 194 #define OCTEON_CONSOLE_MAX_READ_BYTES 512 195 struct octeon_console { 196 u32 active; 197 u32 waiting; 198 u64 addr; 199 u32 buffer_size; 200 u64 input_base_addr; 201 u64 output_base_addr; 202 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES]; 203 }; 204 205 struct octeon_board_info { 206 char name[OCT_BOARD_NAME]; 207 char serial_number[OCT_SERIAL_LEN]; 208 u64 major; 209 u64 minor; 210 }; 211 212 struct octeon_fn_list { 213 void (*setup_iq_regs)(struct octeon_device *, u32); 214 void (*setup_oq_regs)(struct octeon_device *, u32); 215 216 irqreturn_t (*process_interrupt_regs)(void *); 217 u64 (*msix_interrupt_handler)(void *); 218 219 int (*setup_mbox)(struct octeon_device *); 220 int (*free_mbox)(struct octeon_device *); 221 222 int (*soft_reset)(struct octeon_device *); 223 int (*setup_device_regs)(struct octeon_device *); 224 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int); 225 void (*bar1_idx_write)(struct octeon_device *, u32, u32); 226 u32 (*bar1_idx_read)(struct octeon_device *, u32); 227 u32 (*update_iq_read_idx)(struct octeon_instr_queue *); 228 229 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32); 230 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32); 231 232 void (*enable_interrupt)(struct octeon_device *, u8); 233 void (*disable_interrupt)(struct octeon_device *, u8); 234 235 int (*enable_io_queues)(struct octeon_device *); 236 void (*disable_io_queues)(struct octeon_device *); 237 }; 238 239 /* Must be multiple of 8, changing breaks ABI */ 240 #define CVMX_BOOTMEM_NAME_LEN 128 241 242 /* Structure for named memory blocks 243 * Number of descriptors 244 * available can be changed without affecting compatibility, 245 * but name length changes require a bump in the bootmem 246 * descriptor version 247 * Note: This structure must be naturally 64 bit aligned, as a single 248 * memory image will be used by both 32 and 64 bit programs. 249 */ 250 struct cvmx_bootmem_named_block_desc { 251 /** Base address of named block */ 252 u64 base_addr; 253 254 /** Size actually allocated for named block */ 255 u64 size; 256 257 /** name of named block */ 258 char name[CVMX_BOOTMEM_NAME_LEN]; 259 }; 260 261 struct oct_fw_info { 262 u32 max_nic_ports; /** max nic ports for the device */ 263 u32 num_gmx_ports; /** num gmx ports */ 264 u64 app_cap_flags; /** firmware cap flags */ 265 266 /** The core application is running in this mode. 267 * See octeon-drv-opcodes.h for values. 268 */ 269 u32 app_mode; 270 char liquidio_firmware_version[32]; 271 }; 272 273 /* wrappers around work structs */ 274 struct cavium_wk { 275 struct delayed_work work; 276 void *ctxptr; 277 u64 ctxul; 278 }; 279 280 struct cavium_wq { 281 struct workqueue_struct *wq; 282 struct cavium_wk wk; 283 }; 284 285 struct octdev_props { 286 /* Each interface in the Octeon device has a network 287 * device pointer (used for OS specific calls). 288 */ 289 int rx_on; 290 int napi_enabled; 291 int gmxport; 292 struct net_device *netdev; 293 }; 294 295 #define LIO_FLAG_MSIX_ENABLED 0x1 296 #define MSIX_PO_INT 0x1 297 #define MSIX_PI_INT 0x2 298 #define MSIX_MBOX_INT 0x4 299 300 struct octeon_pf_vf_hs_word { 301 #ifdef __LITTLE_ENDIAN_BITFIELD 302 /** PKIND value assigned for the DPI interface */ 303 u64 pkind : 8; 304 305 /** OCTEON core clock multiplier */ 306 u64 core_tics_per_us : 16; 307 308 /** OCTEON coprocessor clock multiplier */ 309 u64 coproc_tics_per_us : 16; 310 311 /** app that currently running on OCTEON */ 312 u64 app_mode : 8; 313 314 /** RESERVED */ 315 u64 reserved : 16; 316 317 #else 318 319 /** RESERVED */ 320 u64 reserved : 16; 321 322 /** app that currently running on OCTEON */ 323 u64 app_mode : 8; 324 325 /** OCTEON coprocessor clock multiplier */ 326 u64 coproc_tics_per_us : 16; 327 328 /** OCTEON core clock multiplier */ 329 u64 core_tics_per_us : 16; 330 331 /** PKIND value assigned for the DPI interface */ 332 u64 pkind : 8; 333 #endif 334 }; 335 336 struct octeon_sriov_info { 337 /* Number of rings assigned to VF */ 338 u32 rings_per_vf; 339 340 /** Max Number of VF devices that can be enabled. This variable can 341 * specified during load time or it will be derived after allocating 342 * PF queues. When max_vfs is derived then each VF will get one queue 343 **/ 344 u32 max_vfs; 345 346 /** Number of VF devices enabled using sysfs. */ 347 u32 num_vfs_alloced; 348 349 /* Actual rings left for PF device */ 350 u32 num_pf_rings; 351 352 /* SRN of PF usable IO queues */ 353 u32 pf_srn; 354 355 /* total pf rings */ 356 u32 trs; 357 358 u32 sriov_enabled; 359 360 /*lookup table that maps DPI ring number to VF pci_dev struct pointer*/ 361 struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS]; 362 363 u64 vf_macaddr[MAX_POSSIBLE_VFS]; 364 365 u16 vf_vlantci[MAX_POSSIBLE_VFS]; 366 367 int vf_linkstate[MAX_POSSIBLE_VFS]; 368 369 u64 vf_drv_loaded_mask; 370 }; 371 372 struct octeon_ioq_vector { 373 struct octeon_device *oct_dev; 374 int iq_index; 375 int droq_index; 376 int vector; 377 struct octeon_mbox *mbox; 378 struct cpumask affinity_mask; 379 u32 ioq_num; 380 }; 381 382 /** The Octeon device. 383 * Each Octeon device has this structure to represent all its 384 * components. 385 */ 386 struct octeon_device { 387 /** Lock for PCI window configuration accesses */ 388 spinlock_t pci_win_lock; 389 390 /** Lock for memory accesses */ 391 spinlock_t mem_access_lock; 392 393 /** PCI device pointer */ 394 struct pci_dev *pci_dev; 395 396 /** Chip specific information. */ 397 void *chip; 398 399 /** Number of interfaces detected in this octeon device. */ 400 u32 ifcount; 401 402 struct octdev_props props[MAX_OCTEON_LINKS]; 403 404 /** Octeon Chip type. */ 405 u16 chip_id; 406 407 u16 rev_id; 408 409 u16 pf_num; 410 411 u16 vf_num; 412 413 /** This device's id - set by the driver. */ 414 u32 octeon_id; 415 416 /** This device's PCIe port used for traffic. */ 417 u16 pcie_port; 418 419 u16 flags; 420 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1) 421 422 /** The state of this device */ 423 atomic_t status; 424 425 /** memory mapped io range */ 426 struct octeon_mmio mmio[OCT_MEM_REGIONS]; 427 428 struct octeon_reg_list reg_list; 429 430 struct octeon_fn_list fn_list; 431 432 struct octeon_board_info boardinfo; 433 434 u32 num_iqs; 435 436 /* The pool containing pre allocated buffers used for soft commands */ 437 struct octeon_sc_buffer_pool sc_buf_pool; 438 439 /** The input instruction queues */ 440 struct octeon_instr_queue *instr_queue 441 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 442 443 /** The doubly-linked list of instruction response */ 444 struct octeon_response_list response_list[MAX_RESPONSE_LISTS]; 445 446 u32 num_oqs; 447 448 /** The DROQ output queues */ 449 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES]; 450 451 struct octeon_io_enable io_qmask; 452 453 /** List of dispatch functions */ 454 struct octeon_dispatch_list dispatch; 455 456 u32 int_status; 457 458 u64 droq_intr; 459 460 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */ 461 u64 bootmem_desc_addr; 462 463 /** Placeholder memory for named blocks. 464 * Assumes single-threaded access 465 */ 466 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; 467 468 /** Address of consoles descriptor */ 469 u64 console_desc_addr; 470 471 /** Number of consoles available. 0 means they are inaccessible */ 472 u32 num_consoles; 473 474 /* Console caches */ 475 struct octeon_console console[MAX_OCTEON_MAPS]; 476 477 /* Console named block info */ 478 struct { 479 u64 dram_region_base; 480 int bar1_index; 481 } console_nb_info; 482 483 /* Coprocessor clock rate. */ 484 u64 coproc_clock_rate; 485 486 /** The core application is running in this mode. See liquidio_common.h 487 * for values. 488 */ 489 u32 app_mode; 490 491 struct oct_fw_info fw_info; 492 493 /** The name given to this device. */ 494 char device_name[32]; 495 496 /** Application Context */ 497 void *app_ctx; 498 499 struct cavium_wq dma_comp_wq; 500 501 /** Lock for dma response list */ 502 spinlock_t cmd_resp_wqlock; 503 u32 cmd_resp_state; 504 505 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 506 507 struct cavium_wk nic_poll_work; 508 509 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS]; 510 511 void *priv; 512 513 int num_msix_irqs; 514 515 void *msix_entries; 516 517 /* when requesting IRQs, the names are stored here */ 518 void *irq_name_storage; 519 520 struct octeon_sriov_info sriov_info; 521 522 struct octeon_pf_vf_hs_word pfvf_hsword; 523 524 int msix_on; 525 526 /** Mail Box details of each octeon queue. */ 527 struct octeon_mbox *mbox[MAX_POSSIBLE_VFS]; 528 529 /** IOq information of it's corresponding MSI-X interrupt. */ 530 struct octeon_ioq_vector *ioq_vector; 531 532 int rx_pause; 533 int tx_pause; 534 535 struct oct_link_stats link_stats; /*stastics from firmware*/ 536 537 /* private flags to control driver-specific features through ethtool */ 538 u32 priv_flags; 539 540 void *watchdog_task; 541 542 u32 rx_coalesce_usecs; 543 u32 rx_max_coalesced_frames; 544 u32 tx_max_coalesced_frames; 545 546 bool cores_crashed; 547 548 struct { 549 int bus; 550 int dev; 551 int func; 552 } loc; 553 554 atomic_t *adapter_refcount; /* reference count of adapter */ 555 }; 556 557 #define OCT_DRV_ONLINE 1 558 #define OCT_DRV_OFFLINE 2 559 #define OCTEON_CN6XXX(oct) ({ \ 560 typeof(oct) _oct = (oct); \ 561 ((_oct->chip_id == OCTEON_CN66XX) || \ 562 (_oct->chip_id == OCTEON_CN68XX)); }) 563 #define OCTEON_CN23XX_PF(oct) ((oct)->chip_id == OCTEON_CN23XX_PF_VID) 564 #define OCTEON_CN23XX_VF(oct) ((oct)->chip_id == OCTEON_CN23XX_VF_VID) 565 #define CHIP_CONF(oct, TYPE) \ 566 (((struct octeon_ ## TYPE *)((oct)->chip))->conf) 567 568 /*------------------ Function Prototypes ----------------------*/ 569 570 /** Initialize device list memory */ 571 void octeon_init_device_list(int conf_type); 572 573 /** Free memory for Input and Output queue structures for a octeon device */ 574 void octeon_free_device_mem(struct octeon_device *oct); 575 576 /* Look up a free entry in the octeon_device table and allocate resources 577 * for the octeon_device structure for an octeon device. Called at init 578 * time. 579 */ 580 struct octeon_device *octeon_allocate_device(u32 pci_id, 581 u32 priv_size); 582 583 /** Register a device's bus location at initialization time. 584 * @param octeon_dev - pointer to the octeon device structure. 585 * @param bus - PCIe bus # 586 * @param dev - PCIe device # 587 * @param func - PCIe function # 588 * @param is_pf - TRUE for PF, FALSE for VF 589 * @return reference count of device's adapter 590 */ 591 int octeon_register_device(struct octeon_device *oct, 592 int bus, int dev, int func, int is_pf); 593 594 /** Deregister a device at de-initialization time. 595 * @param octeon_dev - pointer to the octeon device structure. 596 * @return reference count of device's adapter 597 */ 598 int octeon_deregister_device(struct octeon_device *oct); 599 600 /** Initialize the driver's dispatch list which is a mix of a hash table 601 * and a linked list. This is done at driver load time. 602 * @param octeon_dev - pointer to the octeon device structure. 603 * @return 0 on success, else -ve error value 604 */ 605 int octeon_init_dispatch_list(struct octeon_device *octeon_dev); 606 607 /** Delete the driver's dispatch list and all registered entries. 608 * This is done at driver unload time. 609 * @param octeon_dev - pointer to the octeon device structure. 610 */ 611 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); 612 613 /** Initialize the core device fields with the info returned by the FW. 614 * @param recv_info - Receive info structure 615 * @param buf - Receive buffer 616 */ 617 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); 618 619 /** Gets the dispatch function registered to receive packets with a 620 * given opcode/subcode. 621 * @param octeon_dev - the octeon device pointer. 622 * @param opcode - the opcode for which the dispatch function 623 * is to checked. 624 * @param subcode - the subcode for which the dispatch function 625 * is to checked. 626 * 627 * @return Success: octeon_dispatch_fn_t (dispatch function pointer) 628 * @return Failure: NULL 629 * 630 * Looks up the dispatch list to get the dispatch function for a 631 * given opcode. 632 */ 633 octeon_dispatch_fn_t 634 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 635 u16 subcode); 636 637 /** Get the octeon device pointer. 638 * @param octeon_id - The id for which the octeon device pointer is required. 639 * @return Success: Octeon device pointer. 640 * @return Failure: NULL. 641 */ 642 struct octeon_device *lio_get_device(u32 octeon_id); 643 644 /** Get the octeon id assigned to the octeon device passed as argument. 645 * This function is exported to other modules. 646 * @param dev - octeon device pointer passed as a void *. 647 * @return octeon device id 648 */ 649 int lio_get_device_id(void *dev); 650 651 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct) 652 { 653 u16 rev = (oct->rev_id & 0xC) >> 2; 654 655 return (rev == 0) ? 1 : rev; 656 } 657 658 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct) 659 { 660 return oct->rev_id & 0x3; 661 } 662 663 /** Read windowed register. 664 * @param oct - pointer to the Octeon device. 665 * @param addr - Address of the register to read. 666 * 667 * This routine is called to read from the indirectly accessed 668 * Octeon registers that are visible through a PCI BAR0 mapped window 669 * register. 670 * @return - 64 bit value read from the register. 671 */ 672 673 u64 lio_pci_readq(struct octeon_device *oct, u64 addr); 674 675 /** Write windowed register. 676 * @param oct - pointer to the Octeon device. 677 * @param val - Value to write 678 * @param addr - Address of the register to write 679 * 680 * This routine is called to write to the indirectly accessed 681 * Octeon registers that are visible through a PCI BAR0 mapped window 682 * register. 683 * @return Nothing. 684 */ 685 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); 686 687 /* Routines for reading and writing CSRs */ 688 #define octeon_write_csr(oct_dev, reg_off, value) \ 689 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) 690 691 #define octeon_write_csr64(oct_dev, reg_off, val64) \ 692 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) 693 694 #define octeon_read_csr(oct_dev, reg_off) \ 695 readl((oct_dev)->mmio[0].hw_addr + (reg_off)) 696 697 #define octeon_read_csr64(oct_dev, reg_off) \ 698 readq((oct_dev)->mmio[0].hw_addr + (reg_off)) 699 700 /** 701 * Checks if memory access is okay 702 * 703 * @param oct which octeon to send to 704 * @return Zero on success, negative on failure. 705 */ 706 int octeon_mem_access_ok(struct octeon_device *oct); 707 708 /** 709 * Waits for DDR initialization. 710 * 711 * @param oct which octeon to send to 712 * @param timeout_in_ms pointer to how long to wait until DDR is initialized 713 * in ms. 714 * If contents are 0, it waits until contents are non-zero 715 * before starting to check. 716 * @return Zero on success, negative on failure. 717 */ 718 int octeon_wait_for_ddr_init(struct octeon_device *oct, 719 u32 *timeout_in_ms); 720 721 /** 722 * Wait for u-boot to boot and be waiting for a command. 723 * 724 * @param wait_time_hundredths 725 * Maximum time to wait 726 * 727 * @return Zero on success, negative on failure. 728 */ 729 int octeon_wait_for_bootloader(struct octeon_device *oct, 730 u32 wait_time_hundredths); 731 732 /** 733 * Initialize console access 734 * 735 * @param oct which octeon initialize 736 * @return Zero on success, negative on failure. 737 */ 738 int octeon_init_consoles(struct octeon_device *oct); 739 740 /** 741 * Adds access to a console to the device. 742 * 743 * @param oct which octeon to add to 744 * @param console_num which console 745 * @return Zero on success, negative on failure. 746 */ 747 int octeon_add_console(struct octeon_device *oct, u32 console_num); 748 749 /** write or read from a console */ 750 int octeon_console_write(struct octeon_device *oct, u32 console_num, 751 char *buffer, u32 write_request_size, u32 flags); 752 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); 753 754 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); 755 756 /** Removes all attached consoles. */ 757 void octeon_remove_consoles(struct octeon_device *oct); 758 759 /** 760 * Send a string to u-boot on console 0 as a command. 761 * 762 * @param oct which octeon to send to 763 * @param cmd_str String to send 764 * @param wait_hundredths Time to wait for u-boot to accept the command. 765 * 766 * @return Zero on success, negative on failure. 767 */ 768 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 769 u32 wait_hundredths); 770 771 /** Parses, validates, and downloads firmware, then boots associated cores. 772 * @param oct which octeon to download firmware to 773 * @param data - The complete firmware file image 774 * @param size - The size of the data 775 * 776 * @return 0 if success. 777 * -EINVAL if file is incompatible or badly formatted. 778 * -ENODEV if no handler was found for the application type or an 779 * invalid octeon id was passed. 780 */ 781 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 782 size_t size); 783 784 char *lio_get_state_string(atomic_t *state_ptr); 785 786 /** Sets up instruction queues for the device 787 * @param oct which octeon to setup 788 * 789 * @return 0 if success. 1 if fails 790 */ 791 int octeon_setup_instr_queues(struct octeon_device *oct); 792 793 /** Sets up output queues for the device 794 * @param oct which octeon to setup 795 * 796 * @return 0 if success. 1 if fails 797 */ 798 int octeon_setup_output_queues(struct octeon_device *oct); 799 800 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); 801 802 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); 803 804 /** Turns off the input and output queues for the device 805 * @param oct which octeon to disable 806 */ 807 int octeon_set_io_queues_off(struct octeon_device *oct); 808 809 /** Turns on or off the given output queue for the device 810 * @param oct which octeon to change 811 * @param q_no which queue 812 * @param enable 1 to enable, 0 to disable 813 */ 814 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); 815 816 /** Retrieve the config for the device 817 * @param oct which octeon 818 * @param card_type type of card 819 * 820 * @returns pointer to configuration 821 */ 822 void *oct_get_config_info(struct octeon_device *oct, u16 card_type); 823 824 /** Gets the octeon device configuration 825 * @return - pointer to the octeon configuration struture 826 */ 827 struct octeon_config *octeon_get_conf(struct octeon_device *oct); 828 829 void octeon_free_ioq_vector(struct octeon_device *oct); 830 int octeon_allocate_ioq_vector(struct octeon_device *oct); 831 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq); 832 833 /* LiquidIO driver pivate flags */ 834 enum { 835 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */ 836 }; 837 838 #define OCT_PRIV_FLAG_DEFAULT 0x0 839 840 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag) 841 { 842 return !!(octdev->priv_flags & (0x1 << flag)); 843 } 844 845 static inline void lio_set_priv_flag(struct octeon_device *octdev, 846 u32 flag, u32 val) 847 { 848 if (val) 849 octdev->priv_flags |= (0x1 << flag); 850 else 851 octdev->priv_flags &= ~(0x1 << flag); 852 } 853 #endif 854