1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2015 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 23 /*! \file octeon_device.h 24 * \brief Host Driver: This file defines the octeon device structure. 25 */ 26 27 #ifndef _OCTEON_DEVICE_H_ 28 #define _OCTEON_DEVICE_H_ 29 30 /** PCI VendorId Device Id */ 31 #define OCTEON_CN68XX_PCIID 0x91177d 32 #define OCTEON_CN66XX_PCIID 0x92177d 33 34 /** Driver identifies chips by these Ids, created by clubbing together 35 * DeviceId+RevisionId; Where Revision Id is not used to distinguish 36 * between chips, a value of 0 is used for revision id. 37 */ 38 #define OCTEON_CN68XX 0x0091 39 #define OCTEON_CN66XX 0x0092 40 41 /** Endian-swap modes supported by Octeon. */ 42 enum octeon_pci_swap_mode { 43 OCTEON_PCI_PASSTHROUGH = 0, 44 OCTEON_PCI_64BIT_SWAP = 1, 45 OCTEON_PCI_32BIT_BYTE_SWAP = 2, 46 OCTEON_PCI_32BIT_LW_SWAP = 3 47 }; 48 49 /*--------------- PCI BAR1 index registers -------------*/ 50 51 /* BAR1 Mask */ 52 #define PCI_BAR1_ENABLE_CA 1 53 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP 54 #define PCI_BAR1_ENTRY_VALID 1 55 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \ 56 | (PCI_BAR1_ENDIAN_MODE << 1) \ 57 | PCI_BAR1_ENTRY_VALID) 58 59 /** Octeon Device state. 60 * Each octeon device goes through each of these states 61 * as it is initialized. 62 */ 63 #define OCT_DEV_BEGIN_STATE 0x0 64 #define OCT_DEV_PCI_MAP_DONE 0x1 65 #define OCT_DEV_DISPATCH_INIT_DONE 0x2 66 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x3 67 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x4 68 #define OCT_DEV_RESP_LIST_INIT_DONE 0x5 69 #define OCT_DEV_DROQ_INIT_DONE 0x6 70 #define OCT_DEV_IO_QUEUES_DONE 0x7 71 #define OCT_DEV_CONSOLE_INIT_DONE 0x8 72 #define OCT_DEV_HOST_OK 0x9 73 #define OCT_DEV_CORE_OK 0xa 74 #define OCT_DEV_RUNNING 0xb 75 #define OCT_DEV_IN_RESET 0xc 76 #define OCT_DEV_STATE_INVALID 0xd 77 78 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID 79 80 /** Octeon Device interrupts 81 * These interrupt bits are set in int_status filed of 82 * octeon_device structure 83 */ 84 #define OCT_DEV_INTR_DMA0_FORCE 0x01 85 #define OCT_DEV_INTR_DMA1_FORCE 0x02 86 #define OCT_DEV_INTR_PKT_DATA 0x04 87 88 #define LIO_RESET_SECS (3) 89 90 /*---------------------------DISPATCH LIST-------------------------------*/ 91 92 /** The dispatch list entry. 93 * The driver keeps a record of functions registered for each 94 * response header opcode in this structure. Since the opcode is 95 * hashed to index into the driver's list, more than one opcode 96 * can hash to the same entry, in which case the list field points 97 * to a linked list with the other entries. 98 */ 99 struct octeon_dispatch { 100 /** List head for this entry */ 101 struct list_head list; 102 103 /** The opcode for which the dispatch function & arg should be used */ 104 u16 opcode; 105 106 /** The function to be called for a packet received by the driver */ 107 octeon_dispatch_fn_t dispatch_fn; 108 109 /* The application specified argument to be passed to the above 110 * function along with the received packet 111 */ 112 void *arg; 113 }; 114 115 /** The dispatch list structure. */ 116 struct octeon_dispatch_list { 117 /** access to dispatch list must be atomic */ 118 spinlock_t lock; 119 120 /** Count of dispatch functions currently registered */ 121 u32 count; 122 123 /** The list of dispatch functions */ 124 struct octeon_dispatch *dlist; 125 }; 126 127 /*----------------------- THE OCTEON DEVICE ---------------------------*/ 128 129 #define OCT_MEM_REGIONS 3 130 /** PCI address space mapping information. 131 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 132 * Octeon gets mapped to different physical address spaces in 133 * the kernel. 134 */ 135 struct octeon_mmio { 136 /** PCI address to which the BAR is mapped. */ 137 u64 start; 138 139 /** Length of this PCI address space. */ 140 u32 len; 141 142 /** Length that has been mapped to phys. address space. */ 143 u32 mapped_len; 144 145 /** The physical address to which the PCI address space is mapped. */ 146 u8 __iomem *hw_addr; 147 148 /** Flag indicating the mapping was successful. */ 149 u32 done; 150 }; 151 152 #define MAX_OCTEON_MAPS 32 153 154 struct octeon_io_enable { 155 u64 iq; 156 u64 oq; 157 u64 iq64B; 158 }; 159 160 struct octeon_reg_list { 161 u32 __iomem *pci_win_wr_addr_hi; 162 u32 __iomem *pci_win_wr_addr_lo; 163 u64 __iomem *pci_win_wr_addr; 164 165 u32 __iomem *pci_win_rd_addr_hi; 166 u32 __iomem *pci_win_rd_addr_lo; 167 u64 __iomem *pci_win_rd_addr; 168 169 u32 __iomem *pci_win_wr_data_hi; 170 u32 __iomem *pci_win_wr_data_lo; 171 u64 __iomem *pci_win_wr_data; 172 173 u32 __iomem *pci_win_rd_data_hi; 174 u32 __iomem *pci_win_rd_data_lo; 175 u64 __iomem *pci_win_rd_data; 176 }; 177 178 #define OCTEON_CONSOLE_MAX_READ_BYTES 512 179 struct octeon_console { 180 u32 active; 181 u32 waiting; 182 u64 addr; 183 u32 buffer_size; 184 u64 input_base_addr; 185 u64 output_base_addr; 186 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES]; 187 }; 188 189 struct octeon_board_info { 190 char name[OCT_BOARD_NAME]; 191 char serial_number[OCT_SERIAL_LEN]; 192 u64 major; 193 u64 minor; 194 }; 195 196 struct octeon_fn_list { 197 void (*setup_iq_regs)(struct octeon_device *, u32); 198 void (*setup_oq_regs)(struct octeon_device *, u32); 199 200 irqreturn_t (*process_interrupt_regs)(void *); 201 int (*soft_reset)(struct octeon_device *); 202 int (*setup_device_regs)(struct octeon_device *); 203 void (*reinit_regs)(struct octeon_device *); 204 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int); 205 void (*bar1_idx_write)(struct octeon_device *, u32, u32); 206 u32 (*bar1_idx_read)(struct octeon_device *, u32); 207 u32 (*update_iq_read_idx)(struct octeon_instr_queue *); 208 209 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32); 210 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32); 211 212 void (*enable_interrupt)(void *); 213 void (*disable_interrupt)(void *); 214 215 void (*enable_io_queues)(struct octeon_device *); 216 void (*disable_io_queues)(struct octeon_device *); 217 }; 218 219 /* Must be multiple of 8, changing breaks ABI */ 220 #define CVMX_BOOTMEM_NAME_LEN 128 221 222 /* Structure for named memory blocks 223 * Number of descriptors 224 * available can be changed without affecting compatibility, 225 * but name length changes require a bump in the bootmem 226 * descriptor version 227 * Note: This structure must be naturally 64 bit aligned, as a single 228 * memory image will be used by both 32 and 64 bit programs. 229 */ 230 struct cvmx_bootmem_named_block_desc { 231 /** Base address of named block */ 232 u64 base_addr; 233 234 /** Size actually allocated for named block */ 235 u64 size; 236 237 /** name of named block */ 238 char name[CVMX_BOOTMEM_NAME_LEN]; 239 }; 240 241 struct oct_fw_info { 242 u32 max_nic_ports; /** max nic ports for the device */ 243 u32 num_gmx_ports; /** num gmx ports */ 244 u64 app_cap_flags; /** firmware cap flags */ 245 246 /** The core application is running in this mode. 247 * See octeon-drv-opcodes.h for values. 248 */ 249 u32 app_mode; 250 char liquidio_firmware_version[32]; 251 }; 252 253 /* wrappers around work structs */ 254 struct cavium_wk { 255 struct delayed_work work; 256 void *ctxptr; 257 u64 ctxul; 258 }; 259 260 struct cavium_wq { 261 struct workqueue_struct *wq; 262 struct cavium_wk wk; 263 }; 264 265 struct octdev_props { 266 /* Each interface in the Octeon device has a network 267 * device pointer (used for OS specific calls). 268 */ 269 int napi_enabled; 270 int gmxport; 271 struct net_device *netdev; 272 }; 273 274 /** The Octeon device. 275 * Each Octeon device has this structure to represent all its 276 * components. 277 */ 278 struct octeon_device { 279 /** Lock for PCI window configuration accesses */ 280 spinlock_t pci_win_lock; 281 282 /** Lock for memory accesses */ 283 spinlock_t mem_access_lock; 284 285 /** PCI device pointer */ 286 struct pci_dev *pci_dev; 287 288 /** Chip specific information. */ 289 void *chip; 290 291 /** Number of interfaces detected in this octeon device. */ 292 u32 ifcount; 293 294 struct octdev_props props[MAX_OCTEON_LINKS]; 295 296 /** Octeon Chip type. */ 297 u16 chip_id; 298 u16 rev_id; 299 300 /** This device's id - set by the driver. */ 301 u32 octeon_id; 302 303 /** This device's PCIe port used for traffic. */ 304 u16 pcie_port; 305 306 u16 flags; 307 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1) 308 #define LIO_FLAG_MSIX_ENABLED (u32)(1 << 2) 309 310 /** The state of this device */ 311 atomic_t status; 312 313 /** memory mapped io range */ 314 struct octeon_mmio mmio[OCT_MEM_REGIONS]; 315 316 struct octeon_reg_list reg_list; 317 318 struct octeon_fn_list fn_list; 319 320 struct octeon_board_info boardinfo; 321 322 u32 num_iqs; 323 324 /* The pool containing pre allocated buffers used for soft commands */ 325 struct octeon_sc_buffer_pool sc_buf_pool; 326 327 /** The input instruction queues */ 328 struct octeon_instr_queue *instr_queue 329 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 330 331 /** The doubly-linked list of instruction response */ 332 struct octeon_response_list response_list[MAX_RESPONSE_LISTS]; 333 334 u32 num_oqs; 335 336 /** The DROQ output queues */ 337 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES]; 338 339 struct octeon_io_enable io_qmask; 340 341 /** List of dispatch functions */ 342 struct octeon_dispatch_list dispatch; 343 344 /* Interrupt Moderation */ 345 struct oct_intrmod_cfg intrmod; 346 347 u32 int_status; 348 349 u64 droq_intr; 350 351 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */ 352 u64 bootmem_desc_addr; 353 354 /** Placeholder memory for named blocks. 355 * Assumes single-threaded access 356 */ 357 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; 358 359 /** Address of consoles descriptor */ 360 u64 console_desc_addr; 361 362 /** Number of consoles available. 0 means they are inaccessible */ 363 u32 num_consoles; 364 365 /* Console caches */ 366 struct octeon_console console[MAX_OCTEON_MAPS]; 367 368 /* Coprocessor clock rate. */ 369 u64 coproc_clock_rate; 370 371 /** The core application is running in this mode. See liquidio_common.h 372 * for values. 373 */ 374 u32 app_mode; 375 376 struct oct_fw_info fw_info; 377 378 /** The name given to this device. */ 379 char device_name[32]; 380 381 /** Application Context */ 382 void *app_ctx; 383 384 struct cavium_wq dma_comp_wq; 385 386 /** Lock for dma response list */ 387 spinlock_t cmd_resp_wqlock; 388 u32 cmd_resp_state; 389 390 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 391 392 struct cavium_wk nic_poll_work; 393 394 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS]; 395 396 void *priv; 397 398 int rx_pause; 399 int tx_pause; 400 401 struct oct_link_stats link_stats; /*stastics from firmware*/ 402 403 /* private flags to control driver-specific features through ethtool */ 404 u32 priv_flags; 405 }; 406 407 #define OCT_DRV_ONLINE 1 408 #define OCT_DRV_OFFLINE 2 409 #define OCTEON_CN6XXX(oct) ((oct->chip_id == OCTEON_CN66XX) || \ 410 (oct->chip_id == OCTEON_CN68XX)) 411 #define CHIP_FIELD(oct, TYPE, field) \ 412 (((struct octeon_ ## TYPE *)(oct->chip))->field) 413 414 struct oct_intrmod_cmd { 415 struct octeon_device *oct_dev; 416 struct octeon_soft_command *sc; 417 struct oct_intrmod_cfg *cfg; 418 }; 419 420 /*------------------ Function Prototypes ----------------------*/ 421 422 /** Initialize device list memory */ 423 void octeon_init_device_list(int conf_type); 424 425 /** Free memory for Input and Output queue structures for a octeon device */ 426 void octeon_free_device_mem(struct octeon_device *); 427 428 /* Look up a free entry in the octeon_device table and allocate resources 429 * for the octeon_device structure for an octeon device. Called at init 430 * time. 431 */ 432 struct octeon_device *octeon_allocate_device(u32 pci_id, 433 u32 priv_size); 434 435 /** Initialize the driver's dispatch list which is a mix of a hash table 436 * and a linked list. This is done at driver load time. 437 * @param octeon_dev - pointer to the octeon device structure. 438 * @return 0 on success, else -ve error value 439 */ 440 int octeon_init_dispatch_list(struct octeon_device *octeon_dev); 441 442 /** Delete the driver's dispatch list and all registered entries. 443 * This is done at driver unload time. 444 * @param octeon_dev - pointer to the octeon device structure. 445 */ 446 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); 447 448 /** Initialize the core device fields with the info returned by the FW. 449 * @param recv_info - Receive info structure 450 * @param buf - Receive buffer 451 */ 452 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); 453 454 /** Gets the dispatch function registered to receive packets with a 455 * given opcode/subcode. 456 * @param octeon_dev - the octeon device pointer. 457 * @param opcode - the opcode for which the dispatch function 458 * is to checked. 459 * @param subcode - the subcode for which the dispatch function 460 * is to checked. 461 * 462 * @return Success: octeon_dispatch_fn_t (dispatch function pointer) 463 * @return Failure: NULL 464 * 465 * Looks up the dispatch list to get the dispatch function for a 466 * given opcode. 467 */ 468 octeon_dispatch_fn_t 469 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 470 u16 subcode); 471 472 /** Get the octeon device pointer. 473 * @param octeon_id - The id for which the octeon device pointer is required. 474 * @return Success: Octeon device pointer. 475 * @return Failure: NULL. 476 */ 477 struct octeon_device *lio_get_device(u32 octeon_id); 478 479 /** Get the octeon id assigned to the octeon device passed as argument. 480 * This function is exported to other modules. 481 * @param dev - octeon device pointer passed as a void *. 482 * @return octeon device id 483 */ 484 int lio_get_device_id(void *dev); 485 486 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct) 487 { 488 u16 rev = (oct->rev_id & 0xC) >> 2; 489 490 return (rev == 0) ? 1 : rev; 491 } 492 493 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct) 494 { 495 return oct->rev_id & 0x3; 496 } 497 498 /** Read windowed register. 499 * @param oct - pointer to the Octeon device. 500 * @param addr - Address of the register to read. 501 * 502 * This routine is called to read from the indirectly accessed 503 * Octeon registers that are visible through a PCI BAR0 mapped window 504 * register. 505 * @return - 64 bit value read from the register. 506 */ 507 508 u64 lio_pci_readq(struct octeon_device *oct, u64 addr); 509 510 /** Write windowed register. 511 * @param oct - pointer to the Octeon device. 512 * @param val - Value to write 513 * @param addr - Address of the register to write 514 * 515 * This routine is called to write to the indirectly accessed 516 * Octeon registers that are visible through a PCI BAR0 mapped window 517 * register. 518 * @return Nothing. 519 */ 520 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); 521 522 /* Routines for reading and writing CSRs */ 523 #define octeon_write_csr(oct_dev, reg_off, value) \ 524 writel(value, oct_dev->mmio[0].hw_addr + reg_off) 525 526 #define octeon_write_csr64(oct_dev, reg_off, val64) \ 527 writeq(val64, oct_dev->mmio[0].hw_addr + reg_off) 528 529 #define octeon_read_csr(oct_dev, reg_off) \ 530 readl(oct_dev->mmio[0].hw_addr + reg_off) 531 532 #define octeon_read_csr64(oct_dev, reg_off) \ 533 readq(oct_dev->mmio[0].hw_addr + reg_off) 534 535 /** 536 * Checks if memory access is okay 537 * 538 * @param oct which octeon to send to 539 * @return Zero on success, negative on failure. 540 */ 541 int octeon_mem_access_ok(struct octeon_device *oct); 542 543 /** 544 * Waits for DDR initialization. 545 * 546 * @param oct which octeon to send to 547 * @param timeout_in_ms pointer to how long to wait until DDR is initialized 548 * in ms. 549 * If contents are 0, it waits until contents are non-zero 550 * before starting to check. 551 * @return Zero on success, negative on failure. 552 */ 553 int octeon_wait_for_ddr_init(struct octeon_device *oct, 554 u32 *timeout_in_ms); 555 556 /** 557 * Wait for u-boot to boot and be waiting for a command. 558 * 559 * @param wait_time_hundredths 560 * Maximum time to wait 561 * 562 * @return Zero on success, negative on failure. 563 */ 564 int octeon_wait_for_bootloader(struct octeon_device *oct, 565 u32 wait_time_hundredths); 566 567 /** 568 * Initialize console access 569 * 570 * @param oct which octeon initialize 571 * @return Zero on success, negative on failure. 572 */ 573 int octeon_init_consoles(struct octeon_device *oct); 574 575 /** 576 * Adds access to a console to the device. 577 * 578 * @param oct which octeon to add to 579 * @param console_num which console 580 * @return Zero on success, negative on failure. 581 */ 582 int octeon_add_console(struct octeon_device *oct, u32 console_num); 583 584 /** write or read from a console */ 585 int octeon_console_write(struct octeon_device *oct, u32 console_num, 586 char *buffer, u32 write_request_size, u32 flags); 587 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); 588 589 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); 590 591 /** Removes all attached consoles. */ 592 void octeon_remove_consoles(struct octeon_device *oct); 593 594 /** 595 * Send a string to u-boot on console 0 as a command. 596 * 597 * @param oct which octeon to send to 598 * @param cmd_str String to send 599 * @param wait_hundredths Time to wait for u-boot to accept the command. 600 * 601 * @return Zero on success, negative on failure. 602 */ 603 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 604 u32 wait_hundredths); 605 606 /** Parses, validates, and downloads firmware, then boots associated cores. 607 * @param oct which octeon to download firmware to 608 * @param data - The complete firmware file image 609 * @param size - The size of the data 610 * 611 * @return 0 if success. 612 * -EINVAL if file is incompatible or badly formatted. 613 * -ENODEV if no handler was found for the application type or an 614 * invalid octeon id was passed. 615 */ 616 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 617 size_t size); 618 619 char *lio_get_state_string(atomic_t *state_ptr); 620 621 /** Sets up instruction queues for the device 622 * @param oct which octeon to setup 623 * 624 * @return 0 if success. 1 if fails 625 */ 626 int octeon_setup_instr_queues(struct octeon_device *oct); 627 628 /** Sets up output queues for the device 629 * @param oct which octeon to setup 630 * 631 * @return 0 if success. 1 if fails 632 */ 633 int octeon_setup_output_queues(struct octeon_device *oct); 634 635 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); 636 637 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); 638 639 /** Turns off the input and output queues for the device 640 * @param oct which octeon to disable 641 */ 642 void octeon_set_io_queues_off(struct octeon_device *oct); 643 644 /** Turns on or off the given output queue for the device 645 * @param oct which octeon to change 646 * @param q_no which queue 647 * @param enable 1 to enable, 0 to disable 648 */ 649 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); 650 651 /** Retrieve the config for the device 652 * @param oct which octeon 653 * @param card_type type of card 654 * 655 * @returns pointer to configuration 656 */ 657 void *oct_get_config_info(struct octeon_device *oct, u16 card_type); 658 659 /** Gets the octeon device configuration 660 * @return - pointer to the octeon configuration struture 661 */ 662 struct octeon_config *octeon_get_conf(struct octeon_device *oct); 663 664 /* LiquidIO driver pivate flags */ 665 enum { 666 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */ 667 }; 668 669 static inline void lio_set_priv_flag(struct octeon_device *octdev, u32 flag, 670 u32 val) 671 { 672 if (val) 673 octdev->priv_flags |= (0x1 << flag); 674 else 675 octdev->priv_flags &= ~(0x1 << flag); 676 } 677 #endif 678