1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_device.h 19 * \brief Host Driver: This file defines the octeon device structure. 20 */ 21 22 #ifndef _OCTEON_DEVICE_H_ 23 #define _OCTEON_DEVICE_H_ 24 25 #include <linux/interrupt.h> 26 #include <net/devlink.h> 27 28 /** PCI VendorId Device Id */ 29 #define OCTEON_CN68XX_PCIID 0x91177d 30 #define OCTEON_CN66XX_PCIID 0x92177d 31 #define OCTEON_CN23XX_PCIID_PF 0x9702177d 32 /** Driver identifies chips by these Ids, created by clubbing together 33 * DeviceId+RevisionId; Where Revision Id is not used to distinguish 34 * between chips, a value of 0 is used for revision id. 35 */ 36 #define OCTEON_CN68XX 0x0091 37 #define OCTEON_CN66XX 0x0092 38 #define OCTEON_CN23XX_PF_VID 0x9702 39 #define OCTEON_CN23XX_VF_VID 0x9712 40 41 /**RevisionId for the chips */ 42 #define OCTEON_CN23XX_REV_1_0 0x00 43 #define OCTEON_CN23XX_REV_1_1 0x01 44 #define OCTEON_CN23XX_REV_2_0 0x80 45 46 /**SubsystemId for the chips */ 47 #define OCTEON_CN2350_10GB_SUBSYS_ID_1 0X3177d 48 #define OCTEON_CN2350_10GB_SUBSYS_ID_2 0X4177d 49 #define OCTEON_CN2360_10GB_SUBSYS_ID 0X5177d 50 #define OCTEON_CN2350_25GB_SUBSYS_ID 0X7177d 51 #define OCTEON_CN2360_25GB_SUBSYS_ID 0X6177d 52 53 /** Endian-swap modes supported by Octeon. */ 54 enum octeon_pci_swap_mode { 55 OCTEON_PCI_PASSTHROUGH = 0, 56 OCTEON_PCI_64BIT_SWAP = 1, 57 OCTEON_PCI_32BIT_BYTE_SWAP = 2, 58 OCTEON_PCI_32BIT_LW_SWAP = 3 59 }; 60 61 enum lio_fw_state { 62 FW_IS_PRELOADED = 0, 63 FW_NEEDS_TO_BE_LOADED = 1, 64 FW_IS_BEING_LOADED = 2, 65 FW_HAS_BEEN_LOADED = 3, 66 }; 67 68 enum { 69 OCTEON_CONFIG_TYPE_DEFAULT = 0, 70 NUM_OCTEON_CONFS, 71 }; 72 73 #define OCTEON_INPUT_INTR (1) 74 #define OCTEON_OUTPUT_INTR (2) 75 #define OCTEON_MBOX_INTR (4) 76 #define OCTEON_ALL_INTR 0xff 77 78 /*--------------- PCI BAR1 index registers -------------*/ 79 80 /* BAR1 Mask */ 81 #define PCI_BAR1_ENABLE_CA 1 82 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP 83 #define PCI_BAR1_ENTRY_VALID 1 84 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \ 85 | (PCI_BAR1_ENDIAN_MODE << 1) \ 86 | PCI_BAR1_ENTRY_VALID) 87 88 /** Octeon Device state. 89 * Each octeon device goes through each of these states 90 * as it is initialized. 91 */ 92 #define OCT_DEV_BEGIN_STATE 0x0 93 #define OCT_DEV_PCI_ENABLE_DONE 0x1 94 #define OCT_DEV_PCI_MAP_DONE 0x2 95 #define OCT_DEV_DISPATCH_INIT_DONE 0x3 96 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x4 97 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5 98 #define OCT_DEV_RESP_LIST_INIT_DONE 0x6 99 #define OCT_DEV_DROQ_INIT_DONE 0x7 100 #define OCT_DEV_MBOX_SETUP_DONE 0x8 101 #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9 102 #define OCT_DEV_INTR_SET_DONE 0xa 103 #define OCT_DEV_IO_QUEUES_DONE 0xb 104 #define OCT_DEV_CONSOLE_INIT_DONE 0xc 105 #define OCT_DEV_HOST_OK 0xd 106 #define OCT_DEV_CORE_OK 0xe 107 #define OCT_DEV_RUNNING 0xf 108 #define OCT_DEV_IN_RESET 0x10 109 #define OCT_DEV_STATE_INVALID 0x11 110 111 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID 112 113 /** Octeon Device interrupts 114 * These interrupt bits are set in int_status filed of 115 * octeon_device structure 116 */ 117 #define OCT_DEV_INTR_DMA0_FORCE 0x01 118 #define OCT_DEV_INTR_DMA1_FORCE 0x02 119 #define OCT_DEV_INTR_PKT_DATA 0x04 120 121 #define LIO_RESET_SECS (3) 122 123 /*---------------------------DISPATCH LIST-------------------------------*/ 124 125 /** The dispatch list entry. 126 * The driver keeps a record of functions registered for each 127 * response header opcode in this structure. Since the opcode is 128 * hashed to index into the driver's list, more than one opcode 129 * can hash to the same entry, in which case the list field points 130 * to a linked list with the other entries. 131 */ 132 struct octeon_dispatch { 133 /** List head for this entry */ 134 struct list_head list; 135 136 /** The opcode for which the dispatch function & arg should be used */ 137 u16 opcode; 138 139 /** The function to be called for a packet received by the driver */ 140 octeon_dispatch_fn_t dispatch_fn; 141 142 /* The application specified argument to be passed to the above 143 * function along with the received packet 144 */ 145 void *arg; 146 }; 147 148 /** The dispatch list structure. */ 149 struct octeon_dispatch_list { 150 /** access to dispatch list must be atomic */ 151 spinlock_t lock; 152 153 /** Count of dispatch functions currently registered */ 154 u32 count; 155 156 /** The list of dispatch functions */ 157 struct octeon_dispatch *dlist; 158 }; 159 160 /*----------------------- THE OCTEON DEVICE ---------------------------*/ 161 162 #define OCT_MEM_REGIONS 3 163 /** PCI address space mapping information. 164 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 165 * Octeon gets mapped to different physical address spaces in 166 * the kernel. 167 */ 168 struct octeon_mmio { 169 /** PCI address to which the BAR is mapped. */ 170 u64 start; 171 172 /** Length of this PCI address space. */ 173 u32 len; 174 175 /** Length that has been mapped to phys. address space. */ 176 u32 mapped_len; 177 178 /** The physical address to which the PCI address space is mapped. */ 179 u8 __iomem *hw_addr; 180 181 /** Flag indicating the mapping was successful. */ 182 u32 done; 183 }; 184 185 #define MAX_OCTEON_MAPS 32 186 187 struct octeon_io_enable { 188 u64 iq; 189 u64 oq; 190 u64 iq64B; 191 }; 192 193 struct octeon_reg_list { 194 u32 __iomem *pci_win_wr_addr_hi; 195 u32 __iomem *pci_win_wr_addr_lo; 196 u64 __iomem *pci_win_wr_addr; 197 198 u32 __iomem *pci_win_rd_addr_hi; 199 u32 __iomem *pci_win_rd_addr_lo; 200 u64 __iomem *pci_win_rd_addr; 201 202 u32 __iomem *pci_win_wr_data_hi; 203 u32 __iomem *pci_win_wr_data_lo; 204 u64 __iomem *pci_win_wr_data; 205 206 u32 __iomem *pci_win_rd_data_hi; 207 u32 __iomem *pci_win_rd_data_lo; 208 u64 __iomem *pci_win_rd_data; 209 }; 210 211 #define OCTEON_CONSOLE_MAX_READ_BYTES 512 212 typedef int (*octeon_console_print_fn)(struct octeon_device *oct, 213 u32 num, char *pre, char *suf); 214 struct octeon_console { 215 u32 active; 216 u32 waiting; 217 u64 addr; 218 u32 buffer_size; 219 u64 input_base_addr; 220 u64 output_base_addr; 221 octeon_console_print_fn print; 222 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES]; 223 }; 224 225 struct octeon_board_info { 226 char name[OCT_BOARD_NAME]; 227 char serial_number[OCT_SERIAL_LEN]; 228 u64 major; 229 u64 minor; 230 }; 231 232 struct octeon_fn_list { 233 void (*setup_iq_regs)(struct octeon_device *, u32); 234 void (*setup_oq_regs)(struct octeon_device *, u32); 235 236 irqreturn_t (*process_interrupt_regs)(void *); 237 u64 (*msix_interrupt_handler)(void *); 238 239 int (*setup_mbox)(struct octeon_device *); 240 int (*free_mbox)(struct octeon_device *); 241 242 int (*soft_reset)(struct octeon_device *); 243 int (*setup_device_regs)(struct octeon_device *); 244 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int); 245 void (*bar1_idx_write)(struct octeon_device *, u32, u32); 246 u32 (*bar1_idx_read)(struct octeon_device *, u32); 247 u32 (*update_iq_read_idx)(struct octeon_instr_queue *); 248 249 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32); 250 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32); 251 252 void (*enable_interrupt)(struct octeon_device *, u8); 253 void (*disable_interrupt)(struct octeon_device *, u8); 254 255 int (*enable_io_queues)(struct octeon_device *); 256 void (*disable_io_queues)(struct octeon_device *); 257 }; 258 259 /* Must be multiple of 8, changing breaks ABI */ 260 #define CVMX_BOOTMEM_NAME_LEN 128 261 262 /* Structure for named memory blocks 263 * Number of descriptors 264 * available can be changed without affecting compatibility, 265 * but name length changes require a bump in the bootmem 266 * descriptor version 267 * Note: This structure must be naturally 64 bit aligned, as a single 268 * memory image will be used by both 32 and 64 bit programs. 269 */ 270 struct cvmx_bootmem_named_block_desc { 271 /** Base address of named block */ 272 u64 base_addr; 273 274 /** Size actually allocated for named block */ 275 u64 size; 276 277 /** name of named block */ 278 char name[CVMX_BOOTMEM_NAME_LEN]; 279 }; 280 281 struct oct_fw_info { 282 u32 max_nic_ports; /** max nic ports for the device */ 283 u32 num_gmx_ports; /** num gmx ports */ 284 u64 app_cap_flags; /** firmware cap flags */ 285 286 /** The core application is running in this mode. 287 * See octeon-drv-opcodes.h for values. 288 */ 289 u32 app_mode; 290 char liquidio_firmware_version[32]; 291 }; 292 293 /* wrappers around work structs */ 294 struct cavium_wk { 295 struct delayed_work work; 296 void *ctxptr; 297 u64 ctxul; 298 }; 299 300 struct cavium_wq { 301 struct workqueue_struct *wq; 302 struct cavium_wk wk; 303 }; 304 305 struct octdev_props { 306 /* Each interface in the Octeon device has a network 307 * device pointer (used for OS specific calls). 308 */ 309 int rx_on; 310 int napi_enabled; 311 int gmxport; 312 struct net_device *netdev; 313 }; 314 315 #define LIO_FLAG_MSIX_ENABLED 0x1 316 #define MSIX_PO_INT 0x1 317 #define MSIX_PI_INT 0x2 318 #define MSIX_MBOX_INT 0x4 319 320 struct octeon_pf_vf_hs_word { 321 #ifdef __LITTLE_ENDIAN_BITFIELD 322 /** PKIND value assigned for the DPI interface */ 323 u64 pkind : 8; 324 325 /** OCTEON core clock multiplier */ 326 u64 core_tics_per_us : 16; 327 328 /** OCTEON coprocessor clock multiplier */ 329 u64 coproc_tics_per_us : 16; 330 331 /** app that currently running on OCTEON */ 332 u64 app_mode : 8; 333 334 /** RESERVED */ 335 u64 reserved : 16; 336 337 #else 338 339 /** RESERVED */ 340 u64 reserved : 16; 341 342 /** app that currently running on OCTEON */ 343 u64 app_mode : 8; 344 345 /** OCTEON coprocessor clock multiplier */ 346 u64 coproc_tics_per_us : 16; 347 348 /** OCTEON core clock multiplier */ 349 u64 core_tics_per_us : 16; 350 351 /** PKIND value assigned for the DPI interface */ 352 u64 pkind : 8; 353 #endif 354 }; 355 356 struct octeon_sriov_info { 357 /* Number of rings assigned to VF */ 358 u32 rings_per_vf; 359 360 /** Max Number of VF devices that can be enabled. This variable can 361 * specified during load time or it will be derived after allocating 362 * PF queues. When max_vfs is derived then each VF will get one queue 363 **/ 364 u32 max_vfs; 365 366 /** Number of VF devices enabled using sysfs. */ 367 u32 num_vfs_alloced; 368 369 /* Actual rings left for PF device */ 370 u32 num_pf_rings; 371 372 /* SRN of PF usable IO queues */ 373 u32 pf_srn; 374 375 /* total pf rings */ 376 u32 trs; 377 378 u32 sriov_enabled; 379 380 struct lio_trusted_vf trusted_vf; 381 382 /*lookup table that maps DPI ring number to VF pci_dev struct pointer*/ 383 struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS]; 384 385 u64 vf_macaddr[MAX_POSSIBLE_VFS]; 386 387 u16 vf_vlantci[MAX_POSSIBLE_VFS]; 388 389 int vf_linkstate[MAX_POSSIBLE_VFS]; 390 391 u64 vf_drv_loaded_mask; 392 }; 393 394 struct octeon_ioq_vector { 395 struct octeon_device *oct_dev; 396 int iq_index; 397 int droq_index; 398 int vector; 399 struct octeon_mbox *mbox; 400 struct cpumask affinity_mask; 401 u32 ioq_num; 402 }; 403 404 struct lio_vf_rep_list { 405 int num_vfs; 406 struct net_device *ndev[CN23XX_MAX_VFS_PER_PF]; 407 }; 408 409 struct lio_devlink_priv { 410 struct octeon_device *oct; 411 }; 412 413 /** The Octeon device. 414 * Each Octeon device has this structure to represent all its 415 * components. 416 */ 417 struct octeon_device { 418 /** Lock for PCI window configuration accesses */ 419 spinlock_t pci_win_lock; 420 421 /** Lock for memory accesses */ 422 spinlock_t mem_access_lock; 423 424 /** PCI device pointer */ 425 struct pci_dev *pci_dev; 426 427 /** Chip specific information. */ 428 void *chip; 429 430 /** Number of interfaces detected in this octeon device. */ 431 u32 ifcount; 432 433 struct octdev_props props[MAX_OCTEON_LINKS]; 434 435 /** Octeon Chip type. */ 436 u16 chip_id; 437 438 u16 rev_id; 439 440 u32 subsystem_id; 441 442 u16 pf_num; 443 444 u16 vf_num; 445 446 /** This device's id - set by the driver. */ 447 u32 octeon_id; 448 449 /** This device's PCIe port used for traffic. */ 450 u16 pcie_port; 451 452 u16 flags; 453 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1) 454 455 /** The state of this device */ 456 atomic_t status; 457 458 /** memory mapped io range */ 459 struct octeon_mmio mmio[OCT_MEM_REGIONS]; 460 461 struct octeon_reg_list reg_list; 462 463 struct octeon_fn_list fn_list; 464 465 struct octeon_board_info boardinfo; 466 467 u32 num_iqs; 468 469 /* The pool containing pre allocated buffers used for soft commands */ 470 struct octeon_sc_buffer_pool sc_buf_pool; 471 472 /** The input instruction queues */ 473 struct octeon_instr_queue *instr_queue 474 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 475 476 /** The doubly-linked list of instruction response */ 477 struct octeon_response_list response_list[MAX_RESPONSE_LISTS]; 478 479 u32 num_oqs; 480 481 /** The DROQ output queues */ 482 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES]; 483 484 struct octeon_io_enable io_qmask; 485 486 /** List of dispatch functions */ 487 struct octeon_dispatch_list dispatch; 488 489 u32 int_status; 490 491 u64 droq_intr; 492 493 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */ 494 u64 bootmem_desc_addr; 495 496 /** Placeholder memory for named blocks. 497 * Assumes single-threaded access 498 */ 499 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; 500 501 /** Address of consoles descriptor */ 502 u64 console_desc_addr; 503 504 /** Number of consoles available. 0 means they are inaccessible */ 505 u32 num_consoles; 506 507 /* Console caches */ 508 struct octeon_console console[MAX_OCTEON_MAPS]; 509 510 /* Console named block info */ 511 struct { 512 u64 dram_region_base; 513 int bar1_index; 514 } console_nb_info; 515 516 /* Coprocessor clock rate. */ 517 u64 coproc_clock_rate; 518 519 /** The core application is running in this mode. See liquidio_common.h 520 * for values. 521 */ 522 u32 app_mode; 523 524 struct oct_fw_info fw_info; 525 526 /** The name given to this device. */ 527 char device_name[32]; 528 529 /** Application Context */ 530 void *app_ctx; 531 532 struct cavium_wq dma_comp_wq; 533 534 /** Lock for dma response list */ 535 spinlock_t cmd_resp_wqlock; 536 u32 cmd_resp_state; 537 538 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 539 540 struct cavium_wk nic_poll_work; 541 542 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS]; 543 544 void *priv; 545 546 int num_msix_irqs; 547 548 void *msix_entries; 549 550 /* when requesting IRQs, the names are stored here */ 551 void *irq_name_storage; 552 553 struct octeon_sriov_info sriov_info; 554 555 struct octeon_pf_vf_hs_word pfvf_hsword; 556 557 int msix_on; 558 559 /** Mail Box details of each octeon queue. */ 560 struct octeon_mbox *mbox[MAX_POSSIBLE_VFS]; 561 562 /** IOq information of it's corresponding MSI-X interrupt. */ 563 struct octeon_ioq_vector *ioq_vector; 564 565 int rx_pause; 566 int tx_pause; 567 568 struct oct_link_stats link_stats; /*stastics from firmware*/ 569 570 /* private flags to control driver-specific features through ethtool */ 571 u32 priv_flags; 572 573 void *watchdog_task; 574 575 u32 rx_coalesce_usecs; 576 u32 rx_max_coalesced_frames; 577 u32 tx_max_coalesced_frames; 578 579 bool cores_crashed; 580 581 struct { 582 int bus; 583 int dev; 584 int func; 585 } loc; 586 587 atomic_t *adapter_refcount; /* reference count of adapter */ 588 589 atomic_t *adapter_fw_state; /* per-adapter, lio_fw_state */ 590 591 bool ptp_enable; 592 593 struct lio_vf_rep_list vf_rep_list; 594 struct devlink *devlink; 595 enum devlink_eswitch_mode eswitch_mode; 596 597 /* for 25G NIC speed change */ 598 u8 speed_boot; 599 u8 speed_setting; 600 u8 no_speed_setting; 601 }; 602 603 #define OCT_DRV_ONLINE 1 604 #define OCT_DRV_OFFLINE 2 605 #define OCTEON_CN6XXX(oct) ({ \ 606 typeof(oct) _oct = (oct); \ 607 ((_oct->chip_id == OCTEON_CN66XX) || \ 608 (_oct->chip_id == OCTEON_CN68XX)); }) 609 #define OCTEON_CN23XX_PF(oct) ((oct)->chip_id == OCTEON_CN23XX_PF_VID) 610 #define OCTEON_CN23XX_VF(oct) ((oct)->chip_id == OCTEON_CN23XX_VF_VID) 611 #define CHIP_CONF(oct, TYPE) \ 612 (((struct octeon_ ## TYPE *)((oct)->chip))->conf) 613 614 #define MAX_IO_PENDING_PKT_COUNT 100 615 616 /*------------------ Function Prototypes ----------------------*/ 617 618 /** Initialize device list memory */ 619 void octeon_init_device_list(int conf_type); 620 621 /** Free memory for Input and Output queue structures for a octeon device */ 622 void octeon_free_device_mem(struct octeon_device *oct); 623 624 /* Look up a free entry in the octeon_device table and allocate resources 625 * for the octeon_device structure for an octeon device. Called at init 626 * time. 627 */ 628 struct octeon_device *octeon_allocate_device(u32 pci_id, 629 u32 priv_size); 630 631 /** Register a device's bus location at initialization time. 632 * @param octeon_dev - pointer to the octeon device structure. 633 * @param bus - PCIe bus # 634 * @param dev - PCIe device # 635 * @param func - PCIe function # 636 * @param is_pf - TRUE for PF, FALSE for VF 637 * @return reference count of device's adapter 638 */ 639 int octeon_register_device(struct octeon_device *oct, 640 int bus, int dev, int func, int is_pf); 641 642 /** Deregister a device at de-initialization time. 643 * @param octeon_dev - pointer to the octeon device structure. 644 * @return reference count of device's adapter 645 */ 646 int octeon_deregister_device(struct octeon_device *oct); 647 648 /** Initialize the driver's dispatch list which is a mix of a hash table 649 * and a linked list. This is done at driver load time. 650 * @param octeon_dev - pointer to the octeon device structure. 651 * @return 0 on success, else -ve error value 652 */ 653 int octeon_init_dispatch_list(struct octeon_device *octeon_dev); 654 655 /** Delete the driver's dispatch list and all registered entries. 656 * This is done at driver unload time. 657 * @param octeon_dev - pointer to the octeon device structure. 658 */ 659 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); 660 661 /** Initialize the core device fields with the info returned by the FW. 662 * @param recv_info - Receive info structure 663 * @param buf - Receive buffer 664 */ 665 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); 666 667 /** Gets the dispatch function registered to receive packets with a 668 * given opcode/subcode. 669 * @param octeon_dev - the octeon device pointer. 670 * @param opcode - the opcode for which the dispatch function 671 * is to checked. 672 * @param subcode - the subcode for which the dispatch function 673 * is to checked. 674 * 675 * @return Success: octeon_dispatch_fn_t (dispatch function pointer) 676 * @return Failure: NULL 677 * 678 * Looks up the dispatch list to get the dispatch function for a 679 * given opcode. 680 */ 681 octeon_dispatch_fn_t 682 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 683 u16 subcode); 684 685 /** Get the octeon device pointer. 686 * @param octeon_id - The id for which the octeon device pointer is required. 687 * @return Success: Octeon device pointer. 688 * @return Failure: NULL. 689 */ 690 struct octeon_device *lio_get_device(u32 octeon_id); 691 692 /** Get the octeon id assigned to the octeon device passed as argument. 693 * This function is exported to other modules. 694 * @param dev - octeon device pointer passed as a void *. 695 * @return octeon device id 696 */ 697 int lio_get_device_id(void *dev); 698 699 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct) 700 { 701 u16 rev = (oct->rev_id & 0xC) >> 2; 702 703 return (rev == 0) ? 1 : rev; 704 } 705 706 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct) 707 { 708 return oct->rev_id & 0x3; 709 } 710 711 /** Read windowed register. 712 * @param oct - pointer to the Octeon device. 713 * @param addr - Address of the register to read. 714 * 715 * This routine is called to read from the indirectly accessed 716 * Octeon registers that are visible through a PCI BAR0 mapped window 717 * register. 718 * @return - 64 bit value read from the register. 719 */ 720 721 u64 lio_pci_readq(struct octeon_device *oct, u64 addr); 722 723 /** Write windowed register. 724 * @param oct - pointer to the Octeon device. 725 * @param val - Value to write 726 * @param addr - Address of the register to write 727 * 728 * This routine is called to write to the indirectly accessed 729 * Octeon registers that are visible through a PCI BAR0 mapped window 730 * register. 731 * @return Nothing. 732 */ 733 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); 734 735 /* Routines for reading and writing CSRs */ 736 #define octeon_write_csr(oct_dev, reg_off, value) \ 737 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) 738 739 #define octeon_write_csr64(oct_dev, reg_off, val64) \ 740 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) 741 742 #define octeon_read_csr(oct_dev, reg_off) \ 743 readl((oct_dev)->mmio[0].hw_addr + (reg_off)) 744 745 #define octeon_read_csr64(oct_dev, reg_off) \ 746 readq((oct_dev)->mmio[0].hw_addr + (reg_off)) 747 748 /** 749 * Checks if memory access is okay 750 * 751 * @param oct which octeon to send to 752 * @return Zero on success, negative on failure. 753 */ 754 int octeon_mem_access_ok(struct octeon_device *oct); 755 756 /** 757 * Waits for DDR initialization. 758 * 759 * @param oct which octeon to send to 760 * @param timeout_in_ms pointer to how long to wait until DDR is initialized 761 * in ms. 762 * If contents are 0, it waits until contents are non-zero 763 * before starting to check. 764 * @return Zero on success, negative on failure. 765 */ 766 int octeon_wait_for_ddr_init(struct octeon_device *oct, 767 u32 *timeout_in_ms); 768 769 /** 770 * Wait for u-boot to boot and be waiting for a command. 771 * 772 * @param wait_time_hundredths 773 * Maximum time to wait 774 * 775 * @return Zero on success, negative on failure. 776 */ 777 int octeon_wait_for_bootloader(struct octeon_device *oct, 778 u32 wait_time_hundredths); 779 780 /** 781 * Initialize console access 782 * 783 * @param oct which octeon initialize 784 * @return Zero on success, negative on failure. 785 */ 786 int octeon_init_consoles(struct octeon_device *oct); 787 788 /** 789 * Adds access to a console to the device. 790 * 791 * @param oct: which octeon to add to 792 * @param console_num: which console 793 * @param dbg_enb: ptr to debug enablement string, one of: 794 * * NULL for no debug output (i.e. disabled) 795 * * empty string enables debug output (via default method) 796 * * specific string to enable debug console output 797 * 798 * @return Zero on success, negative on failure. 799 */ 800 int octeon_add_console(struct octeon_device *oct, u32 console_num, 801 char *dbg_enb); 802 803 /** write or read from a console */ 804 int octeon_console_write(struct octeon_device *oct, u32 console_num, 805 char *buffer, u32 write_request_size, u32 flags); 806 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); 807 808 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); 809 810 /** Removes all attached consoles. */ 811 void octeon_remove_consoles(struct octeon_device *oct); 812 813 /** 814 * Send a string to u-boot on console 0 as a command. 815 * 816 * @param oct which octeon to send to 817 * @param cmd_str String to send 818 * @param wait_hundredths Time to wait for u-boot to accept the command. 819 * 820 * @return Zero on success, negative on failure. 821 */ 822 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 823 u32 wait_hundredths); 824 825 /** Parses, validates, and downloads firmware, then boots associated cores. 826 * @param oct which octeon to download firmware to 827 * @param data - The complete firmware file image 828 * @param size - The size of the data 829 * 830 * @return 0 if success. 831 * -EINVAL if file is incompatible or badly formatted. 832 * -ENODEV if no handler was found for the application type or an 833 * invalid octeon id was passed. 834 */ 835 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 836 size_t size); 837 838 char *lio_get_state_string(atomic_t *state_ptr); 839 840 /** Sets up instruction queues for the device 841 * @param oct which octeon to setup 842 * 843 * @return 0 if success. 1 if fails 844 */ 845 int octeon_setup_instr_queues(struct octeon_device *oct); 846 847 /** Sets up output queues for the device 848 * @param oct which octeon to setup 849 * 850 * @return 0 if success. 1 if fails 851 */ 852 int octeon_setup_output_queues(struct octeon_device *oct); 853 854 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); 855 856 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); 857 858 /** Turns off the input and output queues for the device 859 * @param oct which octeon to disable 860 */ 861 int octeon_set_io_queues_off(struct octeon_device *oct); 862 863 /** Turns on or off the given output queue for the device 864 * @param oct which octeon to change 865 * @param q_no which queue 866 * @param enable 1 to enable, 0 to disable 867 */ 868 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); 869 870 /** Retrieve the config for the device 871 * @param oct which octeon 872 * @param card_type type of card 873 * 874 * @returns pointer to configuration 875 */ 876 void *oct_get_config_info(struct octeon_device *oct, u16 card_type); 877 878 /** Gets the octeon device configuration 879 * @return - pointer to the octeon configuration struture 880 */ 881 struct octeon_config *octeon_get_conf(struct octeon_device *oct); 882 883 void octeon_free_ioq_vector(struct octeon_device *oct); 884 int octeon_allocate_ioq_vector(struct octeon_device *oct, u32 num_ioqs); 885 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq); 886 887 /* LiquidIO driver pivate flags */ 888 enum { 889 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */ 890 }; 891 892 #define OCT_PRIV_FLAG_DEFAULT 0x0 893 894 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag) 895 { 896 return !!(octdev->priv_flags & (0x1 << flag)); 897 } 898 899 static inline void lio_set_priv_flag(struct octeon_device *octdev, 900 u32 flag, u32 val) 901 { 902 if (val) 903 octdev->priv_flags |= (0x1 << flag); 904 else 905 octdev->priv_flags &= ~(0x1 << flag); 906 } 907 #endif 908