1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_device.h 19 * \brief Host Driver: This file defines the octeon device structure. 20 */ 21 22 #ifndef _OCTEON_DEVICE_H_ 23 #define _OCTEON_DEVICE_H_ 24 25 #include <linux/interrupt.h> 26 27 /** PCI VendorId Device Id */ 28 #define OCTEON_CN68XX_PCIID 0x91177d 29 #define OCTEON_CN66XX_PCIID 0x92177d 30 #define OCTEON_CN23XX_PCIID_PF 0x9702177d 31 /** Driver identifies chips by these Ids, created by clubbing together 32 * DeviceId+RevisionId; Where Revision Id is not used to distinguish 33 * between chips, a value of 0 is used for revision id. 34 */ 35 #define OCTEON_CN68XX 0x0091 36 #define OCTEON_CN66XX 0x0092 37 #define OCTEON_CN23XX_PF_VID 0x9702 38 #define OCTEON_CN23XX_VF_VID 0x9712 39 40 /**RevisionId for the chips */ 41 #define OCTEON_CN23XX_REV_1_0 0x00 42 #define OCTEON_CN23XX_REV_1_1 0x01 43 #define OCTEON_CN23XX_REV_2_0 0x80 44 45 /** Endian-swap modes supported by Octeon. */ 46 enum octeon_pci_swap_mode { 47 OCTEON_PCI_PASSTHROUGH = 0, 48 OCTEON_PCI_64BIT_SWAP = 1, 49 OCTEON_PCI_32BIT_BYTE_SWAP = 2, 50 OCTEON_PCI_32BIT_LW_SWAP = 3 51 }; 52 53 enum lio_fw_state { 54 FW_IS_PRELOADED = 0, 55 FW_NEEDS_TO_BE_LOADED = 1, 56 FW_IS_BEING_LOADED = 2, 57 FW_HAS_BEEN_LOADED = 3, 58 }; 59 60 enum { 61 OCTEON_CONFIG_TYPE_DEFAULT = 0, 62 NUM_OCTEON_CONFS, 63 }; 64 65 #define OCTEON_INPUT_INTR (1) 66 #define OCTEON_OUTPUT_INTR (2) 67 #define OCTEON_MBOX_INTR (4) 68 #define OCTEON_ALL_INTR 0xff 69 70 /*--------------- PCI BAR1 index registers -------------*/ 71 72 /* BAR1 Mask */ 73 #define PCI_BAR1_ENABLE_CA 1 74 #define PCI_BAR1_ENDIAN_MODE OCTEON_PCI_64BIT_SWAP 75 #define PCI_BAR1_ENTRY_VALID 1 76 #define PCI_BAR1_MASK ((PCI_BAR1_ENABLE_CA << 3) \ 77 | (PCI_BAR1_ENDIAN_MODE << 1) \ 78 | PCI_BAR1_ENTRY_VALID) 79 80 /** Octeon Device state. 81 * Each octeon device goes through each of these states 82 * as it is initialized. 83 */ 84 #define OCT_DEV_BEGIN_STATE 0x0 85 #define OCT_DEV_PCI_ENABLE_DONE 0x1 86 #define OCT_DEV_PCI_MAP_DONE 0x2 87 #define OCT_DEV_DISPATCH_INIT_DONE 0x3 88 #define OCT_DEV_INSTR_QUEUE_INIT_DONE 0x4 89 #define OCT_DEV_SC_BUFF_POOL_INIT_DONE 0x5 90 #define OCT_DEV_RESP_LIST_INIT_DONE 0x6 91 #define OCT_DEV_DROQ_INIT_DONE 0x7 92 #define OCT_DEV_MBOX_SETUP_DONE 0x8 93 #define OCT_DEV_MSIX_ALLOC_VECTOR_DONE 0x9 94 #define OCT_DEV_INTR_SET_DONE 0xa 95 #define OCT_DEV_IO_QUEUES_DONE 0xb 96 #define OCT_DEV_CONSOLE_INIT_DONE 0xc 97 #define OCT_DEV_HOST_OK 0xd 98 #define OCT_DEV_CORE_OK 0xe 99 #define OCT_DEV_RUNNING 0xf 100 #define OCT_DEV_IN_RESET 0x10 101 #define OCT_DEV_STATE_INVALID 0x11 102 103 #define OCT_DEV_STATES OCT_DEV_STATE_INVALID 104 105 /** Octeon Device interrupts 106 * These interrupt bits are set in int_status filed of 107 * octeon_device structure 108 */ 109 #define OCT_DEV_INTR_DMA0_FORCE 0x01 110 #define OCT_DEV_INTR_DMA1_FORCE 0x02 111 #define OCT_DEV_INTR_PKT_DATA 0x04 112 113 #define LIO_RESET_SECS (3) 114 115 /*---------------------------DISPATCH LIST-------------------------------*/ 116 117 /** The dispatch list entry. 118 * The driver keeps a record of functions registered for each 119 * response header opcode in this structure. Since the opcode is 120 * hashed to index into the driver's list, more than one opcode 121 * can hash to the same entry, in which case the list field points 122 * to a linked list with the other entries. 123 */ 124 struct octeon_dispatch { 125 /** List head for this entry */ 126 struct list_head list; 127 128 /** The opcode for which the dispatch function & arg should be used */ 129 u16 opcode; 130 131 /** The function to be called for a packet received by the driver */ 132 octeon_dispatch_fn_t dispatch_fn; 133 134 /* The application specified argument to be passed to the above 135 * function along with the received packet 136 */ 137 void *arg; 138 }; 139 140 /** The dispatch list structure. */ 141 struct octeon_dispatch_list { 142 /** access to dispatch list must be atomic */ 143 spinlock_t lock; 144 145 /** Count of dispatch functions currently registered */ 146 u32 count; 147 148 /** The list of dispatch functions */ 149 struct octeon_dispatch *dlist; 150 }; 151 152 /*----------------------- THE OCTEON DEVICE ---------------------------*/ 153 154 #define OCT_MEM_REGIONS 3 155 /** PCI address space mapping information. 156 * Each of the 3 address spaces given by BAR0, BAR2 and BAR4 of 157 * Octeon gets mapped to different physical address spaces in 158 * the kernel. 159 */ 160 struct octeon_mmio { 161 /** PCI address to which the BAR is mapped. */ 162 u64 start; 163 164 /** Length of this PCI address space. */ 165 u32 len; 166 167 /** Length that has been mapped to phys. address space. */ 168 u32 mapped_len; 169 170 /** The physical address to which the PCI address space is mapped. */ 171 u8 __iomem *hw_addr; 172 173 /** Flag indicating the mapping was successful. */ 174 u32 done; 175 }; 176 177 #define MAX_OCTEON_MAPS 32 178 179 struct octeon_io_enable { 180 u64 iq; 181 u64 oq; 182 u64 iq64B; 183 }; 184 185 struct octeon_reg_list { 186 u32 __iomem *pci_win_wr_addr_hi; 187 u32 __iomem *pci_win_wr_addr_lo; 188 u64 __iomem *pci_win_wr_addr; 189 190 u32 __iomem *pci_win_rd_addr_hi; 191 u32 __iomem *pci_win_rd_addr_lo; 192 u64 __iomem *pci_win_rd_addr; 193 194 u32 __iomem *pci_win_wr_data_hi; 195 u32 __iomem *pci_win_wr_data_lo; 196 u64 __iomem *pci_win_wr_data; 197 198 u32 __iomem *pci_win_rd_data_hi; 199 u32 __iomem *pci_win_rd_data_lo; 200 u64 __iomem *pci_win_rd_data; 201 }; 202 203 #define OCTEON_CONSOLE_MAX_READ_BYTES 512 204 typedef int (*octeon_console_print_fn)(struct octeon_device *oct, 205 u32 num, char *pre, char *suf); 206 struct octeon_console { 207 u32 active; 208 u32 waiting; 209 u64 addr; 210 u32 buffer_size; 211 u64 input_base_addr; 212 u64 output_base_addr; 213 octeon_console_print_fn print; 214 char leftover[OCTEON_CONSOLE_MAX_READ_BYTES]; 215 }; 216 217 struct octeon_board_info { 218 char name[OCT_BOARD_NAME]; 219 char serial_number[OCT_SERIAL_LEN]; 220 u64 major; 221 u64 minor; 222 }; 223 224 struct octeon_fn_list { 225 void (*setup_iq_regs)(struct octeon_device *, u32); 226 void (*setup_oq_regs)(struct octeon_device *, u32); 227 228 irqreturn_t (*process_interrupt_regs)(void *); 229 u64 (*msix_interrupt_handler)(void *); 230 231 int (*setup_mbox)(struct octeon_device *); 232 int (*free_mbox)(struct octeon_device *); 233 234 int (*soft_reset)(struct octeon_device *); 235 int (*setup_device_regs)(struct octeon_device *); 236 void (*bar1_idx_setup)(struct octeon_device *, u64, u32, int); 237 void (*bar1_idx_write)(struct octeon_device *, u32, u32); 238 u32 (*bar1_idx_read)(struct octeon_device *, u32); 239 u32 (*update_iq_read_idx)(struct octeon_instr_queue *); 240 241 void (*enable_oq_pkt_time_intr)(struct octeon_device *, u32); 242 void (*disable_oq_pkt_time_intr)(struct octeon_device *, u32); 243 244 void (*enable_interrupt)(struct octeon_device *, u8); 245 void (*disable_interrupt)(struct octeon_device *, u8); 246 247 int (*enable_io_queues)(struct octeon_device *); 248 void (*disable_io_queues)(struct octeon_device *); 249 }; 250 251 /* Must be multiple of 8, changing breaks ABI */ 252 #define CVMX_BOOTMEM_NAME_LEN 128 253 254 /* Structure for named memory blocks 255 * Number of descriptors 256 * available can be changed without affecting compatibility, 257 * but name length changes require a bump in the bootmem 258 * descriptor version 259 * Note: This structure must be naturally 64 bit aligned, as a single 260 * memory image will be used by both 32 and 64 bit programs. 261 */ 262 struct cvmx_bootmem_named_block_desc { 263 /** Base address of named block */ 264 u64 base_addr; 265 266 /** Size actually allocated for named block */ 267 u64 size; 268 269 /** name of named block */ 270 char name[CVMX_BOOTMEM_NAME_LEN]; 271 }; 272 273 struct oct_fw_info { 274 u32 max_nic_ports; /** max nic ports for the device */ 275 u32 num_gmx_ports; /** num gmx ports */ 276 u64 app_cap_flags; /** firmware cap flags */ 277 278 /** The core application is running in this mode. 279 * See octeon-drv-opcodes.h for values. 280 */ 281 u32 app_mode; 282 char liquidio_firmware_version[32]; 283 }; 284 285 /* wrappers around work structs */ 286 struct cavium_wk { 287 struct delayed_work work; 288 void *ctxptr; 289 u64 ctxul; 290 }; 291 292 struct cavium_wq { 293 struct workqueue_struct *wq; 294 struct cavium_wk wk; 295 }; 296 297 struct octdev_props { 298 /* Each interface in the Octeon device has a network 299 * device pointer (used for OS specific calls). 300 */ 301 int rx_on; 302 int napi_enabled; 303 int gmxport; 304 struct net_device *netdev; 305 }; 306 307 #define LIO_FLAG_MSIX_ENABLED 0x1 308 #define MSIX_PO_INT 0x1 309 #define MSIX_PI_INT 0x2 310 #define MSIX_MBOX_INT 0x4 311 312 struct octeon_pf_vf_hs_word { 313 #ifdef __LITTLE_ENDIAN_BITFIELD 314 /** PKIND value assigned for the DPI interface */ 315 u64 pkind : 8; 316 317 /** OCTEON core clock multiplier */ 318 u64 core_tics_per_us : 16; 319 320 /** OCTEON coprocessor clock multiplier */ 321 u64 coproc_tics_per_us : 16; 322 323 /** app that currently running on OCTEON */ 324 u64 app_mode : 8; 325 326 /** RESERVED */ 327 u64 reserved : 16; 328 329 #else 330 331 /** RESERVED */ 332 u64 reserved : 16; 333 334 /** app that currently running on OCTEON */ 335 u64 app_mode : 8; 336 337 /** OCTEON coprocessor clock multiplier */ 338 u64 coproc_tics_per_us : 16; 339 340 /** OCTEON core clock multiplier */ 341 u64 core_tics_per_us : 16; 342 343 /** PKIND value assigned for the DPI interface */ 344 u64 pkind : 8; 345 #endif 346 }; 347 348 struct octeon_sriov_info { 349 /* Number of rings assigned to VF */ 350 u32 rings_per_vf; 351 352 /** Max Number of VF devices that can be enabled. This variable can 353 * specified during load time or it will be derived after allocating 354 * PF queues. When max_vfs is derived then each VF will get one queue 355 **/ 356 u32 max_vfs; 357 358 /** Number of VF devices enabled using sysfs. */ 359 u32 num_vfs_alloced; 360 361 /* Actual rings left for PF device */ 362 u32 num_pf_rings; 363 364 /* SRN of PF usable IO queues */ 365 u32 pf_srn; 366 367 /* total pf rings */ 368 u32 trs; 369 370 u32 sriov_enabled; 371 372 /*lookup table that maps DPI ring number to VF pci_dev struct pointer*/ 373 struct pci_dev *dpiring_to_vfpcidev_lut[MAX_POSSIBLE_VFS]; 374 375 u64 vf_macaddr[MAX_POSSIBLE_VFS]; 376 377 u16 vf_vlantci[MAX_POSSIBLE_VFS]; 378 379 int vf_linkstate[MAX_POSSIBLE_VFS]; 380 381 u64 vf_drv_loaded_mask; 382 }; 383 384 struct octeon_ioq_vector { 385 struct octeon_device *oct_dev; 386 int iq_index; 387 int droq_index; 388 int vector; 389 struct octeon_mbox *mbox; 390 struct cpumask affinity_mask; 391 u32 ioq_num; 392 }; 393 394 /** The Octeon device. 395 * Each Octeon device has this structure to represent all its 396 * components. 397 */ 398 struct octeon_device { 399 /** Lock for PCI window configuration accesses */ 400 spinlock_t pci_win_lock; 401 402 /** Lock for memory accesses */ 403 spinlock_t mem_access_lock; 404 405 /** PCI device pointer */ 406 struct pci_dev *pci_dev; 407 408 /** Chip specific information. */ 409 void *chip; 410 411 /** Number of interfaces detected in this octeon device. */ 412 u32 ifcount; 413 414 struct octdev_props props[MAX_OCTEON_LINKS]; 415 416 /** Octeon Chip type. */ 417 u16 chip_id; 418 419 u16 rev_id; 420 421 u16 pf_num; 422 423 u16 vf_num; 424 425 /** This device's id - set by the driver. */ 426 u32 octeon_id; 427 428 /** This device's PCIe port used for traffic. */ 429 u16 pcie_port; 430 431 u16 flags; 432 #define LIO_FLAG_MSI_ENABLED (u32)(1 << 1) 433 434 /** The state of this device */ 435 atomic_t status; 436 437 /** memory mapped io range */ 438 struct octeon_mmio mmio[OCT_MEM_REGIONS]; 439 440 struct octeon_reg_list reg_list; 441 442 struct octeon_fn_list fn_list; 443 444 struct octeon_board_info boardinfo; 445 446 u32 num_iqs; 447 448 /* The pool containing pre allocated buffers used for soft commands */ 449 struct octeon_sc_buffer_pool sc_buf_pool; 450 451 /** The input instruction queues */ 452 struct octeon_instr_queue *instr_queue 453 [MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 454 455 /** The doubly-linked list of instruction response */ 456 struct octeon_response_list response_list[MAX_RESPONSE_LISTS]; 457 458 u32 num_oqs; 459 460 /** The DROQ output queues */ 461 struct octeon_droq *droq[MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES]; 462 463 struct octeon_io_enable io_qmask; 464 465 /** List of dispatch functions */ 466 struct octeon_dispatch_list dispatch; 467 468 u32 int_status; 469 470 u64 droq_intr; 471 472 /** Physical location of the cvmx_bootmem_desc_t in octeon memory */ 473 u64 bootmem_desc_addr; 474 475 /** Placeholder memory for named blocks. 476 * Assumes single-threaded access 477 */ 478 struct cvmx_bootmem_named_block_desc bootmem_named_block_desc; 479 480 /** Address of consoles descriptor */ 481 u64 console_desc_addr; 482 483 /** Number of consoles available. 0 means they are inaccessible */ 484 u32 num_consoles; 485 486 /* Console caches */ 487 struct octeon_console console[MAX_OCTEON_MAPS]; 488 489 /* Console named block info */ 490 struct { 491 u64 dram_region_base; 492 int bar1_index; 493 } console_nb_info; 494 495 /* Coprocessor clock rate. */ 496 u64 coproc_clock_rate; 497 498 /** The core application is running in this mode. See liquidio_common.h 499 * for values. 500 */ 501 u32 app_mode; 502 503 struct oct_fw_info fw_info; 504 505 /** The name given to this device. */ 506 char device_name[32]; 507 508 /** Application Context */ 509 void *app_ctx; 510 511 struct cavium_wq dma_comp_wq; 512 513 /** Lock for dma response list */ 514 spinlock_t cmd_resp_wqlock; 515 u32 cmd_resp_state; 516 517 struct cavium_wq check_db_wq[MAX_POSSIBLE_OCTEON_INSTR_QUEUES]; 518 519 struct cavium_wk nic_poll_work; 520 521 struct cavium_wk console_poll_work[MAX_OCTEON_MAPS]; 522 523 void *priv; 524 525 int num_msix_irqs; 526 527 void *msix_entries; 528 529 /* when requesting IRQs, the names are stored here */ 530 void *irq_name_storage; 531 532 struct octeon_sriov_info sriov_info; 533 534 struct octeon_pf_vf_hs_word pfvf_hsword; 535 536 int msix_on; 537 538 /** Mail Box details of each octeon queue. */ 539 struct octeon_mbox *mbox[MAX_POSSIBLE_VFS]; 540 541 /** IOq information of it's corresponding MSI-X interrupt. */ 542 struct octeon_ioq_vector *ioq_vector; 543 544 int rx_pause; 545 int tx_pause; 546 547 struct oct_link_stats link_stats; /*stastics from firmware*/ 548 549 /* private flags to control driver-specific features through ethtool */ 550 u32 priv_flags; 551 552 void *watchdog_task; 553 554 u32 rx_coalesce_usecs; 555 u32 rx_max_coalesced_frames; 556 u32 tx_max_coalesced_frames; 557 558 bool cores_crashed; 559 560 struct { 561 int bus; 562 int dev; 563 int func; 564 } loc; 565 566 atomic_t *adapter_refcount; /* reference count of adapter */ 567 568 atomic_t *adapter_fw_state; /* per-adapter, lio_fw_state */ 569 570 bool ptp_enable; 571 }; 572 573 #define OCT_DRV_ONLINE 1 574 #define OCT_DRV_OFFLINE 2 575 #define OCTEON_CN6XXX(oct) ({ \ 576 typeof(oct) _oct = (oct); \ 577 ((_oct->chip_id == OCTEON_CN66XX) || \ 578 (_oct->chip_id == OCTEON_CN68XX)); }) 579 #define OCTEON_CN23XX_PF(oct) ((oct)->chip_id == OCTEON_CN23XX_PF_VID) 580 #define OCTEON_CN23XX_VF(oct) ((oct)->chip_id == OCTEON_CN23XX_VF_VID) 581 #define CHIP_CONF(oct, TYPE) \ 582 (((struct octeon_ ## TYPE *)((oct)->chip))->conf) 583 584 #define MAX_IO_PENDING_PKT_COUNT 100 585 586 /*------------------ Function Prototypes ----------------------*/ 587 588 /** Initialize device list memory */ 589 void octeon_init_device_list(int conf_type); 590 591 /** Free memory for Input and Output queue structures for a octeon device */ 592 void octeon_free_device_mem(struct octeon_device *oct); 593 594 /* Look up a free entry in the octeon_device table and allocate resources 595 * for the octeon_device structure for an octeon device. Called at init 596 * time. 597 */ 598 struct octeon_device *octeon_allocate_device(u32 pci_id, 599 u32 priv_size); 600 601 /** Register a device's bus location at initialization time. 602 * @param octeon_dev - pointer to the octeon device structure. 603 * @param bus - PCIe bus # 604 * @param dev - PCIe device # 605 * @param func - PCIe function # 606 * @param is_pf - TRUE for PF, FALSE for VF 607 * @return reference count of device's adapter 608 */ 609 int octeon_register_device(struct octeon_device *oct, 610 int bus, int dev, int func, int is_pf); 611 612 /** Deregister a device at de-initialization time. 613 * @param octeon_dev - pointer to the octeon device structure. 614 * @return reference count of device's adapter 615 */ 616 int octeon_deregister_device(struct octeon_device *oct); 617 618 /** Initialize the driver's dispatch list which is a mix of a hash table 619 * and a linked list. This is done at driver load time. 620 * @param octeon_dev - pointer to the octeon device structure. 621 * @return 0 on success, else -ve error value 622 */ 623 int octeon_init_dispatch_list(struct octeon_device *octeon_dev); 624 625 /** Delete the driver's dispatch list and all registered entries. 626 * This is done at driver unload time. 627 * @param octeon_dev - pointer to the octeon device structure. 628 */ 629 void octeon_delete_dispatch_list(struct octeon_device *octeon_dev); 630 631 /** Initialize the core device fields with the info returned by the FW. 632 * @param recv_info - Receive info structure 633 * @param buf - Receive buffer 634 */ 635 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf); 636 637 /** Gets the dispatch function registered to receive packets with a 638 * given opcode/subcode. 639 * @param octeon_dev - the octeon device pointer. 640 * @param opcode - the opcode for which the dispatch function 641 * is to checked. 642 * @param subcode - the subcode for which the dispatch function 643 * is to checked. 644 * 645 * @return Success: octeon_dispatch_fn_t (dispatch function pointer) 646 * @return Failure: NULL 647 * 648 * Looks up the dispatch list to get the dispatch function for a 649 * given opcode. 650 */ 651 octeon_dispatch_fn_t 652 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 653 u16 subcode); 654 655 /** Get the octeon device pointer. 656 * @param octeon_id - The id for which the octeon device pointer is required. 657 * @return Success: Octeon device pointer. 658 * @return Failure: NULL. 659 */ 660 struct octeon_device *lio_get_device(u32 octeon_id); 661 662 /** Get the octeon id assigned to the octeon device passed as argument. 663 * This function is exported to other modules. 664 * @param dev - octeon device pointer passed as a void *. 665 * @return octeon device id 666 */ 667 int lio_get_device_id(void *dev); 668 669 static inline u16 OCTEON_MAJOR_REV(struct octeon_device *oct) 670 { 671 u16 rev = (oct->rev_id & 0xC) >> 2; 672 673 return (rev == 0) ? 1 : rev; 674 } 675 676 static inline u16 OCTEON_MINOR_REV(struct octeon_device *oct) 677 { 678 return oct->rev_id & 0x3; 679 } 680 681 /** Read windowed register. 682 * @param oct - pointer to the Octeon device. 683 * @param addr - Address of the register to read. 684 * 685 * This routine is called to read from the indirectly accessed 686 * Octeon registers that are visible through a PCI BAR0 mapped window 687 * register. 688 * @return - 64 bit value read from the register. 689 */ 690 691 u64 lio_pci_readq(struct octeon_device *oct, u64 addr); 692 693 /** Write windowed register. 694 * @param oct - pointer to the Octeon device. 695 * @param val - Value to write 696 * @param addr - Address of the register to write 697 * 698 * This routine is called to write to the indirectly accessed 699 * Octeon registers that are visible through a PCI BAR0 mapped window 700 * register. 701 * @return Nothing. 702 */ 703 void lio_pci_writeq(struct octeon_device *oct, u64 val, u64 addr); 704 705 /* Routines for reading and writing CSRs */ 706 #define octeon_write_csr(oct_dev, reg_off, value) \ 707 writel(value, (oct_dev)->mmio[0].hw_addr + (reg_off)) 708 709 #define octeon_write_csr64(oct_dev, reg_off, val64) \ 710 writeq(val64, (oct_dev)->mmio[0].hw_addr + (reg_off)) 711 712 #define octeon_read_csr(oct_dev, reg_off) \ 713 readl((oct_dev)->mmio[0].hw_addr + (reg_off)) 714 715 #define octeon_read_csr64(oct_dev, reg_off) \ 716 readq((oct_dev)->mmio[0].hw_addr + (reg_off)) 717 718 /** 719 * Checks if memory access is okay 720 * 721 * @param oct which octeon to send to 722 * @return Zero on success, negative on failure. 723 */ 724 int octeon_mem_access_ok(struct octeon_device *oct); 725 726 /** 727 * Waits for DDR initialization. 728 * 729 * @param oct which octeon to send to 730 * @param timeout_in_ms pointer to how long to wait until DDR is initialized 731 * in ms. 732 * If contents are 0, it waits until contents are non-zero 733 * before starting to check. 734 * @return Zero on success, negative on failure. 735 */ 736 int octeon_wait_for_ddr_init(struct octeon_device *oct, 737 u32 *timeout_in_ms); 738 739 /** 740 * Wait for u-boot to boot and be waiting for a command. 741 * 742 * @param wait_time_hundredths 743 * Maximum time to wait 744 * 745 * @return Zero on success, negative on failure. 746 */ 747 int octeon_wait_for_bootloader(struct octeon_device *oct, 748 u32 wait_time_hundredths); 749 750 /** 751 * Initialize console access 752 * 753 * @param oct which octeon initialize 754 * @return Zero on success, negative on failure. 755 */ 756 int octeon_init_consoles(struct octeon_device *oct); 757 758 /** 759 * Adds access to a console to the device. 760 * 761 * @param oct: which octeon to add to 762 * @param console_num: which console 763 * @param dbg_enb: ptr to debug enablement string, one of: 764 * * NULL for no debug output (i.e. disabled) 765 * * empty string enables debug output (via default method) 766 * * specific string to enable debug console output 767 * 768 * @return Zero on success, negative on failure. 769 */ 770 int octeon_add_console(struct octeon_device *oct, u32 console_num, 771 char *dbg_enb); 772 773 /** write or read from a console */ 774 int octeon_console_write(struct octeon_device *oct, u32 console_num, 775 char *buffer, u32 write_request_size, u32 flags); 776 int octeon_console_write_avail(struct octeon_device *oct, u32 console_num); 777 778 int octeon_console_read_avail(struct octeon_device *oct, u32 console_num); 779 780 /** Removes all attached consoles. */ 781 void octeon_remove_consoles(struct octeon_device *oct); 782 783 /** 784 * Send a string to u-boot on console 0 as a command. 785 * 786 * @param oct which octeon to send to 787 * @param cmd_str String to send 788 * @param wait_hundredths Time to wait for u-boot to accept the command. 789 * 790 * @return Zero on success, negative on failure. 791 */ 792 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 793 u32 wait_hundredths); 794 795 /** Parses, validates, and downloads firmware, then boots associated cores. 796 * @param oct which octeon to download firmware to 797 * @param data - The complete firmware file image 798 * @param size - The size of the data 799 * 800 * @return 0 if success. 801 * -EINVAL if file is incompatible or badly formatted. 802 * -ENODEV if no handler was found for the application type or an 803 * invalid octeon id was passed. 804 */ 805 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 806 size_t size); 807 808 char *lio_get_state_string(atomic_t *state_ptr); 809 810 /** Sets up instruction queues for the device 811 * @param oct which octeon to setup 812 * 813 * @return 0 if success. 1 if fails 814 */ 815 int octeon_setup_instr_queues(struct octeon_device *oct); 816 817 /** Sets up output queues for the device 818 * @param oct which octeon to setup 819 * 820 * @return 0 if success. 1 if fails 821 */ 822 int octeon_setup_output_queues(struct octeon_device *oct); 823 824 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no); 825 826 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no); 827 828 /** Turns off the input and output queues for the device 829 * @param oct which octeon to disable 830 */ 831 int octeon_set_io_queues_off(struct octeon_device *oct); 832 833 /** Turns on or off the given output queue for the device 834 * @param oct which octeon to change 835 * @param q_no which queue 836 * @param enable 1 to enable, 0 to disable 837 */ 838 void octeon_set_droq_pkt_op(struct octeon_device *oct, u32 q_no, u32 enable); 839 840 /** Retrieve the config for the device 841 * @param oct which octeon 842 * @param card_type type of card 843 * 844 * @returns pointer to configuration 845 */ 846 void *oct_get_config_info(struct octeon_device *oct, u16 card_type); 847 848 /** Gets the octeon device configuration 849 * @return - pointer to the octeon configuration struture 850 */ 851 struct octeon_config *octeon_get_conf(struct octeon_device *oct); 852 853 void octeon_free_ioq_vector(struct octeon_device *oct); 854 int octeon_allocate_ioq_vector(struct octeon_device *oct); 855 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq); 856 857 /* LiquidIO driver pivate flags */ 858 enum { 859 OCT_PRIV_FLAG_TX_BYTES = 0, /* Tx interrupts by pending byte count */ 860 }; 861 862 #define OCT_PRIV_FLAG_DEFAULT 0x0 863 864 static inline u32 lio_get_priv_flag(struct octeon_device *octdev, u32 flag) 865 { 866 return !!(octdev->priv_flags & (0x1 << flag)); 867 } 868 869 static inline void lio_set_priv_flag(struct octeon_device *octdev, 870 u32 flag, u32 val) 871 { 872 if (val) 873 octdev->priv_flags |= (0x1 << flag); 874 else 875 octdev->priv_flags &= ~(0x1 << flag); 876 } 877 #endif 878