1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 #include <linux/pci.h> 19 #include <linux/netdevice.h> 20 #include <linux/vmalloc.h> 21 #include "liquidio_common.h" 22 #include "octeon_droq.h" 23 #include "octeon_iq.h" 24 #include "response_manager.h" 25 #include "octeon_device.h" 26 #include "octeon_main.h" 27 #include "octeon_network.h" 28 #include "cn66xx_regs.h" 29 #include "cn66xx_device.h" 30 #include "cn23xx_pf_device.h" 31 #include "cn23xx_vf_device.h" 32 33 /** Default configuration 34 * for CN66XX OCTEON Models. 35 */ 36 static struct octeon_config default_cn66xx_conf = { 37 .card_type = LIO_210SV, 38 .card_name = LIO_210SV_NAME, 39 40 /** IQ attributes */ 41 .iq = { 42 .max_iqs = CN6XXX_CFG_IO_QUEUES, 43 .pending_list_size = 44 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES), 45 .instr_type = OCTEON_64BYTE_INSTR, 46 .db_min = CN6XXX_DB_MIN, 47 .db_timeout = CN6XXX_DB_TIMEOUT, 48 } 49 , 50 51 /** OQ attributes */ 52 .oq = { 53 .max_oqs = CN6XXX_CFG_IO_QUEUES, 54 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD, 55 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT, 56 .oq_intr_time = CN6XXX_OQ_INTR_TIME, 57 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR, 58 } 59 , 60 61 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_66XX, 62 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 63 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 64 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE, 65 66 /* For ethernet interface 0: Port cfg Attributes */ 67 .nic_if_cfg[0] = { 68 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 69 .max_txqs = MAX_TXQS_PER_INTF, 70 71 /* Actual configured value. Range could be: 1...max_txqs */ 72 .num_txqs = DEF_TXQS_PER_INTF, 73 74 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 75 .max_rxqs = MAX_RXQS_PER_INTF, 76 77 /* Actual configured value. Range could be: 1...max_rxqs */ 78 .num_rxqs = DEF_RXQS_PER_INTF, 79 80 /* Num of desc for rx rings */ 81 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 82 83 /* Num of desc for tx rings */ 84 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 85 86 /* SKB size, We need not change buf size even for Jumbo frames. 87 * Octeon can send jumbo frames in 4 consecutive descriptors, 88 */ 89 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 90 91 .base_queue = BASE_QUEUE_NOT_REQUESTED, 92 93 .gmx_port_id = 0, 94 }, 95 96 .nic_if_cfg[1] = { 97 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 98 .max_txqs = MAX_TXQS_PER_INTF, 99 100 /* Actual configured value. Range could be: 1...max_txqs */ 101 .num_txqs = DEF_TXQS_PER_INTF, 102 103 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 104 .max_rxqs = MAX_RXQS_PER_INTF, 105 106 /* Actual configured value. Range could be: 1...max_rxqs */ 107 .num_rxqs = DEF_RXQS_PER_INTF, 108 109 /* Num of desc for rx rings */ 110 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 111 112 /* Num of desc for tx rings */ 113 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 114 115 /* SKB size, We need not change buf size even for Jumbo frames. 116 * Octeon can send jumbo frames in 4 consecutive descriptors, 117 */ 118 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 119 120 .base_queue = BASE_QUEUE_NOT_REQUESTED, 121 122 .gmx_port_id = 1, 123 }, 124 125 /** Miscellaneous attributes */ 126 .misc = { 127 /* Host driver link query interval */ 128 .oct_link_query_interval = 100, 129 130 /* Octeon link query interval */ 131 .host_link_query_interval = 500, 132 133 .enable_sli_oq_bp = 0, 134 135 /* Control queue group */ 136 .ctrlq_grp = 1, 137 } 138 , 139 }; 140 141 /** Default configuration 142 * for CN68XX OCTEON Model. 143 */ 144 145 static struct octeon_config default_cn68xx_conf = { 146 .card_type = LIO_410NV, 147 .card_name = LIO_410NV_NAME, 148 149 /** IQ attributes */ 150 .iq = { 151 .max_iqs = CN6XXX_CFG_IO_QUEUES, 152 .pending_list_size = 153 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES), 154 .instr_type = OCTEON_64BYTE_INSTR, 155 .db_min = CN6XXX_DB_MIN, 156 .db_timeout = CN6XXX_DB_TIMEOUT, 157 } 158 , 159 160 /** OQ attributes */ 161 .oq = { 162 .max_oqs = CN6XXX_CFG_IO_QUEUES, 163 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD, 164 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT, 165 .oq_intr_time = CN6XXX_OQ_INTR_TIME, 166 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR, 167 } 168 , 169 170 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX, 171 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 172 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 173 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE, 174 175 .nic_if_cfg[0] = { 176 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 177 .max_txqs = MAX_TXQS_PER_INTF, 178 179 /* Actual configured value. Range could be: 1...max_txqs */ 180 .num_txqs = DEF_TXQS_PER_INTF, 181 182 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 183 .max_rxqs = MAX_RXQS_PER_INTF, 184 185 /* Actual configured value. Range could be: 1...max_rxqs */ 186 .num_rxqs = DEF_RXQS_PER_INTF, 187 188 /* Num of desc for rx rings */ 189 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 190 191 /* Num of desc for tx rings */ 192 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 193 194 /* SKB size, We need not change buf size even for Jumbo frames. 195 * Octeon can send jumbo frames in 4 consecutive descriptors, 196 */ 197 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 198 199 .base_queue = BASE_QUEUE_NOT_REQUESTED, 200 201 .gmx_port_id = 0, 202 }, 203 204 .nic_if_cfg[1] = { 205 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 206 .max_txqs = MAX_TXQS_PER_INTF, 207 208 /* Actual configured value. Range could be: 1...max_txqs */ 209 .num_txqs = DEF_TXQS_PER_INTF, 210 211 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 212 .max_rxqs = MAX_RXQS_PER_INTF, 213 214 /* Actual configured value. Range could be: 1...max_rxqs */ 215 .num_rxqs = DEF_RXQS_PER_INTF, 216 217 /* Num of desc for rx rings */ 218 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 219 220 /* Num of desc for tx rings */ 221 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 222 223 /* SKB size, We need not change buf size even for Jumbo frames. 224 * Octeon can send jumbo frames in 4 consecutive descriptors, 225 */ 226 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 227 228 .base_queue = BASE_QUEUE_NOT_REQUESTED, 229 230 .gmx_port_id = 1, 231 }, 232 233 .nic_if_cfg[2] = { 234 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 235 .max_txqs = MAX_TXQS_PER_INTF, 236 237 /* Actual configured value. Range could be: 1...max_txqs */ 238 .num_txqs = DEF_TXQS_PER_INTF, 239 240 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 241 .max_rxqs = MAX_RXQS_PER_INTF, 242 243 /* Actual configured value. Range could be: 1...max_rxqs */ 244 .num_rxqs = DEF_RXQS_PER_INTF, 245 246 /* Num of desc for rx rings */ 247 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 248 249 /* Num of desc for tx rings */ 250 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 251 252 /* SKB size, We need not change buf size even for Jumbo frames. 253 * Octeon can send jumbo frames in 4 consecutive descriptors, 254 */ 255 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 256 257 .base_queue = BASE_QUEUE_NOT_REQUESTED, 258 259 .gmx_port_id = 2, 260 }, 261 262 .nic_if_cfg[3] = { 263 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 264 .max_txqs = MAX_TXQS_PER_INTF, 265 266 /* Actual configured value. Range could be: 1...max_txqs */ 267 .num_txqs = DEF_TXQS_PER_INTF, 268 269 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 270 .max_rxqs = MAX_RXQS_PER_INTF, 271 272 /* Actual configured value. Range could be: 1...max_rxqs */ 273 .num_rxqs = DEF_RXQS_PER_INTF, 274 275 /* Num of desc for rx rings */ 276 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 277 278 /* Num of desc for tx rings */ 279 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 280 281 /* SKB size, We need not change buf size even for Jumbo frames. 282 * Octeon can send jumbo frames in 4 consecutive descriptors, 283 */ 284 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 285 286 .base_queue = BASE_QUEUE_NOT_REQUESTED, 287 288 .gmx_port_id = 3, 289 }, 290 291 /** Miscellaneous attributes */ 292 .misc = { 293 /* Host driver link query interval */ 294 .oct_link_query_interval = 100, 295 296 /* Octeon link query interval */ 297 .host_link_query_interval = 500, 298 299 .enable_sli_oq_bp = 0, 300 301 /* Control queue group */ 302 .ctrlq_grp = 1, 303 } 304 , 305 }; 306 307 /** Default configuration 308 * for CN68XX OCTEON Model. 309 */ 310 static struct octeon_config default_cn68xx_210nv_conf = { 311 .card_type = LIO_210NV, 312 .card_name = LIO_210NV_NAME, 313 314 /** IQ attributes */ 315 316 .iq = { 317 .max_iqs = CN6XXX_CFG_IO_QUEUES, 318 .pending_list_size = 319 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES), 320 .instr_type = OCTEON_64BYTE_INSTR, 321 .db_min = CN6XXX_DB_MIN, 322 .db_timeout = CN6XXX_DB_TIMEOUT, 323 } 324 , 325 326 /** OQ attributes */ 327 .oq = { 328 .max_oqs = CN6XXX_CFG_IO_QUEUES, 329 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD, 330 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT, 331 .oq_intr_time = CN6XXX_OQ_INTR_TIME, 332 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR, 333 } 334 , 335 336 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX_210NV, 337 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 338 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 339 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE, 340 341 .nic_if_cfg[0] = { 342 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 343 .max_txqs = MAX_TXQS_PER_INTF, 344 345 /* Actual configured value. Range could be: 1...max_txqs */ 346 .num_txqs = DEF_TXQS_PER_INTF, 347 348 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 349 .max_rxqs = MAX_RXQS_PER_INTF, 350 351 /* Actual configured value. Range could be: 1...max_rxqs */ 352 .num_rxqs = DEF_RXQS_PER_INTF, 353 354 /* Num of desc for rx rings */ 355 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 356 357 /* Num of desc for tx rings */ 358 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 359 360 /* SKB size, We need not change buf size even for Jumbo frames. 361 * Octeon can send jumbo frames in 4 consecutive descriptors, 362 */ 363 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 364 365 .base_queue = BASE_QUEUE_NOT_REQUESTED, 366 367 .gmx_port_id = 0, 368 }, 369 370 .nic_if_cfg[1] = { 371 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 372 .max_txqs = MAX_TXQS_PER_INTF, 373 374 /* Actual configured value. Range could be: 1...max_txqs */ 375 .num_txqs = DEF_TXQS_PER_INTF, 376 377 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 378 .max_rxqs = MAX_RXQS_PER_INTF, 379 380 /* Actual configured value. Range could be: 1...max_rxqs */ 381 .num_rxqs = DEF_RXQS_PER_INTF, 382 383 /* Num of desc for rx rings */ 384 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 385 386 /* Num of desc for tx rings */ 387 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 388 389 /* SKB size, We need not change buf size even for Jumbo frames. 390 * Octeon can send jumbo frames in 4 consecutive descriptors, 391 */ 392 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 393 394 .base_queue = BASE_QUEUE_NOT_REQUESTED, 395 396 .gmx_port_id = 1, 397 }, 398 399 /** Miscellaneous attributes */ 400 .misc = { 401 /* Host driver link query interval */ 402 .oct_link_query_interval = 100, 403 404 /* Octeon link query interval */ 405 .host_link_query_interval = 500, 406 407 .enable_sli_oq_bp = 0, 408 409 /* Control queue group */ 410 .ctrlq_grp = 1, 411 } 412 , 413 }; 414 415 static struct octeon_config default_cn23xx_conf = { 416 .card_type = LIO_23XX, 417 .card_name = LIO_23XX_NAME, 418 /** IQ attributes */ 419 .iq = { 420 .max_iqs = CN23XX_CFG_IO_QUEUES, 421 .pending_list_size = (CN23XX_MAX_IQ_DESCRIPTORS * 422 CN23XX_CFG_IO_QUEUES), 423 .instr_type = OCTEON_64BYTE_INSTR, 424 .db_min = CN23XX_DB_MIN, 425 .db_timeout = CN23XX_DB_TIMEOUT, 426 .iq_intr_pkt = CN23XX_DEF_IQ_INTR_THRESHOLD, 427 }, 428 429 /** OQ attributes */ 430 .oq = { 431 .max_oqs = CN23XX_CFG_IO_QUEUES, 432 .pkts_per_intr = CN23XX_OQ_PKTSPER_INTR, 433 .refill_threshold = CN23XX_OQ_REFIL_THRESHOLD, 434 .oq_intr_pkt = CN23XX_OQ_INTR_PKT, 435 .oq_intr_time = CN23XX_OQ_INTR_TIME, 436 }, 437 438 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_23XX, 439 .num_def_rx_descs = CN23XX_MAX_OQ_DESCRIPTORS, 440 .num_def_tx_descs = CN23XX_MAX_IQ_DESCRIPTORS, 441 .def_rx_buf_size = CN23XX_OQ_BUF_SIZE, 442 443 /* For ethernet interface 0: Port cfg Attributes */ 444 .nic_if_cfg[0] = { 445 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 446 .max_txqs = MAX_TXQS_PER_INTF, 447 448 /* Actual configured value. Range could be: 1...max_txqs */ 449 .num_txqs = DEF_TXQS_PER_INTF, 450 451 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 452 .max_rxqs = MAX_RXQS_PER_INTF, 453 454 /* Actual configured value. Range could be: 1...max_rxqs */ 455 .num_rxqs = DEF_RXQS_PER_INTF, 456 457 /* Num of desc for rx rings */ 458 .num_rx_descs = CN23XX_MAX_OQ_DESCRIPTORS, 459 460 /* Num of desc for tx rings */ 461 .num_tx_descs = CN23XX_MAX_IQ_DESCRIPTORS, 462 463 /* SKB size, We need not change buf size even for Jumbo frames. 464 * Octeon can send jumbo frames in 4 consecutive descriptors, 465 */ 466 .rx_buf_size = CN23XX_OQ_BUF_SIZE, 467 468 .base_queue = BASE_QUEUE_NOT_REQUESTED, 469 470 .gmx_port_id = 0, 471 }, 472 473 .nic_if_cfg[1] = { 474 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 475 .max_txqs = MAX_TXQS_PER_INTF, 476 477 /* Actual configured value. Range could be: 1...max_txqs */ 478 .num_txqs = DEF_TXQS_PER_INTF, 479 480 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 481 .max_rxqs = MAX_RXQS_PER_INTF, 482 483 /* Actual configured value. Range could be: 1...max_rxqs */ 484 .num_rxqs = DEF_RXQS_PER_INTF, 485 486 /* Num of desc for rx rings */ 487 .num_rx_descs = CN23XX_MAX_OQ_DESCRIPTORS, 488 489 /* Num of desc for tx rings */ 490 .num_tx_descs = CN23XX_MAX_IQ_DESCRIPTORS, 491 492 /* SKB size, We need not change buf size even for Jumbo frames. 493 * Octeon can send jumbo frames in 4 consecutive descriptors, 494 */ 495 .rx_buf_size = CN23XX_OQ_BUF_SIZE, 496 497 .base_queue = BASE_QUEUE_NOT_REQUESTED, 498 499 .gmx_port_id = 1, 500 }, 501 502 .misc = { 503 /* Host driver link query interval */ 504 .oct_link_query_interval = 100, 505 506 /* Octeon link query interval */ 507 .host_link_query_interval = 500, 508 509 .enable_sli_oq_bp = 0, 510 511 /* Control queue group */ 512 .ctrlq_grp = 1, 513 } 514 }; 515 516 static struct octeon_config_ptr { 517 u32 conf_type; 518 } oct_conf_info[MAX_OCTEON_DEVICES] = { 519 { 520 OCTEON_CONFIG_TYPE_DEFAULT, 521 }, { 522 OCTEON_CONFIG_TYPE_DEFAULT, 523 }, { 524 OCTEON_CONFIG_TYPE_DEFAULT, 525 }, { 526 OCTEON_CONFIG_TYPE_DEFAULT, 527 }, 528 }; 529 530 static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = { 531 "BEGIN", "PCI-MAP-DONE", "DISPATCH-INIT-DONE", 532 "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE", 533 "DROQ-INIT-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE", 534 "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET", 535 "INVALID" 536 }; 537 538 static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = { 539 "BASE", "NIC", "UNKNOWN"}; 540 541 static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES]; 542 static atomic_t adapter_refcounts[MAX_OCTEON_DEVICES]; 543 544 static u32 octeon_device_count; 545 /* locks device array (i.e. octeon_device[]) */ 546 static spinlock_t octeon_devices_lock; 547 548 static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES]; 549 550 static void oct_set_config_info(int oct_id, int conf_type) 551 { 552 if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1)) 553 conf_type = OCTEON_CONFIG_TYPE_DEFAULT; 554 oct_conf_info[oct_id].conf_type = conf_type; 555 } 556 557 void octeon_init_device_list(int conf_type) 558 { 559 int i; 560 561 memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES)); 562 for (i = 0; i < MAX_OCTEON_DEVICES; i++) 563 oct_set_config_info(i, conf_type); 564 spin_lock_init(&octeon_devices_lock); 565 } 566 567 static void *__retrieve_octeon_config_info(struct octeon_device *oct, 568 u16 card_type) 569 { 570 u32 oct_id = oct->octeon_id; 571 void *ret = NULL; 572 573 switch (oct_conf_info[oct_id].conf_type) { 574 case OCTEON_CONFIG_TYPE_DEFAULT: 575 if (oct->chip_id == OCTEON_CN66XX) { 576 ret = &default_cn66xx_conf; 577 } else if ((oct->chip_id == OCTEON_CN68XX) && 578 (card_type == LIO_210NV)) { 579 ret = &default_cn68xx_210nv_conf; 580 } else if ((oct->chip_id == OCTEON_CN68XX) && 581 (card_type == LIO_410NV)) { 582 ret = &default_cn68xx_conf; 583 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) { 584 ret = &default_cn23xx_conf; 585 } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) { 586 ret = &default_cn23xx_conf; 587 } 588 break; 589 default: 590 break; 591 } 592 return ret; 593 } 594 595 static int __verify_octeon_config_info(struct octeon_device *oct, void *conf) 596 { 597 switch (oct->chip_id) { 598 case OCTEON_CN66XX: 599 case OCTEON_CN68XX: 600 return lio_validate_cn6xxx_config_info(oct, conf); 601 case OCTEON_CN23XX_PF_VID: 602 case OCTEON_CN23XX_VF_VID: 603 return 0; 604 default: 605 break; 606 } 607 608 return 1; 609 } 610 611 void *oct_get_config_info(struct octeon_device *oct, u16 card_type) 612 { 613 void *conf = NULL; 614 615 conf = __retrieve_octeon_config_info(oct, card_type); 616 if (!conf) 617 return NULL; 618 619 if (__verify_octeon_config_info(oct, conf)) { 620 dev_err(&oct->pci_dev->dev, "Configuration verification failed\n"); 621 return NULL; 622 } 623 624 return conf; 625 } 626 627 char *lio_get_state_string(atomic_t *state_ptr) 628 { 629 s32 istate = (s32)atomic_read(state_ptr); 630 631 if (istate > OCT_DEV_STATES || istate < 0) 632 return oct_dev_state_str[OCT_DEV_STATE_INVALID]; 633 return oct_dev_state_str[istate]; 634 } 635 636 static char *get_oct_app_string(u32 app_mode) 637 { 638 if (app_mode <= CVM_DRV_APP_END) 639 return oct_dev_app_str[app_mode - CVM_DRV_APP_START]; 640 return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START]; 641 } 642 643 void octeon_free_device_mem(struct octeon_device *oct) 644 { 645 int i; 646 647 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { 648 if (oct->io_qmask.oq & BIT_ULL(i)) 649 vfree(oct->droq[i]); 650 } 651 652 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { 653 if (oct->io_qmask.iq & BIT_ULL(i)) 654 vfree(oct->instr_queue[i]); 655 } 656 657 i = oct->octeon_id; 658 vfree(oct); 659 660 octeon_device[i] = NULL; 661 octeon_device_count--; 662 } 663 664 static struct octeon_device *octeon_allocate_device_mem(u32 pci_id, 665 u32 priv_size) 666 { 667 struct octeon_device *oct; 668 u8 *buf = NULL; 669 u32 octdevsize = 0, configsize = 0, size; 670 671 switch (pci_id) { 672 case OCTEON_CN68XX: 673 case OCTEON_CN66XX: 674 configsize = sizeof(struct octeon_cn6xxx); 675 break; 676 677 case OCTEON_CN23XX_PF_VID: 678 configsize = sizeof(struct octeon_cn23xx_pf); 679 break; 680 case OCTEON_CN23XX_VF_VID: 681 configsize = sizeof(struct octeon_cn23xx_vf); 682 break; 683 default: 684 pr_err("%s: Unknown PCI Device: 0x%x\n", 685 __func__, 686 pci_id); 687 return NULL; 688 } 689 690 if (configsize & 0x7) 691 configsize += (8 - (configsize & 0x7)); 692 693 octdevsize = sizeof(struct octeon_device); 694 if (octdevsize & 0x7) 695 octdevsize += (8 - (octdevsize & 0x7)); 696 697 if (priv_size & 0x7) 698 priv_size += (8 - (priv_size & 0x7)); 699 700 size = octdevsize + priv_size + configsize + 701 (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE); 702 703 buf = vmalloc(size); 704 if (!buf) 705 return NULL; 706 707 memset(buf, 0, size); 708 709 oct = (struct octeon_device *)buf; 710 oct->priv = (void *)(buf + octdevsize); 711 oct->chip = (void *)(buf + octdevsize + priv_size); 712 oct->dispatch.dlist = (struct octeon_dispatch *) 713 (buf + octdevsize + priv_size + configsize); 714 715 return oct; 716 } 717 718 struct octeon_device *octeon_allocate_device(u32 pci_id, 719 u32 priv_size) 720 { 721 u32 oct_idx = 0; 722 struct octeon_device *oct = NULL; 723 724 spin_lock(&octeon_devices_lock); 725 726 for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++) 727 if (!octeon_device[oct_idx]) 728 break; 729 730 if (oct_idx < MAX_OCTEON_DEVICES) { 731 oct = octeon_allocate_device_mem(pci_id, priv_size); 732 if (oct) { 733 octeon_device_count++; 734 octeon_device[oct_idx] = oct; 735 } 736 } 737 738 spin_unlock(&octeon_devices_lock); 739 if (!oct) 740 return NULL; 741 742 spin_lock_init(&oct->pci_win_lock); 743 spin_lock_init(&oct->mem_access_lock); 744 745 oct->octeon_id = oct_idx; 746 snprintf(oct->device_name, sizeof(oct->device_name), 747 "LiquidIO%d", (oct->octeon_id)); 748 749 return oct; 750 } 751 752 /** Register a device's bus location at initialization time. 753 * @param octeon_dev - pointer to the octeon device structure. 754 * @param bus - PCIe bus # 755 * @param dev - PCIe device # 756 * @param func - PCIe function # 757 * @param is_pf - TRUE for PF, FALSE for VF 758 * @return reference count of device's adapter 759 */ 760 int octeon_register_device(struct octeon_device *oct, 761 int bus, int dev, int func, int is_pf) 762 { 763 int idx, refcount; 764 765 oct->loc.bus = bus; 766 oct->loc.dev = dev; 767 oct->loc.func = func; 768 769 oct->adapter_refcount = &adapter_refcounts[oct->octeon_id]; 770 atomic_set(oct->adapter_refcount, 0); 771 772 spin_lock(&octeon_devices_lock); 773 for (idx = (int)oct->octeon_id - 1; idx >= 0; idx--) { 774 if (!octeon_device[idx]) { 775 dev_err(&oct->pci_dev->dev, 776 "%s: Internal driver error, missing dev", 777 __func__); 778 spin_unlock(&octeon_devices_lock); 779 atomic_inc(oct->adapter_refcount); 780 return 1; /* here, refcount is guaranteed to be 1 */ 781 } 782 /* if another device is at same bus/dev, use its refcounter */ 783 if ((octeon_device[idx]->loc.bus == bus) && 784 (octeon_device[idx]->loc.dev == dev)) { 785 oct->adapter_refcount = 786 octeon_device[idx]->adapter_refcount; 787 break; 788 } 789 } 790 spin_unlock(&octeon_devices_lock); 791 792 atomic_inc(oct->adapter_refcount); 793 refcount = atomic_read(oct->adapter_refcount); 794 795 dev_dbg(&oct->pci_dev->dev, "%s: %02x:%02x:%d refcount %u", __func__, 796 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount); 797 798 return refcount; 799 } 800 801 /** Deregister a device at de-initialization time. 802 * @param octeon_dev - pointer to the octeon device structure. 803 * @return reference count of device's adapter 804 */ 805 int octeon_deregister_device(struct octeon_device *oct) 806 { 807 int refcount; 808 809 atomic_dec(oct->adapter_refcount); 810 refcount = atomic_read(oct->adapter_refcount); 811 812 dev_dbg(&oct->pci_dev->dev, "%s: %04d:%02d:%d refcount %u", __func__, 813 oct->loc.bus, oct->loc.dev, oct->loc.func, refcount); 814 815 return refcount; 816 } 817 818 int 819 octeon_allocate_ioq_vector(struct octeon_device *oct) 820 { 821 int i, num_ioqs = 0; 822 struct octeon_ioq_vector *ioq_vector; 823 int cpu_num; 824 int size; 825 826 if (OCTEON_CN23XX_PF(oct)) 827 num_ioqs = oct->sriov_info.num_pf_rings; 828 else if (OCTEON_CN23XX_VF(oct)) 829 num_ioqs = oct->sriov_info.rings_per_vf; 830 831 size = sizeof(struct octeon_ioq_vector) * num_ioqs; 832 833 oct->ioq_vector = vmalloc(size); 834 if (!oct->ioq_vector) 835 return 1; 836 memset(oct->ioq_vector, 0, size); 837 for (i = 0; i < num_ioqs; i++) { 838 ioq_vector = &oct->ioq_vector[i]; 839 ioq_vector->oct_dev = oct; 840 ioq_vector->iq_index = i; 841 ioq_vector->droq_index = i; 842 ioq_vector->mbox = oct->mbox[i]; 843 844 cpu_num = i % num_online_cpus(); 845 cpumask_set_cpu(cpu_num, &ioq_vector->affinity_mask); 846 847 if (oct->chip_id == OCTEON_CN23XX_PF_VID) 848 ioq_vector->ioq_num = i + oct->sriov_info.pf_srn; 849 else 850 ioq_vector->ioq_num = i; 851 } 852 return 0; 853 } 854 855 void 856 octeon_free_ioq_vector(struct octeon_device *oct) 857 { 858 vfree(oct->ioq_vector); 859 } 860 861 /* this function is only for setting up the first queue */ 862 int octeon_setup_instr_queues(struct octeon_device *oct) 863 { 864 u32 num_descs = 0; 865 u32 iq_no = 0; 866 union oct_txpciq txpciq; 867 int numa_node = dev_to_node(&oct->pci_dev->dev); 868 869 if (OCTEON_CN6XXX(oct)) 870 num_descs = 871 CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn6xxx)); 872 else if (OCTEON_CN23XX_PF(oct)) 873 num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_pf)); 874 else if (OCTEON_CN23XX_VF(oct)) 875 num_descs = CFG_GET_NUM_DEF_TX_DESCS(CHIP_CONF(oct, cn23xx_vf)); 876 877 oct->num_iqs = 0; 878 879 oct->instr_queue[0] = vmalloc_node(sizeof(*oct->instr_queue[0]), 880 numa_node); 881 if (!oct->instr_queue[0]) 882 oct->instr_queue[0] = 883 vmalloc(sizeof(struct octeon_instr_queue)); 884 if (!oct->instr_queue[0]) 885 return 1; 886 memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue)); 887 oct->instr_queue[0]->q_index = 0; 888 oct->instr_queue[0]->app_ctx = (void *)(size_t)0; 889 oct->instr_queue[0]->ifidx = 0; 890 txpciq.u64 = 0; 891 txpciq.s.q_no = iq_no; 892 txpciq.s.pkind = oct->pfvf_hsword.pkind; 893 txpciq.s.use_qpg = 0; 894 txpciq.s.qpg = 0; 895 if (octeon_init_instr_queue(oct, txpciq, num_descs)) { 896 /* prevent memory leak */ 897 vfree(oct->instr_queue[0]); 898 oct->instr_queue[0] = NULL; 899 return 1; 900 } 901 902 oct->num_iqs++; 903 return 0; 904 } 905 906 int octeon_setup_output_queues(struct octeon_device *oct) 907 { 908 u32 num_descs = 0; 909 u32 desc_size = 0; 910 u32 oq_no = 0; 911 int numa_node = dev_to_node(&oct->pci_dev->dev); 912 913 if (OCTEON_CN6XXX(oct)) { 914 num_descs = 915 CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn6xxx)); 916 desc_size = 917 CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn6xxx)); 918 } else if (OCTEON_CN23XX_PF(oct)) { 919 num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_pf)); 920 desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_pf)); 921 } else if (OCTEON_CN23XX_VF(oct)) { 922 num_descs = CFG_GET_NUM_DEF_RX_DESCS(CHIP_CONF(oct, cn23xx_vf)); 923 desc_size = CFG_GET_DEF_RX_BUF_SIZE(CHIP_CONF(oct, cn23xx_vf)); 924 } 925 oct->num_oqs = 0; 926 oct->droq[0] = vmalloc_node(sizeof(*oct->droq[0]), numa_node); 927 if (!oct->droq[0]) 928 oct->droq[0] = vmalloc(sizeof(*oct->droq[0])); 929 if (!oct->droq[0]) 930 return 1; 931 932 if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) { 933 vfree(oct->droq[oq_no]); 934 oct->droq[oq_no] = NULL; 935 return 1; 936 } 937 oct->num_oqs++; 938 939 return 0; 940 } 941 942 int octeon_set_io_queues_off(struct octeon_device *oct) 943 { 944 int loop = BUSY_READING_REG_VF_LOOP_COUNT; 945 946 if (OCTEON_CN6XXX(oct)) { 947 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0); 948 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0); 949 } else if (oct->chip_id == OCTEON_CN23XX_VF_VID) { 950 u32 q_no; 951 952 /* IOQs will already be in reset. 953 * If RST bit is set, wait for quiet bit to be set. 954 * Once quiet bit is set, clear the RST bit. 955 */ 956 for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) { 957 u64 reg_val = octeon_read_csr64( 958 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); 959 960 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) && 961 !(reg_val & CN23XX_PKT_INPUT_CTL_QUIET) && 962 loop) { 963 reg_val = octeon_read_csr64( 964 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 965 loop--; 966 } 967 if (!loop) { 968 dev_err(&oct->pci_dev->dev, 969 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n", 970 q_no); 971 return -1; 972 } 973 974 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST; 975 octeon_write_csr64(oct, 976 CN23XX_SLI_IQ_PKT_CONTROL64(q_no), 977 reg_val); 978 979 reg_val = octeon_read_csr64( 980 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); 981 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) { 982 dev_err(&oct->pci_dev->dev, 983 "unable to reset qno %u\n", q_no); 984 return -1; 985 } 986 } 987 } 988 return 0; 989 } 990 991 void octeon_set_droq_pkt_op(struct octeon_device *oct, 992 u32 q_no, 993 u32 enable) 994 { 995 u32 reg_val = 0; 996 997 /* Disable the i/p and o/p queues for this Octeon. */ 998 if (OCTEON_CN6XXX(oct)) { 999 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); 1000 1001 if (enable) 1002 reg_val = reg_val | (1 << q_no); 1003 else 1004 reg_val = reg_val & (~(1 << q_no)); 1005 1006 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val); 1007 } 1008 } 1009 1010 int octeon_init_dispatch_list(struct octeon_device *oct) 1011 { 1012 u32 i; 1013 1014 oct->dispatch.count = 0; 1015 1016 for (i = 0; i < DISPATCH_LIST_SIZE; i++) { 1017 oct->dispatch.dlist[i].opcode = 0; 1018 INIT_LIST_HEAD(&oct->dispatch.dlist[i].list); 1019 } 1020 1021 for (i = 0; i <= REQTYPE_LAST; i++) 1022 octeon_register_reqtype_free_fn(oct, i, NULL); 1023 1024 spin_lock_init(&oct->dispatch.lock); 1025 1026 return 0; 1027 } 1028 1029 void octeon_delete_dispatch_list(struct octeon_device *oct) 1030 { 1031 u32 i; 1032 struct list_head freelist, *temp, *tmp2; 1033 1034 INIT_LIST_HEAD(&freelist); 1035 1036 spin_lock_bh(&oct->dispatch.lock); 1037 1038 for (i = 0; i < DISPATCH_LIST_SIZE; i++) { 1039 struct list_head *dispatch; 1040 1041 dispatch = &oct->dispatch.dlist[i].list; 1042 while (dispatch->next != dispatch) { 1043 temp = dispatch->next; 1044 list_del(temp); 1045 list_add_tail(temp, &freelist); 1046 } 1047 1048 oct->dispatch.dlist[i].opcode = 0; 1049 } 1050 1051 oct->dispatch.count = 0; 1052 1053 spin_unlock_bh(&oct->dispatch.lock); 1054 1055 list_for_each_safe(temp, tmp2, &freelist) { 1056 list_del(temp); 1057 vfree(temp); 1058 } 1059 } 1060 1061 octeon_dispatch_fn_t 1062 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 1063 u16 subcode) 1064 { 1065 u32 idx; 1066 struct list_head *dispatch; 1067 octeon_dispatch_fn_t fn = NULL; 1068 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode); 1069 1070 idx = combined_opcode & OCTEON_OPCODE_MASK; 1071 1072 spin_lock_bh(&octeon_dev->dispatch.lock); 1073 1074 if (octeon_dev->dispatch.count == 0) { 1075 spin_unlock_bh(&octeon_dev->dispatch.lock); 1076 return NULL; 1077 } 1078 1079 if (!(octeon_dev->dispatch.dlist[idx].opcode)) { 1080 spin_unlock_bh(&octeon_dev->dispatch.lock); 1081 return NULL; 1082 } 1083 1084 if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) { 1085 fn = octeon_dev->dispatch.dlist[idx].dispatch_fn; 1086 } else { 1087 list_for_each(dispatch, 1088 &octeon_dev->dispatch.dlist[idx].list) { 1089 if (((struct octeon_dispatch *)dispatch)->opcode == 1090 combined_opcode) { 1091 fn = ((struct octeon_dispatch *) 1092 dispatch)->dispatch_fn; 1093 break; 1094 } 1095 } 1096 } 1097 1098 spin_unlock_bh(&octeon_dev->dispatch.lock); 1099 return fn; 1100 } 1101 1102 /* octeon_register_dispatch_fn 1103 * Parameters: 1104 * octeon_id - id of the octeon device. 1105 * opcode - opcode for which driver should call the registered function 1106 * subcode - subcode for which driver should call the registered function 1107 * fn - The function to call when a packet with "opcode" arrives in 1108 * octeon output queues. 1109 * fn_arg - The argument to be passed when calling function "fn". 1110 * Description: 1111 * Registers a function and its argument to be called when a packet 1112 * arrives in Octeon output queues with "opcode". 1113 * Returns: 1114 * Success: 0 1115 * Failure: 1 1116 * Locks: 1117 * No locks are held. 1118 */ 1119 int 1120 octeon_register_dispatch_fn(struct octeon_device *oct, 1121 u16 opcode, 1122 u16 subcode, 1123 octeon_dispatch_fn_t fn, void *fn_arg) 1124 { 1125 u32 idx; 1126 octeon_dispatch_fn_t pfn; 1127 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode); 1128 1129 idx = combined_opcode & OCTEON_OPCODE_MASK; 1130 1131 spin_lock_bh(&oct->dispatch.lock); 1132 /* Add dispatch function to first level of lookup table */ 1133 if (oct->dispatch.dlist[idx].opcode == 0) { 1134 oct->dispatch.dlist[idx].opcode = combined_opcode; 1135 oct->dispatch.dlist[idx].dispatch_fn = fn; 1136 oct->dispatch.dlist[idx].arg = fn_arg; 1137 oct->dispatch.count++; 1138 spin_unlock_bh(&oct->dispatch.lock); 1139 return 0; 1140 } 1141 1142 spin_unlock_bh(&oct->dispatch.lock); 1143 1144 /* Check if there was a function already registered for this 1145 * opcode/subcode. 1146 */ 1147 pfn = octeon_get_dispatch(oct, opcode, subcode); 1148 if (!pfn) { 1149 struct octeon_dispatch *dispatch; 1150 1151 dev_dbg(&oct->pci_dev->dev, 1152 "Adding opcode to dispatch list linked list\n"); 1153 dispatch = (struct octeon_dispatch *) 1154 vmalloc(sizeof(struct octeon_dispatch)); 1155 if (!dispatch) { 1156 dev_err(&oct->pci_dev->dev, 1157 "No memory to add dispatch function\n"); 1158 return 1; 1159 } 1160 dispatch->opcode = combined_opcode; 1161 dispatch->dispatch_fn = fn; 1162 dispatch->arg = fn_arg; 1163 1164 /* Add dispatch function to linked list of fn ptrs 1165 * at the hashed index. 1166 */ 1167 spin_lock_bh(&oct->dispatch.lock); 1168 list_add(&dispatch->list, &oct->dispatch.dlist[idx].list); 1169 oct->dispatch.count++; 1170 spin_unlock_bh(&oct->dispatch.lock); 1171 1172 } else { 1173 dev_err(&oct->pci_dev->dev, 1174 "Found previously registered dispatch fn for opcode/subcode: %x/%x\n", 1175 opcode, subcode); 1176 return 1; 1177 } 1178 1179 return 0; 1180 } 1181 1182 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf) 1183 { 1184 u32 i; 1185 char app_name[16]; 1186 struct octeon_device *oct = (struct octeon_device *)buf; 1187 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt; 1188 struct octeon_core_setup *cs = NULL; 1189 u32 num_nic_ports = 0; 1190 1191 if (OCTEON_CN6XXX(oct)) 1192 num_nic_ports = 1193 CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn6xxx)); 1194 else if (OCTEON_CN23XX_PF(oct)) 1195 num_nic_ports = 1196 CFG_GET_NUM_NIC_PORTS(CHIP_CONF(oct, cn23xx_pf)); 1197 1198 if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) { 1199 dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n", 1200 atomic_read(&oct->status)); 1201 goto core_drv_init_err; 1202 } 1203 1204 strncpy(app_name, 1205 get_oct_app_string( 1206 (u32)recv_pkt->rh.r_core_drv_init.app_mode), 1207 sizeof(app_name) - 1); 1208 oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode; 1209 if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) { 1210 oct->fw_info.max_nic_ports = 1211 (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports; 1212 oct->fw_info.num_gmx_ports = 1213 (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports; 1214 } 1215 1216 if (oct->fw_info.max_nic_ports < num_nic_ports) { 1217 dev_err(&oct->pci_dev->dev, 1218 "Config has more ports than firmware allows (%d > %d).\n", 1219 num_nic_ports, oct->fw_info.max_nic_ports); 1220 goto core_drv_init_err; 1221 } 1222 oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags; 1223 oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode; 1224 oct->pfvf_hsword.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode; 1225 1226 oct->pfvf_hsword.pkind = recv_pkt->rh.r_core_drv_init.pkind; 1227 1228 for (i = 0; i < oct->num_iqs; i++) 1229 oct->instr_queue[i]->txpciq.s.pkind = oct->pfvf_hsword.pkind; 1230 1231 atomic_set(&oct->status, OCT_DEV_CORE_OK); 1232 1233 cs = &core_setup[oct->octeon_id]; 1234 1235 if (recv_pkt->buffer_size[0] != (sizeof(*cs) + OCT_DROQ_INFO_SIZE)) { 1236 dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n", 1237 (u32)sizeof(*cs), 1238 recv_pkt->buffer_size[0]); 1239 } 1240 1241 memcpy(cs, get_rbd( 1242 recv_pkt->buffer_ptr[0]) + OCT_DROQ_INFO_SIZE, sizeof(*cs)); 1243 1244 strncpy(oct->boardinfo.name, cs->boardname, OCT_BOARD_NAME); 1245 strncpy(oct->boardinfo.serial_number, cs->board_serial_number, 1246 OCT_SERIAL_LEN); 1247 1248 octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3)); 1249 1250 oct->boardinfo.major = cs->board_rev_major; 1251 oct->boardinfo.minor = cs->board_rev_minor; 1252 1253 dev_info(&oct->pci_dev->dev, 1254 "Running %s (%llu Hz)\n", 1255 app_name, CVM_CAST64(cs->corefreq)); 1256 1257 core_drv_init_err: 1258 for (i = 0; i < recv_pkt->buffer_count; i++) 1259 recv_buffer_free(recv_pkt->buffer_ptr[i]); 1260 octeon_free_recv_info(recv_info); 1261 return 0; 1262 } 1263 1264 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no) 1265 1266 { 1267 if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES(oct)) && 1268 (oct->io_qmask.iq & BIT_ULL(q_no))) 1269 return oct->instr_queue[q_no]->max_count; 1270 1271 return -1; 1272 } 1273 1274 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no) 1275 { 1276 if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES(oct)) && 1277 (oct->io_qmask.oq & BIT_ULL(q_no))) 1278 return oct->droq[q_no]->max_count; 1279 return -1; 1280 } 1281 1282 /* Retruns the host firmware handshake OCTEON specific configuration */ 1283 struct octeon_config *octeon_get_conf(struct octeon_device *oct) 1284 { 1285 struct octeon_config *default_oct_conf = NULL; 1286 1287 /* check the OCTEON Device model & return the corresponding octeon 1288 * configuration 1289 */ 1290 1291 if (OCTEON_CN6XXX(oct)) { 1292 default_oct_conf = 1293 (struct octeon_config *)(CHIP_CONF(oct, cn6xxx)); 1294 } else if (OCTEON_CN23XX_PF(oct)) { 1295 default_oct_conf = (struct octeon_config *) 1296 (CHIP_CONF(oct, cn23xx_pf)); 1297 } else if (OCTEON_CN23XX_VF(oct)) { 1298 default_oct_conf = (struct octeon_config *) 1299 (CHIP_CONF(oct, cn23xx_vf)); 1300 } 1301 return default_oct_conf; 1302 } 1303 1304 /* scratch register address is same in all the OCT-II and CN70XX models */ 1305 #define CNXX_SLI_SCRATCH1 0x3C0 1306 1307 /** Get the octeon device pointer. 1308 * @param octeon_id - The id for which the octeon device pointer is required. 1309 * @return Success: Octeon device pointer. 1310 * @return Failure: NULL. 1311 */ 1312 struct octeon_device *lio_get_device(u32 octeon_id) 1313 { 1314 if (octeon_id >= MAX_OCTEON_DEVICES) 1315 return NULL; 1316 else 1317 return octeon_device[octeon_id]; 1318 } 1319 1320 u64 lio_pci_readq(struct octeon_device *oct, u64 addr) 1321 { 1322 u64 val64; 1323 unsigned long flags; 1324 u32 val32, addrhi; 1325 1326 spin_lock_irqsave(&oct->pci_win_lock, flags); 1327 1328 /* The windowed read happens when the LSB of the addr is written. 1329 * So write MSB first 1330 */ 1331 addrhi = (addr >> 32); 1332 if ((oct->chip_id == OCTEON_CN66XX) || 1333 (oct->chip_id == OCTEON_CN68XX) || 1334 (oct->chip_id == OCTEON_CN23XX_PF_VID)) 1335 addrhi |= 0x00060000; 1336 writel(addrhi, oct->reg_list.pci_win_rd_addr_hi); 1337 1338 /* Read back to preserve ordering of writes */ 1339 val32 = readl(oct->reg_list.pci_win_rd_addr_hi); 1340 1341 writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo); 1342 val32 = readl(oct->reg_list.pci_win_rd_addr_lo); 1343 1344 val64 = readq(oct->reg_list.pci_win_rd_data); 1345 1346 spin_unlock_irqrestore(&oct->pci_win_lock, flags); 1347 1348 return val64; 1349 } 1350 1351 void lio_pci_writeq(struct octeon_device *oct, 1352 u64 val, 1353 u64 addr) 1354 { 1355 u32 val32; 1356 unsigned long flags; 1357 1358 spin_lock_irqsave(&oct->pci_win_lock, flags); 1359 1360 writeq(addr, oct->reg_list.pci_win_wr_addr); 1361 1362 /* The write happens when the LSB is written. So write MSB first. */ 1363 writel(val >> 32, oct->reg_list.pci_win_wr_data_hi); 1364 /* Read the MSB to ensure ordering of writes. */ 1365 val32 = readl(oct->reg_list.pci_win_wr_data_hi); 1366 1367 writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo); 1368 1369 spin_unlock_irqrestore(&oct->pci_win_lock, flags); 1370 } 1371 1372 int octeon_mem_access_ok(struct octeon_device *oct) 1373 { 1374 u64 access_okay = 0; 1375 u64 lmc0_reset_ctl; 1376 1377 /* Check to make sure a DDR interface is enabled */ 1378 if (OCTEON_CN23XX_PF(oct)) { 1379 lmc0_reset_ctl = lio_pci_readq(oct, CN23XX_LMC0_RESET_CTL); 1380 access_okay = 1381 (lmc0_reset_ctl & CN23XX_LMC0_RESET_CTL_DDR3RST_MASK); 1382 } else { 1383 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL); 1384 access_okay = 1385 (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK); 1386 } 1387 1388 return access_okay ? 0 : 1; 1389 } 1390 1391 int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout) 1392 { 1393 int ret = 1; 1394 u32 ms; 1395 1396 if (!timeout) 1397 return ret; 1398 1399 for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout)); 1400 ms += HZ / 10) { 1401 ret = octeon_mem_access_ok(oct); 1402 1403 /* wait 100 ms */ 1404 if (ret) 1405 schedule_timeout_uninterruptible(HZ / 10); 1406 } 1407 1408 return ret; 1409 } 1410 1411 /** Get the octeon id assigned to the octeon device passed as argument. 1412 * This function is exported to other modules. 1413 * @param dev - octeon device pointer passed as a void *. 1414 * @return octeon device id 1415 */ 1416 int lio_get_device_id(void *dev) 1417 { 1418 struct octeon_device *octeon_dev = (struct octeon_device *)dev; 1419 u32 i; 1420 1421 for (i = 0; i < MAX_OCTEON_DEVICES; i++) 1422 if (octeon_device[i] == octeon_dev) 1423 return octeon_dev->octeon_id; 1424 return -1; 1425 } 1426 1427 void lio_enable_irq(struct octeon_droq *droq, struct octeon_instr_queue *iq) 1428 { 1429 u64 instr_cnt; 1430 u32 pkts_pend; 1431 struct octeon_device *oct = NULL; 1432 1433 /* the whole thing needs to be atomic, ideally */ 1434 if (droq) { 1435 pkts_pend = (u32)atomic_read(&droq->pkts_pending); 1436 spin_lock_bh(&droq->lock); 1437 writel(droq->pkt_count - pkts_pend, droq->pkts_sent_reg); 1438 droq->pkt_count = pkts_pend; 1439 /* this write needs to be flushed before we release the lock */ 1440 mmiowb(); 1441 spin_unlock_bh(&droq->lock); 1442 oct = droq->oct_dev; 1443 } 1444 if (iq) { 1445 spin_lock_bh(&iq->lock); 1446 writel(iq->pkt_in_done, iq->inst_cnt_reg); 1447 iq->pkt_in_done = 0; 1448 /* this write needs to be flushed before we release the lock */ 1449 mmiowb(); 1450 spin_unlock_bh(&iq->lock); 1451 oct = iq->oct_dev; 1452 } 1453 /*write resend. Writing RESEND in SLI_PKTX_CNTS should be enough 1454 *to trigger tx interrupts as well, if they are pending. 1455 */ 1456 if (oct && (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct))) { 1457 if (droq) 1458 writeq(CN23XX_INTR_RESEND, droq->pkts_sent_reg); 1459 /*we race with firmrware here. read and write the IN_DONE_CNTS*/ 1460 else if (iq) { 1461 instr_cnt = readq(iq->inst_cnt_reg); 1462 writeq(((instr_cnt & 0xFFFFFFFF00000000ULL) | 1463 CN23XX_INTR_RESEND), 1464 iq->inst_cnt_reg); 1465 } 1466 } 1467 } 1468