1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2015 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 #include <linux/pci.h> 23 #include <linux/crc32.h> 24 #include <linux/netdevice.h> 25 #include <linux/vmalloc.h> 26 #include "liquidio_common.h" 27 #include "octeon_droq.h" 28 #include "octeon_iq.h" 29 #include "response_manager.h" 30 #include "octeon_device.h" 31 #include "octeon_main.h" 32 #include "octeon_network.h" 33 #include "cn66xx_regs.h" 34 #include "cn66xx_device.h" 35 #include "liquidio_image.h" 36 #include "octeon_mem_ops.h" 37 38 /** Default configuration 39 * for CN66XX OCTEON Models. 40 */ 41 static struct octeon_config default_cn66xx_conf = { 42 .card_type = LIO_210SV, 43 .card_name = LIO_210SV_NAME, 44 45 /** IQ attributes */ 46 .iq = { 47 .max_iqs = CN6XXX_CFG_IO_QUEUES, 48 .pending_list_size = 49 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES), 50 .instr_type = OCTEON_64BYTE_INSTR, 51 .db_min = CN6XXX_DB_MIN, 52 .db_timeout = CN6XXX_DB_TIMEOUT, 53 } 54 , 55 56 /** OQ attributes */ 57 .oq = { 58 .max_oqs = CN6XXX_CFG_IO_QUEUES, 59 .info_ptr = OCTEON_OQ_INFOPTR_MODE, 60 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD, 61 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT, 62 .oq_intr_time = CN6XXX_OQ_INTR_TIME, 63 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR, 64 } 65 , 66 67 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_66XX, 68 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 69 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 70 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE, 71 72 /* For ethernet interface 0: Port cfg Attributes */ 73 .nic_if_cfg[0] = { 74 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 75 .max_txqs = MAX_TXQS_PER_INTF, 76 77 /* Actual configured value. Range could be: 1...max_txqs */ 78 .num_txqs = DEF_TXQS_PER_INTF, 79 80 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 81 .max_rxqs = MAX_RXQS_PER_INTF, 82 83 /* Actual configured value. Range could be: 1...max_rxqs */ 84 .num_rxqs = DEF_RXQS_PER_INTF, 85 86 /* Num of desc for rx rings */ 87 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 88 89 /* Num of desc for tx rings */ 90 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 91 92 /* SKB size, We need not change buf size even for Jumbo frames. 93 * Octeon can send jumbo frames in 4 consecutive descriptors, 94 */ 95 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 96 97 .base_queue = BASE_QUEUE_NOT_REQUESTED, 98 99 .gmx_port_id = 0, 100 }, 101 102 .nic_if_cfg[1] = { 103 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 104 .max_txqs = MAX_TXQS_PER_INTF, 105 106 /* Actual configured value. Range could be: 1...max_txqs */ 107 .num_txqs = DEF_TXQS_PER_INTF, 108 109 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 110 .max_rxqs = MAX_RXQS_PER_INTF, 111 112 /* Actual configured value. Range could be: 1...max_rxqs */ 113 .num_rxqs = DEF_RXQS_PER_INTF, 114 115 /* Num of desc for rx rings */ 116 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 117 118 /* Num of desc for tx rings */ 119 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 120 121 /* SKB size, We need not change buf size even for Jumbo frames. 122 * Octeon can send jumbo frames in 4 consecutive descriptors, 123 */ 124 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 125 126 .base_queue = BASE_QUEUE_NOT_REQUESTED, 127 128 .gmx_port_id = 1, 129 }, 130 131 /** Miscellaneous attributes */ 132 .misc = { 133 /* Host driver link query interval */ 134 .oct_link_query_interval = 100, 135 136 /* Octeon link query interval */ 137 .host_link_query_interval = 500, 138 139 .enable_sli_oq_bp = 0, 140 141 /* Control queue group */ 142 .ctrlq_grp = 1, 143 } 144 , 145 }; 146 147 /** Default configuration 148 * for CN68XX OCTEON Model. 149 */ 150 151 static struct octeon_config default_cn68xx_conf = { 152 .card_type = LIO_410NV, 153 .card_name = LIO_410NV_NAME, 154 155 /** IQ attributes */ 156 .iq = { 157 .max_iqs = CN6XXX_CFG_IO_QUEUES, 158 .pending_list_size = 159 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES), 160 .instr_type = OCTEON_64BYTE_INSTR, 161 .db_min = CN6XXX_DB_MIN, 162 .db_timeout = CN6XXX_DB_TIMEOUT, 163 } 164 , 165 166 /** OQ attributes */ 167 .oq = { 168 .max_oqs = CN6XXX_CFG_IO_QUEUES, 169 .info_ptr = OCTEON_OQ_INFOPTR_MODE, 170 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD, 171 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT, 172 .oq_intr_time = CN6XXX_OQ_INTR_TIME, 173 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR, 174 } 175 , 176 177 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX, 178 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 179 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 180 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE, 181 182 .nic_if_cfg[0] = { 183 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 184 .max_txqs = MAX_TXQS_PER_INTF, 185 186 /* Actual configured value. Range could be: 1...max_txqs */ 187 .num_txqs = DEF_TXQS_PER_INTF, 188 189 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 190 .max_rxqs = MAX_RXQS_PER_INTF, 191 192 /* Actual configured value. Range could be: 1...max_rxqs */ 193 .num_rxqs = DEF_RXQS_PER_INTF, 194 195 /* Num of desc for rx rings */ 196 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 197 198 /* Num of desc for tx rings */ 199 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 200 201 /* SKB size, We need not change buf size even for Jumbo frames. 202 * Octeon can send jumbo frames in 4 consecutive descriptors, 203 */ 204 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 205 206 .base_queue = BASE_QUEUE_NOT_REQUESTED, 207 208 .gmx_port_id = 0, 209 }, 210 211 .nic_if_cfg[1] = { 212 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 213 .max_txqs = MAX_TXQS_PER_INTF, 214 215 /* Actual configured value. Range could be: 1...max_txqs */ 216 .num_txqs = DEF_TXQS_PER_INTF, 217 218 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 219 .max_rxqs = MAX_RXQS_PER_INTF, 220 221 /* Actual configured value. Range could be: 1...max_rxqs */ 222 .num_rxqs = DEF_RXQS_PER_INTF, 223 224 /* Num of desc for rx rings */ 225 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 226 227 /* Num of desc for tx rings */ 228 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 229 230 /* SKB size, We need not change buf size even for Jumbo frames. 231 * Octeon can send jumbo frames in 4 consecutive descriptors, 232 */ 233 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 234 235 .base_queue = BASE_QUEUE_NOT_REQUESTED, 236 237 .gmx_port_id = 1, 238 }, 239 240 .nic_if_cfg[2] = { 241 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 242 .max_txqs = MAX_TXQS_PER_INTF, 243 244 /* Actual configured value. Range could be: 1...max_txqs */ 245 .num_txqs = DEF_TXQS_PER_INTF, 246 247 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 248 .max_rxqs = MAX_RXQS_PER_INTF, 249 250 /* Actual configured value. Range could be: 1...max_rxqs */ 251 .num_rxqs = DEF_RXQS_PER_INTF, 252 253 /* Num of desc for rx rings */ 254 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 255 256 /* Num of desc for tx rings */ 257 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 258 259 /* SKB size, We need not change buf size even for Jumbo frames. 260 * Octeon can send jumbo frames in 4 consecutive descriptors, 261 */ 262 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 263 264 .base_queue = BASE_QUEUE_NOT_REQUESTED, 265 266 .gmx_port_id = 2, 267 }, 268 269 .nic_if_cfg[3] = { 270 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 271 .max_txqs = MAX_TXQS_PER_INTF, 272 273 /* Actual configured value. Range could be: 1...max_txqs */ 274 .num_txqs = DEF_TXQS_PER_INTF, 275 276 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 277 .max_rxqs = MAX_RXQS_PER_INTF, 278 279 /* Actual configured value. Range could be: 1...max_rxqs */ 280 .num_rxqs = DEF_RXQS_PER_INTF, 281 282 /* Num of desc for rx rings */ 283 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 284 285 /* Num of desc for tx rings */ 286 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 287 288 /* SKB size, We need not change buf size even for Jumbo frames. 289 * Octeon can send jumbo frames in 4 consecutive descriptors, 290 */ 291 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 292 293 .base_queue = BASE_QUEUE_NOT_REQUESTED, 294 295 .gmx_port_id = 3, 296 }, 297 298 /** Miscellaneous attributes */ 299 .misc = { 300 /* Host driver link query interval */ 301 .oct_link_query_interval = 100, 302 303 /* Octeon link query interval */ 304 .host_link_query_interval = 500, 305 306 .enable_sli_oq_bp = 0, 307 308 /* Control queue group */ 309 .ctrlq_grp = 1, 310 } 311 , 312 }; 313 314 /** Default configuration 315 * for CN68XX OCTEON Model. 316 */ 317 static struct octeon_config default_cn68xx_210nv_conf = { 318 .card_type = LIO_210NV, 319 .card_name = LIO_210NV_NAME, 320 321 /** IQ attributes */ 322 323 .iq = { 324 .max_iqs = CN6XXX_CFG_IO_QUEUES, 325 .pending_list_size = 326 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES), 327 .instr_type = OCTEON_64BYTE_INSTR, 328 .db_min = CN6XXX_DB_MIN, 329 .db_timeout = CN6XXX_DB_TIMEOUT, 330 } 331 , 332 333 /** OQ attributes */ 334 .oq = { 335 .max_oqs = CN6XXX_CFG_IO_QUEUES, 336 .info_ptr = OCTEON_OQ_INFOPTR_MODE, 337 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD, 338 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT, 339 .oq_intr_time = CN6XXX_OQ_INTR_TIME, 340 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR, 341 } 342 , 343 344 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX_210NV, 345 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 346 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 347 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE, 348 349 .nic_if_cfg[0] = { 350 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 351 .max_txqs = MAX_TXQS_PER_INTF, 352 353 /* Actual configured value. Range could be: 1...max_txqs */ 354 .num_txqs = DEF_TXQS_PER_INTF, 355 356 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 357 .max_rxqs = MAX_RXQS_PER_INTF, 358 359 /* Actual configured value. Range could be: 1...max_rxqs */ 360 .num_rxqs = DEF_RXQS_PER_INTF, 361 362 /* Num of desc for rx rings */ 363 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 364 365 /* Num of desc for tx rings */ 366 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 367 368 /* SKB size, We need not change buf size even for Jumbo frames. 369 * Octeon can send jumbo frames in 4 consecutive descriptors, 370 */ 371 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 372 373 .base_queue = BASE_QUEUE_NOT_REQUESTED, 374 375 .gmx_port_id = 0, 376 }, 377 378 .nic_if_cfg[1] = { 379 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 380 .max_txqs = MAX_TXQS_PER_INTF, 381 382 /* Actual configured value. Range could be: 1...max_txqs */ 383 .num_txqs = DEF_TXQS_PER_INTF, 384 385 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 386 .max_rxqs = MAX_RXQS_PER_INTF, 387 388 /* Actual configured value. Range could be: 1...max_rxqs */ 389 .num_rxqs = DEF_RXQS_PER_INTF, 390 391 /* Num of desc for rx rings */ 392 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS, 393 394 /* Num of desc for tx rings */ 395 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS, 396 397 /* SKB size, We need not change buf size even for Jumbo frames. 398 * Octeon can send jumbo frames in 4 consecutive descriptors, 399 */ 400 .rx_buf_size = CN6XXX_OQ_BUF_SIZE, 401 402 .base_queue = BASE_QUEUE_NOT_REQUESTED, 403 404 .gmx_port_id = 1, 405 }, 406 407 /** Miscellaneous attributes */ 408 .misc = { 409 /* Host driver link query interval */ 410 .oct_link_query_interval = 100, 411 412 /* Octeon link query interval */ 413 .host_link_query_interval = 500, 414 415 .enable_sli_oq_bp = 0, 416 417 /* Control queue group */ 418 .ctrlq_grp = 1, 419 } 420 , 421 }; 422 423 enum { 424 OCTEON_CONFIG_TYPE_DEFAULT = 0, 425 NUM_OCTEON_CONFS, 426 }; 427 428 static struct octeon_config_ptr { 429 u32 conf_type; 430 } oct_conf_info[MAX_OCTEON_DEVICES] = { 431 { 432 OCTEON_CONFIG_TYPE_DEFAULT, 433 }, { 434 OCTEON_CONFIG_TYPE_DEFAULT, 435 }, { 436 OCTEON_CONFIG_TYPE_DEFAULT, 437 }, { 438 OCTEON_CONFIG_TYPE_DEFAULT, 439 }, 440 }; 441 442 static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = { 443 "BEGIN", "PCI-MAP-DONE", "DISPATCH-INIT-DONE", 444 "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE", 445 "DROQ-INIT-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE", 446 "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET", 447 "INVALID" 448 }; 449 450 static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = { 451 "BASE", "NIC", "UNKNOWN"}; 452 453 static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES]; 454 static u32 octeon_device_count; 455 456 static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES]; 457 458 static void oct_set_config_info(int oct_id, int conf_type) 459 { 460 if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1)) 461 conf_type = OCTEON_CONFIG_TYPE_DEFAULT; 462 oct_conf_info[oct_id].conf_type = conf_type; 463 } 464 465 void octeon_init_device_list(int conf_type) 466 { 467 int i; 468 469 memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES)); 470 for (i = 0; i < MAX_OCTEON_DEVICES; i++) 471 oct_set_config_info(i, conf_type); 472 } 473 474 static void *__retrieve_octeon_config_info(struct octeon_device *oct, 475 u16 card_type) 476 { 477 u32 oct_id = oct->octeon_id; 478 void *ret = NULL; 479 480 switch (oct_conf_info[oct_id].conf_type) { 481 case OCTEON_CONFIG_TYPE_DEFAULT: 482 if (oct->chip_id == OCTEON_CN66XX) { 483 ret = (void *)&default_cn66xx_conf; 484 } else if ((oct->chip_id == OCTEON_CN68XX) && 485 (card_type == LIO_210NV)) { 486 ret = (void *)&default_cn68xx_210nv_conf; 487 } else if ((oct->chip_id == OCTEON_CN68XX) && 488 (card_type == LIO_410NV)) { 489 ret = (void *)&default_cn68xx_conf; 490 } 491 break; 492 default: 493 break; 494 } 495 return ret; 496 } 497 498 static int __verify_octeon_config_info(struct octeon_device *oct, void *conf) 499 { 500 switch (oct->chip_id) { 501 case OCTEON_CN66XX: 502 case OCTEON_CN68XX: 503 return lio_validate_cn6xxx_config_info(oct, conf); 504 505 default: 506 break; 507 } 508 509 return 1; 510 } 511 512 void *oct_get_config_info(struct octeon_device *oct, u16 card_type) 513 { 514 void *conf = NULL; 515 516 conf = __retrieve_octeon_config_info(oct, card_type); 517 if (!conf) 518 return NULL; 519 520 if (__verify_octeon_config_info(oct, conf)) { 521 dev_err(&oct->pci_dev->dev, "Configuration verification failed\n"); 522 return NULL; 523 } 524 525 return conf; 526 } 527 528 char *lio_get_state_string(atomic_t *state_ptr) 529 { 530 s32 istate = (s32)atomic_read(state_ptr); 531 532 if (istate > OCT_DEV_STATES || istate < 0) 533 return oct_dev_state_str[OCT_DEV_STATE_INVALID]; 534 return oct_dev_state_str[istate]; 535 } 536 537 static char *get_oct_app_string(u32 app_mode) 538 { 539 if (app_mode <= CVM_DRV_APP_END) 540 return oct_dev_app_str[app_mode - CVM_DRV_APP_START]; 541 return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START]; 542 } 543 544 u8 fbuf[4 * 1024 * 1024]; 545 546 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 547 size_t size) 548 { 549 int ret = 0; 550 u8 *p = fbuf; 551 u32 crc32_result; 552 u64 load_addr; 553 u32 image_len; 554 struct octeon_firmware_file_header *h; 555 u32 i, rem, base_len = strlen(LIQUIDIO_BASE_VERSION); 556 char *base; 557 558 if (size < sizeof(struct octeon_firmware_file_header)) { 559 dev_err(&oct->pci_dev->dev, "Firmware file too small (%d < %d).\n", 560 (u32)size, 561 (u32)sizeof(struct octeon_firmware_file_header)); 562 return -EINVAL; 563 } 564 565 h = (struct octeon_firmware_file_header *)data; 566 567 if (be32_to_cpu(h->magic) != LIO_NIC_MAGIC) { 568 dev_err(&oct->pci_dev->dev, "Unrecognized firmware file.\n"); 569 return -EINVAL; 570 } 571 572 crc32_result = crc32((unsigned int)~0, data, 573 sizeof(struct octeon_firmware_file_header) - 574 sizeof(u32)) ^ ~0U; 575 if (crc32_result != be32_to_cpu(h->crc32)) { 576 dev_err(&oct->pci_dev->dev, "Firmware CRC mismatch (0x%08x != 0x%08x).\n", 577 crc32_result, be32_to_cpu(h->crc32)); 578 return -EINVAL; 579 } 580 581 if (strncmp(LIQUIDIO_PACKAGE, h->version, strlen(LIQUIDIO_PACKAGE))) { 582 dev_err(&oct->pci_dev->dev, "Unmatched firmware package type. Expected %s, got %s.\n", 583 LIQUIDIO_PACKAGE, h->version); 584 return -EINVAL; 585 } 586 587 base = h->version + strlen(LIQUIDIO_PACKAGE); 588 ret = memcmp(LIQUIDIO_BASE_VERSION, base, base_len); 589 if (ret) { 590 dev_err(&oct->pci_dev->dev, "Unmatched firmware version. Expected %s.x, got %s.\n", 591 LIQUIDIO_BASE_VERSION, base); 592 return -EINVAL; 593 } 594 595 if (be32_to_cpu(h->num_images) > LIO_MAX_IMAGES) { 596 dev_err(&oct->pci_dev->dev, "Too many images in firmware file (%d).\n", 597 be32_to_cpu(h->num_images)); 598 return -EINVAL; 599 } 600 601 dev_info(&oct->pci_dev->dev, "Firmware version: %s\n", h->version); 602 snprintf(oct->fw_info.liquidio_firmware_version, 32, "LIQUIDIO: %s", 603 h->version); 604 605 data += sizeof(struct octeon_firmware_file_header); 606 607 dev_info(&oct->pci_dev->dev, "%s: Loading %d images\n", __func__, 608 be32_to_cpu(h->num_images)); 609 /* load all images */ 610 for (i = 0; i < be32_to_cpu(h->num_images); i++) { 611 load_addr = be64_to_cpu(h->desc[i].addr); 612 image_len = be32_to_cpu(h->desc[i].len); 613 614 dev_info(&oct->pci_dev->dev, "Loading firmware %d at %llx\n", 615 image_len, load_addr); 616 617 /* Write in 4MB chunks*/ 618 rem = image_len; 619 620 while (rem) { 621 if (rem < (4 * 1024 * 1024)) 622 size = rem; 623 else 624 size = 4 * 1024 * 1024; 625 626 memcpy(p, data, size); 627 628 /* download the image */ 629 octeon_pci_write_core_mem(oct, load_addr, p, (u32)size); 630 631 data += size; 632 rem -= (u32)size; 633 load_addr += size; 634 } 635 } 636 dev_info(&oct->pci_dev->dev, "Writing boot command: %s\n", 637 h->bootcmd); 638 639 /* Invoke the bootcmd */ 640 ret = octeon_console_send_cmd(oct, h->bootcmd, 50); 641 642 return 0; 643 } 644 645 void octeon_free_device_mem(struct octeon_device *oct) 646 { 647 int i; 648 649 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { 650 if (oct->io_qmask.oq & (1ULL << i)) 651 vfree(oct->droq[i]); 652 } 653 654 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { 655 if (oct->io_qmask.iq & (1ULL << i)) 656 vfree(oct->instr_queue[i]); 657 } 658 659 i = oct->octeon_id; 660 vfree(oct); 661 662 octeon_device[i] = NULL; 663 octeon_device_count--; 664 } 665 666 static struct octeon_device *octeon_allocate_device_mem(u32 pci_id, 667 u32 priv_size) 668 { 669 struct octeon_device *oct; 670 u8 *buf = NULL; 671 u32 octdevsize = 0, configsize = 0, size; 672 673 switch (pci_id) { 674 case OCTEON_CN68XX: 675 case OCTEON_CN66XX: 676 configsize = sizeof(struct octeon_cn6xxx); 677 break; 678 679 default: 680 pr_err("%s: Unknown PCI Device: 0x%x\n", 681 __func__, 682 pci_id); 683 return NULL; 684 } 685 686 if (configsize & 0x7) 687 configsize += (8 - (configsize & 0x7)); 688 689 octdevsize = sizeof(struct octeon_device); 690 if (octdevsize & 0x7) 691 octdevsize += (8 - (octdevsize & 0x7)); 692 693 if (priv_size & 0x7) 694 priv_size += (8 - (priv_size & 0x7)); 695 696 size = octdevsize + priv_size + configsize + 697 (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE); 698 699 buf = vmalloc(size); 700 if (!buf) 701 return NULL; 702 703 memset(buf, 0, size); 704 705 oct = (struct octeon_device *)buf; 706 oct->priv = (void *)(buf + octdevsize); 707 oct->chip = (void *)(buf + octdevsize + priv_size); 708 oct->dispatch.dlist = (struct octeon_dispatch *) 709 (buf + octdevsize + priv_size + configsize); 710 711 return oct; 712 } 713 714 struct octeon_device *octeon_allocate_device(u32 pci_id, 715 u32 priv_size) 716 { 717 u32 oct_idx = 0; 718 struct octeon_device *oct = NULL; 719 720 for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++) 721 if (!octeon_device[oct_idx]) 722 break; 723 724 if (oct_idx == MAX_OCTEON_DEVICES) 725 return NULL; 726 727 oct = octeon_allocate_device_mem(pci_id, priv_size); 728 if (!oct) 729 return NULL; 730 731 spin_lock_init(&oct->pci_win_lock); 732 spin_lock_init(&oct->mem_access_lock); 733 734 octeon_device_count++; 735 octeon_device[oct_idx] = oct; 736 737 oct->octeon_id = oct_idx; 738 snprintf(oct->device_name, sizeof(oct->device_name), 739 "LiquidIO%d", (oct->octeon_id)); 740 741 return oct; 742 } 743 744 /* this function is only for setting up the first queue */ 745 int octeon_setup_instr_queues(struct octeon_device *oct) 746 { 747 u32 num_descs = 0; 748 u32 iq_no = 0; 749 union oct_txpciq txpciq; 750 int numa_node = cpu_to_node(iq_no % num_online_cpus()); 751 752 /* this causes queue 0 to be default queue */ 753 if (OCTEON_CN6XXX(oct)) 754 num_descs = 755 CFG_GET_NUM_DEF_TX_DESCS(CHIP_FIELD(oct, cn6xxx, conf)); 756 757 oct->num_iqs = 0; 758 759 oct->instr_queue[0] = vmalloc_node(sizeof(*oct->instr_queue[0]), 760 numa_node); 761 if (!oct->instr_queue[0]) 762 oct->instr_queue[0] = 763 vmalloc(sizeof(struct octeon_instr_queue)); 764 if (!oct->instr_queue[0]) 765 return 1; 766 memset(oct->instr_queue[0], 0, sizeof(struct octeon_instr_queue)); 767 oct->instr_queue[0]->q_index = 0; 768 oct->instr_queue[0]->app_ctx = (void *)(size_t)0; 769 oct->instr_queue[0]->ifidx = 0; 770 txpciq.u64 = 0; 771 txpciq.s.q_no = iq_no; 772 txpciq.s.use_qpg = 0; 773 txpciq.s.qpg = 0; 774 if (octeon_init_instr_queue(oct, txpciq, num_descs)) { 775 /* prevent memory leak */ 776 vfree(oct->instr_queue[0]); 777 return 1; 778 } 779 780 oct->num_iqs++; 781 return 0; 782 } 783 784 int octeon_setup_output_queues(struct octeon_device *oct) 785 { 786 u32 num_descs = 0; 787 u32 desc_size = 0; 788 u32 oq_no = 0; 789 int numa_node = cpu_to_node(oq_no % num_online_cpus()); 790 791 /* this causes queue 0 to be default queue */ 792 if (OCTEON_CN6XXX(oct)) { 793 num_descs = 794 CFG_GET_NUM_DEF_RX_DESCS(CHIP_FIELD(oct, cn6xxx, conf)); 795 desc_size = 796 CFG_GET_DEF_RX_BUF_SIZE(CHIP_FIELD(oct, cn6xxx, conf)); 797 } 798 799 oct->num_oqs = 0; 800 oct->droq[0] = vmalloc_node(sizeof(*oct->droq[0]), numa_node); 801 if (!oct->droq[0]) 802 oct->droq[0] = vmalloc(sizeof(*oct->droq[0])); 803 if (!oct->droq[0]) 804 return 1; 805 806 if (octeon_init_droq(oct, oq_no, num_descs, desc_size, NULL)) 807 return 1; 808 oct->num_oqs++; 809 810 return 0; 811 } 812 813 void octeon_set_io_queues_off(struct octeon_device *oct) 814 { 815 /* Disable the i/p and o/p queues for this Octeon. */ 816 817 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0); 818 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0); 819 } 820 821 void octeon_set_droq_pkt_op(struct octeon_device *oct, 822 u32 q_no, 823 u32 enable) 824 { 825 u32 reg_val = 0; 826 827 /* Disable the i/p and o/p queues for this Octeon. */ 828 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB); 829 830 if (enable) 831 reg_val = reg_val | (1 << q_no); 832 else 833 reg_val = reg_val & (~(1 << q_no)); 834 835 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val); 836 } 837 838 int octeon_init_dispatch_list(struct octeon_device *oct) 839 { 840 u32 i; 841 842 oct->dispatch.count = 0; 843 844 for (i = 0; i < DISPATCH_LIST_SIZE; i++) { 845 oct->dispatch.dlist[i].opcode = 0; 846 INIT_LIST_HEAD(&oct->dispatch.dlist[i].list); 847 } 848 849 for (i = 0; i <= REQTYPE_LAST; i++) 850 octeon_register_reqtype_free_fn(oct, i, NULL); 851 852 spin_lock_init(&oct->dispatch.lock); 853 854 return 0; 855 } 856 857 void octeon_delete_dispatch_list(struct octeon_device *oct) 858 { 859 u32 i; 860 struct list_head freelist, *temp, *tmp2; 861 862 INIT_LIST_HEAD(&freelist); 863 864 spin_lock_bh(&oct->dispatch.lock); 865 866 for (i = 0; i < DISPATCH_LIST_SIZE; i++) { 867 struct list_head *dispatch; 868 869 dispatch = &oct->dispatch.dlist[i].list; 870 while (dispatch->next != dispatch) { 871 temp = dispatch->next; 872 list_del(temp); 873 list_add_tail(temp, &freelist); 874 } 875 876 oct->dispatch.dlist[i].opcode = 0; 877 } 878 879 oct->dispatch.count = 0; 880 881 spin_unlock_bh(&oct->dispatch.lock); 882 883 list_for_each_safe(temp, tmp2, &freelist) { 884 list_del(temp); 885 vfree(temp); 886 } 887 } 888 889 octeon_dispatch_fn_t 890 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode, 891 u16 subcode) 892 { 893 u32 idx; 894 struct list_head *dispatch; 895 octeon_dispatch_fn_t fn = NULL; 896 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode); 897 898 idx = combined_opcode & OCTEON_OPCODE_MASK; 899 900 spin_lock_bh(&octeon_dev->dispatch.lock); 901 902 if (octeon_dev->dispatch.count == 0) { 903 spin_unlock_bh(&octeon_dev->dispatch.lock); 904 return NULL; 905 } 906 907 if (!(octeon_dev->dispatch.dlist[idx].opcode)) { 908 spin_unlock_bh(&octeon_dev->dispatch.lock); 909 return NULL; 910 } 911 912 if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) { 913 fn = octeon_dev->dispatch.dlist[idx].dispatch_fn; 914 } else { 915 list_for_each(dispatch, 916 &octeon_dev->dispatch.dlist[idx].list) { 917 if (((struct octeon_dispatch *)dispatch)->opcode == 918 combined_opcode) { 919 fn = ((struct octeon_dispatch *) 920 dispatch)->dispatch_fn; 921 break; 922 } 923 } 924 } 925 926 spin_unlock_bh(&octeon_dev->dispatch.lock); 927 return fn; 928 } 929 930 /* octeon_register_dispatch_fn 931 * Parameters: 932 * octeon_id - id of the octeon device. 933 * opcode - opcode for which driver should call the registered function 934 * subcode - subcode for which driver should call the registered function 935 * fn - The function to call when a packet with "opcode" arrives in 936 * octeon output queues. 937 * fn_arg - The argument to be passed when calling function "fn". 938 * Description: 939 * Registers a function and its argument to be called when a packet 940 * arrives in Octeon output queues with "opcode". 941 * Returns: 942 * Success: 0 943 * Failure: 1 944 * Locks: 945 * No locks are held. 946 */ 947 int 948 octeon_register_dispatch_fn(struct octeon_device *oct, 949 u16 opcode, 950 u16 subcode, 951 octeon_dispatch_fn_t fn, void *fn_arg) 952 { 953 u32 idx; 954 octeon_dispatch_fn_t pfn; 955 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode); 956 957 idx = combined_opcode & OCTEON_OPCODE_MASK; 958 959 spin_lock_bh(&oct->dispatch.lock); 960 /* Add dispatch function to first level of lookup table */ 961 if (oct->dispatch.dlist[idx].opcode == 0) { 962 oct->dispatch.dlist[idx].opcode = combined_opcode; 963 oct->dispatch.dlist[idx].dispatch_fn = fn; 964 oct->dispatch.dlist[idx].arg = fn_arg; 965 oct->dispatch.count++; 966 spin_unlock_bh(&oct->dispatch.lock); 967 return 0; 968 } 969 970 spin_unlock_bh(&oct->dispatch.lock); 971 972 /* Check if there was a function already registered for this 973 * opcode/subcode. 974 */ 975 pfn = octeon_get_dispatch(oct, opcode, subcode); 976 if (!pfn) { 977 struct octeon_dispatch *dispatch; 978 979 dev_dbg(&oct->pci_dev->dev, 980 "Adding opcode to dispatch list linked list\n"); 981 dispatch = (struct octeon_dispatch *) 982 vmalloc(sizeof(struct octeon_dispatch)); 983 if (!dispatch) { 984 dev_err(&oct->pci_dev->dev, 985 "No memory to add dispatch function\n"); 986 return 1; 987 } 988 dispatch->opcode = combined_opcode; 989 dispatch->dispatch_fn = fn; 990 dispatch->arg = fn_arg; 991 992 /* Add dispatch function to linked list of fn ptrs 993 * at the hashed index. 994 */ 995 spin_lock_bh(&oct->dispatch.lock); 996 list_add(&dispatch->list, &oct->dispatch.dlist[idx].list); 997 oct->dispatch.count++; 998 spin_unlock_bh(&oct->dispatch.lock); 999 1000 } else { 1001 dev_err(&oct->pci_dev->dev, 1002 "Found previously registered dispatch fn for opcode/subcode: %x/%x\n", 1003 opcode, subcode); 1004 return 1; 1005 } 1006 1007 return 0; 1008 } 1009 1010 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf) 1011 { 1012 u32 i; 1013 char app_name[16]; 1014 struct octeon_device *oct = (struct octeon_device *)buf; 1015 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt; 1016 struct octeon_core_setup *cs = NULL; 1017 u32 num_nic_ports = 0; 1018 1019 if (OCTEON_CN6XXX(oct)) 1020 num_nic_ports = 1021 CFG_GET_NUM_NIC_PORTS(CHIP_FIELD(oct, cn6xxx, conf)); 1022 1023 if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) { 1024 dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n", 1025 atomic_read(&oct->status)); 1026 goto core_drv_init_err; 1027 } 1028 1029 strncpy(app_name, 1030 get_oct_app_string( 1031 (u32)recv_pkt->rh.r_core_drv_init.app_mode), 1032 sizeof(app_name) - 1); 1033 oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode; 1034 if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) { 1035 oct->fw_info.max_nic_ports = 1036 (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports; 1037 oct->fw_info.num_gmx_ports = 1038 (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports; 1039 } 1040 1041 if (oct->fw_info.max_nic_ports < num_nic_ports) { 1042 dev_err(&oct->pci_dev->dev, 1043 "Config has more ports than firmware allows (%d > %d).\n", 1044 num_nic_ports, oct->fw_info.max_nic_ports); 1045 goto core_drv_init_err; 1046 } 1047 oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags; 1048 oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode; 1049 1050 atomic_set(&oct->status, OCT_DEV_CORE_OK); 1051 1052 cs = &core_setup[oct->octeon_id]; 1053 1054 if (recv_pkt->buffer_size[0] != sizeof(*cs)) { 1055 dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n", 1056 (u32)sizeof(*cs), 1057 recv_pkt->buffer_size[0]); 1058 } 1059 1060 memcpy(cs, get_rbd(recv_pkt->buffer_ptr[0]), sizeof(*cs)); 1061 strncpy(oct->boardinfo.name, cs->boardname, OCT_BOARD_NAME); 1062 strncpy(oct->boardinfo.serial_number, cs->board_serial_number, 1063 OCT_SERIAL_LEN); 1064 1065 octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3)); 1066 1067 oct->boardinfo.major = cs->board_rev_major; 1068 oct->boardinfo.minor = cs->board_rev_minor; 1069 1070 dev_info(&oct->pci_dev->dev, 1071 "Running %s (%llu Hz)\n", 1072 app_name, CVM_CAST64(cs->corefreq)); 1073 1074 core_drv_init_err: 1075 for (i = 0; i < recv_pkt->buffer_count; i++) 1076 recv_buffer_free(recv_pkt->buffer_ptr[i]); 1077 octeon_free_recv_info(recv_info); 1078 return 0; 1079 } 1080 1081 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no) 1082 1083 { 1084 if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES(oct)) && 1085 (oct->io_qmask.iq & (1ULL << q_no))) 1086 return oct->instr_queue[q_no]->max_count; 1087 1088 return -1; 1089 } 1090 1091 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no) 1092 { 1093 if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES(oct)) && 1094 (oct->io_qmask.oq & (1ULL << q_no))) 1095 return oct->droq[q_no]->max_count; 1096 return -1; 1097 } 1098 1099 /* Retruns the host firmware handshake OCTEON specific configuration */ 1100 struct octeon_config *octeon_get_conf(struct octeon_device *oct) 1101 { 1102 struct octeon_config *default_oct_conf = NULL; 1103 1104 /* check the OCTEON Device model & return the corresponding octeon 1105 * configuration 1106 */ 1107 1108 if (OCTEON_CN6XXX(oct)) { 1109 default_oct_conf = 1110 (struct octeon_config *)(CHIP_FIELD(oct, cn6xxx, conf)); 1111 } 1112 1113 return default_oct_conf; 1114 } 1115 1116 /* scratch register address is same in all the OCT-II and CN70XX models */ 1117 #define CNXX_SLI_SCRATCH1 0x3C0 1118 1119 /** Get the octeon device pointer. 1120 * @param octeon_id - The id for which the octeon device pointer is required. 1121 * @return Success: Octeon device pointer. 1122 * @return Failure: NULL. 1123 */ 1124 struct octeon_device *lio_get_device(u32 octeon_id) 1125 { 1126 if (octeon_id >= MAX_OCTEON_DEVICES) 1127 return NULL; 1128 else 1129 return octeon_device[octeon_id]; 1130 } 1131 1132 u64 lio_pci_readq(struct octeon_device *oct, u64 addr) 1133 { 1134 u64 val64; 1135 unsigned long flags; 1136 u32 val32, addrhi; 1137 1138 spin_lock_irqsave(&oct->pci_win_lock, flags); 1139 1140 /* The windowed read happens when the LSB of the addr is written. 1141 * So write MSB first 1142 */ 1143 addrhi = (addr >> 32); 1144 if ((oct->chip_id == OCTEON_CN66XX) || (oct->chip_id == OCTEON_CN68XX)) 1145 addrhi |= 0x00060000; 1146 writel(addrhi, oct->reg_list.pci_win_rd_addr_hi); 1147 1148 /* Read back to preserve ordering of writes */ 1149 val32 = readl(oct->reg_list.pci_win_rd_addr_hi); 1150 1151 writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo); 1152 val32 = readl(oct->reg_list.pci_win_rd_addr_lo); 1153 1154 val64 = readq(oct->reg_list.pci_win_rd_data); 1155 1156 spin_unlock_irqrestore(&oct->pci_win_lock, flags); 1157 1158 return val64; 1159 } 1160 1161 void lio_pci_writeq(struct octeon_device *oct, 1162 u64 val, 1163 u64 addr) 1164 { 1165 u32 val32; 1166 unsigned long flags; 1167 1168 spin_lock_irqsave(&oct->pci_win_lock, flags); 1169 1170 writeq(addr, oct->reg_list.pci_win_wr_addr); 1171 1172 /* The write happens when the LSB is written. So write MSB first. */ 1173 writel(val >> 32, oct->reg_list.pci_win_wr_data_hi); 1174 /* Read the MSB to ensure ordering of writes. */ 1175 val32 = readl(oct->reg_list.pci_win_wr_data_hi); 1176 1177 writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo); 1178 1179 spin_unlock_irqrestore(&oct->pci_win_lock, flags); 1180 } 1181 1182 int octeon_mem_access_ok(struct octeon_device *oct) 1183 { 1184 u64 access_okay = 0; 1185 u64 lmc0_reset_ctl; 1186 1187 /* Check to make sure a DDR interface is enabled */ 1188 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL); 1189 access_okay = (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK); 1190 1191 return access_okay ? 0 : 1; 1192 } 1193 1194 int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout) 1195 { 1196 int ret = 1; 1197 u32 ms; 1198 1199 if (!timeout) 1200 return ret; 1201 1202 for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout)); 1203 ms += HZ / 10) { 1204 ret = octeon_mem_access_ok(oct); 1205 1206 /* wait 100 ms */ 1207 if (ret) 1208 schedule_timeout_uninterruptible(HZ / 10); 1209 } 1210 1211 return ret; 1212 } 1213 1214 /** Get the octeon id assigned to the octeon device passed as argument. 1215 * This function is exported to other modules. 1216 * @param dev - octeon device pointer passed as a void *. 1217 * @return octeon device id 1218 */ 1219 int lio_get_device_id(void *dev) 1220 { 1221 struct octeon_device *octeon_dev = (struct octeon_device *)dev; 1222 u32 i; 1223 1224 for (i = 0; i < MAX_OCTEON_DEVICES; i++) 1225 if (octeon_device[i] == octeon_dev) 1226 return octeon_dev->octeon_id; 1227 return -1; 1228 } 1229