1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /** 19 * @file octeon_console.c 20 */ 21 #include <linux/pci.h> 22 #include <linux/netdevice.h> 23 #include <linux/crc32.h> 24 #include "liquidio_common.h" 25 #include "octeon_droq.h" 26 #include "octeon_iq.h" 27 #include "response_manager.h" 28 #include "octeon_device.h" 29 #include "liquidio_image.h" 30 #include "octeon_mem_ops.h" 31 32 static void octeon_remote_lock(void); 33 static void octeon_remote_unlock(void); 34 static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct, 35 const char *name, 36 u32 flags); 37 static int octeon_console_read(struct octeon_device *oct, u32 console_num, 38 char *buffer, u32 buf_size); 39 static u32 console_bitmask; 40 module_param(console_bitmask, int, 0644); 41 MODULE_PARM_DESC(console_bitmask, 42 "Bitmask indicating which consoles have debug output redirected to syslog."); 43 44 #define MIN(a, b) min((a), (b)) 45 #define CAST_ULL(v) ((u64)(v)) 46 47 #define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR 0x0006c008 48 #define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR 0x0006c004 49 #define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR 0x0006c000 50 #define BOOTLOADER_PCI_READ_DESC_ADDR 0x0006c100 51 #define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN 248 52 53 #define OCTEON_PCI_IO_BUF_OWNER_OCTEON 0x00000001 54 #define OCTEON_PCI_IO_BUF_OWNER_HOST 0x00000002 55 56 /** Can change without breaking ABI */ 57 #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 58 59 /** minimum alignment of bootmem alloced blocks */ 60 #define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) 61 62 /** CVMX bootmem descriptor major version */ 63 #define CVMX_BOOTMEM_DESC_MAJ_VER 3 64 /* CVMX bootmem descriptor minor version */ 65 #define CVMX_BOOTMEM_DESC_MIN_VER 0 66 67 /* Current versions */ 68 #define OCTEON_PCI_CONSOLE_MAJOR_VERSION 1 69 #define OCTEON_PCI_CONSOLE_MINOR_VERSION 0 70 #define OCTEON_PCI_CONSOLE_BLOCK_NAME "__pci_console" 71 #define OCTEON_CONSOLE_POLL_INTERVAL_MS 100 /* 10 times per second */ 72 73 /* First three members of cvmx_bootmem_desc are left in original 74 * positions for backwards compatibility. 75 * Assumes big endian target 76 */ 77 struct cvmx_bootmem_desc { 78 /** spinlock to control access to list */ 79 u32 lock; 80 81 /** flags for indicating various conditions */ 82 u32 flags; 83 84 u64 head_addr; 85 86 /** incremented changed when incompatible changes made */ 87 u32 major_version; 88 89 /** incremented changed when compatible changes made, 90 * reset to zero when major incremented 91 */ 92 u32 minor_version; 93 94 u64 app_data_addr; 95 u64 app_data_size; 96 97 /** number of elements in named blocks array */ 98 u32 nb_num_blocks; 99 100 /** length of name array in bootmem blocks */ 101 u32 named_block_name_len; 102 103 /** address of named memory block descriptors */ 104 u64 named_block_array_addr; 105 }; 106 107 /* Structure that defines a single console. 108 * 109 * Note: when read_index == write_index, the buffer is empty. 110 * The actual usable size of each console is console_buf_size -1; 111 */ 112 struct octeon_pci_console { 113 u64 input_base_addr; 114 u32 input_read_index; 115 u32 input_write_index; 116 u64 output_base_addr; 117 u32 output_read_index; 118 u32 output_write_index; 119 u32 lock; 120 u32 buf_size; 121 }; 122 123 /* This is the main container structure that contains all the information 124 * about all PCI consoles. The address of this structure is passed to various 125 * routines that operation on PCI consoles. 126 */ 127 struct octeon_pci_console_desc { 128 u32 major_version; 129 u32 minor_version; 130 u32 lock; 131 u32 flags; 132 u32 num_consoles; 133 u32 pad; 134 /* must be 64 bit aligned here... */ 135 /* Array of addresses of octeon_pci_console structures */ 136 u64 console_addr_array[0]; 137 /* Implicit storage for console_addr_array */ 138 }; 139 140 /** 141 * \brief determines if a given console has debug enabled. 142 * @param console console to check 143 * @returns 1 = enabled. 0 otherwise 144 */ 145 static int octeon_console_debug_enabled(u32 console) 146 { 147 return (console_bitmask >> (console)) & 0x1; 148 } 149 150 /** 151 * This function is the implementation of the get macros defined 152 * for individual structure members. The argument are generated 153 * by the macros inorder to read only the needed memory. 154 * 155 * @param oct Pointer to current octeon device 156 * @param base 64bit physical address of the complete structure 157 * @param offset Offset from the beginning of the structure to the member being 158 * accessed. 159 * @param size Size of the structure member. 160 * 161 * @return Value of the structure member promoted into a u64. 162 */ 163 static inline u64 __cvmx_bootmem_desc_get(struct octeon_device *oct, 164 u64 base, 165 u32 offset, 166 u32 size) 167 { 168 base = (1ull << 63) | (base + offset); 169 switch (size) { 170 case 4: 171 return octeon_read_device_mem32(oct, base); 172 case 8: 173 return octeon_read_device_mem64(oct, base); 174 default: 175 return 0; 176 } 177 } 178 179 /** 180 * This function retrieves the string name of a named block. It is 181 * more complicated than a simple memcpy() since the named block 182 * descriptor may not be directly accessible. 183 * 184 * @param addr Physical address of the named block descriptor 185 * @param str String to receive the named block string name 186 * @param len Length of the string buffer, which must match the length 187 * stored in the bootmem descriptor. 188 */ 189 static void CVMX_BOOTMEM_NAMED_GET_NAME(struct octeon_device *oct, 190 u64 addr, 191 char *str, 192 u32 len) 193 { 194 addr += offsetof(struct cvmx_bootmem_named_block_desc, name); 195 octeon_pci_read_core_mem(oct, addr, (u8 *)str, len); 196 str[len] = 0; 197 } 198 199 /* See header file for descriptions of functions */ 200 201 /** 202 * Check the version information on the bootmem descriptor 203 * 204 * @param exact_match 205 * Exact major version to check against. A zero means 206 * check that the version supports named blocks. 207 * 208 * @return Zero if the version is correct. Negative if the version is 209 * incorrect. Failures also cause a message to be displayed. 210 */ 211 static int __cvmx_bootmem_check_version(struct octeon_device *oct, 212 u32 exact_match) 213 { 214 u32 major_version; 215 u32 minor_version; 216 217 if (!oct->bootmem_desc_addr) 218 oct->bootmem_desc_addr = 219 octeon_read_device_mem64(oct, 220 BOOTLOADER_PCI_READ_DESC_ADDR); 221 major_version = (u32)__cvmx_bootmem_desc_get( 222 oct, oct->bootmem_desc_addr, 223 offsetof(struct cvmx_bootmem_desc, major_version), 224 FIELD_SIZEOF(struct cvmx_bootmem_desc, major_version)); 225 minor_version = (u32)__cvmx_bootmem_desc_get( 226 oct, oct->bootmem_desc_addr, 227 offsetof(struct cvmx_bootmem_desc, minor_version), 228 FIELD_SIZEOF(struct cvmx_bootmem_desc, minor_version)); 229 230 dev_dbg(&oct->pci_dev->dev, "%s: major_version=%d\n", __func__, 231 major_version); 232 if ((major_version > 3) || 233 (exact_match && major_version != exact_match)) { 234 dev_err(&oct->pci_dev->dev, "bootmem ver mismatch %d.%d addr:0x%llx\n", 235 major_version, minor_version, 236 CAST_ULL(oct->bootmem_desc_addr)); 237 return -1; 238 } else { 239 return 0; 240 } 241 } 242 243 static const struct cvmx_bootmem_named_block_desc 244 *__cvmx_bootmem_find_named_block_flags(struct octeon_device *oct, 245 const char *name, u32 flags) 246 { 247 struct cvmx_bootmem_named_block_desc *desc = 248 &oct->bootmem_named_block_desc; 249 u64 named_addr = cvmx_bootmem_phy_named_block_find(oct, name, flags); 250 251 if (named_addr) { 252 desc->base_addr = __cvmx_bootmem_desc_get( 253 oct, named_addr, 254 offsetof(struct cvmx_bootmem_named_block_desc, 255 base_addr), 256 FIELD_SIZEOF( 257 struct cvmx_bootmem_named_block_desc, 258 base_addr)); 259 desc->size = __cvmx_bootmem_desc_get(oct, named_addr, 260 offsetof(struct cvmx_bootmem_named_block_desc, 261 size), 262 FIELD_SIZEOF( 263 struct cvmx_bootmem_named_block_desc, 264 size)); 265 266 strncpy(desc->name, name, sizeof(desc->name)); 267 desc->name[sizeof(desc->name) - 1] = 0; 268 return &oct->bootmem_named_block_desc; 269 } else { 270 return NULL; 271 } 272 } 273 274 static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct, 275 const char *name, 276 u32 flags) 277 { 278 u64 result = 0; 279 280 if (!__cvmx_bootmem_check_version(oct, 3)) { 281 u32 i; 282 283 u64 named_block_array_addr = __cvmx_bootmem_desc_get( 284 oct, oct->bootmem_desc_addr, 285 offsetof(struct cvmx_bootmem_desc, 286 named_block_array_addr), 287 FIELD_SIZEOF(struct cvmx_bootmem_desc, 288 named_block_array_addr)); 289 u32 num_blocks = (u32)__cvmx_bootmem_desc_get( 290 oct, oct->bootmem_desc_addr, 291 offsetof(struct cvmx_bootmem_desc, 292 nb_num_blocks), 293 FIELD_SIZEOF(struct cvmx_bootmem_desc, 294 nb_num_blocks)); 295 296 u32 name_length = (u32)__cvmx_bootmem_desc_get( 297 oct, oct->bootmem_desc_addr, 298 offsetof(struct cvmx_bootmem_desc, 299 named_block_name_len), 300 FIELD_SIZEOF(struct cvmx_bootmem_desc, 301 named_block_name_len)); 302 303 u64 named_addr = named_block_array_addr; 304 305 for (i = 0; i < num_blocks; i++) { 306 u64 named_size = __cvmx_bootmem_desc_get( 307 oct, named_addr, 308 offsetof( 309 struct cvmx_bootmem_named_block_desc, 310 size), 311 FIELD_SIZEOF( 312 struct cvmx_bootmem_named_block_desc, 313 size)); 314 315 if (name && named_size) { 316 char *name_tmp = 317 kmalloc(name_length + 1, GFP_KERNEL); 318 if (!name_tmp) 319 break; 320 321 CVMX_BOOTMEM_NAMED_GET_NAME(oct, named_addr, 322 name_tmp, 323 name_length); 324 if (!strncmp(name, name_tmp, name_length)) { 325 result = named_addr; 326 kfree(name_tmp); 327 break; 328 } 329 kfree(name_tmp); 330 } else if (!name && !named_size) { 331 result = named_addr; 332 break; 333 } 334 335 named_addr += 336 sizeof(struct cvmx_bootmem_named_block_desc); 337 } 338 } 339 return result; 340 } 341 342 /** 343 * Find a named block on the remote Octeon 344 * 345 * @param name Name of block to find 346 * @param base_addr Address the block is at (OUTPUT) 347 * @param size The size of the block (OUTPUT) 348 * 349 * @return Zero on success, One on failure. 350 */ 351 static int octeon_named_block_find(struct octeon_device *oct, const char *name, 352 u64 *base_addr, u64 *size) 353 { 354 const struct cvmx_bootmem_named_block_desc *named_block; 355 356 octeon_remote_lock(); 357 named_block = __cvmx_bootmem_find_named_block_flags(oct, name, 0); 358 octeon_remote_unlock(); 359 if (named_block) { 360 *base_addr = named_block->base_addr; 361 *size = named_block->size; 362 return 0; 363 } 364 return 1; 365 } 366 367 static void octeon_remote_lock(void) 368 { 369 /* fill this in if any sharing is needed */ 370 } 371 372 static void octeon_remote_unlock(void) 373 { 374 /* fill this in if any sharing is needed */ 375 } 376 377 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 378 u32 wait_hundredths) 379 { 380 u32 len = (u32)strlen(cmd_str); 381 382 dev_dbg(&oct->pci_dev->dev, "sending \"%s\" to bootloader\n", cmd_str); 383 384 if (len > BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1) { 385 dev_err(&oct->pci_dev->dev, "Command string too long, max length is: %d\n", 386 BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1); 387 return -1; 388 } 389 390 if (octeon_wait_for_bootloader(oct, wait_hundredths) != 0) { 391 dev_err(&oct->pci_dev->dev, "Bootloader not ready for command.\n"); 392 return -1; 393 } 394 395 /* Write command to bootloader */ 396 octeon_remote_lock(); 397 octeon_pci_write_core_mem(oct, BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR, 398 (u8 *)cmd_str, len); 399 octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR, 400 len); 401 octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR, 402 OCTEON_PCI_IO_BUF_OWNER_OCTEON); 403 404 /* Bootloader should accept command very quickly 405 * if it really was ready 406 */ 407 if (octeon_wait_for_bootloader(oct, 200) != 0) { 408 octeon_remote_unlock(); 409 dev_err(&oct->pci_dev->dev, "Bootloader did not accept command.\n"); 410 return -1; 411 } 412 octeon_remote_unlock(); 413 return 0; 414 } 415 416 int octeon_wait_for_bootloader(struct octeon_device *oct, 417 u32 wait_time_hundredths) 418 { 419 dev_dbg(&oct->pci_dev->dev, "waiting %d0 ms for bootloader\n", 420 wait_time_hundredths); 421 422 if (octeon_mem_access_ok(oct)) 423 return -1; 424 425 while (wait_time_hundredths > 0 && 426 octeon_read_device_mem32(oct, 427 BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR) 428 != OCTEON_PCI_IO_BUF_OWNER_HOST) { 429 if (--wait_time_hundredths <= 0) 430 return -1; 431 schedule_timeout_uninterruptible(HZ / 100); 432 } 433 return 0; 434 } 435 436 static void octeon_console_handle_result(struct octeon_device *oct, 437 size_t console_num) 438 { 439 struct octeon_console *console; 440 441 console = &oct->console[console_num]; 442 443 console->waiting = 0; 444 } 445 446 static char console_buffer[OCTEON_CONSOLE_MAX_READ_BYTES]; 447 448 static void output_console_line(struct octeon_device *oct, 449 struct octeon_console *console, 450 size_t console_num, 451 char *console_buffer, 452 s32 bytes_read) 453 { 454 char *line; 455 s32 i; 456 457 line = console_buffer; 458 for (i = 0; i < bytes_read; i++) { 459 /* Output a line at a time, prefixed */ 460 if (console_buffer[i] == '\n') { 461 console_buffer[i] = '\0'; 462 if (console->leftover[0]) { 463 dev_info(&oct->pci_dev->dev, "%lu: %s%s\n", 464 console_num, console->leftover, 465 line); 466 console->leftover[0] = '\0'; 467 } else { 468 dev_info(&oct->pci_dev->dev, "%lu: %s\n", 469 console_num, line); 470 } 471 line = &console_buffer[i + 1]; 472 } 473 } 474 475 /* Save off any leftovers */ 476 if (line != &console_buffer[bytes_read]) { 477 console_buffer[bytes_read] = '\0'; 478 strcpy(console->leftover, line); 479 } 480 } 481 482 static void check_console(struct work_struct *work) 483 { 484 s32 bytes_read, tries, total_read; 485 struct octeon_console *console; 486 struct cavium_wk *wk = (struct cavium_wk *)work; 487 struct octeon_device *oct = (struct octeon_device *)wk->ctxptr; 488 u32 console_num = (u32)wk->ctxul; 489 u32 delay; 490 491 console = &oct->console[console_num]; 492 tries = 0; 493 total_read = 0; 494 495 do { 496 /* Take console output regardless of whether it will 497 * be logged 498 */ 499 bytes_read = 500 octeon_console_read(oct, console_num, console_buffer, 501 sizeof(console_buffer) - 1); 502 if (bytes_read > 0) { 503 total_read += bytes_read; 504 if (console->waiting) 505 octeon_console_handle_result(oct, console_num); 506 if (octeon_console_debug_enabled(console_num)) { 507 output_console_line(oct, console, console_num, 508 console_buffer, bytes_read); 509 } 510 } else if (bytes_read < 0) { 511 dev_err(&oct->pci_dev->dev, "Error reading console %u, ret=%d\n", 512 console_num, bytes_read); 513 } 514 515 tries++; 516 } while ((bytes_read > 0) && (tries < 16)); 517 518 /* If nothing is read after polling the console, 519 * output any leftovers if any 520 */ 521 if (octeon_console_debug_enabled(console_num) && 522 (total_read == 0) && (console->leftover[0])) { 523 dev_info(&oct->pci_dev->dev, "%u: %s\n", 524 console_num, console->leftover); 525 console->leftover[0] = '\0'; 526 } 527 528 delay = OCTEON_CONSOLE_POLL_INTERVAL_MS; 529 530 schedule_delayed_work(&wk->work, msecs_to_jiffies(delay)); 531 } 532 533 int octeon_init_consoles(struct octeon_device *oct) 534 { 535 int ret = 0; 536 u64 addr, size; 537 538 ret = octeon_mem_access_ok(oct); 539 if (ret) { 540 dev_err(&oct->pci_dev->dev, "Memory access not okay'\n"); 541 return ret; 542 } 543 544 ret = octeon_named_block_find(oct, OCTEON_PCI_CONSOLE_BLOCK_NAME, &addr, 545 &size); 546 if (ret) { 547 dev_err(&oct->pci_dev->dev, "Could not find console '%s'\n", 548 OCTEON_PCI_CONSOLE_BLOCK_NAME); 549 return ret; 550 } 551 552 /* num_consoles > 0, is an indication that the consoles 553 * are accessible 554 */ 555 oct->num_consoles = octeon_read_device_mem32(oct, 556 addr + offsetof(struct octeon_pci_console_desc, 557 num_consoles)); 558 oct->console_desc_addr = addr; 559 560 dev_dbg(&oct->pci_dev->dev, "Initialized consoles. %d available\n", 561 oct->num_consoles); 562 563 return ret; 564 } 565 566 int octeon_add_console(struct octeon_device *oct, u32 console_num) 567 { 568 int ret = 0; 569 u32 delay; 570 u64 coreaddr; 571 struct delayed_work *work; 572 struct octeon_console *console; 573 574 if (console_num >= oct->num_consoles) { 575 dev_err(&oct->pci_dev->dev, 576 "trying to read from console number %d when only 0 to %d exist\n", 577 console_num, oct->num_consoles); 578 } else { 579 console = &oct->console[console_num]; 580 581 console->waiting = 0; 582 583 coreaddr = oct->console_desc_addr + console_num * 8 + 584 offsetof(struct octeon_pci_console_desc, 585 console_addr_array); 586 console->addr = octeon_read_device_mem64(oct, coreaddr); 587 coreaddr = console->addr + offsetof(struct octeon_pci_console, 588 buf_size); 589 console->buffer_size = octeon_read_device_mem32(oct, coreaddr); 590 coreaddr = console->addr + offsetof(struct octeon_pci_console, 591 input_base_addr); 592 console->input_base_addr = 593 octeon_read_device_mem64(oct, coreaddr); 594 coreaddr = console->addr + offsetof(struct octeon_pci_console, 595 output_base_addr); 596 console->output_base_addr = 597 octeon_read_device_mem64(oct, coreaddr); 598 console->leftover[0] = '\0'; 599 600 work = &oct->console_poll_work[console_num].work; 601 602 INIT_DELAYED_WORK(work, check_console); 603 oct->console_poll_work[console_num].ctxptr = (void *)oct; 604 oct->console_poll_work[console_num].ctxul = console_num; 605 delay = OCTEON_CONSOLE_POLL_INTERVAL_MS; 606 schedule_delayed_work(work, msecs_to_jiffies(delay)); 607 608 if (octeon_console_debug_enabled(console_num)) { 609 ret = octeon_console_send_cmd(oct, 610 "setenv pci_console_active 1", 611 2000); 612 } 613 614 console->active = 1; 615 } 616 617 return ret; 618 } 619 620 /** 621 * Removes all consoles 622 * 623 * @param oct octeon device 624 */ 625 void octeon_remove_consoles(struct octeon_device *oct) 626 { 627 u32 i; 628 struct octeon_console *console; 629 630 for (i = 0; i < oct->num_consoles; i++) { 631 console = &oct->console[i]; 632 633 if (!console->active) 634 continue; 635 636 cancel_delayed_work_sync(&oct->console_poll_work[i]. 637 work); 638 console->addr = 0; 639 console->buffer_size = 0; 640 console->input_base_addr = 0; 641 console->output_base_addr = 0; 642 } 643 644 oct->num_consoles = 0; 645 } 646 647 static inline int octeon_console_free_bytes(u32 buffer_size, 648 u32 wr_idx, 649 u32 rd_idx) 650 { 651 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 652 return -1; 653 654 return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size; 655 } 656 657 static inline int octeon_console_avail_bytes(u32 buffer_size, 658 u32 wr_idx, 659 u32 rd_idx) 660 { 661 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 662 return -1; 663 664 return buffer_size - 1 - 665 octeon_console_free_bytes(buffer_size, wr_idx, rd_idx); 666 } 667 668 static int octeon_console_read(struct octeon_device *oct, u32 console_num, 669 char *buffer, u32 buf_size) 670 { 671 int bytes_to_read; 672 u32 rd_idx, wr_idx; 673 struct octeon_console *console; 674 675 if (console_num >= oct->num_consoles) { 676 dev_err(&oct->pci_dev->dev, "Attempted to read from disabled console %d\n", 677 console_num); 678 return 0; 679 } 680 681 console = &oct->console[console_num]; 682 683 /* Check to see if any data is available. 684 * Maybe optimize this with 64-bit read. 685 */ 686 rd_idx = octeon_read_device_mem32(oct, console->addr + 687 offsetof(struct octeon_pci_console, output_read_index)); 688 wr_idx = octeon_read_device_mem32(oct, console->addr + 689 offsetof(struct octeon_pci_console, output_write_index)); 690 691 bytes_to_read = octeon_console_avail_bytes(console->buffer_size, 692 wr_idx, rd_idx); 693 if (bytes_to_read <= 0) 694 return bytes_to_read; 695 696 bytes_to_read = MIN(bytes_to_read, (s32)buf_size); 697 698 /* Check to see if what we want to read is not contiguous, and limit 699 * ourselves to the contiguous block 700 */ 701 if (rd_idx + bytes_to_read >= console->buffer_size) 702 bytes_to_read = console->buffer_size - rd_idx; 703 704 octeon_pci_read_core_mem(oct, console->output_base_addr + rd_idx, 705 (u8 *)buffer, bytes_to_read); 706 octeon_write_device_mem32(oct, console->addr + 707 offsetof(struct octeon_pci_console, 708 output_read_index), 709 (rd_idx + bytes_to_read) % 710 console->buffer_size); 711 712 return bytes_to_read; 713 } 714 715 #define FBUF_SIZE (4 * 1024 * 1024) 716 u8 fbuf[FBUF_SIZE]; 717 718 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 719 size_t size) 720 { 721 int ret = 0; 722 u8 *p = fbuf; 723 u32 crc32_result; 724 u64 load_addr; 725 u32 image_len; 726 struct octeon_firmware_file_header *h; 727 u32 i, rem; 728 729 if (size < sizeof(struct octeon_firmware_file_header)) { 730 dev_err(&oct->pci_dev->dev, "Firmware file too small (%d < %d).\n", 731 (u32)size, 732 (u32)sizeof(struct octeon_firmware_file_header)); 733 return -EINVAL; 734 } 735 736 h = (struct octeon_firmware_file_header *)data; 737 738 if (be32_to_cpu(h->magic) != LIO_NIC_MAGIC) { 739 dev_err(&oct->pci_dev->dev, "Unrecognized firmware file.\n"); 740 return -EINVAL; 741 } 742 743 crc32_result = crc32((unsigned int)~0, data, 744 sizeof(struct octeon_firmware_file_header) - 745 sizeof(u32)) ^ ~0U; 746 if (crc32_result != be32_to_cpu(h->crc32)) { 747 dev_err(&oct->pci_dev->dev, "Firmware CRC mismatch (0x%08x != 0x%08x).\n", 748 crc32_result, be32_to_cpu(h->crc32)); 749 return -EINVAL; 750 } 751 752 if (strncmp(LIQUIDIO_PACKAGE, h->version, strlen(LIQUIDIO_PACKAGE))) { 753 dev_err(&oct->pci_dev->dev, "Unmatched firmware package type. Expected %s, got %s.\n", 754 LIQUIDIO_PACKAGE, h->version); 755 return -EINVAL; 756 } 757 758 if (memcmp(LIQUIDIO_BASE_VERSION, h->version + strlen(LIQUIDIO_PACKAGE), 759 strlen(LIQUIDIO_BASE_VERSION))) { 760 dev_err(&oct->pci_dev->dev, "Unmatched firmware version. Expected %s.x, got %s.\n", 761 LIQUIDIO_BASE_VERSION, 762 h->version + strlen(LIQUIDIO_PACKAGE)); 763 return -EINVAL; 764 } 765 766 if (be32_to_cpu(h->num_images) > LIO_MAX_IMAGES) { 767 dev_err(&oct->pci_dev->dev, "Too many images in firmware file (%d).\n", 768 be32_to_cpu(h->num_images)); 769 return -EINVAL; 770 } 771 772 dev_info(&oct->pci_dev->dev, "Firmware version: %s\n", h->version); 773 snprintf(oct->fw_info.liquidio_firmware_version, 32, "LIQUIDIO: %s", 774 h->version); 775 776 data += sizeof(struct octeon_firmware_file_header); 777 778 dev_info(&oct->pci_dev->dev, "%s: Loading %d images\n", __func__, 779 be32_to_cpu(h->num_images)); 780 /* load all images */ 781 for (i = 0; i < be32_to_cpu(h->num_images); i++) { 782 load_addr = be64_to_cpu(h->desc[i].addr); 783 image_len = be32_to_cpu(h->desc[i].len); 784 785 dev_info(&oct->pci_dev->dev, "Loading firmware %d at %llx\n", 786 image_len, load_addr); 787 788 /* Write in 4MB chunks*/ 789 rem = image_len; 790 791 while (rem) { 792 if (rem < FBUF_SIZE) 793 size = rem; 794 else 795 size = FBUF_SIZE; 796 797 memcpy(p, data, size); 798 799 /* download the image */ 800 octeon_pci_write_core_mem(oct, load_addr, p, (u32)size); 801 802 data += size; 803 rem -= (u32)size; 804 load_addr += size; 805 } 806 } 807 dev_info(&oct->pci_dev->dev, "Writing boot command: %s\n", 808 h->bootcmd); 809 810 /* Invoke the bootcmd */ 811 ret = octeon_console_send_cmd(oct, h->bootcmd, 50); 812 813 return 0; 814 } 815