1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /** 19 * @file octeon_console.c 20 */ 21 #include <linux/moduleparam.h> 22 #include <linux/pci.h> 23 #include <linux/netdevice.h> 24 #include <linux/crc32.h> 25 #include "liquidio_common.h" 26 #include "octeon_droq.h" 27 #include "octeon_iq.h" 28 #include "response_manager.h" 29 #include "octeon_device.h" 30 #include "liquidio_image.h" 31 #include "octeon_mem_ops.h" 32 33 static void octeon_remote_lock(void); 34 static void octeon_remote_unlock(void); 35 static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct, 36 const char *name, 37 u32 flags); 38 static int octeon_console_read(struct octeon_device *oct, u32 console_num, 39 char *buffer, u32 buf_size); 40 static u32 console_bitmask; 41 module_param(console_bitmask, int, 0644); 42 MODULE_PARM_DESC(console_bitmask, 43 "Bitmask indicating which consoles have debug output redirected to syslog."); 44 45 #define MIN(a, b) min((a), (b)) 46 #define CAST_ULL(v) ((u64)(v)) 47 48 #define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR 0x0006c008 49 #define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR 0x0006c004 50 #define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR 0x0006c000 51 #define BOOTLOADER_PCI_READ_DESC_ADDR 0x0006c100 52 #define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN 248 53 54 #define OCTEON_PCI_IO_BUF_OWNER_OCTEON 0x00000001 55 #define OCTEON_PCI_IO_BUF_OWNER_HOST 0x00000002 56 57 /** Can change without breaking ABI */ 58 #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 59 60 /** minimum alignment of bootmem alloced blocks */ 61 #define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) 62 63 /** CVMX bootmem descriptor major version */ 64 #define CVMX_BOOTMEM_DESC_MAJ_VER 3 65 /* CVMX bootmem descriptor minor version */ 66 #define CVMX_BOOTMEM_DESC_MIN_VER 0 67 68 /* Current versions */ 69 #define OCTEON_PCI_CONSOLE_MAJOR_VERSION 1 70 #define OCTEON_PCI_CONSOLE_MINOR_VERSION 0 71 #define OCTEON_PCI_CONSOLE_BLOCK_NAME "__pci_console" 72 #define OCTEON_CONSOLE_POLL_INTERVAL_MS 100 /* 10 times per second */ 73 74 /* First three members of cvmx_bootmem_desc are left in original 75 * positions for backwards compatibility. 76 * Assumes big endian target 77 */ 78 struct cvmx_bootmem_desc { 79 /** spinlock to control access to list */ 80 u32 lock; 81 82 /** flags for indicating various conditions */ 83 u32 flags; 84 85 u64 head_addr; 86 87 /** incremented changed when incompatible changes made */ 88 u32 major_version; 89 90 /** incremented changed when compatible changes made, 91 * reset to zero when major incremented 92 */ 93 u32 minor_version; 94 95 u64 app_data_addr; 96 u64 app_data_size; 97 98 /** number of elements in named blocks array */ 99 u32 nb_num_blocks; 100 101 /** length of name array in bootmem blocks */ 102 u32 named_block_name_len; 103 104 /** address of named memory block descriptors */ 105 u64 named_block_array_addr; 106 }; 107 108 /* Structure that defines a single console. 109 * 110 * Note: when read_index == write_index, the buffer is empty. 111 * The actual usable size of each console is console_buf_size -1; 112 */ 113 struct octeon_pci_console { 114 u64 input_base_addr; 115 u32 input_read_index; 116 u32 input_write_index; 117 u64 output_base_addr; 118 u32 output_read_index; 119 u32 output_write_index; 120 u32 lock; 121 u32 buf_size; 122 }; 123 124 /* This is the main container structure that contains all the information 125 * about all PCI consoles. The address of this structure is passed to various 126 * routines that operation on PCI consoles. 127 */ 128 struct octeon_pci_console_desc { 129 u32 major_version; 130 u32 minor_version; 131 u32 lock; 132 u32 flags; 133 u32 num_consoles; 134 u32 pad; 135 /* must be 64 bit aligned here... */ 136 /* Array of addresses of octeon_pci_console structures */ 137 u64 console_addr_array[0]; 138 /* Implicit storage for console_addr_array */ 139 }; 140 141 /** 142 * \brief determines if a given console has debug enabled. 143 * @param console console to check 144 * @returns 1 = enabled. 0 otherwise 145 */ 146 static int octeon_console_debug_enabled(u32 console) 147 { 148 return (console_bitmask >> (console)) & 0x1; 149 } 150 151 /** 152 * This function is the implementation of the get macros defined 153 * for individual structure members. The argument are generated 154 * by the macros inorder to read only the needed memory. 155 * 156 * @param oct Pointer to current octeon device 157 * @param base 64bit physical address of the complete structure 158 * @param offset Offset from the beginning of the structure to the member being 159 * accessed. 160 * @param size Size of the structure member. 161 * 162 * @return Value of the structure member promoted into a u64. 163 */ 164 static inline u64 __cvmx_bootmem_desc_get(struct octeon_device *oct, 165 u64 base, 166 u32 offset, 167 u32 size) 168 { 169 base = (1ull << 63) | (base + offset); 170 switch (size) { 171 case 4: 172 return octeon_read_device_mem32(oct, base); 173 case 8: 174 return octeon_read_device_mem64(oct, base); 175 default: 176 return 0; 177 } 178 } 179 180 /** 181 * This function retrieves the string name of a named block. It is 182 * more complicated than a simple memcpy() since the named block 183 * descriptor may not be directly accessible. 184 * 185 * @param addr Physical address of the named block descriptor 186 * @param str String to receive the named block string name 187 * @param len Length of the string buffer, which must match the length 188 * stored in the bootmem descriptor. 189 */ 190 static void CVMX_BOOTMEM_NAMED_GET_NAME(struct octeon_device *oct, 191 u64 addr, 192 char *str, 193 u32 len) 194 { 195 addr += offsetof(struct cvmx_bootmem_named_block_desc, name); 196 octeon_pci_read_core_mem(oct, addr, (u8 *)str, len); 197 str[len] = 0; 198 } 199 200 /* See header file for descriptions of functions */ 201 202 /** 203 * Check the version information on the bootmem descriptor 204 * 205 * @param exact_match 206 * Exact major version to check against. A zero means 207 * check that the version supports named blocks. 208 * 209 * @return Zero if the version is correct. Negative if the version is 210 * incorrect. Failures also cause a message to be displayed. 211 */ 212 static int __cvmx_bootmem_check_version(struct octeon_device *oct, 213 u32 exact_match) 214 { 215 u32 major_version; 216 u32 minor_version; 217 218 if (!oct->bootmem_desc_addr) 219 oct->bootmem_desc_addr = 220 octeon_read_device_mem64(oct, 221 BOOTLOADER_PCI_READ_DESC_ADDR); 222 major_version = (u32)__cvmx_bootmem_desc_get( 223 oct, oct->bootmem_desc_addr, 224 offsetof(struct cvmx_bootmem_desc, major_version), 225 FIELD_SIZEOF(struct cvmx_bootmem_desc, major_version)); 226 minor_version = (u32)__cvmx_bootmem_desc_get( 227 oct, oct->bootmem_desc_addr, 228 offsetof(struct cvmx_bootmem_desc, minor_version), 229 FIELD_SIZEOF(struct cvmx_bootmem_desc, minor_version)); 230 231 dev_dbg(&oct->pci_dev->dev, "%s: major_version=%d\n", __func__, 232 major_version); 233 if ((major_version > 3) || 234 (exact_match && major_version != exact_match)) { 235 dev_err(&oct->pci_dev->dev, "bootmem ver mismatch %d.%d addr:0x%llx\n", 236 major_version, minor_version, 237 CAST_ULL(oct->bootmem_desc_addr)); 238 return -1; 239 } else { 240 return 0; 241 } 242 } 243 244 static const struct cvmx_bootmem_named_block_desc 245 *__cvmx_bootmem_find_named_block_flags(struct octeon_device *oct, 246 const char *name, u32 flags) 247 { 248 struct cvmx_bootmem_named_block_desc *desc = 249 &oct->bootmem_named_block_desc; 250 u64 named_addr = cvmx_bootmem_phy_named_block_find(oct, name, flags); 251 252 if (named_addr) { 253 desc->base_addr = __cvmx_bootmem_desc_get( 254 oct, named_addr, 255 offsetof(struct cvmx_bootmem_named_block_desc, 256 base_addr), 257 FIELD_SIZEOF( 258 struct cvmx_bootmem_named_block_desc, 259 base_addr)); 260 desc->size = __cvmx_bootmem_desc_get(oct, named_addr, 261 offsetof(struct cvmx_bootmem_named_block_desc, 262 size), 263 FIELD_SIZEOF( 264 struct cvmx_bootmem_named_block_desc, 265 size)); 266 267 strncpy(desc->name, name, sizeof(desc->name)); 268 desc->name[sizeof(desc->name) - 1] = 0; 269 return &oct->bootmem_named_block_desc; 270 } else { 271 return NULL; 272 } 273 } 274 275 static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct, 276 const char *name, 277 u32 flags) 278 { 279 u64 result = 0; 280 281 if (!__cvmx_bootmem_check_version(oct, 3)) { 282 u32 i; 283 284 u64 named_block_array_addr = __cvmx_bootmem_desc_get( 285 oct, oct->bootmem_desc_addr, 286 offsetof(struct cvmx_bootmem_desc, 287 named_block_array_addr), 288 FIELD_SIZEOF(struct cvmx_bootmem_desc, 289 named_block_array_addr)); 290 u32 num_blocks = (u32)__cvmx_bootmem_desc_get( 291 oct, oct->bootmem_desc_addr, 292 offsetof(struct cvmx_bootmem_desc, 293 nb_num_blocks), 294 FIELD_SIZEOF(struct cvmx_bootmem_desc, 295 nb_num_blocks)); 296 297 u32 name_length = (u32)__cvmx_bootmem_desc_get( 298 oct, oct->bootmem_desc_addr, 299 offsetof(struct cvmx_bootmem_desc, 300 named_block_name_len), 301 FIELD_SIZEOF(struct cvmx_bootmem_desc, 302 named_block_name_len)); 303 304 u64 named_addr = named_block_array_addr; 305 306 for (i = 0; i < num_blocks; i++) { 307 u64 named_size = __cvmx_bootmem_desc_get( 308 oct, named_addr, 309 offsetof( 310 struct cvmx_bootmem_named_block_desc, 311 size), 312 FIELD_SIZEOF( 313 struct cvmx_bootmem_named_block_desc, 314 size)); 315 316 if (name && named_size) { 317 char *name_tmp = 318 kmalloc(name_length + 1, GFP_KERNEL); 319 if (!name_tmp) 320 break; 321 322 CVMX_BOOTMEM_NAMED_GET_NAME(oct, named_addr, 323 name_tmp, 324 name_length); 325 if (!strncmp(name, name_tmp, name_length)) { 326 result = named_addr; 327 kfree(name_tmp); 328 break; 329 } 330 kfree(name_tmp); 331 } else if (!name && !named_size) { 332 result = named_addr; 333 break; 334 } 335 336 named_addr += 337 sizeof(struct cvmx_bootmem_named_block_desc); 338 } 339 } 340 return result; 341 } 342 343 /** 344 * Find a named block on the remote Octeon 345 * 346 * @param name Name of block to find 347 * @param base_addr Address the block is at (OUTPUT) 348 * @param size The size of the block (OUTPUT) 349 * 350 * @return Zero on success, One on failure. 351 */ 352 static int octeon_named_block_find(struct octeon_device *oct, const char *name, 353 u64 *base_addr, u64 *size) 354 { 355 const struct cvmx_bootmem_named_block_desc *named_block; 356 357 octeon_remote_lock(); 358 named_block = __cvmx_bootmem_find_named_block_flags(oct, name, 0); 359 octeon_remote_unlock(); 360 if (named_block) { 361 *base_addr = named_block->base_addr; 362 *size = named_block->size; 363 return 0; 364 } 365 return 1; 366 } 367 368 static void octeon_remote_lock(void) 369 { 370 /* fill this in if any sharing is needed */ 371 } 372 373 static void octeon_remote_unlock(void) 374 { 375 /* fill this in if any sharing is needed */ 376 } 377 378 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, 379 u32 wait_hundredths) 380 { 381 u32 len = (u32)strlen(cmd_str); 382 383 dev_dbg(&oct->pci_dev->dev, "sending \"%s\" to bootloader\n", cmd_str); 384 385 if (len > BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1) { 386 dev_err(&oct->pci_dev->dev, "Command string too long, max length is: %d\n", 387 BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1); 388 return -1; 389 } 390 391 if (octeon_wait_for_bootloader(oct, wait_hundredths) != 0) { 392 dev_err(&oct->pci_dev->dev, "Bootloader not ready for command.\n"); 393 return -1; 394 } 395 396 /* Write command to bootloader */ 397 octeon_remote_lock(); 398 octeon_pci_write_core_mem(oct, BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR, 399 (u8 *)cmd_str, len); 400 octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR, 401 len); 402 octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR, 403 OCTEON_PCI_IO_BUF_OWNER_OCTEON); 404 405 /* Bootloader should accept command very quickly 406 * if it really was ready 407 */ 408 if (octeon_wait_for_bootloader(oct, 200) != 0) { 409 octeon_remote_unlock(); 410 dev_err(&oct->pci_dev->dev, "Bootloader did not accept command.\n"); 411 return -1; 412 } 413 octeon_remote_unlock(); 414 return 0; 415 } 416 417 int octeon_wait_for_bootloader(struct octeon_device *oct, 418 u32 wait_time_hundredths) 419 { 420 dev_dbg(&oct->pci_dev->dev, "waiting %d0 ms for bootloader\n", 421 wait_time_hundredths); 422 423 if (octeon_mem_access_ok(oct)) 424 return -1; 425 426 while (wait_time_hundredths > 0 && 427 octeon_read_device_mem32(oct, 428 BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR) 429 != OCTEON_PCI_IO_BUF_OWNER_HOST) { 430 if (--wait_time_hundredths <= 0) 431 return -1; 432 schedule_timeout_uninterruptible(HZ / 100); 433 } 434 return 0; 435 } 436 437 static void octeon_console_handle_result(struct octeon_device *oct, 438 size_t console_num) 439 { 440 struct octeon_console *console; 441 442 console = &oct->console[console_num]; 443 444 console->waiting = 0; 445 } 446 447 static char console_buffer[OCTEON_CONSOLE_MAX_READ_BYTES]; 448 449 static void output_console_line(struct octeon_device *oct, 450 struct octeon_console *console, 451 size_t console_num, 452 char *console_buffer, 453 s32 bytes_read) 454 { 455 char *line; 456 s32 i; 457 458 line = console_buffer; 459 for (i = 0; i < bytes_read; i++) { 460 /* Output a line at a time, prefixed */ 461 if (console_buffer[i] == '\n') { 462 console_buffer[i] = '\0'; 463 if (console->leftover[0]) { 464 dev_info(&oct->pci_dev->dev, "%lu: %s%s\n", 465 console_num, console->leftover, 466 line); 467 console->leftover[0] = '\0'; 468 } else { 469 dev_info(&oct->pci_dev->dev, "%lu: %s\n", 470 console_num, line); 471 } 472 line = &console_buffer[i + 1]; 473 } 474 } 475 476 /* Save off any leftovers */ 477 if (line != &console_buffer[bytes_read]) { 478 console_buffer[bytes_read] = '\0'; 479 strcpy(console->leftover, line); 480 } 481 } 482 483 static void check_console(struct work_struct *work) 484 { 485 s32 bytes_read, tries, total_read; 486 struct octeon_console *console; 487 struct cavium_wk *wk = (struct cavium_wk *)work; 488 struct octeon_device *oct = (struct octeon_device *)wk->ctxptr; 489 u32 console_num = (u32)wk->ctxul; 490 u32 delay; 491 492 console = &oct->console[console_num]; 493 tries = 0; 494 total_read = 0; 495 496 do { 497 /* Take console output regardless of whether it will 498 * be logged 499 */ 500 bytes_read = 501 octeon_console_read(oct, console_num, console_buffer, 502 sizeof(console_buffer) - 1); 503 if (bytes_read > 0) { 504 total_read += bytes_read; 505 if (console->waiting) 506 octeon_console_handle_result(oct, console_num); 507 if (octeon_console_debug_enabled(console_num)) { 508 output_console_line(oct, console, console_num, 509 console_buffer, bytes_read); 510 } 511 } else if (bytes_read < 0) { 512 dev_err(&oct->pci_dev->dev, "Error reading console %u, ret=%d\n", 513 console_num, bytes_read); 514 } 515 516 tries++; 517 } while ((bytes_read > 0) && (tries < 16)); 518 519 /* If nothing is read after polling the console, 520 * output any leftovers if any 521 */ 522 if (octeon_console_debug_enabled(console_num) && 523 (total_read == 0) && (console->leftover[0])) { 524 dev_info(&oct->pci_dev->dev, "%u: %s\n", 525 console_num, console->leftover); 526 console->leftover[0] = '\0'; 527 } 528 529 delay = OCTEON_CONSOLE_POLL_INTERVAL_MS; 530 531 schedule_delayed_work(&wk->work, msecs_to_jiffies(delay)); 532 } 533 534 int octeon_init_consoles(struct octeon_device *oct) 535 { 536 int ret = 0; 537 u64 addr, size; 538 539 ret = octeon_mem_access_ok(oct); 540 if (ret) { 541 dev_err(&oct->pci_dev->dev, "Memory access not okay'\n"); 542 return ret; 543 } 544 545 ret = octeon_named_block_find(oct, OCTEON_PCI_CONSOLE_BLOCK_NAME, &addr, 546 &size); 547 if (ret) { 548 dev_err(&oct->pci_dev->dev, "Could not find console '%s'\n", 549 OCTEON_PCI_CONSOLE_BLOCK_NAME); 550 return ret; 551 } 552 553 /* Dedicate one of Octeon's BAR1 index registers to create a static 554 * mapping to a region of Octeon DRAM that contains the PCI console 555 * named block. 556 */ 557 oct->console_nb_info.bar1_index = BAR1_INDEX_STATIC_MAP; 558 oct->fn_list.bar1_idx_setup(oct, addr, oct->console_nb_info.bar1_index, 559 true); 560 oct->console_nb_info.dram_region_base = addr 561 & ~(OCTEON_BAR1_ENTRY_SIZE - 1ULL); 562 563 /* num_consoles > 0, is an indication that the consoles 564 * are accessible 565 */ 566 oct->num_consoles = octeon_read_device_mem32(oct, 567 addr + offsetof(struct octeon_pci_console_desc, 568 num_consoles)); 569 oct->console_desc_addr = addr; 570 571 dev_dbg(&oct->pci_dev->dev, "Initialized consoles. %d available\n", 572 oct->num_consoles); 573 574 return ret; 575 } 576 577 int octeon_add_console(struct octeon_device *oct, u32 console_num) 578 { 579 int ret = 0; 580 u32 delay; 581 u64 coreaddr; 582 struct delayed_work *work; 583 struct octeon_console *console; 584 585 if (console_num >= oct->num_consoles) { 586 dev_err(&oct->pci_dev->dev, 587 "trying to read from console number %d when only 0 to %d exist\n", 588 console_num, oct->num_consoles); 589 } else { 590 console = &oct->console[console_num]; 591 592 console->waiting = 0; 593 594 coreaddr = oct->console_desc_addr + console_num * 8 + 595 offsetof(struct octeon_pci_console_desc, 596 console_addr_array); 597 console->addr = octeon_read_device_mem64(oct, coreaddr); 598 coreaddr = console->addr + offsetof(struct octeon_pci_console, 599 buf_size); 600 console->buffer_size = octeon_read_device_mem32(oct, coreaddr); 601 coreaddr = console->addr + offsetof(struct octeon_pci_console, 602 input_base_addr); 603 console->input_base_addr = 604 octeon_read_device_mem64(oct, coreaddr); 605 coreaddr = console->addr + offsetof(struct octeon_pci_console, 606 output_base_addr); 607 console->output_base_addr = 608 octeon_read_device_mem64(oct, coreaddr); 609 console->leftover[0] = '\0'; 610 611 work = &oct->console_poll_work[console_num].work; 612 613 INIT_DELAYED_WORK(work, check_console); 614 oct->console_poll_work[console_num].ctxptr = (void *)oct; 615 oct->console_poll_work[console_num].ctxul = console_num; 616 delay = OCTEON_CONSOLE_POLL_INTERVAL_MS; 617 schedule_delayed_work(work, msecs_to_jiffies(delay)); 618 619 if (octeon_console_debug_enabled(console_num)) { 620 ret = octeon_console_send_cmd(oct, 621 "setenv pci_console_active 1", 622 2000); 623 } 624 625 console->active = 1; 626 } 627 628 return ret; 629 } 630 631 /** 632 * Removes all consoles 633 * 634 * @param oct octeon device 635 */ 636 void octeon_remove_consoles(struct octeon_device *oct) 637 { 638 u32 i; 639 struct octeon_console *console; 640 641 for (i = 0; i < oct->num_consoles; i++) { 642 console = &oct->console[i]; 643 644 if (!console->active) 645 continue; 646 647 cancel_delayed_work_sync(&oct->console_poll_work[i]. 648 work); 649 console->addr = 0; 650 console->buffer_size = 0; 651 console->input_base_addr = 0; 652 console->output_base_addr = 0; 653 } 654 655 oct->num_consoles = 0; 656 } 657 658 static inline int octeon_console_free_bytes(u32 buffer_size, 659 u32 wr_idx, 660 u32 rd_idx) 661 { 662 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 663 return -1; 664 665 return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size; 666 } 667 668 static inline int octeon_console_avail_bytes(u32 buffer_size, 669 u32 wr_idx, 670 u32 rd_idx) 671 { 672 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 673 return -1; 674 675 return buffer_size - 1 - 676 octeon_console_free_bytes(buffer_size, wr_idx, rd_idx); 677 } 678 679 static int octeon_console_read(struct octeon_device *oct, u32 console_num, 680 char *buffer, u32 buf_size) 681 { 682 int bytes_to_read; 683 u32 rd_idx, wr_idx; 684 struct octeon_console *console; 685 686 if (console_num >= oct->num_consoles) { 687 dev_err(&oct->pci_dev->dev, "Attempted to read from disabled console %d\n", 688 console_num); 689 return 0; 690 } 691 692 console = &oct->console[console_num]; 693 694 /* Check to see if any data is available. 695 * Maybe optimize this with 64-bit read. 696 */ 697 rd_idx = octeon_read_device_mem32(oct, console->addr + 698 offsetof(struct octeon_pci_console, output_read_index)); 699 wr_idx = octeon_read_device_mem32(oct, console->addr + 700 offsetof(struct octeon_pci_console, output_write_index)); 701 702 bytes_to_read = octeon_console_avail_bytes(console->buffer_size, 703 wr_idx, rd_idx); 704 if (bytes_to_read <= 0) 705 return bytes_to_read; 706 707 bytes_to_read = MIN(bytes_to_read, (s32)buf_size); 708 709 /* Check to see if what we want to read is not contiguous, and limit 710 * ourselves to the contiguous block 711 */ 712 if (rd_idx + bytes_to_read >= console->buffer_size) 713 bytes_to_read = console->buffer_size - rd_idx; 714 715 octeon_pci_read_core_mem(oct, console->output_base_addr + rd_idx, 716 (u8 *)buffer, bytes_to_read); 717 octeon_write_device_mem32(oct, console->addr + 718 offsetof(struct octeon_pci_console, 719 output_read_index), 720 (rd_idx + bytes_to_read) % 721 console->buffer_size); 722 723 return bytes_to_read; 724 } 725 726 #define FBUF_SIZE (4 * 1024 * 1024) 727 728 int octeon_download_firmware(struct octeon_device *oct, const u8 *data, 729 size_t size) 730 { 731 int ret = 0; 732 u32 crc32_result; 733 u64 load_addr; 734 u32 image_len; 735 struct octeon_firmware_file_header *h; 736 u32 i, rem; 737 738 if (size < sizeof(struct octeon_firmware_file_header)) { 739 dev_err(&oct->pci_dev->dev, "Firmware file too small (%d < %d).\n", 740 (u32)size, 741 (u32)sizeof(struct octeon_firmware_file_header)); 742 return -EINVAL; 743 } 744 745 h = (struct octeon_firmware_file_header *)data; 746 747 if (be32_to_cpu(h->magic) != LIO_NIC_MAGIC) { 748 dev_err(&oct->pci_dev->dev, "Unrecognized firmware file.\n"); 749 return -EINVAL; 750 } 751 752 crc32_result = crc32((unsigned int)~0, data, 753 sizeof(struct octeon_firmware_file_header) - 754 sizeof(u32)) ^ ~0U; 755 if (crc32_result != be32_to_cpu(h->crc32)) { 756 dev_err(&oct->pci_dev->dev, "Firmware CRC mismatch (0x%08x != 0x%08x).\n", 757 crc32_result, be32_to_cpu(h->crc32)); 758 return -EINVAL; 759 } 760 761 if (strncmp(LIQUIDIO_PACKAGE, h->version, strlen(LIQUIDIO_PACKAGE))) { 762 dev_err(&oct->pci_dev->dev, "Unmatched firmware package type. Expected %s, got %s.\n", 763 LIQUIDIO_PACKAGE, h->version); 764 return -EINVAL; 765 } 766 767 if (memcmp(LIQUIDIO_BASE_VERSION, h->version + strlen(LIQUIDIO_PACKAGE), 768 strlen(LIQUIDIO_BASE_VERSION))) { 769 dev_err(&oct->pci_dev->dev, "Unmatched firmware version. Expected %s.x, got %s.\n", 770 LIQUIDIO_BASE_VERSION, 771 h->version + strlen(LIQUIDIO_PACKAGE)); 772 return -EINVAL; 773 } 774 775 if (be32_to_cpu(h->num_images) > LIO_MAX_IMAGES) { 776 dev_err(&oct->pci_dev->dev, "Too many images in firmware file (%d).\n", 777 be32_to_cpu(h->num_images)); 778 return -EINVAL; 779 } 780 781 dev_info(&oct->pci_dev->dev, "Firmware version: %s\n", h->version); 782 snprintf(oct->fw_info.liquidio_firmware_version, 32, "LIQUIDIO: %s", 783 h->version); 784 785 data += sizeof(struct octeon_firmware_file_header); 786 787 dev_info(&oct->pci_dev->dev, "%s: Loading %d images\n", __func__, 788 be32_to_cpu(h->num_images)); 789 /* load all images */ 790 for (i = 0; i < be32_to_cpu(h->num_images); i++) { 791 load_addr = be64_to_cpu(h->desc[i].addr); 792 image_len = be32_to_cpu(h->desc[i].len); 793 794 dev_info(&oct->pci_dev->dev, "Loading firmware %d at %llx\n", 795 image_len, load_addr); 796 797 /* Write in 4MB chunks*/ 798 rem = image_len; 799 800 while (rem) { 801 if (rem < FBUF_SIZE) 802 size = rem; 803 else 804 size = FBUF_SIZE; 805 806 /* download the image */ 807 octeon_pci_write_core_mem(oct, load_addr, data, (u32)size); 808 809 data += size; 810 rem -= (u32)size; 811 load_addr += size; 812 } 813 } 814 dev_info(&oct->pci_dev->dev, "Writing boot command: %s\n", 815 h->bootcmd); 816 817 /* Invoke the bootcmd */ 818 ret = octeon_console_send_cmd(oct, h->bootcmd, 50); 819 820 return 0; 821 } 822