1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file octeon_config.h 19 * \brief Host Driver: Configuration data structures for the host driver. 20 */ 21 22 #ifndef __OCTEON_CONFIG_H__ 23 #define __OCTEON_CONFIG_H__ 24 25 /*--------------------------CONFIG VALUES------------------------*/ 26 27 /* The following macros affect the way the driver data structures 28 * are generated for Octeon devices. 29 * They can be modified. 30 */ 31 32 /* Maximum octeon devices defined as MAX_OCTEON_NICIF to support 33 * multiple(<= MAX_OCTEON_NICIF) Miniports 34 */ 35 #define MAX_OCTEON_NICIF 128 36 #define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF 37 #define MAX_OCTEON_LINKS MAX_OCTEON_NICIF 38 #define MAX_OCTEON_MULTICAST_ADDR 32 39 40 /* CN6xxx IQ configuration macros */ 41 #define CN6XXX_MAX_INPUT_QUEUES 32 42 #define CN6XXX_MAX_IQ_DESCRIPTORS 2048 43 #define CN6XXX_DB_MIN 1 44 #define CN6XXX_DB_MAX 8 45 #define CN6XXX_DB_TIMEOUT 1 46 47 /* CN6xxx OQ configuration macros */ 48 #define CN6XXX_MAX_OUTPUT_QUEUES 32 49 #define CN6XXX_MAX_OQ_DESCRIPTORS 2048 50 #define CN6XXX_OQ_BUF_SIZE 1664 51 #define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \ 52 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128) 53 #define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \ 54 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128) 55 56 #define CN6XXX_OQ_INTR_PKT 64 57 #define CN6XXX_OQ_INTR_TIME 100 58 #define DEFAULT_NUM_NIC_PORTS_66XX 2 59 #define DEFAULT_NUM_NIC_PORTS_68XX 4 60 #define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2 61 62 /* CN23xx IQ configuration macros */ 63 #define CN23XX_MAX_VFS_PER_PF_PASS_1_0 8 64 #define CN23XX_MAX_VFS_PER_PF_PASS_1_1 31 65 #define CN23XX_MAX_VFS_PER_PF 63 66 #define CN23XX_MAX_RINGS_PER_VF 8 67 68 #define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12 69 #define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32 70 #define CN23XX_MAX_RINGS_PER_PF 64 71 #define CN23XX_MAX_RINGS_PER_VF 8 72 73 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF 74 #define CN23XX_MAX_IQ_DESCRIPTORS 2048 75 #define CN23XX_DEFAULT_IQ_DESCRIPTORS 512 76 #define CN23XX_MIN_IQ_DESCRIPTORS 128 77 #define CN23XX_DB_MIN 1 78 #define CN23XX_DB_MAX 8 79 #define CN23XX_DB_TIMEOUT 1 80 81 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF 82 #define CN23XX_MAX_OQ_DESCRIPTORS 2048 83 #define CN23XX_DEFAULT_OQ_DESCRIPTORS 512 84 #define CN23XX_MIN_OQ_DESCRIPTORS 128 85 #define CN23XX_OQ_BUF_SIZE 1664 86 #define CN23XX_OQ_PKTSPER_INTR 128 87 /*#define CAVIUM_ONLY_CN23XX_RX_PERF*/ 88 #define CN23XX_OQ_REFIL_THRESHOLD 16 89 90 #define CN23XX_OQ_INTR_PKT 64 91 #define CN23XX_OQ_INTR_TIME 100 92 #define DEFAULT_NUM_NIC_PORTS_23XX 1 93 94 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF 95 /* PEMs count */ 96 #define CN23XX_MAX_MACS 4 97 98 #define CN23XX_DEF_IQ_INTR_THRESHOLD 32 99 #define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024) 100 /* common OCTEON configuration macros */ 101 #define CN6XXX_CFG_IO_QUEUES 32 102 #define OCTEON_32BYTE_INSTR 32 103 #define OCTEON_64BYTE_INSTR 64 104 #define OCTEON_MAX_BASE_IOQ 4 105 106 #define OCTEON_DMA_INTR_PKT 64 107 #define OCTEON_DMA_INTR_TIME 1000 108 109 #define MAX_TXQS_PER_INTF 8 110 #define MAX_RXQS_PER_INTF 8 111 #define DEF_TXQS_PER_INTF 4 112 #define DEF_RXQS_PER_INTF 4 113 114 #define INVALID_IOQ_NO 0xff 115 116 #define DEFAULT_POW_GRP 0 117 118 /* Macros to get octeon config params */ 119 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) 120 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) 121 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) 122 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) 123 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) 124 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) 125 126 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) 127 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val 128 129 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) 130 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) 131 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) 132 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) 133 #define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time) 134 #define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val 135 #define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val 136 137 #define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt) 138 #define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time) 139 #define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports) 140 #define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs) 141 #define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs) 142 #define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size) 143 144 #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \ 145 ((cfg)->nic_if_cfg[idx].max_txqs) 146 #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \ 147 ((cfg)->nic_if_cfg[idx].num_txqs) 148 #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \ 149 ((cfg)->nic_if_cfg[idx].max_rxqs) 150 #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \ 151 ((cfg)->nic_if_cfg[idx].num_rxqs) 152 #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \ 153 ((cfg)->nic_if_cfg[idx].num_rx_descs) 154 #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \ 155 ((cfg)->nic_if_cfg[idx].num_tx_descs) 156 #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \ 157 ((cfg)->nic_if_cfg[idx].rx_buf_size) 158 #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \ 159 ((cfg)->nic_if_cfg[idx].base_queue) 160 #define CFG_GET_GMXID_NIC_IF(cfg, idx) \ 161 ((cfg)->nic_if_cfg[idx].gmx_port_id) 162 163 #define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp) 164 #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \ 165 ((cfg)->misc.host_link_query_interval) 166 #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \ 167 ((cfg)->misc.oct_link_query_interval) 168 #define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp) 169 170 #define CFG_SET_NUM_RX_DESCS_NIC_IF(cfg, idx, value) \ 171 ((cfg)->nic_if_cfg[idx].num_rx_descs = value) 172 #define CFG_SET_NUM_TX_DESCS_NIC_IF(cfg, idx, value) \ 173 ((cfg)->nic_if_cfg[idx].num_tx_descs = value) 174 175 /* Max IOQs per OCTEON Link */ 176 #define MAX_IOQS_PER_NICIF 64 177 178 enum lio_card_type { 179 LIO_210SV = 0, /* Two port, 66xx */ 180 LIO_210NV, /* Two port, 68xx */ 181 LIO_410NV, /* Four port, 68xx */ 182 LIO_23XX /* 23xx */ 183 }; 184 185 #define LIO_210SV_NAME "210sv" 186 #define LIO_210NV_NAME "210nv" 187 #define LIO_410NV_NAME "410nv" 188 #define LIO_23XX_NAME "23xx" 189 190 /** Structure to define the configuration attributes for each Input queue. 191 * Applicable to all Octeon processors 192 **/ 193 struct octeon_iq_config { 194 #ifdef __BIG_ENDIAN_BITFIELD 195 u64 reserved:16; 196 197 /** Tx interrupt packets. Applicable to 23xx only */ 198 u64 iq_intr_pkt:16; 199 200 /** Minimum ticks to wait before checking for pending instructions. */ 201 u64 db_timeout:16; 202 203 /** Minimum number of commands pending to be posted to Octeon 204 * before driver hits the Input queue doorbell. 205 */ 206 u64 db_min:8; 207 208 /** Command size - 32 or 64 bytes */ 209 u64 instr_type:32; 210 211 /** Pending list size (usually set to the sum of the size of all Input 212 * queues) 213 */ 214 u64 pending_list_size:32; 215 216 /* Max number of IQs available */ 217 u64 max_iqs:8; 218 #else 219 /* Max number of IQs available */ 220 u64 max_iqs:8; 221 222 /** Pending list size (usually set to the sum of the size of all Input 223 * queues) 224 */ 225 u64 pending_list_size:32; 226 227 /** Command size - 32 or 64 bytes */ 228 u64 instr_type:32; 229 230 /** Minimum number of commands pending to be posted to Octeon 231 * before driver hits the Input queue doorbell. 232 */ 233 u64 db_min:8; 234 235 /** Minimum ticks to wait before checking for pending instructions. */ 236 u64 db_timeout:16; 237 238 /** Tx interrupt packets. Applicable to 23xx only */ 239 u64 iq_intr_pkt:16; 240 241 u64 reserved:16; 242 #endif 243 }; 244 245 /** Structure to define the configuration attributes for each Output queue. 246 * Applicable to all Octeon processors 247 **/ 248 struct octeon_oq_config { 249 #ifdef __BIG_ENDIAN_BITFIELD 250 u64 reserved:16; 251 252 u64 pkts_per_intr:16; 253 254 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the 255 * host if atleast one packet was sent in the time interval specified 256 * by this field. The driver uses time interval interrupt coalescing 257 * by default. The time is specified in microseconds. 258 */ 259 u64 oq_intr_time:16; 260 261 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host 262 * only if it sent as many packets as specified by this field. 263 * The driver 264 * usually does not use packet count interrupt coalescing. 265 */ 266 u64 oq_intr_pkt:16; 267 268 /** The number of buffers that were consumed during packet processing by 269 * the driver on this Output queue before the driver attempts to 270 * replenish 271 * the descriptor ring with new buffers. 272 */ 273 u64 refill_threshold:16; 274 275 /* Max number of OQs available */ 276 u64 max_oqs:8; 277 278 #else 279 /* Max number of OQs available */ 280 u64 max_oqs:8; 281 282 /** The number of buffers that were consumed during packet processing by 283 * the driver on this Output queue before the driver attempts to 284 * replenish 285 * the descriptor ring with new buffers. 286 */ 287 u64 refill_threshold:16; 288 289 /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host 290 * only if it sent as many packets as specified by this field. 291 * The driver 292 * usually does not use packet count interrupt coalescing. 293 */ 294 u64 oq_intr_pkt:16; 295 296 /** Interrupt Coalescing (Time Interval). Octeon will interrupt the 297 * host if atleast one packet was sent in the time interval specified 298 * by this field. The driver uses time interval interrupt coalescing 299 * by default. The time is specified in microseconds. 300 */ 301 u64 oq_intr_time:16; 302 303 u64 pkts_per_intr:16; 304 305 u64 reserved:16; 306 #endif 307 308 }; 309 310 /** This structure conatins the NIC link configuration attributes, 311 * common for all the OCTEON Modles. 312 */ 313 struct octeon_nic_if_config { 314 #ifdef __BIG_ENDIAN_BITFIELD 315 u64 reserved:56; 316 317 u64 base_queue:16; 318 319 u64 gmx_port_id:8; 320 321 /* SKB size, We need not change buf size even for Jumbo frames. 322 * Octeon can send jumbo frames in 4 consecutive descriptors, 323 */ 324 u64 rx_buf_size:16; 325 326 /* Num of desc for tx rings */ 327 u64 num_tx_descs:16; 328 329 /* Num of desc for rx rings */ 330 u64 num_rx_descs:16; 331 332 /* Actual configured value. Range could be: 1...max_rxqs */ 333 u64 num_rxqs:16; 334 335 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 336 u64 max_rxqs:16; 337 338 /* Actual configured value. Range could be: 1...max_txqs */ 339 u64 num_txqs:16; 340 341 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 342 u64 max_txqs:16; 343 #else 344 /* Max Txqs: Half for each of the two ports :max_iq/2 */ 345 u64 max_txqs:16; 346 347 /* Actual configured value. Range could be: 1...max_txqs */ 348 u64 num_txqs:16; 349 350 /* Max Rxqs: Half for each of the two ports :max_oq/2 */ 351 u64 max_rxqs:16; 352 353 /* Actual configured value. Range could be: 1...max_rxqs */ 354 u64 num_rxqs:16; 355 356 /* Num of desc for rx rings */ 357 u64 num_rx_descs:16; 358 359 /* Num of desc for tx rings */ 360 u64 num_tx_descs:16; 361 362 /* SKB size, We need not change buf size even for Jumbo frames. 363 * Octeon can send jumbo frames in 4 consecutive descriptors, 364 */ 365 u64 rx_buf_size:16; 366 367 u64 gmx_port_id:8; 368 369 u64 base_queue:16; 370 371 u64 reserved:56; 372 #endif 373 374 }; 375 376 /** Structure to define the configuration attributes for meta data. 377 * Applicable to all Octeon processors. 378 */ 379 380 struct octeon_misc_config { 381 #ifdef __BIG_ENDIAN_BITFIELD 382 /** Host link status polling period */ 383 u64 host_link_query_interval:32; 384 /** Oct link status polling period */ 385 u64 oct_link_query_interval:32; 386 387 u64 enable_sli_oq_bp:1; 388 /** Control IQ Group */ 389 u64 ctrlq_grp:4; 390 #else 391 /** Control IQ Group */ 392 u64 ctrlq_grp:4; 393 /** BP for SLI OQ */ 394 u64 enable_sli_oq_bp:1; 395 /** Host link status polling period */ 396 u64 oct_link_query_interval:32; 397 /** Oct link status polling period */ 398 u64 host_link_query_interval:32; 399 #endif 400 }; 401 402 /** Structure to define the configuration for all OCTEON processors. */ 403 struct octeon_config { 404 u16 card_type; 405 char *card_name; 406 407 /** Input Queue attributes. */ 408 struct octeon_iq_config iq; 409 410 /** Output Queue attributes. */ 411 struct octeon_oq_config oq; 412 413 /** NIC Port Configuration */ 414 struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF]; 415 416 /** Miscellaneous attributes */ 417 struct octeon_misc_config misc; 418 419 int num_nic_ports; 420 421 int num_def_tx_descs; 422 423 /* Num of desc for rx rings */ 424 int num_def_rx_descs; 425 426 int def_rx_buf_size; 427 428 }; 429 430 /* The following config values are fixed and should not be modified. */ 431 432 #define BAR1_INDEX_DYNAMIC_MAP 2 433 #define BAR1_INDEX_STATIC_MAP 15 434 #define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024) 435 436 #define MAX_BAR1_IOREMAP_SIZE (16 * OCTEON_BAR1_ENTRY_SIZE) 437 438 /* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking 439 * NoResponse Lists are now maintained with each IQ. (Dec' 2007). 440 */ 441 #define MAX_RESPONSE_LISTS 4 442 443 /* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the 444 * dispatch table. 445 */ 446 #define OPCODE_MASK_BITS 6 447 448 /* Mask for the 6-bit lookup hash */ 449 #define OCTEON_OPCODE_MASK 0x3f 450 451 /* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */ 452 #define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS) 453 454 /* Maximum number of Octeon Instruction (command) queues */ 455 #define MAX_OCTEON_INSTR_QUEUES(oct) \ 456 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \ 457 CN6XXX_MAX_INPUT_QUEUES) 458 459 /* Maximum number of Octeon Instruction (command) queues */ 460 #define MAX_OCTEON_OUTPUT_QUEUES(oct) \ 461 (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \ 462 CN6XXX_MAX_OUTPUT_QUEUES) 463 464 #define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES 465 #define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES 466 467 #define MAX_POSSIBLE_VFS 64 468 469 #endif /* __OCTEON_CONFIG_H__ */ 470