1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 7 31 #define LIQUIDIO_BASE_MICRO_VERSION 0 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define OPCODE_NIC_SET_TRUSTED_VF 0x13 88 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 89 #define VF_DRV_LOADED 1 90 #define VF_DRV_REMOVED -1 91 #define VF_DRV_MACADDR_CHANGED 2 92 93 #define OPCODE_NIC_VF_REP_PKT 0x15 94 #define OPCODE_NIC_VF_REP_CMD 0x16 95 96 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 97 98 /* Application codes advertised by the core driver initialization packet. */ 99 #define CVM_DRV_APP_START 0x0 100 #define CVM_DRV_NO_APP 0 101 #define CVM_DRV_APP_COUNT 0x2 102 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 103 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 104 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 105 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 106 107 #define BYTES_PER_DHLEN_UNIT 8 108 #define MAX_REG_CNT 2000000U 109 #define INTRNAMSIZ 32 110 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 111 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 112 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 113 114 #define SCR2_BIT_FW_LOADED 63 115 116 /* App specific capabilities from firmware to pf driver */ 117 #define LIQUIDIO_TIME_SYNC_CAP 0x1 118 #define LIQUIDIO_SWITCHDEV_CAP 0x2 119 120 static inline u32 incr_index(u32 index, u32 count, u32 max) 121 { 122 if ((index + count) >= max) 123 index = index + count - max; 124 else 125 index += count; 126 127 return index; 128 } 129 130 #define OCT_BOARD_NAME 32 131 #define OCT_SERIAL_LEN 64 132 133 /* Structure used by core driver to send indication that the Octeon 134 * application is ready. 135 */ 136 struct octeon_core_setup { 137 u64 corefreq; 138 139 char boardname[OCT_BOARD_NAME]; 140 141 char board_serial_number[OCT_SERIAL_LEN]; 142 143 u64 board_rev_major; 144 145 u64 board_rev_minor; 146 147 }; 148 149 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 150 151 /* The Scatter-Gather List Entry. The scatter or gather component used with 152 * a Octeon input instruction has this format. 153 */ 154 struct octeon_sg_entry { 155 /** The first 64 bit gives the size of data in each dptr.*/ 156 union { 157 u16 size[4]; 158 u64 size64; 159 } u; 160 161 /** The 4 dptr pointers for this entry. */ 162 u64 ptr[4]; 163 164 }; 165 166 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 167 168 /* \brief Add size to gather list 169 * @param sg_entry scatter/gather entry 170 * @param size size to add 171 * @param pos position to add it. 172 */ 173 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 174 u16 size, 175 u32 pos) 176 { 177 #ifdef __BIG_ENDIAN_BITFIELD 178 sg_entry->u.size[pos] = size; 179 #else 180 sg_entry->u.size[3 - pos] = size; 181 #endif 182 } 183 184 /*------------------------- End Scatter/Gather ---------------------------*/ 185 186 #define OCTNET_FRM_LENGTH_SIZE 8 187 188 #define OCTNET_FRM_PTP_HEADER_SIZE 8 189 190 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 191 192 #define OCTNET_MIN_FRM_SIZE 64 193 194 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 195 196 #define OCTNET_DEFAULT_MTU (1500) 197 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE) 198 199 /** NIC Commands are sent using this Octeon Input Queue */ 200 #define OCTNET_CMD_Q 0 201 202 /* NIC Command types */ 203 #define OCTNET_CMD_CHANGE_MTU 0x1 204 #define OCTNET_CMD_CHANGE_MACADDR 0x2 205 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 206 #define OCTNET_CMD_RX_CTL 0x4 207 208 #define OCTNET_CMD_SET_MULTI_LIST 0x5 209 #define OCTNET_CMD_CLEAR_STATS 0x6 210 211 /* command for setting the speed, duplex & autoneg */ 212 #define OCTNET_CMD_SET_SETTINGS 0x7 213 #define OCTNET_CMD_SET_FLOW_CTL 0x8 214 215 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 216 #define OCTNET_CMD_GPIO_ACCESS 0xA 217 #define OCTNET_CMD_LRO_ENABLE 0xB 218 #define OCTNET_CMD_LRO_DISABLE 0xC 219 #define OCTNET_CMD_SET_RSS 0xD 220 #define OCTNET_CMD_WRITE_SA 0xE 221 #define OCTNET_CMD_DELETE_SA 0xF 222 #define OCTNET_CMD_UPDATE_SA 0x12 223 224 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 225 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 226 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 227 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 228 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 229 230 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 231 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 232 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 233 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 234 235 #define OCTNET_CMD_ID_ACTIVE 0x1a 236 237 #define OCTNET_CMD_SET_UC_LIST 0x1b 238 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 239 240 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 241 242 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 243 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 244 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 245 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 246 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 247 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 248 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 249 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 250 251 #define LIO_CMD_WAIT_TM 100 252 253 /* RX(packets coming from wire) Checksum verification flags */ 254 /* TCP/UDP csum */ 255 #define CNNIC_L4SUM_VERIFIED 0x1 256 #define CNNIC_IPSUM_VERIFIED 0x2 257 #define CNNIC_TUN_CSUM_VERIFIED 0x4 258 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 259 260 /*LROIPV4 and LROIPV6 Flags*/ 261 #define OCTNIC_LROIPV4 0x1 262 #define OCTNIC_LROIPV6 0x2 263 264 /* Interface flags communicated between host driver and core app. */ 265 enum octnet_ifflags { 266 OCTNET_IFFLAG_PROMISC = 0x01, 267 OCTNET_IFFLAG_ALLMULTI = 0x02, 268 OCTNET_IFFLAG_MULTICAST = 0x04, 269 OCTNET_IFFLAG_BROADCAST = 0x08, 270 OCTNET_IFFLAG_UNICAST = 0x10 271 }; 272 273 /* wqe 274 * --------------- 0 275 * | wqe word0-3 | 276 * --------------- 32 277 * | PCI IH | 278 * --------------- 40 279 * | RPTR | 280 * --------------- 48 281 * | PCI IRH | 282 * --------------- 56 283 * | OCT_NET_CMD | 284 * --------------- 64 285 * | Addtl 8-BData | 286 * | | 287 * --------------- 288 */ 289 290 union octnet_cmd { 291 u64 u64; 292 293 struct { 294 #ifdef __BIG_ENDIAN_BITFIELD 295 u64 cmd:5; 296 297 u64 more:6; /* How many udd words follow the command */ 298 299 u64 reserved:29; 300 301 u64 param1:16; 302 303 u64 param2:8; 304 305 #else 306 307 u64 param2:8; 308 309 u64 param1:16; 310 311 u64 reserved:29; 312 313 u64 more:6; 314 315 u64 cmd:5; 316 317 #endif 318 } s; 319 320 }; 321 322 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 323 324 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 325 #define LIO_SOFTCMDRESP_IH2 40 326 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 327 328 #define LIO_PCICMD_O2 24 329 #define LIO_PCICMD_O3 (24 + 8) 330 331 /* Instruction Header(DPI) - for OCTEON-III models */ 332 struct octeon_instr_ih3 { 333 #ifdef __BIG_ENDIAN_BITFIELD 334 335 /** Reserved3 */ 336 u64 reserved3:1; 337 338 /** Gather indicator 1=gather*/ 339 u64 gather:1; 340 341 /** Data length OR no. of entries in gather list */ 342 u64 dlengsz:14; 343 344 /** Front Data size */ 345 u64 fsz:6; 346 347 /** Reserved2 */ 348 u64 reserved2:4; 349 350 /** PKI port kind - PKIND */ 351 u64 pkind:6; 352 353 /** Reserved1 */ 354 u64 reserved1:32; 355 356 #else 357 /** Reserved1 */ 358 u64 reserved1:32; 359 360 /** PKI port kind - PKIND */ 361 u64 pkind:6; 362 363 /** Reserved2 */ 364 u64 reserved2:4; 365 366 /** Front Data size */ 367 u64 fsz:6; 368 369 /** Data length OR no. of entries in gather list */ 370 u64 dlengsz:14; 371 372 /** Gather indicator 1=gather*/ 373 u64 gather:1; 374 375 /** Reserved3 */ 376 u64 reserved3:1; 377 378 #endif 379 }; 380 381 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 382 /** BIG ENDIAN format. */ 383 struct octeon_instr_pki_ih3 { 384 #ifdef __BIG_ENDIAN_BITFIELD 385 386 /** Wider bit */ 387 u64 w:1; 388 389 /** Raw mode indicator 1 = RAW */ 390 u64 raw:1; 391 392 /** Use Tag */ 393 u64 utag:1; 394 395 /** Use QPG */ 396 u64 uqpg:1; 397 398 /** Reserved2 */ 399 u64 reserved2:1; 400 401 /** Parse Mode */ 402 u64 pm:3; 403 404 /** Skip Length */ 405 u64 sl:8; 406 407 /** Use Tag Type */ 408 u64 utt:1; 409 410 /** Tag type */ 411 u64 tagtype:2; 412 413 /** Reserved1 */ 414 u64 reserved1:2; 415 416 /** QPG Value */ 417 u64 qpg:11; 418 419 /** Tag Value */ 420 u64 tag:32; 421 422 #else 423 424 /** Tag Value */ 425 u64 tag:32; 426 427 /** QPG Value */ 428 u64 qpg:11; 429 430 /** Reserved1 */ 431 u64 reserved1:2; 432 433 /** Tag type */ 434 u64 tagtype:2; 435 436 /** Use Tag Type */ 437 u64 utt:1; 438 439 /** Skip Length */ 440 u64 sl:8; 441 442 /** Parse Mode */ 443 u64 pm:3; 444 445 /** Reserved2 */ 446 u64 reserved2:1; 447 448 /** Use QPG */ 449 u64 uqpg:1; 450 451 /** Use Tag */ 452 u64 utag:1; 453 454 /** Raw mode indicator 1 = RAW */ 455 u64 raw:1; 456 457 /** Wider bit */ 458 u64 w:1; 459 #endif 460 461 }; 462 463 /** Instruction Header */ 464 struct octeon_instr_ih2 { 465 #ifdef __BIG_ENDIAN_BITFIELD 466 /** Raw mode indicator 1 = RAW */ 467 u64 raw:1; 468 469 /** Gather indicator 1=gather*/ 470 u64 gather:1; 471 472 /** Data length OR no. of entries in gather list */ 473 u64 dlengsz:14; 474 475 /** Front Data size */ 476 u64 fsz:6; 477 478 /** Packet Order / Work Unit selection (1 of 8)*/ 479 u64 qos:3; 480 481 /** Core group selection (1 of 16) */ 482 u64 grp:4; 483 484 /** Short Raw Packet Indicator 1=short raw pkt */ 485 u64 rs:1; 486 487 /** Tag type */ 488 u64 tagtype:2; 489 490 /** Tag Value */ 491 u64 tag:32; 492 #else 493 /** Tag Value */ 494 u64 tag:32; 495 496 /** Tag type */ 497 u64 tagtype:2; 498 499 /** Short Raw Packet Indicator 1=short raw pkt */ 500 u64 rs:1; 501 502 /** Core group selection (1 of 16) */ 503 u64 grp:4; 504 505 /** Packet Order / Work Unit selection (1 of 8)*/ 506 u64 qos:3; 507 508 /** Front Data size */ 509 u64 fsz:6; 510 511 /** Data length OR no. of entries in gather list */ 512 u64 dlengsz:14; 513 514 /** Gather indicator 1=gather*/ 515 u64 gather:1; 516 517 /** Raw mode indicator 1 = RAW */ 518 u64 raw:1; 519 #endif 520 }; 521 522 /** Input Request Header */ 523 struct octeon_instr_irh { 524 #ifdef __BIG_ENDIAN_BITFIELD 525 u64 opcode:4; 526 u64 rflag:1; 527 u64 subcode:7; 528 u64 vlan:12; 529 u64 priority:3; 530 u64 reserved:5; 531 u64 ossp:32; /* opcode/subcode specific parameters */ 532 #else 533 u64 ossp:32; /* opcode/subcode specific parameters */ 534 u64 reserved:5; 535 u64 priority:3; 536 u64 vlan:12; 537 u64 subcode:7; 538 u64 rflag:1; 539 u64 opcode:4; 540 #endif 541 }; 542 543 /** Return Data Parameters */ 544 struct octeon_instr_rdp { 545 #ifdef __BIG_ENDIAN_BITFIELD 546 u64 reserved:49; 547 u64 pcie_port:3; 548 u64 rlen:12; 549 #else 550 u64 rlen:12; 551 u64 pcie_port:3; 552 u64 reserved:49; 553 #endif 554 }; 555 556 /** Receive Header */ 557 union octeon_rh { 558 #ifdef __BIG_ENDIAN_BITFIELD 559 u64 u64; 560 struct { 561 u64 opcode:4; 562 u64 subcode:8; 563 u64 len:3; /** additional 64-bit words */ 564 u64 reserved:17; 565 u64 ossp:32; /** opcode/subcode specific parameters */ 566 } r; 567 struct { 568 u64 opcode:4; 569 u64 subcode:8; 570 u64 len:3; /** additional 64-bit words */ 571 u64 extra:28; 572 u64 vlan:12; 573 u64 priority:3; 574 u64 csum_verified:3; /** checksum verified. */ 575 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 576 u64 encap_on:1; 577 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 578 } r_dh; 579 struct { 580 u64 opcode:4; 581 u64 subcode:8; 582 u64 len:3; /** additional 64-bit words */ 583 u64 reserved:11; 584 u64 num_gmx_ports:8; 585 u64 max_nic_ports:10; 586 u64 app_cap_flags:4; 587 u64 app_mode:8; 588 u64 pkind:8; 589 } r_core_drv_init; 590 struct { 591 u64 opcode:4; 592 u64 subcode:8; 593 u64 len:3; /** additional 64-bit words */ 594 u64 reserved:8; 595 u64 extra:25; 596 u64 gmxport:16; 597 } r_nic_info; 598 #else 599 u64 u64; 600 struct { 601 u64 ossp:32; /** opcode/subcode specific parameters */ 602 u64 reserved:17; 603 u64 len:3; /** additional 64-bit words */ 604 u64 subcode:8; 605 u64 opcode:4; 606 } r; 607 struct { 608 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 609 u64 encap_on:1; 610 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 611 u64 csum_verified:3; /** checksum verified. */ 612 u64 priority:3; 613 u64 vlan:12; 614 u64 extra:28; 615 u64 len:3; /** additional 64-bit words */ 616 u64 subcode:8; 617 u64 opcode:4; 618 } r_dh; 619 struct { 620 u64 pkind:8; 621 u64 app_mode:8; 622 u64 app_cap_flags:4; 623 u64 max_nic_ports:10; 624 u64 num_gmx_ports:8; 625 u64 reserved:11; 626 u64 len:3; /** additional 64-bit words */ 627 u64 subcode:8; 628 u64 opcode:4; 629 } r_core_drv_init; 630 struct { 631 u64 gmxport:16; 632 u64 extra:25; 633 u64 reserved:8; 634 u64 len:3; /** additional 64-bit words */ 635 u64 subcode:8; 636 u64 opcode:4; 637 } r_nic_info; 638 #endif 639 }; 640 641 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 642 643 union octnic_packet_params { 644 u32 u32; 645 struct { 646 #ifdef __BIG_ENDIAN_BITFIELD 647 u32 reserved:24; 648 u32 ip_csum:1; /* Perform IP header checksum(s) */ 649 /* Perform Outer transport header checksum */ 650 u32 transport_csum:1; 651 /* Find tunnel, and perform transport csum. */ 652 u32 tnl_csum:1; 653 u32 tsflag:1; /* Timestamp this packet */ 654 u32 ipsec_ops:4; /* IPsec operation */ 655 #else 656 u32 ipsec_ops:4; 657 u32 tsflag:1; 658 u32 tnl_csum:1; 659 u32 transport_csum:1; 660 u32 ip_csum:1; 661 u32 reserved:24; 662 #endif 663 } s; 664 }; 665 666 /** Status of a RGMII Link on Octeon as seen by core driver. */ 667 union oct_link_status { 668 u64 u64; 669 670 struct { 671 #ifdef __BIG_ENDIAN_BITFIELD 672 u64 duplex:8; 673 u64 mtu:16; 674 u64 speed:16; 675 u64 link_up:1; 676 u64 autoneg:1; 677 u64 if_mode:5; 678 u64 pause:1; 679 u64 flashing:1; 680 u64 phy_type:5; 681 u64 reserved:10; 682 #else 683 u64 reserved:10; 684 u64 phy_type:5; 685 u64 flashing:1; 686 u64 pause:1; 687 u64 if_mode:5; 688 u64 autoneg:1; 689 u64 link_up:1; 690 u64 speed:16; 691 u64 mtu:16; 692 u64 duplex:8; 693 #endif 694 } s; 695 }; 696 697 enum lio_phy_type { 698 LIO_PHY_PORT_TP = 0x0, 699 LIO_PHY_PORT_FIBRE = 0x1, 700 LIO_PHY_PORT_UNKNOWN, 701 }; 702 703 /** The txpciq info passed to host from the firmware */ 704 705 union oct_txpciq { 706 u64 u64; 707 708 struct { 709 #ifdef __BIG_ENDIAN_BITFIELD 710 u64 q_no:8; 711 u64 port:8; 712 u64 pkind:6; 713 u64 use_qpg:1; 714 u64 qpg:11; 715 u64 reserved:30; 716 #else 717 u64 reserved:30; 718 u64 qpg:11; 719 u64 use_qpg:1; 720 u64 pkind:6; 721 u64 port:8; 722 u64 q_no:8; 723 #endif 724 } s; 725 }; 726 727 /** The rxpciq info passed to host from the firmware */ 728 729 union oct_rxpciq { 730 u64 u64; 731 732 struct { 733 #ifdef __BIG_ENDIAN_BITFIELD 734 u64 q_no:8; 735 u64 reserved:56; 736 #else 737 u64 reserved:56; 738 u64 q_no:8; 739 #endif 740 } s; 741 }; 742 743 /** Information for a OCTEON ethernet interface shared between core & host. */ 744 struct oct_link_info { 745 union oct_link_status link; 746 u64 hw_addr; 747 748 #ifdef __BIG_ENDIAN_BITFIELD 749 u64 gmxport:16; 750 u64 macaddr_is_admin_asgnd:1; 751 u64 rsvd:31; 752 u64 num_txpciq:8; 753 u64 num_rxpciq:8; 754 #else 755 u64 num_rxpciq:8; 756 u64 num_txpciq:8; 757 u64 rsvd:31; 758 u64 macaddr_is_admin_asgnd:1; 759 u64 gmxport:16; 760 #endif 761 762 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 763 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 764 }; 765 766 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 767 768 struct liquidio_if_cfg_info { 769 u64 iqmask; /** mask for IQs enabled for the port */ 770 u64 oqmask; /** mask for OQs enabled for the port */ 771 struct oct_link_info linfo; /** initial link information */ 772 char liquidio_firmware_version[32]; 773 }; 774 775 /** Stats for each NIC port in RX direction. */ 776 struct nic_rx_stats { 777 /* link-level stats */ 778 u64 total_rcvd; 779 u64 bytes_rcvd; 780 u64 total_bcst; 781 u64 total_mcst; 782 u64 runts; 783 u64 ctl_rcvd; 784 u64 fifo_err; /* Accounts for over/under-run of buffers */ 785 u64 dmac_drop; 786 u64 fcs_err; 787 u64 jabber_err; 788 u64 l2_err; 789 u64 frame_err; 790 791 /* firmware stats */ 792 u64 fw_total_rcvd; 793 u64 fw_total_fwd; 794 u64 fw_total_fwd_bytes; 795 u64 fw_err_pko; 796 u64 fw_err_link; 797 u64 fw_err_drop; 798 u64 fw_rx_vxlan; 799 u64 fw_rx_vxlan_err; 800 801 /* LRO */ 802 u64 fw_lro_pkts; /* Number of packets that are LROed */ 803 u64 fw_lro_octs; /* Number of octets that are LROed */ 804 u64 fw_total_lro; /* Number of LRO packets formed */ 805 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 806 u64 fw_lro_aborts_port; 807 u64 fw_lro_aborts_seq; 808 u64 fw_lro_aborts_tsval; 809 u64 fw_lro_aborts_timer; 810 /* intrmod: packet forward rate */ 811 u64 fwd_rate; 812 }; 813 814 /** Stats for each NIC port in RX direction. */ 815 struct nic_tx_stats { 816 /* link-level stats */ 817 u64 total_pkts_sent; 818 u64 total_bytes_sent; 819 u64 mcast_pkts_sent; 820 u64 bcast_pkts_sent; 821 u64 ctl_sent; 822 u64 one_collision_sent; /* Packets sent after one collision*/ 823 u64 multi_collision_sent; /* Packets sent after multiple collision*/ 824 u64 max_collision_fail; /* Packets not sent due to max collisions */ 825 u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 826 u64 fifo_err; /* Accounts for over/under-run of buffers */ 827 u64 runts; 828 u64 total_collisions; /* Total number of collisions detected */ 829 830 /* firmware stats */ 831 u64 fw_total_sent; 832 u64 fw_total_fwd; 833 u64 fw_total_fwd_bytes; 834 u64 fw_err_pko; 835 u64 fw_err_link; 836 u64 fw_err_drop; 837 u64 fw_err_tso; 838 u64 fw_tso; /* number of tso requests */ 839 u64 fw_tso_fwd; /* number of packets segmented in tso */ 840 u64 fw_tx_vxlan; 841 u64 fw_err_pki; 842 }; 843 844 struct oct_link_stats { 845 struct nic_rx_stats fromwire; 846 struct nic_tx_stats fromhost; 847 848 }; 849 850 static inline int opcode_slow_path(union octeon_rh *rh) 851 { 852 u16 subcode1, subcode2; 853 854 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 855 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 856 857 return (subcode2 != subcode1); 858 } 859 860 #define LIO68XX_LED_CTRL_ADDR 0x3501 861 #define LIO68XX_LED_CTRL_CFGON 0x1f 862 #define LIO68XX_LED_CTRL_CFGOFF 0x100 863 #define LIO68XX_LED_BEACON_ADDR 0x3508 864 #define LIO68XX_LED_BEACON_CFGON 0x47fd 865 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 866 #define VITESSE_PHY_GPIO_DRIVEON 0x1 867 #define VITESSE_PHY_GPIO_CFG 0x8 868 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 869 #define VITESSE_PHY_GPIO_HIGH 0x2 870 #define VITESSE_PHY_GPIO_LOW 0x3 871 #define LED_IDENTIFICATION_ON 0x1 872 #define LED_IDENTIFICATION_OFF 0x0 873 874 struct oct_mdio_cmd { 875 u64 op; 876 u64 mdio_addr; 877 u64 value1; 878 u64 value2; 879 u64 value3; 880 }; 881 882 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 883 884 struct oct_intrmod_cfg { 885 u64 rx_enable; 886 u64 tx_enable; 887 u64 check_intrvl; 888 u64 maxpkt_ratethr; 889 u64 minpkt_ratethr; 890 u64 rx_maxcnt_trigger; 891 u64 rx_mincnt_trigger; 892 u64 rx_maxtmr_trigger; 893 u64 rx_mintmr_trigger; 894 u64 tx_mincnt_trigger; 895 u64 tx_maxcnt_trigger; 896 u64 rx_frames; 897 u64 tx_frames; 898 u64 rx_usecs; 899 }; 900 901 #define BASE_QUEUE_NOT_REQUESTED 65535 902 903 union oct_nic_if_cfg { 904 u64 u64; 905 struct { 906 #ifdef __BIG_ENDIAN_BITFIELD 907 u64 base_queue:16; 908 u64 num_iqueues:16; 909 u64 num_oqueues:16; 910 u64 gmx_port_id:8; 911 u64 vf_id:8; 912 #else 913 u64 vf_id:8; 914 u64 gmx_port_id:8; 915 u64 num_oqueues:16; 916 u64 num_iqueues:16; 917 u64 base_queue:16; 918 #endif 919 } s; 920 }; 921 922 struct lio_trusted_vf { 923 uint64_t active: 1; 924 uint64_t id : 8; 925 uint64_t reserved: 55; 926 }; 927 928 struct lio_time { 929 s64 sec; /* seconds */ 930 s64 nsec; /* nanoseconds */ 931 }; 932 933 struct lio_vf_rep_stats { 934 u64 tx_packets; 935 u64 tx_bytes; 936 u64 tx_dropped; 937 938 u64 rx_packets; 939 u64 rx_bytes; 940 u64 rx_dropped; 941 }; 942 943 enum lio_vf_rep_req_type { 944 LIO_VF_REP_REQ_NONE, 945 LIO_VF_REP_REQ_STATE, 946 LIO_VF_REP_REQ_MTU, 947 LIO_VF_REP_REQ_STATS, 948 LIO_VF_REP_REQ_DEVNAME 949 }; 950 951 enum { 952 LIO_VF_REP_STATE_DOWN, 953 LIO_VF_REP_STATE_UP 954 }; 955 956 #define LIO_IF_NAME_SIZE 16 957 struct lio_vf_rep_req { 958 u8 req_type; 959 u8 ifidx; 960 u8 rsvd[6]; 961 962 union { 963 struct lio_vf_rep_name { 964 char name[LIO_IF_NAME_SIZE]; 965 } rep_name; 966 967 struct lio_vf_rep_mtu { 968 u32 mtu; 969 u32 rsvd; 970 } rep_mtu; 971 972 struct lio_vf_rep_state { 973 u8 state; 974 u8 rsvd[7]; 975 } rep_state; 976 }; 977 }; 978 979 struct lio_vf_rep_resp { 980 u64 rh; 981 u8 status; 982 u8 rsvd[7]; 983 }; 984 #endif 985