1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 7 31 #define LIQUIDIO_BASE_MICRO_VERSION 2 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define OPCODE_NIC_QCOUNT_UPDATE 0x12 88 #define OPCODE_NIC_SET_TRUSTED_VF 0x13 89 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 90 #define VF_DRV_LOADED 1 91 #define VF_DRV_REMOVED -1 92 #define VF_DRV_MACADDR_CHANGED 2 93 94 #define OPCODE_NIC_VF_REP_PKT 0x15 95 #define OPCODE_NIC_VF_REP_CMD 0x16 96 #define OPCODE_NIC_UBOOT_CTL 0x17 97 98 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 99 100 /* Application codes advertised by the core driver initialization packet. */ 101 #define CVM_DRV_APP_START 0x0 102 #define CVM_DRV_NO_APP 0 103 #define CVM_DRV_APP_COUNT 0x2 104 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 105 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 106 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 107 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 108 109 #define BYTES_PER_DHLEN_UNIT 8 110 #define MAX_REG_CNT 2000000U 111 #define INTRNAMSIZ 32 112 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 113 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 114 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 115 116 #define SCR2_BIT_FW_LOADED 63 117 118 /* App specific capabilities from firmware to pf driver */ 119 #define LIQUIDIO_TIME_SYNC_CAP 0x1 120 #define LIQUIDIO_SWITCHDEV_CAP 0x2 121 122 static inline u32 incr_index(u32 index, u32 count, u32 max) 123 { 124 if ((index + count) >= max) 125 index = index + count - max; 126 else 127 index += count; 128 129 return index; 130 } 131 132 #define OCT_BOARD_NAME 32 133 #define OCT_SERIAL_LEN 64 134 135 /* Structure used by core driver to send indication that the Octeon 136 * application is ready. 137 */ 138 struct octeon_core_setup { 139 u64 corefreq; 140 141 char boardname[OCT_BOARD_NAME]; 142 143 char board_serial_number[OCT_SERIAL_LEN]; 144 145 u64 board_rev_major; 146 147 u64 board_rev_minor; 148 149 }; 150 151 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 152 153 /* The Scatter-Gather List Entry. The scatter or gather component used with 154 * a Octeon input instruction has this format. 155 */ 156 struct octeon_sg_entry { 157 /** The first 64 bit gives the size of data in each dptr.*/ 158 union { 159 u16 size[4]; 160 u64 size64; 161 } u; 162 163 /** The 4 dptr pointers for this entry. */ 164 u64 ptr[4]; 165 166 }; 167 168 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 169 170 /* \brief Add size to gather list 171 * @param sg_entry scatter/gather entry 172 * @param size size to add 173 * @param pos position to add it. 174 */ 175 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 176 u16 size, 177 u32 pos) 178 { 179 #ifdef __BIG_ENDIAN_BITFIELD 180 sg_entry->u.size[pos] = size; 181 #else 182 sg_entry->u.size[3 - pos] = size; 183 #endif 184 } 185 186 /*------------------------- End Scatter/Gather ---------------------------*/ 187 188 #define OCTNET_FRM_LENGTH_SIZE 8 189 190 #define OCTNET_FRM_PTP_HEADER_SIZE 8 191 192 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 193 194 #define OCTNET_MIN_FRM_SIZE 64 195 196 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 197 198 #define OCTNET_DEFAULT_MTU (1500) 199 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE) 200 201 /** NIC Commands are sent using this Octeon Input Queue */ 202 #define OCTNET_CMD_Q 0 203 204 /* NIC Command types */ 205 #define OCTNET_CMD_CHANGE_MTU 0x1 206 #define OCTNET_CMD_CHANGE_MACADDR 0x2 207 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 208 #define OCTNET_CMD_RX_CTL 0x4 209 210 #define OCTNET_CMD_SET_MULTI_LIST 0x5 211 #define OCTNET_CMD_CLEAR_STATS 0x6 212 213 /* command for setting the speed, duplex & autoneg */ 214 #define OCTNET_CMD_SET_SETTINGS 0x7 215 #define OCTNET_CMD_SET_FLOW_CTL 0x8 216 217 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 218 #define OCTNET_CMD_GPIO_ACCESS 0xA 219 #define OCTNET_CMD_LRO_ENABLE 0xB 220 #define OCTNET_CMD_LRO_DISABLE 0xC 221 #define OCTNET_CMD_SET_RSS 0xD 222 #define OCTNET_CMD_WRITE_SA 0xE 223 #define OCTNET_CMD_DELETE_SA 0xF 224 #define OCTNET_CMD_UPDATE_SA 0x12 225 226 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 227 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 228 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 229 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 230 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 231 232 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 233 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 234 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 235 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 236 237 #define OCTNET_CMD_ID_ACTIVE 0x1a 238 239 #define OCTNET_CMD_SET_UC_LIST 0x1b 240 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 241 242 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 243 244 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 245 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 246 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 247 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 248 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 249 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 250 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 251 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 252 253 #define SEAPI_CMD_SPEED_SET 0x2 254 #define SEAPI_CMD_SPEED_GET 0x3 255 256 #define LIO_CMD_WAIT_TM 100 257 258 /* RX(packets coming from wire) Checksum verification flags */ 259 /* TCP/UDP csum */ 260 #define CNNIC_L4SUM_VERIFIED 0x1 261 #define CNNIC_IPSUM_VERIFIED 0x2 262 #define CNNIC_TUN_CSUM_VERIFIED 0x4 263 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 264 265 /*LROIPV4 and LROIPV6 Flags*/ 266 #define OCTNIC_LROIPV4 0x1 267 #define OCTNIC_LROIPV6 0x2 268 269 /* Interface flags communicated between host driver and core app. */ 270 enum octnet_ifflags { 271 OCTNET_IFFLAG_PROMISC = 0x01, 272 OCTNET_IFFLAG_ALLMULTI = 0x02, 273 OCTNET_IFFLAG_MULTICAST = 0x04, 274 OCTNET_IFFLAG_BROADCAST = 0x08, 275 OCTNET_IFFLAG_UNICAST = 0x10 276 }; 277 278 /* wqe 279 * --------------- 0 280 * | wqe word0-3 | 281 * --------------- 32 282 * | PCI IH | 283 * --------------- 40 284 * | RPTR | 285 * --------------- 48 286 * | PCI IRH | 287 * --------------- 56 288 * | OCT_NET_CMD | 289 * --------------- 64 290 * | Addtl 8-BData | 291 * | | 292 * --------------- 293 */ 294 295 union octnet_cmd { 296 u64 u64; 297 298 struct { 299 #ifdef __BIG_ENDIAN_BITFIELD 300 u64 cmd:5; 301 302 u64 more:6; /* How many udd words follow the command */ 303 304 u64 reserved:29; 305 306 u64 param1:16; 307 308 u64 param2:8; 309 310 #else 311 312 u64 param2:8; 313 314 u64 param1:16; 315 316 u64 reserved:29; 317 318 u64 more:6; 319 320 u64 cmd:5; 321 322 #endif 323 } s; 324 325 }; 326 327 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 328 329 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 330 #define LIO_SOFTCMDRESP_IH2 40 331 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 332 333 #define LIO_PCICMD_O2 24 334 #define LIO_PCICMD_O3 (24 + 8) 335 336 /* Instruction Header(DPI) - for OCTEON-III models */ 337 struct octeon_instr_ih3 { 338 #ifdef __BIG_ENDIAN_BITFIELD 339 340 /** Reserved3 */ 341 u64 reserved3:1; 342 343 /** Gather indicator 1=gather*/ 344 u64 gather:1; 345 346 /** Data length OR no. of entries in gather list */ 347 u64 dlengsz:14; 348 349 /** Front Data size */ 350 u64 fsz:6; 351 352 /** Reserved2 */ 353 u64 reserved2:4; 354 355 /** PKI port kind - PKIND */ 356 u64 pkind:6; 357 358 /** Reserved1 */ 359 u64 reserved1:32; 360 361 #else 362 /** Reserved1 */ 363 u64 reserved1:32; 364 365 /** PKI port kind - PKIND */ 366 u64 pkind:6; 367 368 /** Reserved2 */ 369 u64 reserved2:4; 370 371 /** Front Data size */ 372 u64 fsz:6; 373 374 /** Data length OR no. of entries in gather list */ 375 u64 dlengsz:14; 376 377 /** Gather indicator 1=gather*/ 378 u64 gather:1; 379 380 /** Reserved3 */ 381 u64 reserved3:1; 382 383 #endif 384 }; 385 386 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 387 /** BIG ENDIAN format. */ 388 struct octeon_instr_pki_ih3 { 389 #ifdef __BIG_ENDIAN_BITFIELD 390 391 /** Wider bit */ 392 u64 w:1; 393 394 /** Raw mode indicator 1 = RAW */ 395 u64 raw:1; 396 397 /** Use Tag */ 398 u64 utag:1; 399 400 /** Use QPG */ 401 u64 uqpg:1; 402 403 /** Reserved2 */ 404 u64 reserved2:1; 405 406 /** Parse Mode */ 407 u64 pm:3; 408 409 /** Skip Length */ 410 u64 sl:8; 411 412 /** Use Tag Type */ 413 u64 utt:1; 414 415 /** Tag type */ 416 u64 tagtype:2; 417 418 /** Reserved1 */ 419 u64 reserved1:2; 420 421 /** QPG Value */ 422 u64 qpg:11; 423 424 /** Tag Value */ 425 u64 tag:32; 426 427 #else 428 429 /** Tag Value */ 430 u64 tag:32; 431 432 /** QPG Value */ 433 u64 qpg:11; 434 435 /** Reserved1 */ 436 u64 reserved1:2; 437 438 /** Tag type */ 439 u64 tagtype:2; 440 441 /** Use Tag Type */ 442 u64 utt:1; 443 444 /** Skip Length */ 445 u64 sl:8; 446 447 /** Parse Mode */ 448 u64 pm:3; 449 450 /** Reserved2 */ 451 u64 reserved2:1; 452 453 /** Use QPG */ 454 u64 uqpg:1; 455 456 /** Use Tag */ 457 u64 utag:1; 458 459 /** Raw mode indicator 1 = RAW */ 460 u64 raw:1; 461 462 /** Wider bit */ 463 u64 w:1; 464 #endif 465 466 }; 467 468 /** Instruction Header */ 469 struct octeon_instr_ih2 { 470 #ifdef __BIG_ENDIAN_BITFIELD 471 /** Raw mode indicator 1 = RAW */ 472 u64 raw:1; 473 474 /** Gather indicator 1=gather*/ 475 u64 gather:1; 476 477 /** Data length OR no. of entries in gather list */ 478 u64 dlengsz:14; 479 480 /** Front Data size */ 481 u64 fsz:6; 482 483 /** Packet Order / Work Unit selection (1 of 8)*/ 484 u64 qos:3; 485 486 /** Core group selection (1 of 16) */ 487 u64 grp:4; 488 489 /** Short Raw Packet Indicator 1=short raw pkt */ 490 u64 rs:1; 491 492 /** Tag type */ 493 u64 tagtype:2; 494 495 /** Tag Value */ 496 u64 tag:32; 497 #else 498 /** Tag Value */ 499 u64 tag:32; 500 501 /** Tag type */ 502 u64 tagtype:2; 503 504 /** Short Raw Packet Indicator 1=short raw pkt */ 505 u64 rs:1; 506 507 /** Core group selection (1 of 16) */ 508 u64 grp:4; 509 510 /** Packet Order / Work Unit selection (1 of 8)*/ 511 u64 qos:3; 512 513 /** Front Data size */ 514 u64 fsz:6; 515 516 /** Data length OR no. of entries in gather list */ 517 u64 dlengsz:14; 518 519 /** Gather indicator 1=gather*/ 520 u64 gather:1; 521 522 /** Raw mode indicator 1 = RAW */ 523 u64 raw:1; 524 #endif 525 }; 526 527 /** Input Request Header */ 528 struct octeon_instr_irh { 529 #ifdef __BIG_ENDIAN_BITFIELD 530 u64 opcode:4; 531 u64 rflag:1; 532 u64 subcode:7; 533 u64 vlan:12; 534 u64 priority:3; 535 u64 reserved:5; 536 u64 ossp:32; /* opcode/subcode specific parameters */ 537 #else 538 u64 ossp:32; /* opcode/subcode specific parameters */ 539 u64 reserved:5; 540 u64 priority:3; 541 u64 vlan:12; 542 u64 subcode:7; 543 u64 rflag:1; 544 u64 opcode:4; 545 #endif 546 }; 547 548 /** Return Data Parameters */ 549 struct octeon_instr_rdp { 550 #ifdef __BIG_ENDIAN_BITFIELD 551 u64 reserved:49; 552 u64 pcie_port:3; 553 u64 rlen:12; 554 #else 555 u64 rlen:12; 556 u64 pcie_port:3; 557 u64 reserved:49; 558 #endif 559 }; 560 561 /** Receive Header */ 562 union octeon_rh { 563 #ifdef __BIG_ENDIAN_BITFIELD 564 u64 u64; 565 struct { 566 u64 opcode:4; 567 u64 subcode:8; 568 u64 len:3; /** additional 64-bit words */ 569 u64 reserved:17; 570 u64 ossp:32; /** opcode/subcode specific parameters */ 571 } r; 572 struct { 573 u64 opcode:4; 574 u64 subcode:8; 575 u64 len:3; /** additional 64-bit words */ 576 u64 extra:28; 577 u64 vlan:12; 578 u64 priority:3; 579 u64 csum_verified:3; /** checksum verified. */ 580 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 581 u64 encap_on:1; 582 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 583 } r_dh; 584 struct { 585 u64 opcode:4; 586 u64 subcode:8; 587 u64 len:3; /** additional 64-bit words */ 588 u64 reserved:11; 589 u64 num_gmx_ports:8; 590 u64 max_nic_ports:10; 591 u64 app_cap_flags:4; 592 u64 app_mode:8; 593 u64 pkind:8; 594 } r_core_drv_init; 595 struct { 596 u64 opcode:4; 597 u64 subcode:8; 598 u64 len:3; /** additional 64-bit words */ 599 u64 reserved:8; 600 u64 extra:25; 601 u64 gmxport:16; 602 } r_nic_info; 603 #else 604 u64 u64; 605 struct { 606 u64 ossp:32; /** opcode/subcode specific parameters */ 607 u64 reserved:17; 608 u64 len:3; /** additional 64-bit words */ 609 u64 subcode:8; 610 u64 opcode:4; 611 } r; 612 struct { 613 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 614 u64 encap_on:1; 615 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 616 u64 csum_verified:3; /** checksum verified. */ 617 u64 priority:3; 618 u64 vlan:12; 619 u64 extra:28; 620 u64 len:3; /** additional 64-bit words */ 621 u64 subcode:8; 622 u64 opcode:4; 623 } r_dh; 624 struct { 625 u64 pkind:8; 626 u64 app_mode:8; 627 u64 app_cap_flags:4; 628 u64 max_nic_ports:10; 629 u64 num_gmx_ports:8; 630 u64 reserved:11; 631 u64 len:3; /** additional 64-bit words */ 632 u64 subcode:8; 633 u64 opcode:4; 634 } r_core_drv_init; 635 struct { 636 u64 gmxport:16; 637 u64 extra:25; 638 u64 reserved:8; 639 u64 len:3; /** additional 64-bit words */ 640 u64 subcode:8; 641 u64 opcode:4; 642 } r_nic_info; 643 #endif 644 }; 645 646 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 647 648 union octnic_packet_params { 649 u32 u32; 650 struct { 651 #ifdef __BIG_ENDIAN_BITFIELD 652 u32 reserved:24; 653 u32 ip_csum:1; /* Perform IP header checksum(s) */ 654 /* Perform Outer transport header checksum */ 655 u32 transport_csum:1; 656 /* Find tunnel, and perform transport csum. */ 657 u32 tnl_csum:1; 658 u32 tsflag:1; /* Timestamp this packet */ 659 u32 ipsec_ops:4; /* IPsec operation */ 660 #else 661 u32 ipsec_ops:4; 662 u32 tsflag:1; 663 u32 tnl_csum:1; 664 u32 transport_csum:1; 665 u32 ip_csum:1; 666 u32 reserved:24; 667 #endif 668 } s; 669 }; 670 671 /** Status of a RGMII Link on Octeon as seen by core driver. */ 672 union oct_link_status { 673 u64 u64; 674 675 struct { 676 #ifdef __BIG_ENDIAN_BITFIELD 677 u64 duplex:8; 678 u64 mtu:16; 679 u64 speed:16; 680 u64 link_up:1; 681 u64 autoneg:1; 682 u64 if_mode:5; 683 u64 pause:1; 684 u64 flashing:1; 685 u64 phy_type:5; 686 u64 reserved:10; 687 #else 688 u64 reserved:10; 689 u64 phy_type:5; 690 u64 flashing:1; 691 u64 pause:1; 692 u64 if_mode:5; 693 u64 autoneg:1; 694 u64 link_up:1; 695 u64 speed:16; 696 u64 mtu:16; 697 u64 duplex:8; 698 #endif 699 } s; 700 }; 701 702 enum lio_phy_type { 703 LIO_PHY_PORT_TP = 0x0, 704 LIO_PHY_PORT_FIBRE = 0x1, 705 LIO_PHY_PORT_UNKNOWN, 706 }; 707 708 /** The txpciq info passed to host from the firmware */ 709 710 union oct_txpciq { 711 u64 u64; 712 713 struct { 714 #ifdef __BIG_ENDIAN_BITFIELD 715 u64 q_no:8; 716 u64 port:8; 717 u64 pkind:6; 718 u64 use_qpg:1; 719 u64 qpg:11; 720 u64 reserved0:10; 721 u64 ctrl_qpg:11; 722 u64 reserved:9; 723 #else 724 u64 reserved:9; 725 u64 ctrl_qpg:11; 726 u64 reserved0:10; 727 u64 qpg:11; 728 u64 use_qpg:1; 729 u64 pkind:6; 730 u64 port:8; 731 u64 q_no:8; 732 #endif 733 } s; 734 }; 735 736 /** The rxpciq info passed to host from the firmware */ 737 738 union oct_rxpciq { 739 u64 u64; 740 741 struct { 742 #ifdef __BIG_ENDIAN_BITFIELD 743 u64 q_no:8; 744 u64 reserved:56; 745 #else 746 u64 reserved:56; 747 u64 q_no:8; 748 #endif 749 } s; 750 }; 751 752 /** Information for a OCTEON ethernet interface shared between core & host. */ 753 struct oct_link_info { 754 union oct_link_status link; 755 u64 hw_addr; 756 757 #ifdef __BIG_ENDIAN_BITFIELD 758 u64 gmxport:16; 759 u64 macaddr_is_admin_asgnd:1; 760 u64 rsvd:31; 761 u64 num_txpciq:8; 762 u64 num_rxpciq:8; 763 #else 764 u64 num_rxpciq:8; 765 u64 num_txpciq:8; 766 u64 rsvd:31; 767 u64 macaddr_is_admin_asgnd:1; 768 u64 gmxport:16; 769 #endif 770 771 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 772 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 773 }; 774 775 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 776 777 struct liquidio_if_cfg_info { 778 u64 iqmask; /** mask for IQs enabled for the port */ 779 u64 oqmask; /** mask for OQs enabled for the port */ 780 struct oct_link_info linfo; /** initial link information */ 781 char liquidio_firmware_version[32]; 782 }; 783 784 /** Stats for each NIC port in RX direction. */ 785 struct nic_rx_stats { 786 /* link-level stats */ 787 u64 total_rcvd; /* Received packets */ 788 u64 bytes_rcvd; /* Octets of received packets */ 789 u64 total_bcst; /* Number of non-dropped L2 broadcast packets */ 790 u64 total_mcst; /* Number of non-dropped L2 multicast packets */ 791 u64 runts; /* Packets shorter than allowed */ 792 u64 ctl_rcvd; /* Received PAUSE packets */ 793 u64 fifo_err; /* Packets dropped due to RX FIFO full */ 794 u64 dmac_drop; /* Packets dropped by the DMAC filter */ 795 u64 fcs_err; /* Sum of fragment, overrun, and FCS errors */ 796 u64 jabber_err; /* Packets larger than allowed */ 797 u64 l2_err; /* Sum of DMA, parity, PCAM access, no memory, 798 * buffer overflow, malformed L2 header or 799 * length, oversize errors 800 **/ 801 u64 frame_err; /* Sum of IPv4 and L4 checksum errors */ 802 u64 red_drops; /* Packets dropped by RED due to buffer 803 * exhaustion 804 **/ 805 806 /* firmware stats */ 807 u64 fw_total_rcvd; 808 u64 fw_total_fwd; 809 u64 fw_total_fwd_bytes; 810 u64 fw_total_mcast; 811 u64 fw_total_bcast; 812 813 u64 fw_err_pko; 814 u64 fw_err_link; 815 u64 fw_err_drop; 816 u64 fw_rx_vxlan; 817 u64 fw_rx_vxlan_err; 818 819 /* LRO */ 820 u64 fw_lro_pkts; /* Number of packets that are LROed */ 821 u64 fw_lro_octs; /* Number of octets that are LROed */ 822 u64 fw_total_lro; /* Number of LRO packets formed */ 823 u64 fw_lro_aborts; /* Number of times LRO of packet aborted */ 824 u64 fw_lro_aborts_port; 825 u64 fw_lro_aborts_seq; 826 u64 fw_lro_aborts_tsval; 827 u64 fw_lro_aborts_timer; /* Timer setting error */ 828 /* intrmod: packet forward rate */ 829 u64 fwd_rate; 830 }; 831 832 /** Stats for each NIC port in RX direction. */ 833 struct nic_tx_stats { 834 /* link-level stats */ 835 u64 total_pkts_sent; /* Total frames sent on the interface */ 836 u64 total_bytes_sent; /* Total octets sent on the interface */ 837 u64 mcast_pkts_sent; /* Packets sent to the multicast DMAC */ 838 u64 bcast_pkts_sent; /* Packets sent to a broadcast DMAC */ 839 u64 ctl_sent; /* Control/PAUSE packets sent */ 840 u64 one_collision_sent; /* Packets sent that experienced a 841 * single collision before successful 842 * transmission 843 **/ 844 u64 multi_collision_sent; /* Packets sent that experienced 845 * multiple collisions before successful 846 * transmission 847 **/ 848 u64 max_collision_fail; /* Packets dropped due to excessive 849 * collisions 850 **/ 851 u64 max_deferral_fail; /* Packets not sent due to max 852 * deferrals 853 **/ 854 u64 fifo_err; /* Packets sent that experienced a 855 * transmit underflow and were 856 * truncated 857 **/ 858 u64 runts; /* Packets sent with an octet count 859 * lessthan 64 860 **/ 861 u64 total_collisions; /* Packets dropped due to excessive 862 * collisions 863 **/ 864 865 /* firmware stats */ 866 u64 fw_total_sent; 867 u64 fw_total_fwd; 868 u64 fw_total_fwd_bytes; 869 u64 fw_total_mcast_sent; 870 u64 fw_total_bcast_sent; 871 u64 fw_err_pko; 872 u64 fw_err_link; 873 u64 fw_err_drop; 874 u64 fw_err_tso; 875 u64 fw_tso; /* number of tso requests */ 876 u64 fw_tso_fwd; /* number of packets segmented in tso */ 877 u64 fw_tx_vxlan; 878 u64 fw_err_pki; 879 }; 880 881 struct oct_link_stats { 882 struct nic_rx_stats fromwire; 883 struct nic_tx_stats fromhost; 884 885 }; 886 887 static inline int opcode_slow_path(union octeon_rh *rh) 888 { 889 u16 subcode1, subcode2; 890 891 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 892 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 893 894 return (subcode2 != subcode1); 895 } 896 897 #define LIO68XX_LED_CTRL_ADDR 0x3501 898 #define LIO68XX_LED_CTRL_CFGON 0x1f 899 #define LIO68XX_LED_CTRL_CFGOFF 0x100 900 #define LIO68XX_LED_BEACON_ADDR 0x3508 901 #define LIO68XX_LED_BEACON_CFGON 0x47fd 902 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 903 #define VITESSE_PHY_GPIO_DRIVEON 0x1 904 #define VITESSE_PHY_GPIO_CFG 0x8 905 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 906 #define VITESSE_PHY_GPIO_HIGH 0x2 907 #define VITESSE_PHY_GPIO_LOW 0x3 908 #define LED_IDENTIFICATION_ON 0x1 909 #define LED_IDENTIFICATION_OFF 0x0 910 #define LIO23XX_COPPERHEAD_LED_GPIO 0x2 911 912 struct oct_mdio_cmd { 913 u64 op; 914 u64 mdio_addr; 915 u64 value1; 916 u64 value2; 917 u64 value3; 918 }; 919 920 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 921 922 struct oct_intrmod_cfg { 923 u64 rx_enable; 924 u64 tx_enable; 925 u64 check_intrvl; 926 u64 maxpkt_ratethr; 927 u64 minpkt_ratethr; 928 u64 rx_maxcnt_trigger; 929 u64 rx_mincnt_trigger; 930 u64 rx_maxtmr_trigger; 931 u64 rx_mintmr_trigger; 932 u64 tx_mincnt_trigger; 933 u64 tx_maxcnt_trigger; 934 u64 rx_frames; 935 u64 tx_frames; 936 u64 rx_usecs; 937 }; 938 939 #define BASE_QUEUE_NOT_REQUESTED 65535 940 941 union oct_nic_if_cfg { 942 u64 u64; 943 struct { 944 #ifdef __BIG_ENDIAN_BITFIELD 945 u64 base_queue:16; 946 u64 num_iqueues:16; 947 u64 num_oqueues:16; 948 u64 gmx_port_id:8; 949 u64 vf_id:8; 950 #else 951 u64 vf_id:8; 952 u64 gmx_port_id:8; 953 u64 num_oqueues:16; 954 u64 num_iqueues:16; 955 u64 base_queue:16; 956 #endif 957 } s; 958 }; 959 960 struct lio_trusted_vf { 961 uint64_t active: 1; 962 uint64_t id : 8; 963 uint64_t reserved: 55; 964 }; 965 966 struct lio_time { 967 s64 sec; /* seconds */ 968 s64 nsec; /* nanoseconds */ 969 }; 970 971 struct lio_vf_rep_stats { 972 u64 tx_packets; 973 u64 tx_bytes; 974 u64 tx_dropped; 975 976 u64 rx_packets; 977 u64 rx_bytes; 978 u64 rx_dropped; 979 }; 980 981 enum lio_vf_rep_req_type { 982 LIO_VF_REP_REQ_NONE, 983 LIO_VF_REP_REQ_STATE, 984 LIO_VF_REP_REQ_MTU, 985 LIO_VF_REP_REQ_STATS, 986 LIO_VF_REP_REQ_DEVNAME 987 }; 988 989 enum { 990 LIO_VF_REP_STATE_DOWN, 991 LIO_VF_REP_STATE_UP 992 }; 993 994 #define LIO_IF_NAME_SIZE 16 995 struct lio_vf_rep_req { 996 u8 req_type; 997 u8 ifidx; 998 u8 rsvd[6]; 999 1000 union { 1001 struct lio_vf_rep_name { 1002 char name[LIO_IF_NAME_SIZE]; 1003 } rep_name; 1004 1005 struct lio_vf_rep_mtu { 1006 u32 mtu; 1007 u32 rsvd; 1008 } rep_mtu; 1009 1010 struct lio_vf_rep_state { 1011 u8 state; 1012 u8 rsvd[7]; 1013 } rep_state; 1014 }; 1015 }; 1016 1017 struct lio_vf_rep_resp { 1018 u64 rh; 1019 u8 status; 1020 u8 rsvd[7]; 1021 }; 1022 #endif 1023