1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 6 31 #define LIQUIDIO_BASE_MICRO_VERSION 0 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define VF_DRV_LOADED 1 88 #define VF_DRV_REMOVED -1 89 #define VF_DRV_MACADDR_CHANGED 2 90 91 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 92 93 /* Application codes advertised by the core driver initialization packet. */ 94 #define CVM_DRV_APP_START 0x0 95 #define CVM_DRV_NO_APP 0 96 #define CVM_DRV_APP_COUNT 0x2 97 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 98 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 99 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 100 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 101 102 #define BYTES_PER_DHLEN_UNIT 8 103 #define MAX_REG_CNT 2000000U 104 #define INTRNAMSIZ 32 105 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 106 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 107 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 108 109 110 static inline u32 incr_index(u32 index, u32 count, u32 max) 111 { 112 if ((index + count) >= max) 113 index = index + count - max; 114 else 115 index += count; 116 117 return index; 118 } 119 120 #define OCT_BOARD_NAME 32 121 #define OCT_SERIAL_LEN 64 122 123 /* Structure used by core driver to send indication that the Octeon 124 * application is ready. 125 */ 126 struct octeon_core_setup { 127 u64 corefreq; 128 129 char boardname[OCT_BOARD_NAME]; 130 131 char board_serial_number[OCT_SERIAL_LEN]; 132 133 u64 board_rev_major; 134 135 u64 board_rev_minor; 136 137 }; 138 139 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 140 141 /* The Scatter-Gather List Entry. The scatter or gather component used with 142 * a Octeon input instruction has this format. 143 */ 144 struct octeon_sg_entry { 145 /** The first 64 bit gives the size of data in each dptr.*/ 146 union { 147 u16 size[4]; 148 u64 size64; 149 } u; 150 151 /** The 4 dptr pointers for this entry. */ 152 u64 ptr[4]; 153 154 }; 155 156 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 157 158 /* \brief Add size to gather list 159 * @param sg_entry scatter/gather entry 160 * @param size size to add 161 * @param pos position to add it. 162 */ 163 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 164 u16 size, 165 u32 pos) 166 { 167 #ifdef __BIG_ENDIAN_BITFIELD 168 sg_entry->u.size[pos] = size; 169 #else 170 sg_entry->u.size[3 - pos] = size; 171 #endif 172 } 173 174 /*------------------------- End Scatter/Gather ---------------------------*/ 175 176 #define OCTNET_FRM_LENGTH_SIZE 8 177 178 #define OCTNET_FRM_PTP_HEADER_SIZE 8 179 180 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 181 182 #define OCTNET_MIN_FRM_SIZE 64 183 184 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 185 186 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE) 187 188 /** NIC Commands are sent using this Octeon Input Queue */ 189 #define OCTNET_CMD_Q 0 190 191 /* NIC Command types */ 192 #define OCTNET_CMD_RESET_PF 0x0 193 #define OCTNET_CMD_CHANGE_MTU 0x1 194 #define OCTNET_CMD_CHANGE_MACADDR 0x2 195 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 196 #define OCTNET_CMD_RX_CTL 0x4 197 198 #define OCTNET_CMD_SET_MULTI_LIST 0x5 199 #define OCTNET_CMD_CLEAR_STATS 0x6 200 201 /* command for setting the speed, duplex & autoneg */ 202 #define OCTNET_CMD_SET_SETTINGS 0x7 203 #define OCTNET_CMD_SET_FLOW_CTL 0x8 204 205 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 206 #define OCTNET_CMD_GPIO_ACCESS 0xA 207 #define OCTNET_CMD_LRO_ENABLE 0xB 208 #define OCTNET_CMD_LRO_DISABLE 0xC 209 #define OCTNET_CMD_SET_RSS 0xD 210 #define OCTNET_CMD_WRITE_SA 0xE 211 #define OCTNET_CMD_DELETE_SA 0xF 212 #define OCTNET_CMD_UPDATE_SA 0x12 213 214 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 215 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 216 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 217 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 218 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 219 220 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 221 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 222 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 223 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 224 225 #define OCTNET_CMD_ID_ACTIVE 0x1a 226 227 #define OCTNET_CMD_SET_UC_LIST 0x1b 228 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 229 230 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 231 232 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 233 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 234 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 235 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 236 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 237 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 238 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 239 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 240 241 /* RX(packets coming from wire) Checksum verification flags */ 242 /* TCP/UDP csum */ 243 #define CNNIC_L4SUM_VERIFIED 0x1 244 #define CNNIC_IPSUM_VERIFIED 0x2 245 #define CNNIC_TUN_CSUM_VERIFIED 0x4 246 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 247 248 /*LROIPV4 and LROIPV6 Flags*/ 249 #define OCTNIC_LROIPV4 0x1 250 #define OCTNIC_LROIPV6 0x2 251 252 /* Interface flags communicated between host driver and core app. */ 253 enum octnet_ifflags { 254 OCTNET_IFFLAG_PROMISC = 0x01, 255 OCTNET_IFFLAG_ALLMULTI = 0x02, 256 OCTNET_IFFLAG_MULTICAST = 0x04, 257 OCTNET_IFFLAG_BROADCAST = 0x08, 258 OCTNET_IFFLAG_UNICAST = 0x10 259 }; 260 261 /* wqe 262 * --------------- 0 263 * | wqe word0-3 | 264 * --------------- 32 265 * | PCI IH | 266 * --------------- 40 267 * | RPTR | 268 * --------------- 48 269 * | PCI IRH | 270 * --------------- 56 271 * | OCT_NET_CMD | 272 * --------------- 64 273 * | Addtl 8-BData | 274 * | | 275 * --------------- 276 */ 277 278 union octnet_cmd { 279 u64 u64; 280 281 struct { 282 #ifdef __BIG_ENDIAN_BITFIELD 283 u64 cmd:5; 284 285 u64 more:6; /* How many udd words follow the command */ 286 287 u64 reserved:29; 288 289 u64 param1:16; 290 291 u64 param2:8; 292 293 #else 294 295 u64 param2:8; 296 297 u64 param1:16; 298 299 u64 reserved:29; 300 301 u64 more:6; 302 303 u64 cmd:5; 304 305 #endif 306 } s; 307 308 }; 309 310 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 311 312 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 313 #define LIO_SOFTCMDRESP_IH2 40 314 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 315 316 #define LIO_PCICMD_O2 24 317 #define LIO_PCICMD_O3 (24 + 8) 318 319 /* Instruction Header(DPI) - for OCTEON-III models */ 320 struct octeon_instr_ih3 { 321 #ifdef __BIG_ENDIAN_BITFIELD 322 323 /** Reserved3 */ 324 u64 reserved3:1; 325 326 /** Gather indicator 1=gather*/ 327 u64 gather:1; 328 329 /** Data length OR no. of entries in gather list */ 330 u64 dlengsz:14; 331 332 /** Front Data size */ 333 u64 fsz:6; 334 335 /** Reserved2 */ 336 u64 reserved2:4; 337 338 /** PKI port kind - PKIND */ 339 u64 pkind:6; 340 341 /** Reserved1 */ 342 u64 reserved1:32; 343 344 #else 345 /** Reserved1 */ 346 u64 reserved1:32; 347 348 /** PKI port kind - PKIND */ 349 u64 pkind:6; 350 351 /** Reserved2 */ 352 u64 reserved2:4; 353 354 /** Front Data size */ 355 u64 fsz:6; 356 357 /** Data length OR no. of entries in gather list */ 358 u64 dlengsz:14; 359 360 /** Gather indicator 1=gather*/ 361 u64 gather:1; 362 363 /** Reserved3 */ 364 u64 reserved3:1; 365 366 #endif 367 }; 368 369 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 370 /** BIG ENDIAN format. */ 371 struct octeon_instr_pki_ih3 { 372 #ifdef __BIG_ENDIAN_BITFIELD 373 374 /** Wider bit */ 375 u64 w:1; 376 377 /** Raw mode indicator 1 = RAW */ 378 u64 raw:1; 379 380 /** Use Tag */ 381 u64 utag:1; 382 383 /** Use QPG */ 384 u64 uqpg:1; 385 386 /** Reserved2 */ 387 u64 reserved2:1; 388 389 /** Parse Mode */ 390 u64 pm:3; 391 392 /** Skip Length */ 393 u64 sl:8; 394 395 /** Use Tag Type */ 396 u64 utt:1; 397 398 /** Tag type */ 399 u64 tagtype:2; 400 401 /** Reserved1 */ 402 u64 reserved1:2; 403 404 /** QPG Value */ 405 u64 qpg:11; 406 407 /** Tag Value */ 408 u64 tag:32; 409 410 #else 411 412 /** Tag Value */ 413 u64 tag:32; 414 415 /** QPG Value */ 416 u64 qpg:11; 417 418 /** Reserved1 */ 419 u64 reserved1:2; 420 421 /** Tag type */ 422 u64 tagtype:2; 423 424 /** Use Tag Type */ 425 u64 utt:1; 426 427 /** Skip Length */ 428 u64 sl:8; 429 430 /** Parse Mode */ 431 u64 pm:3; 432 433 /** Reserved2 */ 434 u64 reserved2:1; 435 436 /** Use QPG */ 437 u64 uqpg:1; 438 439 /** Use Tag */ 440 u64 utag:1; 441 442 /** Raw mode indicator 1 = RAW */ 443 u64 raw:1; 444 445 /** Wider bit */ 446 u64 w:1; 447 #endif 448 449 }; 450 451 /** Instruction Header */ 452 struct octeon_instr_ih2 { 453 #ifdef __BIG_ENDIAN_BITFIELD 454 /** Raw mode indicator 1 = RAW */ 455 u64 raw:1; 456 457 /** Gather indicator 1=gather*/ 458 u64 gather:1; 459 460 /** Data length OR no. of entries in gather list */ 461 u64 dlengsz:14; 462 463 /** Front Data size */ 464 u64 fsz:6; 465 466 /** Packet Order / Work Unit selection (1 of 8)*/ 467 u64 qos:3; 468 469 /** Core group selection (1 of 16) */ 470 u64 grp:4; 471 472 /** Short Raw Packet Indicator 1=short raw pkt */ 473 u64 rs:1; 474 475 /** Tag type */ 476 u64 tagtype:2; 477 478 /** Tag Value */ 479 u64 tag:32; 480 #else 481 /** Tag Value */ 482 u64 tag:32; 483 484 /** Tag type */ 485 u64 tagtype:2; 486 487 /** Short Raw Packet Indicator 1=short raw pkt */ 488 u64 rs:1; 489 490 /** Core group selection (1 of 16) */ 491 u64 grp:4; 492 493 /** Packet Order / Work Unit selection (1 of 8)*/ 494 u64 qos:3; 495 496 /** Front Data size */ 497 u64 fsz:6; 498 499 /** Data length OR no. of entries in gather list */ 500 u64 dlengsz:14; 501 502 /** Gather indicator 1=gather*/ 503 u64 gather:1; 504 505 /** Raw mode indicator 1 = RAW */ 506 u64 raw:1; 507 #endif 508 }; 509 510 /** Input Request Header */ 511 struct octeon_instr_irh { 512 #ifdef __BIG_ENDIAN_BITFIELD 513 u64 opcode:4; 514 u64 rflag:1; 515 u64 subcode:7; 516 u64 vlan:12; 517 u64 priority:3; 518 u64 reserved:5; 519 u64 ossp:32; /* opcode/subcode specific parameters */ 520 #else 521 u64 ossp:32; /* opcode/subcode specific parameters */ 522 u64 reserved:5; 523 u64 priority:3; 524 u64 vlan:12; 525 u64 subcode:7; 526 u64 rflag:1; 527 u64 opcode:4; 528 #endif 529 }; 530 531 /** Return Data Parameters */ 532 struct octeon_instr_rdp { 533 #ifdef __BIG_ENDIAN_BITFIELD 534 u64 reserved:49; 535 u64 pcie_port:3; 536 u64 rlen:12; 537 #else 538 u64 rlen:12; 539 u64 pcie_port:3; 540 u64 reserved:49; 541 #endif 542 }; 543 544 /** Receive Header */ 545 union octeon_rh { 546 #ifdef __BIG_ENDIAN_BITFIELD 547 u64 u64; 548 struct { 549 u64 opcode:4; 550 u64 subcode:8; 551 u64 len:3; /** additional 64-bit words */ 552 u64 reserved:17; 553 u64 ossp:32; /** opcode/subcode specific parameters */ 554 } r; 555 struct { 556 u64 opcode:4; 557 u64 subcode:8; 558 u64 len:3; /** additional 64-bit words */ 559 u64 extra:28; 560 u64 vlan:12; 561 u64 priority:3; 562 u64 csum_verified:3; /** checksum verified. */ 563 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 564 u64 encap_on:1; 565 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 566 } r_dh; 567 struct { 568 u64 opcode:4; 569 u64 subcode:8; 570 u64 len:3; /** additional 64-bit words */ 571 u64 reserved:11; 572 u64 num_gmx_ports:8; 573 u64 max_nic_ports:10; 574 u64 app_cap_flags:4; 575 u64 app_mode:8; 576 u64 pkind:8; 577 } r_core_drv_init; 578 struct { 579 u64 opcode:4; 580 u64 subcode:8; 581 u64 len:3; /** additional 64-bit words */ 582 u64 reserved:8; 583 u64 extra:25; 584 u64 gmxport:16; 585 } r_nic_info; 586 #else 587 u64 u64; 588 struct { 589 u64 ossp:32; /** opcode/subcode specific parameters */ 590 u64 reserved:17; 591 u64 len:3; /** additional 64-bit words */ 592 u64 subcode:8; 593 u64 opcode:4; 594 } r; 595 struct { 596 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 597 u64 encap_on:1; 598 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 599 u64 csum_verified:3; /** checksum verified. */ 600 u64 priority:3; 601 u64 vlan:12; 602 u64 extra:28; 603 u64 len:3; /** additional 64-bit words */ 604 u64 subcode:8; 605 u64 opcode:4; 606 } r_dh; 607 struct { 608 u64 pkind:8; 609 u64 app_mode:8; 610 u64 app_cap_flags:4; 611 u64 max_nic_ports:10; 612 u64 num_gmx_ports:8; 613 u64 reserved:11; 614 u64 len:3; /** additional 64-bit words */ 615 u64 subcode:8; 616 u64 opcode:4; 617 } r_core_drv_init; 618 struct { 619 u64 gmxport:16; 620 u64 extra:25; 621 u64 reserved:8; 622 u64 len:3; /** additional 64-bit words */ 623 u64 subcode:8; 624 u64 opcode:4; 625 } r_nic_info; 626 #endif 627 }; 628 629 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 630 631 union octnic_packet_params { 632 u32 u32; 633 struct { 634 #ifdef __BIG_ENDIAN_BITFIELD 635 u32 reserved:24; 636 u32 ip_csum:1; /* Perform IP header checksum(s) */ 637 /* Perform Outer transport header checksum */ 638 u32 transport_csum:1; 639 /* Find tunnel, and perform transport csum. */ 640 u32 tnl_csum:1; 641 u32 tsflag:1; /* Timestamp this packet */ 642 u32 ipsec_ops:4; /* IPsec operation */ 643 #else 644 u32 ipsec_ops:4; 645 u32 tsflag:1; 646 u32 tnl_csum:1; 647 u32 transport_csum:1; 648 u32 ip_csum:1; 649 u32 reserved:24; 650 #endif 651 } s; 652 }; 653 654 /** Status of a RGMII Link on Octeon as seen by core driver. */ 655 union oct_link_status { 656 u64 u64; 657 658 struct { 659 #ifdef __BIG_ENDIAN_BITFIELD 660 u64 duplex:8; 661 u64 mtu:16; 662 u64 speed:16; 663 u64 link_up:1; 664 u64 autoneg:1; 665 u64 if_mode:5; 666 u64 pause:1; 667 u64 flashing:1; 668 u64 reserved:15; 669 #else 670 u64 reserved:15; 671 u64 flashing:1; 672 u64 pause:1; 673 u64 if_mode:5; 674 u64 autoneg:1; 675 u64 link_up:1; 676 u64 speed:16; 677 u64 mtu:16; 678 u64 duplex:8; 679 #endif 680 } s; 681 }; 682 683 /** The txpciq info passed to host from the firmware */ 684 685 union oct_txpciq { 686 u64 u64; 687 688 struct { 689 #ifdef __BIG_ENDIAN_BITFIELD 690 u64 q_no:8; 691 u64 port:8; 692 u64 pkind:6; 693 u64 use_qpg:1; 694 u64 qpg:11; 695 u64 reserved:30; 696 #else 697 u64 reserved:30; 698 u64 qpg:11; 699 u64 use_qpg:1; 700 u64 pkind:6; 701 u64 port:8; 702 u64 q_no:8; 703 #endif 704 } s; 705 }; 706 707 /** The rxpciq info passed to host from the firmware */ 708 709 union oct_rxpciq { 710 u64 u64; 711 712 struct { 713 #ifdef __BIG_ENDIAN_BITFIELD 714 u64 q_no:8; 715 u64 reserved:56; 716 #else 717 u64 reserved:56; 718 u64 q_no:8; 719 #endif 720 } s; 721 }; 722 723 /** Information for a OCTEON ethernet interface shared between core & host. */ 724 struct oct_link_info { 725 union oct_link_status link; 726 u64 hw_addr; 727 728 #ifdef __BIG_ENDIAN_BITFIELD 729 u64 gmxport:16; 730 u64 macaddr_is_admin_asgnd:1; 731 u64 rsvd:31; 732 u64 num_txpciq:8; 733 u64 num_rxpciq:8; 734 #else 735 u64 num_rxpciq:8; 736 u64 num_txpciq:8; 737 u64 rsvd:31; 738 u64 macaddr_is_admin_asgnd:1; 739 u64 gmxport:16; 740 #endif 741 742 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 743 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 744 }; 745 746 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 747 748 struct liquidio_if_cfg_info { 749 u64 iqmask; /** mask for IQs enabled for the port */ 750 u64 oqmask; /** mask for OQs enabled for the port */ 751 struct oct_link_info linfo; /** initial link information */ 752 char liquidio_firmware_version[32]; 753 }; 754 755 /** Stats for each NIC port in RX direction. */ 756 struct nic_rx_stats { 757 /* link-level stats */ 758 u64 total_rcvd; 759 u64 bytes_rcvd; 760 u64 total_bcst; 761 u64 total_mcst; 762 u64 runts; 763 u64 ctl_rcvd; 764 u64 fifo_err; /* Accounts for over/under-run of buffers */ 765 u64 dmac_drop; 766 u64 fcs_err; 767 u64 jabber_err; 768 u64 l2_err; 769 u64 frame_err; 770 771 /* firmware stats */ 772 u64 fw_total_rcvd; 773 u64 fw_total_fwd; 774 u64 fw_total_fwd_bytes; 775 u64 fw_err_pko; 776 u64 fw_err_link; 777 u64 fw_err_drop; 778 u64 fw_rx_vxlan; 779 u64 fw_rx_vxlan_err; 780 781 /* LRO */ 782 u64 fw_lro_pkts; /* Number of packets that are LROed */ 783 u64 fw_lro_octs; /* Number of octets that are LROed */ 784 u64 fw_total_lro; /* Number of LRO packets formed */ 785 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 786 u64 fw_lro_aborts_port; 787 u64 fw_lro_aborts_seq; 788 u64 fw_lro_aborts_tsval; 789 u64 fw_lro_aborts_timer; 790 /* intrmod: packet forward rate */ 791 u64 fwd_rate; 792 }; 793 794 /** Stats for each NIC port in RX direction. */ 795 struct nic_tx_stats { 796 /* link-level stats */ 797 u64 total_pkts_sent; 798 u64 total_bytes_sent; 799 u64 mcast_pkts_sent; 800 u64 bcast_pkts_sent; 801 u64 ctl_sent; 802 u64 one_collision_sent; /* Packets sent after one collision*/ 803 u64 multi_collision_sent; /* Packets sent after multiple collision*/ 804 u64 max_collision_fail; /* Packets not sent due to max collisions */ 805 u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 806 u64 fifo_err; /* Accounts for over/under-run of buffers */ 807 u64 runts; 808 u64 total_collisions; /* Total number of collisions detected */ 809 810 /* firmware stats */ 811 u64 fw_total_sent; 812 u64 fw_total_fwd; 813 u64 fw_total_fwd_bytes; 814 u64 fw_err_pko; 815 u64 fw_err_link; 816 u64 fw_err_drop; 817 u64 fw_err_tso; 818 u64 fw_tso; /* number of tso requests */ 819 u64 fw_tso_fwd; /* number of packets segmented in tso */ 820 u64 fw_tx_vxlan; 821 u64 fw_err_pki; 822 }; 823 824 struct oct_link_stats { 825 struct nic_rx_stats fromwire; 826 struct nic_tx_stats fromhost; 827 828 }; 829 830 static inline int opcode_slow_path(union octeon_rh *rh) 831 { 832 u16 subcode1, subcode2; 833 834 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 835 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 836 837 return (subcode2 != subcode1); 838 } 839 840 #define LIO68XX_LED_CTRL_ADDR 0x3501 841 #define LIO68XX_LED_CTRL_CFGON 0x1f 842 #define LIO68XX_LED_CTRL_CFGOFF 0x100 843 #define LIO68XX_LED_BEACON_ADDR 0x3508 844 #define LIO68XX_LED_BEACON_CFGON 0x47fd 845 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 846 #define VITESSE_PHY_GPIO_DRIVEON 0x1 847 #define VITESSE_PHY_GPIO_CFG 0x8 848 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 849 #define VITESSE_PHY_GPIO_HIGH 0x2 850 #define VITESSE_PHY_GPIO_LOW 0x3 851 #define LED_IDENTIFICATION_ON 0x1 852 #define LED_IDENTIFICATION_OFF 0x0 853 854 struct oct_mdio_cmd { 855 u64 op; 856 u64 mdio_addr; 857 u64 value1; 858 u64 value2; 859 u64 value3; 860 }; 861 862 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 863 864 struct oct_intrmod_cfg { 865 u64 rx_enable; 866 u64 tx_enable; 867 u64 check_intrvl; 868 u64 maxpkt_ratethr; 869 u64 minpkt_ratethr; 870 u64 rx_maxcnt_trigger; 871 u64 rx_mincnt_trigger; 872 u64 rx_maxtmr_trigger; 873 u64 rx_mintmr_trigger; 874 u64 tx_mincnt_trigger; 875 u64 tx_maxcnt_trigger; 876 u64 rx_frames; 877 u64 tx_frames; 878 u64 rx_usecs; 879 }; 880 881 #define BASE_QUEUE_NOT_REQUESTED 65535 882 883 union oct_nic_if_cfg { 884 u64 u64; 885 struct { 886 #ifdef __BIG_ENDIAN_BITFIELD 887 u64 base_queue:16; 888 u64 num_iqueues:16; 889 u64 num_oqueues:16; 890 u64 gmx_port_id:8; 891 u64 vf_id:8; 892 #else 893 u64 vf_id:8; 894 u64 gmx_port_id:8; 895 u64 num_oqueues:16; 896 u64 num_iqueues:16; 897 u64 base_queue:16; 898 #endif 899 } s; 900 }; 901 902 #endif 903