1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 6 31 #define LIQUIDIO_BASE_MICRO_VERSION 1 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 88 #define VF_DRV_LOADED 1 89 #define VF_DRV_REMOVED -1 90 #define VF_DRV_MACADDR_CHANGED 2 91 92 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 93 94 /* Application codes advertised by the core driver initialization packet. */ 95 #define CVM_DRV_APP_START 0x0 96 #define CVM_DRV_NO_APP 0 97 #define CVM_DRV_APP_COUNT 0x2 98 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 99 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 100 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 101 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 102 103 #define BYTES_PER_DHLEN_UNIT 8 104 #define MAX_REG_CNT 2000000U 105 #define INTRNAMSIZ 32 106 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 107 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 108 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 109 110 #define SCR2_BIT_FW_LOADED 63 111 112 /* App specific capabilities from firmware to pf driver */ 113 #define LIQUIDIO_TIME_SYNC_CAP 0x1 114 115 static inline u32 incr_index(u32 index, u32 count, u32 max) 116 { 117 if ((index + count) >= max) 118 index = index + count - max; 119 else 120 index += count; 121 122 return index; 123 } 124 125 #define OCT_BOARD_NAME 32 126 #define OCT_SERIAL_LEN 64 127 128 /* Structure used by core driver to send indication that the Octeon 129 * application is ready. 130 */ 131 struct octeon_core_setup { 132 u64 corefreq; 133 134 char boardname[OCT_BOARD_NAME]; 135 136 char board_serial_number[OCT_SERIAL_LEN]; 137 138 u64 board_rev_major; 139 140 u64 board_rev_minor; 141 142 }; 143 144 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 145 146 /* The Scatter-Gather List Entry. The scatter or gather component used with 147 * a Octeon input instruction has this format. 148 */ 149 struct octeon_sg_entry { 150 /** The first 64 bit gives the size of data in each dptr.*/ 151 union { 152 u16 size[4]; 153 u64 size64; 154 } u; 155 156 /** The 4 dptr pointers for this entry. */ 157 u64 ptr[4]; 158 159 }; 160 161 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 162 163 /* \brief Add size to gather list 164 * @param sg_entry scatter/gather entry 165 * @param size size to add 166 * @param pos position to add it. 167 */ 168 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 169 u16 size, 170 u32 pos) 171 { 172 #ifdef __BIG_ENDIAN_BITFIELD 173 sg_entry->u.size[pos] = size; 174 #else 175 sg_entry->u.size[3 - pos] = size; 176 #endif 177 } 178 179 /*------------------------- End Scatter/Gather ---------------------------*/ 180 181 #define OCTNET_FRM_LENGTH_SIZE 8 182 183 #define OCTNET_FRM_PTP_HEADER_SIZE 8 184 185 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 186 187 #define OCTNET_MIN_FRM_SIZE 64 188 189 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 190 191 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE) 192 193 /** NIC Commands are sent using this Octeon Input Queue */ 194 #define OCTNET_CMD_Q 0 195 196 /* NIC Command types */ 197 #define OCTNET_CMD_CHANGE_MTU 0x1 198 #define OCTNET_CMD_CHANGE_MACADDR 0x2 199 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 200 #define OCTNET_CMD_RX_CTL 0x4 201 202 #define OCTNET_CMD_SET_MULTI_LIST 0x5 203 #define OCTNET_CMD_CLEAR_STATS 0x6 204 205 /* command for setting the speed, duplex & autoneg */ 206 #define OCTNET_CMD_SET_SETTINGS 0x7 207 #define OCTNET_CMD_SET_FLOW_CTL 0x8 208 209 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 210 #define OCTNET_CMD_GPIO_ACCESS 0xA 211 #define OCTNET_CMD_LRO_ENABLE 0xB 212 #define OCTNET_CMD_LRO_DISABLE 0xC 213 #define OCTNET_CMD_SET_RSS 0xD 214 #define OCTNET_CMD_WRITE_SA 0xE 215 #define OCTNET_CMD_DELETE_SA 0xF 216 #define OCTNET_CMD_UPDATE_SA 0x12 217 218 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 219 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 220 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 221 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 222 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 223 224 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 225 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 226 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 227 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 228 229 #define OCTNET_CMD_ID_ACTIVE 0x1a 230 231 #define OCTNET_CMD_SET_UC_LIST 0x1b 232 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 233 234 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 235 236 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 237 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 238 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 239 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 240 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 241 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 242 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 243 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 244 245 #define LIO_CMD_WAIT_TM 100 246 247 /* RX(packets coming from wire) Checksum verification flags */ 248 /* TCP/UDP csum */ 249 #define CNNIC_L4SUM_VERIFIED 0x1 250 #define CNNIC_IPSUM_VERIFIED 0x2 251 #define CNNIC_TUN_CSUM_VERIFIED 0x4 252 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 253 254 /*LROIPV4 and LROIPV6 Flags*/ 255 #define OCTNIC_LROIPV4 0x1 256 #define OCTNIC_LROIPV6 0x2 257 258 /* Interface flags communicated between host driver and core app. */ 259 enum octnet_ifflags { 260 OCTNET_IFFLAG_PROMISC = 0x01, 261 OCTNET_IFFLAG_ALLMULTI = 0x02, 262 OCTNET_IFFLAG_MULTICAST = 0x04, 263 OCTNET_IFFLAG_BROADCAST = 0x08, 264 OCTNET_IFFLAG_UNICAST = 0x10 265 }; 266 267 /* wqe 268 * --------------- 0 269 * | wqe word0-3 | 270 * --------------- 32 271 * | PCI IH | 272 * --------------- 40 273 * | RPTR | 274 * --------------- 48 275 * | PCI IRH | 276 * --------------- 56 277 * | OCT_NET_CMD | 278 * --------------- 64 279 * | Addtl 8-BData | 280 * | | 281 * --------------- 282 */ 283 284 union octnet_cmd { 285 u64 u64; 286 287 struct { 288 #ifdef __BIG_ENDIAN_BITFIELD 289 u64 cmd:5; 290 291 u64 more:6; /* How many udd words follow the command */ 292 293 u64 reserved:29; 294 295 u64 param1:16; 296 297 u64 param2:8; 298 299 #else 300 301 u64 param2:8; 302 303 u64 param1:16; 304 305 u64 reserved:29; 306 307 u64 more:6; 308 309 u64 cmd:5; 310 311 #endif 312 } s; 313 314 }; 315 316 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 317 318 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 319 #define LIO_SOFTCMDRESP_IH2 40 320 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 321 322 #define LIO_PCICMD_O2 24 323 #define LIO_PCICMD_O3 (24 + 8) 324 325 /* Instruction Header(DPI) - for OCTEON-III models */ 326 struct octeon_instr_ih3 { 327 #ifdef __BIG_ENDIAN_BITFIELD 328 329 /** Reserved3 */ 330 u64 reserved3:1; 331 332 /** Gather indicator 1=gather*/ 333 u64 gather:1; 334 335 /** Data length OR no. of entries in gather list */ 336 u64 dlengsz:14; 337 338 /** Front Data size */ 339 u64 fsz:6; 340 341 /** Reserved2 */ 342 u64 reserved2:4; 343 344 /** PKI port kind - PKIND */ 345 u64 pkind:6; 346 347 /** Reserved1 */ 348 u64 reserved1:32; 349 350 #else 351 /** Reserved1 */ 352 u64 reserved1:32; 353 354 /** PKI port kind - PKIND */ 355 u64 pkind:6; 356 357 /** Reserved2 */ 358 u64 reserved2:4; 359 360 /** Front Data size */ 361 u64 fsz:6; 362 363 /** Data length OR no. of entries in gather list */ 364 u64 dlengsz:14; 365 366 /** Gather indicator 1=gather*/ 367 u64 gather:1; 368 369 /** Reserved3 */ 370 u64 reserved3:1; 371 372 #endif 373 }; 374 375 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 376 /** BIG ENDIAN format. */ 377 struct octeon_instr_pki_ih3 { 378 #ifdef __BIG_ENDIAN_BITFIELD 379 380 /** Wider bit */ 381 u64 w:1; 382 383 /** Raw mode indicator 1 = RAW */ 384 u64 raw:1; 385 386 /** Use Tag */ 387 u64 utag:1; 388 389 /** Use QPG */ 390 u64 uqpg:1; 391 392 /** Reserved2 */ 393 u64 reserved2:1; 394 395 /** Parse Mode */ 396 u64 pm:3; 397 398 /** Skip Length */ 399 u64 sl:8; 400 401 /** Use Tag Type */ 402 u64 utt:1; 403 404 /** Tag type */ 405 u64 tagtype:2; 406 407 /** Reserved1 */ 408 u64 reserved1:2; 409 410 /** QPG Value */ 411 u64 qpg:11; 412 413 /** Tag Value */ 414 u64 tag:32; 415 416 #else 417 418 /** Tag Value */ 419 u64 tag:32; 420 421 /** QPG Value */ 422 u64 qpg:11; 423 424 /** Reserved1 */ 425 u64 reserved1:2; 426 427 /** Tag type */ 428 u64 tagtype:2; 429 430 /** Use Tag Type */ 431 u64 utt:1; 432 433 /** Skip Length */ 434 u64 sl:8; 435 436 /** Parse Mode */ 437 u64 pm:3; 438 439 /** Reserved2 */ 440 u64 reserved2:1; 441 442 /** Use QPG */ 443 u64 uqpg:1; 444 445 /** Use Tag */ 446 u64 utag:1; 447 448 /** Raw mode indicator 1 = RAW */ 449 u64 raw:1; 450 451 /** Wider bit */ 452 u64 w:1; 453 #endif 454 455 }; 456 457 /** Instruction Header */ 458 struct octeon_instr_ih2 { 459 #ifdef __BIG_ENDIAN_BITFIELD 460 /** Raw mode indicator 1 = RAW */ 461 u64 raw:1; 462 463 /** Gather indicator 1=gather*/ 464 u64 gather:1; 465 466 /** Data length OR no. of entries in gather list */ 467 u64 dlengsz:14; 468 469 /** Front Data size */ 470 u64 fsz:6; 471 472 /** Packet Order / Work Unit selection (1 of 8)*/ 473 u64 qos:3; 474 475 /** Core group selection (1 of 16) */ 476 u64 grp:4; 477 478 /** Short Raw Packet Indicator 1=short raw pkt */ 479 u64 rs:1; 480 481 /** Tag type */ 482 u64 tagtype:2; 483 484 /** Tag Value */ 485 u64 tag:32; 486 #else 487 /** Tag Value */ 488 u64 tag:32; 489 490 /** Tag type */ 491 u64 tagtype:2; 492 493 /** Short Raw Packet Indicator 1=short raw pkt */ 494 u64 rs:1; 495 496 /** Core group selection (1 of 16) */ 497 u64 grp:4; 498 499 /** Packet Order / Work Unit selection (1 of 8)*/ 500 u64 qos:3; 501 502 /** Front Data size */ 503 u64 fsz:6; 504 505 /** Data length OR no. of entries in gather list */ 506 u64 dlengsz:14; 507 508 /** Gather indicator 1=gather*/ 509 u64 gather:1; 510 511 /** Raw mode indicator 1 = RAW */ 512 u64 raw:1; 513 #endif 514 }; 515 516 /** Input Request Header */ 517 struct octeon_instr_irh { 518 #ifdef __BIG_ENDIAN_BITFIELD 519 u64 opcode:4; 520 u64 rflag:1; 521 u64 subcode:7; 522 u64 vlan:12; 523 u64 priority:3; 524 u64 reserved:5; 525 u64 ossp:32; /* opcode/subcode specific parameters */ 526 #else 527 u64 ossp:32; /* opcode/subcode specific parameters */ 528 u64 reserved:5; 529 u64 priority:3; 530 u64 vlan:12; 531 u64 subcode:7; 532 u64 rflag:1; 533 u64 opcode:4; 534 #endif 535 }; 536 537 /** Return Data Parameters */ 538 struct octeon_instr_rdp { 539 #ifdef __BIG_ENDIAN_BITFIELD 540 u64 reserved:49; 541 u64 pcie_port:3; 542 u64 rlen:12; 543 #else 544 u64 rlen:12; 545 u64 pcie_port:3; 546 u64 reserved:49; 547 #endif 548 }; 549 550 /** Receive Header */ 551 union octeon_rh { 552 #ifdef __BIG_ENDIAN_BITFIELD 553 u64 u64; 554 struct { 555 u64 opcode:4; 556 u64 subcode:8; 557 u64 len:3; /** additional 64-bit words */ 558 u64 reserved:17; 559 u64 ossp:32; /** opcode/subcode specific parameters */ 560 } r; 561 struct { 562 u64 opcode:4; 563 u64 subcode:8; 564 u64 len:3; /** additional 64-bit words */ 565 u64 extra:28; 566 u64 vlan:12; 567 u64 priority:3; 568 u64 csum_verified:3; /** checksum verified. */ 569 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 570 u64 encap_on:1; 571 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 572 } r_dh; 573 struct { 574 u64 opcode:4; 575 u64 subcode:8; 576 u64 len:3; /** additional 64-bit words */ 577 u64 reserved:11; 578 u64 num_gmx_ports:8; 579 u64 max_nic_ports:10; 580 u64 app_cap_flags:4; 581 u64 app_mode:8; 582 u64 pkind:8; 583 } r_core_drv_init; 584 struct { 585 u64 opcode:4; 586 u64 subcode:8; 587 u64 len:3; /** additional 64-bit words */ 588 u64 reserved:8; 589 u64 extra:25; 590 u64 gmxport:16; 591 } r_nic_info; 592 #else 593 u64 u64; 594 struct { 595 u64 ossp:32; /** opcode/subcode specific parameters */ 596 u64 reserved:17; 597 u64 len:3; /** additional 64-bit words */ 598 u64 subcode:8; 599 u64 opcode:4; 600 } r; 601 struct { 602 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 603 u64 encap_on:1; 604 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 605 u64 csum_verified:3; /** checksum verified. */ 606 u64 priority:3; 607 u64 vlan:12; 608 u64 extra:28; 609 u64 len:3; /** additional 64-bit words */ 610 u64 subcode:8; 611 u64 opcode:4; 612 } r_dh; 613 struct { 614 u64 pkind:8; 615 u64 app_mode:8; 616 u64 app_cap_flags:4; 617 u64 max_nic_ports:10; 618 u64 num_gmx_ports:8; 619 u64 reserved:11; 620 u64 len:3; /** additional 64-bit words */ 621 u64 subcode:8; 622 u64 opcode:4; 623 } r_core_drv_init; 624 struct { 625 u64 gmxport:16; 626 u64 extra:25; 627 u64 reserved:8; 628 u64 len:3; /** additional 64-bit words */ 629 u64 subcode:8; 630 u64 opcode:4; 631 } r_nic_info; 632 #endif 633 }; 634 635 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 636 637 union octnic_packet_params { 638 u32 u32; 639 struct { 640 #ifdef __BIG_ENDIAN_BITFIELD 641 u32 reserved:24; 642 u32 ip_csum:1; /* Perform IP header checksum(s) */ 643 /* Perform Outer transport header checksum */ 644 u32 transport_csum:1; 645 /* Find tunnel, and perform transport csum. */ 646 u32 tnl_csum:1; 647 u32 tsflag:1; /* Timestamp this packet */ 648 u32 ipsec_ops:4; /* IPsec operation */ 649 #else 650 u32 ipsec_ops:4; 651 u32 tsflag:1; 652 u32 tnl_csum:1; 653 u32 transport_csum:1; 654 u32 ip_csum:1; 655 u32 reserved:24; 656 #endif 657 } s; 658 }; 659 660 /** Status of a RGMII Link on Octeon as seen by core driver. */ 661 union oct_link_status { 662 u64 u64; 663 664 struct { 665 #ifdef __BIG_ENDIAN_BITFIELD 666 u64 duplex:8; 667 u64 mtu:16; 668 u64 speed:16; 669 u64 link_up:1; 670 u64 autoneg:1; 671 u64 if_mode:5; 672 u64 pause:1; 673 u64 flashing:1; 674 u64 reserved:15; 675 #else 676 u64 reserved:15; 677 u64 flashing:1; 678 u64 pause:1; 679 u64 if_mode:5; 680 u64 autoneg:1; 681 u64 link_up:1; 682 u64 speed:16; 683 u64 mtu:16; 684 u64 duplex:8; 685 #endif 686 } s; 687 }; 688 689 /** The txpciq info passed to host from the firmware */ 690 691 union oct_txpciq { 692 u64 u64; 693 694 struct { 695 #ifdef __BIG_ENDIAN_BITFIELD 696 u64 q_no:8; 697 u64 port:8; 698 u64 pkind:6; 699 u64 use_qpg:1; 700 u64 qpg:11; 701 u64 reserved:30; 702 #else 703 u64 reserved:30; 704 u64 qpg:11; 705 u64 use_qpg:1; 706 u64 pkind:6; 707 u64 port:8; 708 u64 q_no:8; 709 #endif 710 } s; 711 }; 712 713 /** The rxpciq info passed to host from the firmware */ 714 715 union oct_rxpciq { 716 u64 u64; 717 718 struct { 719 #ifdef __BIG_ENDIAN_BITFIELD 720 u64 q_no:8; 721 u64 reserved:56; 722 #else 723 u64 reserved:56; 724 u64 q_no:8; 725 #endif 726 } s; 727 }; 728 729 /** Information for a OCTEON ethernet interface shared between core & host. */ 730 struct oct_link_info { 731 union oct_link_status link; 732 u64 hw_addr; 733 734 #ifdef __BIG_ENDIAN_BITFIELD 735 u64 gmxport:16; 736 u64 macaddr_is_admin_asgnd:1; 737 u64 rsvd:31; 738 u64 num_txpciq:8; 739 u64 num_rxpciq:8; 740 #else 741 u64 num_rxpciq:8; 742 u64 num_txpciq:8; 743 u64 rsvd:31; 744 u64 macaddr_is_admin_asgnd:1; 745 u64 gmxport:16; 746 #endif 747 748 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 749 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 750 }; 751 752 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 753 754 struct liquidio_if_cfg_info { 755 u64 iqmask; /** mask for IQs enabled for the port */ 756 u64 oqmask; /** mask for OQs enabled for the port */ 757 struct oct_link_info linfo; /** initial link information */ 758 char liquidio_firmware_version[32]; 759 }; 760 761 /** Stats for each NIC port in RX direction. */ 762 struct nic_rx_stats { 763 /* link-level stats */ 764 u64 total_rcvd; 765 u64 bytes_rcvd; 766 u64 total_bcst; 767 u64 total_mcst; 768 u64 runts; 769 u64 ctl_rcvd; 770 u64 fifo_err; /* Accounts for over/under-run of buffers */ 771 u64 dmac_drop; 772 u64 fcs_err; 773 u64 jabber_err; 774 u64 l2_err; 775 u64 frame_err; 776 777 /* firmware stats */ 778 u64 fw_total_rcvd; 779 u64 fw_total_fwd; 780 u64 fw_total_fwd_bytes; 781 u64 fw_err_pko; 782 u64 fw_err_link; 783 u64 fw_err_drop; 784 u64 fw_rx_vxlan; 785 u64 fw_rx_vxlan_err; 786 787 /* LRO */ 788 u64 fw_lro_pkts; /* Number of packets that are LROed */ 789 u64 fw_lro_octs; /* Number of octets that are LROed */ 790 u64 fw_total_lro; /* Number of LRO packets formed */ 791 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 792 u64 fw_lro_aborts_port; 793 u64 fw_lro_aborts_seq; 794 u64 fw_lro_aborts_tsval; 795 u64 fw_lro_aborts_timer; 796 /* intrmod: packet forward rate */ 797 u64 fwd_rate; 798 }; 799 800 /** Stats for each NIC port in RX direction. */ 801 struct nic_tx_stats { 802 /* link-level stats */ 803 u64 total_pkts_sent; 804 u64 total_bytes_sent; 805 u64 mcast_pkts_sent; 806 u64 bcast_pkts_sent; 807 u64 ctl_sent; 808 u64 one_collision_sent; /* Packets sent after one collision*/ 809 u64 multi_collision_sent; /* Packets sent after multiple collision*/ 810 u64 max_collision_fail; /* Packets not sent due to max collisions */ 811 u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 812 u64 fifo_err; /* Accounts for over/under-run of buffers */ 813 u64 runts; 814 u64 total_collisions; /* Total number of collisions detected */ 815 816 /* firmware stats */ 817 u64 fw_total_sent; 818 u64 fw_total_fwd; 819 u64 fw_total_fwd_bytes; 820 u64 fw_err_pko; 821 u64 fw_err_link; 822 u64 fw_err_drop; 823 u64 fw_err_tso; 824 u64 fw_tso; /* number of tso requests */ 825 u64 fw_tso_fwd; /* number of packets segmented in tso */ 826 u64 fw_tx_vxlan; 827 u64 fw_err_pki; 828 }; 829 830 struct oct_link_stats { 831 struct nic_rx_stats fromwire; 832 struct nic_tx_stats fromhost; 833 834 }; 835 836 static inline int opcode_slow_path(union octeon_rh *rh) 837 { 838 u16 subcode1, subcode2; 839 840 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 841 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 842 843 return (subcode2 != subcode1); 844 } 845 846 #define LIO68XX_LED_CTRL_ADDR 0x3501 847 #define LIO68XX_LED_CTRL_CFGON 0x1f 848 #define LIO68XX_LED_CTRL_CFGOFF 0x100 849 #define LIO68XX_LED_BEACON_ADDR 0x3508 850 #define LIO68XX_LED_BEACON_CFGON 0x47fd 851 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 852 #define VITESSE_PHY_GPIO_DRIVEON 0x1 853 #define VITESSE_PHY_GPIO_CFG 0x8 854 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 855 #define VITESSE_PHY_GPIO_HIGH 0x2 856 #define VITESSE_PHY_GPIO_LOW 0x3 857 #define LED_IDENTIFICATION_ON 0x1 858 #define LED_IDENTIFICATION_OFF 0x0 859 860 struct oct_mdio_cmd { 861 u64 op; 862 u64 mdio_addr; 863 u64 value1; 864 u64 value2; 865 u64 value3; 866 }; 867 868 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 869 870 struct oct_intrmod_cfg { 871 u64 rx_enable; 872 u64 tx_enable; 873 u64 check_intrvl; 874 u64 maxpkt_ratethr; 875 u64 minpkt_ratethr; 876 u64 rx_maxcnt_trigger; 877 u64 rx_mincnt_trigger; 878 u64 rx_maxtmr_trigger; 879 u64 rx_mintmr_trigger; 880 u64 tx_mincnt_trigger; 881 u64 tx_maxcnt_trigger; 882 u64 rx_frames; 883 u64 tx_frames; 884 u64 rx_usecs; 885 }; 886 887 #define BASE_QUEUE_NOT_REQUESTED 65535 888 889 union oct_nic_if_cfg { 890 u64 u64; 891 struct { 892 #ifdef __BIG_ENDIAN_BITFIELD 893 u64 base_queue:16; 894 u64 num_iqueues:16; 895 u64 num_oqueues:16; 896 u64 gmx_port_id:8; 897 u64 vf_id:8; 898 #else 899 u64 vf_id:8; 900 u64 gmx_port_id:8; 901 u64 num_oqueues:16; 902 u64 num_iqueues:16; 903 u64 base_queue:16; 904 #endif 905 } s; 906 }; 907 908 struct lio_time { 909 s64 sec; /* seconds */ 910 s64 nsec; /* nanoseconds */ 911 }; 912 #endif 913