1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 7 31 #define LIQUIDIO_BASE_MICRO_VERSION 0 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 88 #define VF_DRV_LOADED 1 89 #define VF_DRV_REMOVED -1 90 #define VF_DRV_MACADDR_CHANGED 2 91 92 #define OPCODE_NIC_VF_REP_PKT 0x15 93 #define OPCODE_NIC_VF_REP_CMD 0x16 94 95 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 96 97 /* Application codes advertised by the core driver initialization packet. */ 98 #define CVM_DRV_APP_START 0x0 99 #define CVM_DRV_NO_APP 0 100 #define CVM_DRV_APP_COUNT 0x2 101 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 102 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 103 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 104 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 105 106 #define BYTES_PER_DHLEN_UNIT 8 107 #define MAX_REG_CNT 2000000U 108 #define INTRNAMSIZ 32 109 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 110 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 111 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 112 113 #define SCR2_BIT_FW_LOADED 63 114 115 /* App specific capabilities from firmware to pf driver */ 116 #define LIQUIDIO_TIME_SYNC_CAP 0x1 117 #define LIQUIDIO_SWITCHDEV_CAP 0x2 118 119 static inline u32 incr_index(u32 index, u32 count, u32 max) 120 { 121 if ((index + count) >= max) 122 index = index + count - max; 123 else 124 index += count; 125 126 return index; 127 } 128 129 #define OCT_BOARD_NAME 32 130 #define OCT_SERIAL_LEN 64 131 132 /* Structure used by core driver to send indication that the Octeon 133 * application is ready. 134 */ 135 struct octeon_core_setup { 136 u64 corefreq; 137 138 char boardname[OCT_BOARD_NAME]; 139 140 char board_serial_number[OCT_SERIAL_LEN]; 141 142 u64 board_rev_major; 143 144 u64 board_rev_minor; 145 146 }; 147 148 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 149 150 /* The Scatter-Gather List Entry. The scatter or gather component used with 151 * a Octeon input instruction has this format. 152 */ 153 struct octeon_sg_entry { 154 /** The first 64 bit gives the size of data in each dptr.*/ 155 union { 156 u16 size[4]; 157 u64 size64; 158 } u; 159 160 /** The 4 dptr pointers for this entry. */ 161 u64 ptr[4]; 162 163 }; 164 165 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 166 167 /* \brief Add size to gather list 168 * @param sg_entry scatter/gather entry 169 * @param size size to add 170 * @param pos position to add it. 171 */ 172 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 173 u16 size, 174 u32 pos) 175 { 176 #ifdef __BIG_ENDIAN_BITFIELD 177 sg_entry->u.size[pos] = size; 178 #else 179 sg_entry->u.size[3 - pos] = size; 180 #endif 181 } 182 183 /*------------------------- End Scatter/Gather ---------------------------*/ 184 185 #define OCTNET_FRM_LENGTH_SIZE 8 186 187 #define OCTNET_FRM_PTP_HEADER_SIZE 8 188 189 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 190 191 #define OCTNET_MIN_FRM_SIZE 64 192 193 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 194 195 #define OCTNET_DEFAULT_MTU (1500) 196 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE) 197 198 /** NIC Commands are sent using this Octeon Input Queue */ 199 #define OCTNET_CMD_Q 0 200 201 /* NIC Command types */ 202 #define OCTNET_CMD_CHANGE_MTU 0x1 203 #define OCTNET_CMD_CHANGE_MACADDR 0x2 204 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 205 #define OCTNET_CMD_RX_CTL 0x4 206 207 #define OCTNET_CMD_SET_MULTI_LIST 0x5 208 #define OCTNET_CMD_CLEAR_STATS 0x6 209 210 /* command for setting the speed, duplex & autoneg */ 211 #define OCTNET_CMD_SET_SETTINGS 0x7 212 #define OCTNET_CMD_SET_FLOW_CTL 0x8 213 214 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 215 #define OCTNET_CMD_GPIO_ACCESS 0xA 216 #define OCTNET_CMD_LRO_ENABLE 0xB 217 #define OCTNET_CMD_LRO_DISABLE 0xC 218 #define OCTNET_CMD_SET_RSS 0xD 219 #define OCTNET_CMD_WRITE_SA 0xE 220 #define OCTNET_CMD_DELETE_SA 0xF 221 #define OCTNET_CMD_UPDATE_SA 0x12 222 223 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 224 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 225 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 226 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 227 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 228 229 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 230 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 231 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 232 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 233 234 #define OCTNET_CMD_ID_ACTIVE 0x1a 235 236 #define OCTNET_CMD_SET_UC_LIST 0x1b 237 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 238 239 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 240 241 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 242 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 243 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 244 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 245 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 246 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 247 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 248 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 249 250 #define LIO_CMD_WAIT_TM 100 251 252 /* RX(packets coming from wire) Checksum verification flags */ 253 /* TCP/UDP csum */ 254 #define CNNIC_L4SUM_VERIFIED 0x1 255 #define CNNIC_IPSUM_VERIFIED 0x2 256 #define CNNIC_TUN_CSUM_VERIFIED 0x4 257 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 258 259 /*LROIPV4 and LROIPV6 Flags*/ 260 #define OCTNIC_LROIPV4 0x1 261 #define OCTNIC_LROIPV6 0x2 262 263 /* Interface flags communicated between host driver and core app. */ 264 enum octnet_ifflags { 265 OCTNET_IFFLAG_PROMISC = 0x01, 266 OCTNET_IFFLAG_ALLMULTI = 0x02, 267 OCTNET_IFFLAG_MULTICAST = 0x04, 268 OCTNET_IFFLAG_BROADCAST = 0x08, 269 OCTNET_IFFLAG_UNICAST = 0x10 270 }; 271 272 /* wqe 273 * --------------- 0 274 * | wqe word0-3 | 275 * --------------- 32 276 * | PCI IH | 277 * --------------- 40 278 * | RPTR | 279 * --------------- 48 280 * | PCI IRH | 281 * --------------- 56 282 * | OCT_NET_CMD | 283 * --------------- 64 284 * | Addtl 8-BData | 285 * | | 286 * --------------- 287 */ 288 289 union octnet_cmd { 290 u64 u64; 291 292 struct { 293 #ifdef __BIG_ENDIAN_BITFIELD 294 u64 cmd:5; 295 296 u64 more:6; /* How many udd words follow the command */ 297 298 u64 reserved:29; 299 300 u64 param1:16; 301 302 u64 param2:8; 303 304 #else 305 306 u64 param2:8; 307 308 u64 param1:16; 309 310 u64 reserved:29; 311 312 u64 more:6; 313 314 u64 cmd:5; 315 316 #endif 317 } s; 318 319 }; 320 321 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 322 323 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 324 #define LIO_SOFTCMDRESP_IH2 40 325 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 326 327 #define LIO_PCICMD_O2 24 328 #define LIO_PCICMD_O3 (24 + 8) 329 330 /* Instruction Header(DPI) - for OCTEON-III models */ 331 struct octeon_instr_ih3 { 332 #ifdef __BIG_ENDIAN_BITFIELD 333 334 /** Reserved3 */ 335 u64 reserved3:1; 336 337 /** Gather indicator 1=gather*/ 338 u64 gather:1; 339 340 /** Data length OR no. of entries in gather list */ 341 u64 dlengsz:14; 342 343 /** Front Data size */ 344 u64 fsz:6; 345 346 /** Reserved2 */ 347 u64 reserved2:4; 348 349 /** PKI port kind - PKIND */ 350 u64 pkind:6; 351 352 /** Reserved1 */ 353 u64 reserved1:32; 354 355 #else 356 /** Reserved1 */ 357 u64 reserved1:32; 358 359 /** PKI port kind - PKIND */ 360 u64 pkind:6; 361 362 /** Reserved2 */ 363 u64 reserved2:4; 364 365 /** Front Data size */ 366 u64 fsz:6; 367 368 /** Data length OR no. of entries in gather list */ 369 u64 dlengsz:14; 370 371 /** Gather indicator 1=gather*/ 372 u64 gather:1; 373 374 /** Reserved3 */ 375 u64 reserved3:1; 376 377 #endif 378 }; 379 380 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 381 /** BIG ENDIAN format. */ 382 struct octeon_instr_pki_ih3 { 383 #ifdef __BIG_ENDIAN_BITFIELD 384 385 /** Wider bit */ 386 u64 w:1; 387 388 /** Raw mode indicator 1 = RAW */ 389 u64 raw:1; 390 391 /** Use Tag */ 392 u64 utag:1; 393 394 /** Use QPG */ 395 u64 uqpg:1; 396 397 /** Reserved2 */ 398 u64 reserved2:1; 399 400 /** Parse Mode */ 401 u64 pm:3; 402 403 /** Skip Length */ 404 u64 sl:8; 405 406 /** Use Tag Type */ 407 u64 utt:1; 408 409 /** Tag type */ 410 u64 tagtype:2; 411 412 /** Reserved1 */ 413 u64 reserved1:2; 414 415 /** QPG Value */ 416 u64 qpg:11; 417 418 /** Tag Value */ 419 u64 tag:32; 420 421 #else 422 423 /** Tag Value */ 424 u64 tag:32; 425 426 /** QPG Value */ 427 u64 qpg:11; 428 429 /** Reserved1 */ 430 u64 reserved1:2; 431 432 /** Tag type */ 433 u64 tagtype:2; 434 435 /** Use Tag Type */ 436 u64 utt:1; 437 438 /** Skip Length */ 439 u64 sl:8; 440 441 /** Parse Mode */ 442 u64 pm:3; 443 444 /** Reserved2 */ 445 u64 reserved2:1; 446 447 /** Use QPG */ 448 u64 uqpg:1; 449 450 /** Use Tag */ 451 u64 utag:1; 452 453 /** Raw mode indicator 1 = RAW */ 454 u64 raw:1; 455 456 /** Wider bit */ 457 u64 w:1; 458 #endif 459 460 }; 461 462 /** Instruction Header */ 463 struct octeon_instr_ih2 { 464 #ifdef __BIG_ENDIAN_BITFIELD 465 /** Raw mode indicator 1 = RAW */ 466 u64 raw:1; 467 468 /** Gather indicator 1=gather*/ 469 u64 gather:1; 470 471 /** Data length OR no. of entries in gather list */ 472 u64 dlengsz:14; 473 474 /** Front Data size */ 475 u64 fsz:6; 476 477 /** Packet Order / Work Unit selection (1 of 8)*/ 478 u64 qos:3; 479 480 /** Core group selection (1 of 16) */ 481 u64 grp:4; 482 483 /** Short Raw Packet Indicator 1=short raw pkt */ 484 u64 rs:1; 485 486 /** Tag type */ 487 u64 tagtype:2; 488 489 /** Tag Value */ 490 u64 tag:32; 491 #else 492 /** Tag Value */ 493 u64 tag:32; 494 495 /** Tag type */ 496 u64 tagtype:2; 497 498 /** Short Raw Packet Indicator 1=short raw pkt */ 499 u64 rs:1; 500 501 /** Core group selection (1 of 16) */ 502 u64 grp:4; 503 504 /** Packet Order / Work Unit selection (1 of 8)*/ 505 u64 qos:3; 506 507 /** Front Data size */ 508 u64 fsz:6; 509 510 /** Data length OR no. of entries in gather list */ 511 u64 dlengsz:14; 512 513 /** Gather indicator 1=gather*/ 514 u64 gather:1; 515 516 /** Raw mode indicator 1 = RAW */ 517 u64 raw:1; 518 #endif 519 }; 520 521 /** Input Request Header */ 522 struct octeon_instr_irh { 523 #ifdef __BIG_ENDIAN_BITFIELD 524 u64 opcode:4; 525 u64 rflag:1; 526 u64 subcode:7; 527 u64 vlan:12; 528 u64 priority:3; 529 u64 reserved:5; 530 u64 ossp:32; /* opcode/subcode specific parameters */ 531 #else 532 u64 ossp:32; /* opcode/subcode specific parameters */ 533 u64 reserved:5; 534 u64 priority:3; 535 u64 vlan:12; 536 u64 subcode:7; 537 u64 rflag:1; 538 u64 opcode:4; 539 #endif 540 }; 541 542 /** Return Data Parameters */ 543 struct octeon_instr_rdp { 544 #ifdef __BIG_ENDIAN_BITFIELD 545 u64 reserved:49; 546 u64 pcie_port:3; 547 u64 rlen:12; 548 #else 549 u64 rlen:12; 550 u64 pcie_port:3; 551 u64 reserved:49; 552 #endif 553 }; 554 555 /** Receive Header */ 556 union octeon_rh { 557 #ifdef __BIG_ENDIAN_BITFIELD 558 u64 u64; 559 struct { 560 u64 opcode:4; 561 u64 subcode:8; 562 u64 len:3; /** additional 64-bit words */ 563 u64 reserved:17; 564 u64 ossp:32; /** opcode/subcode specific parameters */ 565 } r; 566 struct { 567 u64 opcode:4; 568 u64 subcode:8; 569 u64 len:3; /** additional 64-bit words */ 570 u64 extra:28; 571 u64 vlan:12; 572 u64 priority:3; 573 u64 csum_verified:3; /** checksum verified. */ 574 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 575 u64 encap_on:1; 576 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 577 } r_dh; 578 struct { 579 u64 opcode:4; 580 u64 subcode:8; 581 u64 len:3; /** additional 64-bit words */ 582 u64 reserved:11; 583 u64 num_gmx_ports:8; 584 u64 max_nic_ports:10; 585 u64 app_cap_flags:4; 586 u64 app_mode:8; 587 u64 pkind:8; 588 } r_core_drv_init; 589 struct { 590 u64 opcode:4; 591 u64 subcode:8; 592 u64 len:3; /** additional 64-bit words */ 593 u64 reserved:8; 594 u64 extra:25; 595 u64 gmxport:16; 596 } r_nic_info; 597 #else 598 u64 u64; 599 struct { 600 u64 ossp:32; /** opcode/subcode specific parameters */ 601 u64 reserved:17; 602 u64 len:3; /** additional 64-bit words */ 603 u64 subcode:8; 604 u64 opcode:4; 605 } r; 606 struct { 607 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 608 u64 encap_on:1; 609 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 610 u64 csum_verified:3; /** checksum verified. */ 611 u64 priority:3; 612 u64 vlan:12; 613 u64 extra:28; 614 u64 len:3; /** additional 64-bit words */ 615 u64 subcode:8; 616 u64 opcode:4; 617 } r_dh; 618 struct { 619 u64 pkind:8; 620 u64 app_mode:8; 621 u64 app_cap_flags:4; 622 u64 max_nic_ports:10; 623 u64 num_gmx_ports:8; 624 u64 reserved:11; 625 u64 len:3; /** additional 64-bit words */ 626 u64 subcode:8; 627 u64 opcode:4; 628 } r_core_drv_init; 629 struct { 630 u64 gmxport:16; 631 u64 extra:25; 632 u64 reserved:8; 633 u64 len:3; /** additional 64-bit words */ 634 u64 subcode:8; 635 u64 opcode:4; 636 } r_nic_info; 637 #endif 638 }; 639 640 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 641 642 union octnic_packet_params { 643 u32 u32; 644 struct { 645 #ifdef __BIG_ENDIAN_BITFIELD 646 u32 reserved:24; 647 u32 ip_csum:1; /* Perform IP header checksum(s) */ 648 /* Perform Outer transport header checksum */ 649 u32 transport_csum:1; 650 /* Find tunnel, and perform transport csum. */ 651 u32 tnl_csum:1; 652 u32 tsflag:1; /* Timestamp this packet */ 653 u32 ipsec_ops:4; /* IPsec operation */ 654 #else 655 u32 ipsec_ops:4; 656 u32 tsflag:1; 657 u32 tnl_csum:1; 658 u32 transport_csum:1; 659 u32 ip_csum:1; 660 u32 reserved:24; 661 #endif 662 } s; 663 }; 664 665 /** Status of a RGMII Link on Octeon as seen by core driver. */ 666 union oct_link_status { 667 u64 u64; 668 669 struct { 670 #ifdef __BIG_ENDIAN_BITFIELD 671 u64 duplex:8; 672 u64 mtu:16; 673 u64 speed:16; 674 u64 link_up:1; 675 u64 autoneg:1; 676 u64 if_mode:5; 677 u64 pause:1; 678 u64 flashing:1; 679 u64 reserved:15; 680 #else 681 u64 reserved:15; 682 u64 flashing:1; 683 u64 pause:1; 684 u64 if_mode:5; 685 u64 autoneg:1; 686 u64 link_up:1; 687 u64 speed:16; 688 u64 mtu:16; 689 u64 duplex:8; 690 #endif 691 } s; 692 }; 693 694 /** The txpciq info passed to host from the firmware */ 695 696 union oct_txpciq { 697 u64 u64; 698 699 struct { 700 #ifdef __BIG_ENDIAN_BITFIELD 701 u64 q_no:8; 702 u64 port:8; 703 u64 pkind:6; 704 u64 use_qpg:1; 705 u64 qpg:11; 706 u64 reserved:30; 707 #else 708 u64 reserved:30; 709 u64 qpg:11; 710 u64 use_qpg:1; 711 u64 pkind:6; 712 u64 port:8; 713 u64 q_no:8; 714 #endif 715 } s; 716 }; 717 718 /** The rxpciq info passed to host from the firmware */ 719 720 union oct_rxpciq { 721 u64 u64; 722 723 struct { 724 #ifdef __BIG_ENDIAN_BITFIELD 725 u64 q_no:8; 726 u64 reserved:56; 727 #else 728 u64 reserved:56; 729 u64 q_no:8; 730 #endif 731 } s; 732 }; 733 734 /** Information for a OCTEON ethernet interface shared between core & host. */ 735 struct oct_link_info { 736 union oct_link_status link; 737 u64 hw_addr; 738 739 #ifdef __BIG_ENDIAN_BITFIELD 740 u64 gmxport:16; 741 u64 macaddr_is_admin_asgnd:1; 742 u64 rsvd:31; 743 u64 num_txpciq:8; 744 u64 num_rxpciq:8; 745 #else 746 u64 num_rxpciq:8; 747 u64 num_txpciq:8; 748 u64 rsvd:31; 749 u64 macaddr_is_admin_asgnd:1; 750 u64 gmxport:16; 751 #endif 752 753 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 754 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 755 }; 756 757 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 758 759 struct liquidio_if_cfg_info { 760 u64 iqmask; /** mask for IQs enabled for the port */ 761 u64 oqmask; /** mask for OQs enabled for the port */ 762 struct oct_link_info linfo; /** initial link information */ 763 char liquidio_firmware_version[32]; 764 }; 765 766 /** Stats for each NIC port in RX direction. */ 767 struct nic_rx_stats { 768 /* link-level stats */ 769 u64 total_rcvd; 770 u64 bytes_rcvd; 771 u64 total_bcst; 772 u64 total_mcst; 773 u64 runts; 774 u64 ctl_rcvd; 775 u64 fifo_err; /* Accounts for over/under-run of buffers */ 776 u64 dmac_drop; 777 u64 fcs_err; 778 u64 jabber_err; 779 u64 l2_err; 780 u64 frame_err; 781 782 /* firmware stats */ 783 u64 fw_total_rcvd; 784 u64 fw_total_fwd; 785 u64 fw_total_fwd_bytes; 786 u64 fw_err_pko; 787 u64 fw_err_link; 788 u64 fw_err_drop; 789 u64 fw_rx_vxlan; 790 u64 fw_rx_vxlan_err; 791 792 /* LRO */ 793 u64 fw_lro_pkts; /* Number of packets that are LROed */ 794 u64 fw_lro_octs; /* Number of octets that are LROed */ 795 u64 fw_total_lro; /* Number of LRO packets formed */ 796 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 797 u64 fw_lro_aborts_port; 798 u64 fw_lro_aborts_seq; 799 u64 fw_lro_aborts_tsval; 800 u64 fw_lro_aborts_timer; 801 /* intrmod: packet forward rate */ 802 u64 fwd_rate; 803 }; 804 805 /** Stats for each NIC port in RX direction. */ 806 struct nic_tx_stats { 807 /* link-level stats */ 808 u64 total_pkts_sent; 809 u64 total_bytes_sent; 810 u64 mcast_pkts_sent; 811 u64 bcast_pkts_sent; 812 u64 ctl_sent; 813 u64 one_collision_sent; /* Packets sent after one collision*/ 814 u64 multi_collision_sent; /* Packets sent after multiple collision*/ 815 u64 max_collision_fail; /* Packets not sent due to max collisions */ 816 u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 817 u64 fifo_err; /* Accounts for over/under-run of buffers */ 818 u64 runts; 819 u64 total_collisions; /* Total number of collisions detected */ 820 821 /* firmware stats */ 822 u64 fw_total_sent; 823 u64 fw_total_fwd; 824 u64 fw_total_fwd_bytes; 825 u64 fw_err_pko; 826 u64 fw_err_link; 827 u64 fw_err_drop; 828 u64 fw_err_tso; 829 u64 fw_tso; /* number of tso requests */ 830 u64 fw_tso_fwd; /* number of packets segmented in tso */ 831 u64 fw_tx_vxlan; 832 u64 fw_err_pki; 833 }; 834 835 struct oct_link_stats { 836 struct nic_rx_stats fromwire; 837 struct nic_tx_stats fromhost; 838 839 }; 840 841 static inline int opcode_slow_path(union octeon_rh *rh) 842 { 843 u16 subcode1, subcode2; 844 845 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 846 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 847 848 return (subcode2 != subcode1); 849 } 850 851 #define LIO68XX_LED_CTRL_ADDR 0x3501 852 #define LIO68XX_LED_CTRL_CFGON 0x1f 853 #define LIO68XX_LED_CTRL_CFGOFF 0x100 854 #define LIO68XX_LED_BEACON_ADDR 0x3508 855 #define LIO68XX_LED_BEACON_CFGON 0x47fd 856 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 857 #define VITESSE_PHY_GPIO_DRIVEON 0x1 858 #define VITESSE_PHY_GPIO_CFG 0x8 859 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 860 #define VITESSE_PHY_GPIO_HIGH 0x2 861 #define VITESSE_PHY_GPIO_LOW 0x3 862 #define LED_IDENTIFICATION_ON 0x1 863 #define LED_IDENTIFICATION_OFF 0x0 864 865 struct oct_mdio_cmd { 866 u64 op; 867 u64 mdio_addr; 868 u64 value1; 869 u64 value2; 870 u64 value3; 871 }; 872 873 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 874 875 struct oct_intrmod_cfg { 876 u64 rx_enable; 877 u64 tx_enable; 878 u64 check_intrvl; 879 u64 maxpkt_ratethr; 880 u64 minpkt_ratethr; 881 u64 rx_maxcnt_trigger; 882 u64 rx_mincnt_trigger; 883 u64 rx_maxtmr_trigger; 884 u64 rx_mintmr_trigger; 885 u64 tx_mincnt_trigger; 886 u64 tx_maxcnt_trigger; 887 u64 rx_frames; 888 u64 tx_frames; 889 u64 rx_usecs; 890 }; 891 892 #define BASE_QUEUE_NOT_REQUESTED 65535 893 894 union oct_nic_if_cfg { 895 u64 u64; 896 struct { 897 #ifdef __BIG_ENDIAN_BITFIELD 898 u64 base_queue:16; 899 u64 num_iqueues:16; 900 u64 num_oqueues:16; 901 u64 gmx_port_id:8; 902 u64 vf_id:8; 903 #else 904 u64 vf_id:8; 905 u64 gmx_port_id:8; 906 u64 num_oqueues:16; 907 u64 num_iqueues:16; 908 u64 base_queue:16; 909 #endif 910 } s; 911 }; 912 913 struct lio_time { 914 s64 sec; /* seconds */ 915 s64 nsec; /* nanoseconds */ 916 }; 917 918 struct lio_vf_rep_stats { 919 u64 tx_packets; 920 u64 tx_bytes; 921 u64 tx_dropped; 922 923 u64 rx_packets; 924 u64 rx_bytes; 925 u64 rx_dropped; 926 }; 927 928 enum lio_vf_rep_req_type { 929 LIO_VF_REP_REQ_NONE, 930 LIO_VF_REP_REQ_STATE, 931 LIO_VF_REP_REQ_MTU, 932 LIO_VF_REP_REQ_STATS, 933 LIO_VF_REP_REQ_DEVNAME 934 }; 935 936 enum { 937 LIO_VF_REP_STATE_DOWN, 938 LIO_VF_REP_STATE_UP 939 }; 940 941 #define LIO_IF_NAME_SIZE 16 942 struct lio_vf_rep_req { 943 u8 req_type; 944 u8 ifidx; 945 u8 rsvd[6]; 946 947 union { 948 struct lio_vf_rep_name { 949 char name[LIO_IF_NAME_SIZE]; 950 } rep_name; 951 952 struct lio_vf_rep_mtu { 953 u32 mtu; 954 u32 rsvd; 955 } rep_mtu; 956 957 struct lio_vf_rep_state { 958 u8 state; 959 u8 rsvd[7]; 960 } rep_state; 961 }; 962 }; 963 964 struct lio_vf_rep_resp { 965 u64 rh; 966 u8 status; 967 u8 rsvd[7]; 968 }; 969 #endif 970