1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 4 31 #define LIQUIDIO_BASE_MICRO_VERSION 1 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define VF_DRV_LOADED 1 87 #define VF_DRV_REMOVED -1 88 #define VF_DRV_MACADDR_CHANGED 2 89 90 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 91 92 /* Application codes advertised by the core driver initialization packet. */ 93 #define CVM_DRV_APP_START 0x0 94 #define CVM_DRV_NO_APP 0 95 #define CVM_DRV_APP_COUNT 0x2 96 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 97 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 98 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 99 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 100 101 static inline u32 incr_index(u32 index, u32 count, u32 max) 102 { 103 if ((index + count) >= max) 104 index = index + count - max; 105 else 106 index += count; 107 108 return index; 109 } 110 111 #define OCT_BOARD_NAME 32 112 #define OCT_SERIAL_LEN 64 113 114 /* Structure used by core driver to send indication that the Octeon 115 * application is ready. 116 */ 117 struct octeon_core_setup { 118 u64 corefreq; 119 120 char boardname[OCT_BOARD_NAME]; 121 122 char board_serial_number[OCT_SERIAL_LEN]; 123 124 u64 board_rev_major; 125 126 u64 board_rev_minor; 127 128 }; 129 130 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 131 132 /* The Scatter-Gather List Entry. The scatter or gather component used with 133 * a Octeon input instruction has this format. 134 */ 135 struct octeon_sg_entry { 136 /** The first 64 bit gives the size of data in each dptr.*/ 137 union { 138 u16 size[4]; 139 u64 size64; 140 } u; 141 142 /** The 4 dptr pointers for this entry. */ 143 u64 ptr[4]; 144 145 }; 146 147 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 148 149 /* \brief Add size to gather list 150 * @param sg_entry scatter/gather entry 151 * @param size size to add 152 * @param pos position to add it. 153 */ 154 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 155 u16 size, 156 u32 pos) 157 { 158 #ifdef __BIG_ENDIAN_BITFIELD 159 sg_entry->u.size[pos] = size; 160 #else 161 sg_entry->u.size[3 - pos] = size; 162 #endif 163 } 164 165 /*------------------------- End Scatter/Gather ---------------------------*/ 166 167 #define OCTNET_FRM_PTP_HEADER_SIZE 8 168 169 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 170 171 #define OCTNET_MIN_FRM_SIZE 64 172 173 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 174 175 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE) 176 177 /** NIC Commands are sent using this Octeon Input Queue */ 178 #define OCTNET_CMD_Q 0 179 180 /* NIC Command types */ 181 #define OCTNET_CMD_CHANGE_MTU 0x1 182 #define OCTNET_CMD_CHANGE_MACADDR 0x2 183 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 184 #define OCTNET_CMD_RX_CTL 0x4 185 186 #define OCTNET_CMD_SET_MULTI_LIST 0x5 187 #define OCTNET_CMD_CLEAR_STATS 0x6 188 189 /* command for setting the speed, duplex & autoneg */ 190 #define OCTNET_CMD_SET_SETTINGS 0x7 191 #define OCTNET_CMD_SET_FLOW_CTL 0x8 192 193 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 194 #define OCTNET_CMD_GPIO_ACCESS 0xA 195 #define OCTNET_CMD_LRO_ENABLE 0xB 196 #define OCTNET_CMD_LRO_DISABLE 0xC 197 #define OCTNET_CMD_SET_RSS 0xD 198 #define OCTNET_CMD_WRITE_SA 0xE 199 #define OCTNET_CMD_DELETE_SA 0xF 200 #define OCTNET_CMD_UPDATE_SA 0x12 201 202 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 203 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 204 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 205 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 206 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 207 208 #define OCTNET_CMD_ENABLE_VLAN_FILTER 0x16 209 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 210 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 211 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 212 213 #define OCTNET_CMD_ID_ACTIVE 0x1a 214 215 #define OCTNET_CMD_SET_UC_LIST 0x1b 216 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 217 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 218 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 219 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 220 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 221 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 222 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 223 224 /* RX(packets coming from wire) Checksum verification flags */ 225 /* TCP/UDP csum */ 226 #define CNNIC_L4SUM_VERIFIED 0x1 227 #define CNNIC_IPSUM_VERIFIED 0x2 228 #define CNNIC_TUN_CSUM_VERIFIED 0x4 229 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 230 231 /*LROIPV4 and LROIPV6 Flags*/ 232 #define OCTNIC_LROIPV4 0x1 233 #define OCTNIC_LROIPV6 0x2 234 235 /* Interface flags communicated between host driver and core app. */ 236 enum octnet_ifflags { 237 OCTNET_IFFLAG_PROMISC = 0x01, 238 OCTNET_IFFLAG_ALLMULTI = 0x02, 239 OCTNET_IFFLAG_MULTICAST = 0x04, 240 OCTNET_IFFLAG_BROADCAST = 0x08, 241 OCTNET_IFFLAG_UNICAST = 0x10 242 }; 243 244 /* wqe 245 * --------------- 0 246 * | wqe word0-3 | 247 * --------------- 32 248 * | PCI IH | 249 * --------------- 40 250 * | RPTR | 251 * --------------- 48 252 * | PCI IRH | 253 * --------------- 56 254 * | OCT_NET_CMD | 255 * --------------- 64 256 * | Addtl 8-BData | 257 * | | 258 * --------------- 259 */ 260 261 union octnet_cmd { 262 u64 u64; 263 264 struct { 265 #ifdef __BIG_ENDIAN_BITFIELD 266 u64 cmd:5; 267 268 u64 more:6; /* How many udd words follow the command */ 269 270 u64 reserved:29; 271 272 u64 param1:16; 273 274 u64 param2:8; 275 276 #else 277 278 u64 param2:8; 279 280 u64 param1:16; 281 282 u64 reserved:29; 283 284 u64 more:6; 285 286 u64 cmd:5; 287 288 #endif 289 } s; 290 291 }; 292 293 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 294 295 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 296 #define LIO_SOFTCMDRESP_IH2 40 297 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 298 299 #define LIO_PCICMD_O2 24 300 #define LIO_PCICMD_O3 (24 + 8) 301 302 /* Instruction Header(DPI) - for OCTEON-III models */ 303 struct octeon_instr_ih3 { 304 #ifdef __BIG_ENDIAN_BITFIELD 305 306 /** Reserved3 */ 307 u64 reserved3:1; 308 309 /** Gather indicator 1=gather*/ 310 u64 gather:1; 311 312 /** Data length OR no. of entries in gather list */ 313 u64 dlengsz:14; 314 315 /** Front Data size */ 316 u64 fsz:6; 317 318 /** Reserved2 */ 319 u64 reserved2:4; 320 321 /** PKI port kind - PKIND */ 322 u64 pkind:6; 323 324 /** Reserved1 */ 325 u64 reserved1:32; 326 327 #else 328 /** Reserved1 */ 329 u64 reserved1:32; 330 331 /** PKI port kind - PKIND */ 332 u64 pkind:6; 333 334 /** Reserved2 */ 335 u64 reserved2:4; 336 337 /** Front Data size */ 338 u64 fsz:6; 339 340 /** Data length OR no. of entries in gather list */ 341 u64 dlengsz:14; 342 343 /** Gather indicator 1=gather*/ 344 u64 gather:1; 345 346 /** Reserved3 */ 347 u64 reserved3:1; 348 349 #endif 350 }; 351 352 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 353 /** BIG ENDIAN format. */ 354 struct octeon_instr_pki_ih3 { 355 #ifdef __BIG_ENDIAN_BITFIELD 356 357 /** Wider bit */ 358 u64 w:1; 359 360 /** Raw mode indicator 1 = RAW */ 361 u64 raw:1; 362 363 /** Use Tag */ 364 u64 utag:1; 365 366 /** Use QPG */ 367 u64 uqpg:1; 368 369 /** Reserved2 */ 370 u64 reserved2:1; 371 372 /** Parse Mode */ 373 u64 pm:3; 374 375 /** Skip Length */ 376 u64 sl:8; 377 378 /** Use Tag Type */ 379 u64 utt:1; 380 381 /** Tag type */ 382 u64 tagtype:2; 383 384 /** Reserved1 */ 385 u64 reserved1:2; 386 387 /** QPG Value */ 388 u64 qpg:11; 389 390 /** Tag Value */ 391 u64 tag:32; 392 393 #else 394 395 /** Tag Value */ 396 u64 tag:32; 397 398 /** QPG Value */ 399 u64 qpg:11; 400 401 /** Reserved1 */ 402 u64 reserved1:2; 403 404 /** Tag type */ 405 u64 tagtype:2; 406 407 /** Use Tag Type */ 408 u64 utt:1; 409 410 /** Skip Length */ 411 u64 sl:8; 412 413 /** Parse Mode */ 414 u64 pm:3; 415 416 /** Reserved2 */ 417 u64 reserved2:1; 418 419 /** Use QPG */ 420 u64 uqpg:1; 421 422 /** Use Tag */ 423 u64 utag:1; 424 425 /** Raw mode indicator 1 = RAW */ 426 u64 raw:1; 427 428 /** Wider bit */ 429 u64 w:1; 430 #endif 431 432 }; 433 434 /** Instruction Header */ 435 struct octeon_instr_ih2 { 436 #ifdef __BIG_ENDIAN_BITFIELD 437 /** Raw mode indicator 1 = RAW */ 438 u64 raw:1; 439 440 /** Gather indicator 1=gather*/ 441 u64 gather:1; 442 443 /** Data length OR no. of entries in gather list */ 444 u64 dlengsz:14; 445 446 /** Front Data size */ 447 u64 fsz:6; 448 449 /** Packet Order / Work Unit selection (1 of 8)*/ 450 u64 qos:3; 451 452 /** Core group selection (1 of 16) */ 453 u64 grp:4; 454 455 /** Short Raw Packet Indicator 1=short raw pkt */ 456 u64 rs:1; 457 458 /** Tag type */ 459 u64 tagtype:2; 460 461 /** Tag Value */ 462 u64 tag:32; 463 #else 464 /** Tag Value */ 465 u64 tag:32; 466 467 /** Tag type */ 468 u64 tagtype:2; 469 470 /** Short Raw Packet Indicator 1=short raw pkt */ 471 u64 rs:1; 472 473 /** Core group selection (1 of 16) */ 474 u64 grp:4; 475 476 /** Packet Order / Work Unit selection (1 of 8)*/ 477 u64 qos:3; 478 479 /** Front Data size */ 480 u64 fsz:6; 481 482 /** Data length OR no. of entries in gather list */ 483 u64 dlengsz:14; 484 485 /** Gather indicator 1=gather*/ 486 u64 gather:1; 487 488 /** Raw mode indicator 1 = RAW */ 489 u64 raw:1; 490 #endif 491 }; 492 493 /** Input Request Header */ 494 struct octeon_instr_irh { 495 #ifdef __BIG_ENDIAN_BITFIELD 496 u64 opcode:4; 497 u64 rflag:1; 498 u64 subcode:7; 499 u64 vlan:12; 500 u64 priority:3; 501 u64 reserved:5; 502 u64 ossp:32; /* opcode/subcode specific parameters */ 503 #else 504 u64 ossp:32; /* opcode/subcode specific parameters */ 505 u64 reserved:5; 506 u64 priority:3; 507 u64 vlan:12; 508 u64 subcode:7; 509 u64 rflag:1; 510 u64 opcode:4; 511 #endif 512 }; 513 514 /** Return Data Parameters */ 515 struct octeon_instr_rdp { 516 #ifdef __BIG_ENDIAN_BITFIELD 517 u64 reserved:49; 518 u64 pcie_port:3; 519 u64 rlen:12; 520 #else 521 u64 rlen:12; 522 u64 pcie_port:3; 523 u64 reserved:49; 524 #endif 525 }; 526 527 /** Receive Header */ 528 union octeon_rh { 529 #ifdef __BIG_ENDIAN_BITFIELD 530 u64 u64; 531 struct { 532 u64 opcode:4; 533 u64 subcode:8; 534 u64 len:3; /** additional 64-bit words */ 535 u64 reserved:17; 536 u64 ossp:32; /** opcode/subcode specific parameters */ 537 } r; 538 struct { 539 u64 opcode:4; 540 u64 subcode:8; 541 u64 len:3; /** additional 64-bit words */ 542 u64 extra:28; 543 u64 vlan:12; 544 u64 priority:3; 545 u64 csum_verified:3; /** checksum verified. */ 546 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 547 u64 encap_on:1; 548 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 549 } r_dh; 550 struct { 551 u64 opcode:4; 552 u64 subcode:8; 553 u64 len:3; /** additional 64-bit words */ 554 u64 reserved:11; 555 u64 num_gmx_ports:8; 556 u64 max_nic_ports:10; 557 u64 app_cap_flags:4; 558 u64 app_mode:8; 559 u64 pkind:8; 560 } r_core_drv_init; 561 struct { 562 u64 opcode:4; 563 u64 subcode:8; 564 u64 len:3; /** additional 64-bit words */ 565 u64 reserved:8; 566 u64 extra:25; 567 u64 gmxport:16; 568 } r_nic_info; 569 #else 570 u64 u64; 571 struct { 572 u64 ossp:32; /** opcode/subcode specific parameters */ 573 u64 reserved:17; 574 u64 len:3; /** additional 64-bit words */ 575 u64 subcode:8; 576 u64 opcode:4; 577 } r; 578 struct { 579 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 580 u64 encap_on:1; 581 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 582 u64 csum_verified:3; /** checksum verified. */ 583 u64 priority:3; 584 u64 vlan:12; 585 u64 extra:28; 586 u64 len:3; /** additional 64-bit words */ 587 u64 subcode:8; 588 u64 opcode:4; 589 } r_dh; 590 struct { 591 u64 pkind:8; 592 u64 app_mode:8; 593 u64 app_cap_flags:4; 594 u64 max_nic_ports:10; 595 u64 num_gmx_ports:8; 596 u64 reserved:11; 597 u64 len:3; /** additional 64-bit words */ 598 u64 subcode:8; 599 u64 opcode:4; 600 } r_core_drv_init; 601 struct { 602 u64 gmxport:16; 603 u64 extra:25; 604 u64 reserved:8; 605 u64 len:3; /** additional 64-bit words */ 606 u64 subcode:8; 607 u64 opcode:4; 608 } r_nic_info; 609 #endif 610 }; 611 612 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 613 614 union octnic_packet_params { 615 u32 u32; 616 struct { 617 #ifdef __BIG_ENDIAN_BITFIELD 618 u32 reserved:24; 619 u32 ip_csum:1; /* Perform IP header checksum(s) */ 620 /* Perform Outer transport header checksum */ 621 u32 transport_csum:1; 622 /* Find tunnel, and perform transport csum. */ 623 u32 tnl_csum:1; 624 u32 tsflag:1; /* Timestamp this packet */ 625 u32 ipsec_ops:4; /* IPsec operation */ 626 #else 627 u32 ipsec_ops:4; 628 u32 tsflag:1; 629 u32 tnl_csum:1; 630 u32 transport_csum:1; 631 u32 ip_csum:1; 632 u32 reserved:24; 633 #endif 634 } s; 635 }; 636 637 /** Status of a RGMII Link on Octeon as seen by core driver. */ 638 union oct_link_status { 639 u64 u64; 640 641 struct { 642 #ifdef __BIG_ENDIAN_BITFIELD 643 u64 duplex:8; 644 u64 mtu:16; 645 u64 speed:16; 646 u64 link_up:1; 647 u64 autoneg:1; 648 u64 if_mode:5; 649 u64 pause:1; 650 u64 flashing:1; 651 u64 reserved:15; 652 #else 653 u64 reserved:15; 654 u64 flashing:1; 655 u64 pause:1; 656 u64 if_mode:5; 657 u64 autoneg:1; 658 u64 link_up:1; 659 u64 speed:16; 660 u64 mtu:16; 661 u64 duplex:8; 662 #endif 663 } s; 664 }; 665 666 /** The txpciq info passed to host from the firmware */ 667 668 union oct_txpciq { 669 u64 u64; 670 671 struct { 672 #ifdef __BIG_ENDIAN_BITFIELD 673 u64 q_no:8; 674 u64 port:8; 675 u64 pkind:6; 676 u64 use_qpg:1; 677 u64 qpg:11; 678 u64 reserved:30; 679 #else 680 u64 reserved:30; 681 u64 qpg:11; 682 u64 use_qpg:1; 683 u64 pkind:6; 684 u64 port:8; 685 u64 q_no:8; 686 #endif 687 } s; 688 }; 689 690 /** The rxpciq info passed to host from the firmware */ 691 692 union oct_rxpciq { 693 u64 u64; 694 695 struct { 696 #ifdef __BIG_ENDIAN_BITFIELD 697 u64 q_no:8; 698 u64 reserved:56; 699 #else 700 u64 reserved:56; 701 u64 q_no:8; 702 #endif 703 } s; 704 }; 705 706 /** Information for a OCTEON ethernet interface shared between core & host. */ 707 struct oct_link_info { 708 union oct_link_status link; 709 u64 hw_addr; 710 711 #ifdef __BIG_ENDIAN_BITFIELD 712 u64 gmxport:16; 713 u64 macaddr_is_admin_asgnd:1; 714 u64 rsvd:31; 715 u64 num_txpciq:8; 716 u64 num_rxpciq:8; 717 #else 718 u64 num_rxpciq:8; 719 u64 num_txpciq:8; 720 u64 rsvd:31; 721 u64 macaddr_is_admin_asgnd:1; 722 u64 gmxport:16; 723 #endif 724 725 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 726 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 727 }; 728 729 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 730 731 struct liquidio_if_cfg_info { 732 u64 iqmask; /** mask for IQs enabled for the port */ 733 u64 oqmask; /** mask for OQs enabled for the port */ 734 struct oct_link_info linfo; /** initial link information */ 735 char liquidio_firmware_version[32]; 736 }; 737 738 /** Stats for each NIC port in RX direction. */ 739 struct nic_rx_stats { 740 /* link-level stats */ 741 u64 total_rcvd; 742 u64 bytes_rcvd; 743 u64 total_bcst; 744 u64 total_mcst; 745 u64 runts; 746 u64 ctl_rcvd; 747 u64 fifo_err; /* Accounts for over/under-run of buffers */ 748 u64 dmac_drop; 749 u64 fcs_err; 750 u64 jabber_err; 751 u64 l2_err; 752 u64 frame_err; 753 754 /* firmware stats */ 755 u64 fw_total_rcvd; 756 u64 fw_total_fwd; 757 u64 fw_err_pko; 758 u64 fw_err_link; 759 u64 fw_err_drop; 760 u64 fw_rx_vxlan; 761 u64 fw_rx_vxlan_err; 762 763 /* LRO */ 764 u64 fw_lro_pkts; /* Number of packets that are LROed */ 765 u64 fw_lro_octs; /* Number of octets that are LROed */ 766 u64 fw_total_lro; /* Number of LRO packets formed */ 767 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 768 u64 fw_lro_aborts_port; 769 u64 fw_lro_aborts_seq; 770 u64 fw_lro_aborts_tsval; 771 u64 fw_lro_aborts_timer; 772 /* intrmod: packet forward rate */ 773 u64 fwd_rate; 774 }; 775 776 /** Stats for each NIC port in RX direction. */ 777 struct nic_tx_stats { 778 /* link-level stats */ 779 u64 total_pkts_sent; 780 u64 total_bytes_sent; 781 u64 mcast_pkts_sent; 782 u64 bcast_pkts_sent; 783 u64 ctl_sent; 784 u64 one_collision_sent; /* Packets sent after one collision*/ 785 u64 multi_collision_sent; /* Packets sent after multiple collision*/ 786 u64 max_collision_fail; /* Packets not sent due to max collisions */ 787 u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 788 u64 fifo_err; /* Accounts for over/under-run of buffers */ 789 u64 runts; 790 u64 total_collisions; /* Total number of collisions detected */ 791 792 /* firmware stats */ 793 u64 fw_total_sent; 794 u64 fw_total_fwd; 795 u64 fw_total_fwd_bytes; 796 u64 fw_err_pko; 797 u64 fw_err_link; 798 u64 fw_err_drop; 799 u64 fw_err_tso; 800 u64 fw_tso; /* number of tso requests */ 801 u64 fw_tso_fwd; /* number of packets segmented in tso */ 802 u64 fw_tx_vxlan; 803 }; 804 805 struct oct_link_stats { 806 struct nic_rx_stats fromwire; 807 struct nic_tx_stats fromhost; 808 809 }; 810 811 static inline int opcode_slow_path(union octeon_rh *rh) 812 { 813 u16 subcode1, subcode2; 814 815 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 816 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 817 818 return (subcode2 != subcode1); 819 } 820 821 #define LIO68XX_LED_CTRL_ADDR 0x3501 822 #define LIO68XX_LED_CTRL_CFGON 0x1f 823 #define LIO68XX_LED_CTRL_CFGOFF 0x100 824 #define LIO68XX_LED_BEACON_ADDR 0x3508 825 #define LIO68XX_LED_BEACON_CFGON 0x47fd 826 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 827 #define VITESSE_PHY_GPIO_DRIVEON 0x1 828 #define VITESSE_PHY_GPIO_CFG 0x8 829 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 830 #define VITESSE_PHY_GPIO_HIGH 0x2 831 #define VITESSE_PHY_GPIO_LOW 0x3 832 #define LED_IDENTIFICATION_ON 0x1 833 #define LED_IDENTIFICATION_OFF 0x0 834 835 struct oct_mdio_cmd { 836 u64 op; 837 u64 mdio_addr; 838 u64 value1; 839 u64 value2; 840 u64 value3; 841 }; 842 843 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 844 845 /* intrmod: max. packet rate threshold */ 846 #define LIO_INTRMOD_MAXPKT_RATETHR 196608 847 /* intrmod: min. packet rate threshold */ 848 #define LIO_INTRMOD_MINPKT_RATETHR 9216 849 /* intrmod: max. packets to trigger interrupt */ 850 #define LIO_INTRMOD_RXMAXCNT_TRIGGER 384 851 /* intrmod: min. packets to trigger interrupt */ 852 #define LIO_INTRMOD_RXMINCNT_TRIGGER 0 853 /* intrmod: max. time to trigger interrupt */ 854 #define LIO_INTRMOD_RXMAXTMR_TRIGGER 128 855 /* 66xx:intrmod: min. time to trigger interrupt 856 * (value of 1 is optimum for TCP_RR) 857 */ 858 #define LIO_INTRMOD_RXMINTMR_TRIGGER 1 859 860 /* intrmod: max. packets to trigger interrupt */ 861 #define LIO_INTRMOD_TXMAXCNT_TRIGGER 64 862 /* intrmod: min. packets to trigger interrupt */ 863 #define LIO_INTRMOD_TXMINCNT_TRIGGER 0 864 865 /* intrmod: poll interval in seconds */ 866 #define LIO_INTRMOD_CHECK_INTERVAL 1 867 868 struct oct_intrmod_cfg { 869 u64 rx_enable; 870 u64 tx_enable; 871 u64 check_intrvl; 872 u64 maxpkt_ratethr; 873 u64 minpkt_ratethr; 874 u64 rx_maxcnt_trigger; 875 u64 rx_mincnt_trigger; 876 u64 rx_maxtmr_trigger; 877 u64 rx_mintmr_trigger; 878 u64 tx_mincnt_trigger; 879 u64 tx_maxcnt_trigger; 880 u64 rx_frames; 881 u64 tx_frames; 882 u64 rx_usecs; 883 }; 884 885 #define BASE_QUEUE_NOT_REQUESTED 65535 886 887 union oct_nic_if_cfg { 888 u64 u64; 889 struct { 890 #ifdef __BIG_ENDIAN_BITFIELD 891 u64 base_queue:16; 892 u64 num_iqueues:16; 893 u64 num_oqueues:16; 894 u64 gmx_port_id:8; 895 u64 vf_id:8; 896 #else 897 u64 vf_id:8; 898 u64 gmx_port_id:8; 899 u64 num_oqueues:16; 900 u64 num_iqueues:16; 901 u64 base_queue:16; 902 #endif 903 } s; 904 }; 905 906 #endif 907