1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 5 31 #define LIQUIDIO_BASE_MICRO_VERSION 1 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define VF_DRV_LOADED 1 88 #define VF_DRV_REMOVED -1 89 #define VF_DRV_MACADDR_CHANGED 2 90 91 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 92 93 /* Application codes advertised by the core driver initialization packet. */ 94 #define CVM_DRV_APP_START 0x0 95 #define CVM_DRV_NO_APP 0 96 #define CVM_DRV_APP_COUNT 0x2 97 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 98 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 99 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 100 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 101 102 #define BYTES_PER_DHLEN_UNIT 8 103 #define MAX_REG_CNT 2000000U 104 #define INTRNAMSIZ 32 105 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 106 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 107 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 108 109 110 static inline u32 incr_index(u32 index, u32 count, u32 max) 111 { 112 if ((index + count) >= max) 113 index = index + count - max; 114 else 115 index += count; 116 117 return index; 118 } 119 120 #define OCT_BOARD_NAME 32 121 #define OCT_SERIAL_LEN 64 122 123 /* Structure used by core driver to send indication that the Octeon 124 * application is ready. 125 */ 126 struct octeon_core_setup { 127 u64 corefreq; 128 129 char boardname[OCT_BOARD_NAME]; 130 131 char board_serial_number[OCT_SERIAL_LEN]; 132 133 u64 board_rev_major; 134 135 u64 board_rev_minor; 136 137 }; 138 139 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 140 141 /* The Scatter-Gather List Entry. The scatter or gather component used with 142 * a Octeon input instruction has this format. 143 */ 144 struct octeon_sg_entry { 145 /** The first 64 bit gives the size of data in each dptr.*/ 146 union { 147 u16 size[4]; 148 u64 size64; 149 } u; 150 151 /** The 4 dptr pointers for this entry. */ 152 u64 ptr[4]; 153 154 }; 155 156 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 157 158 /* \brief Add size to gather list 159 * @param sg_entry scatter/gather entry 160 * @param size size to add 161 * @param pos position to add it. 162 */ 163 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 164 u16 size, 165 u32 pos) 166 { 167 #ifdef __BIG_ENDIAN_BITFIELD 168 sg_entry->u.size[pos] = size; 169 #else 170 sg_entry->u.size[3 - pos] = size; 171 #endif 172 } 173 174 /*------------------------- End Scatter/Gather ---------------------------*/ 175 176 #define OCTNET_FRM_LENGTH_SIZE 8 177 178 #define OCTNET_FRM_PTP_HEADER_SIZE 8 179 180 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 181 182 #define OCTNET_MIN_FRM_SIZE 64 183 184 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 185 186 #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE) 187 188 /** NIC Commands are sent using this Octeon Input Queue */ 189 #define OCTNET_CMD_Q 0 190 191 /* NIC Command types */ 192 #define OCTNET_CMD_RESET_PF 0x0 193 #define OCTNET_CMD_CHANGE_MTU 0x1 194 #define OCTNET_CMD_CHANGE_MACADDR 0x2 195 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 196 #define OCTNET_CMD_RX_CTL 0x4 197 198 #define OCTNET_CMD_SET_MULTI_LIST 0x5 199 #define OCTNET_CMD_CLEAR_STATS 0x6 200 201 /* command for setting the speed, duplex & autoneg */ 202 #define OCTNET_CMD_SET_SETTINGS 0x7 203 #define OCTNET_CMD_SET_FLOW_CTL 0x8 204 205 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 206 #define OCTNET_CMD_GPIO_ACCESS 0xA 207 #define OCTNET_CMD_LRO_ENABLE 0xB 208 #define OCTNET_CMD_LRO_DISABLE 0xC 209 #define OCTNET_CMD_SET_RSS 0xD 210 #define OCTNET_CMD_WRITE_SA 0xE 211 #define OCTNET_CMD_DELETE_SA 0xF 212 #define OCTNET_CMD_UPDATE_SA 0x12 213 214 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 215 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 216 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 217 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 218 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 219 220 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 221 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 222 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 223 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 224 225 #define OCTNET_CMD_ID_ACTIVE 0x1a 226 227 #define OCTNET_CMD_SET_UC_LIST 0x1b 228 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 229 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 230 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 231 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 232 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 233 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 234 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 235 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 236 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 237 238 /* RX(packets coming from wire) Checksum verification flags */ 239 /* TCP/UDP csum */ 240 #define CNNIC_L4SUM_VERIFIED 0x1 241 #define CNNIC_IPSUM_VERIFIED 0x2 242 #define CNNIC_TUN_CSUM_VERIFIED 0x4 243 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 244 245 /*LROIPV4 and LROIPV6 Flags*/ 246 #define OCTNIC_LROIPV4 0x1 247 #define OCTNIC_LROIPV6 0x2 248 249 /* Interface flags communicated between host driver and core app. */ 250 enum octnet_ifflags { 251 OCTNET_IFFLAG_PROMISC = 0x01, 252 OCTNET_IFFLAG_ALLMULTI = 0x02, 253 OCTNET_IFFLAG_MULTICAST = 0x04, 254 OCTNET_IFFLAG_BROADCAST = 0x08, 255 OCTNET_IFFLAG_UNICAST = 0x10 256 }; 257 258 /* wqe 259 * --------------- 0 260 * | wqe word0-3 | 261 * --------------- 32 262 * | PCI IH | 263 * --------------- 40 264 * | RPTR | 265 * --------------- 48 266 * | PCI IRH | 267 * --------------- 56 268 * | OCT_NET_CMD | 269 * --------------- 64 270 * | Addtl 8-BData | 271 * | | 272 * --------------- 273 */ 274 275 union octnet_cmd { 276 u64 u64; 277 278 struct { 279 #ifdef __BIG_ENDIAN_BITFIELD 280 u64 cmd:5; 281 282 u64 more:6; /* How many udd words follow the command */ 283 284 u64 reserved:29; 285 286 u64 param1:16; 287 288 u64 param2:8; 289 290 #else 291 292 u64 param2:8; 293 294 u64 param1:16; 295 296 u64 reserved:29; 297 298 u64 more:6; 299 300 u64 cmd:5; 301 302 #endif 303 } s; 304 305 }; 306 307 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 308 309 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 310 #define LIO_SOFTCMDRESP_IH2 40 311 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 312 313 #define LIO_PCICMD_O2 24 314 #define LIO_PCICMD_O3 (24 + 8) 315 316 /* Instruction Header(DPI) - for OCTEON-III models */ 317 struct octeon_instr_ih3 { 318 #ifdef __BIG_ENDIAN_BITFIELD 319 320 /** Reserved3 */ 321 u64 reserved3:1; 322 323 /** Gather indicator 1=gather*/ 324 u64 gather:1; 325 326 /** Data length OR no. of entries in gather list */ 327 u64 dlengsz:14; 328 329 /** Front Data size */ 330 u64 fsz:6; 331 332 /** Reserved2 */ 333 u64 reserved2:4; 334 335 /** PKI port kind - PKIND */ 336 u64 pkind:6; 337 338 /** Reserved1 */ 339 u64 reserved1:32; 340 341 #else 342 /** Reserved1 */ 343 u64 reserved1:32; 344 345 /** PKI port kind - PKIND */ 346 u64 pkind:6; 347 348 /** Reserved2 */ 349 u64 reserved2:4; 350 351 /** Front Data size */ 352 u64 fsz:6; 353 354 /** Data length OR no. of entries in gather list */ 355 u64 dlengsz:14; 356 357 /** Gather indicator 1=gather*/ 358 u64 gather:1; 359 360 /** Reserved3 */ 361 u64 reserved3:1; 362 363 #endif 364 }; 365 366 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 367 /** BIG ENDIAN format. */ 368 struct octeon_instr_pki_ih3 { 369 #ifdef __BIG_ENDIAN_BITFIELD 370 371 /** Wider bit */ 372 u64 w:1; 373 374 /** Raw mode indicator 1 = RAW */ 375 u64 raw:1; 376 377 /** Use Tag */ 378 u64 utag:1; 379 380 /** Use QPG */ 381 u64 uqpg:1; 382 383 /** Reserved2 */ 384 u64 reserved2:1; 385 386 /** Parse Mode */ 387 u64 pm:3; 388 389 /** Skip Length */ 390 u64 sl:8; 391 392 /** Use Tag Type */ 393 u64 utt:1; 394 395 /** Tag type */ 396 u64 tagtype:2; 397 398 /** Reserved1 */ 399 u64 reserved1:2; 400 401 /** QPG Value */ 402 u64 qpg:11; 403 404 /** Tag Value */ 405 u64 tag:32; 406 407 #else 408 409 /** Tag Value */ 410 u64 tag:32; 411 412 /** QPG Value */ 413 u64 qpg:11; 414 415 /** Reserved1 */ 416 u64 reserved1:2; 417 418 /** Tag type */ 419 u64 tagtype:2; 420 421 /** Use Tag Type */ 422 u64 utt:1; 423 424 /** Skip Length */ 425 u64 sl:8; 426 427 /** Parse Mode */ 428 u64 pm:3; 429 430 /** Reserved2 */ 431 u64 reserved2:1; 432 433 /** Use QPG */ 434 u64 uqpg:1; 435 436 /** Use Tag */ 437 u64 utag:1; 438 439 /** Raw mode indicator 1 = RAW */ 440 u64 raw:1; 441 442 /** Wider bit */ 443 u64 w:1; 444 #endif 445 446 }; 447 448 /** Instruction Header */ 449 struct octeon_instr_ih2 { 450 #ifdef __BIG_ENDIAN_BITFIELD 451 /** Raw mode indicator 1 = RAW */ 452 u64 raw:1; 453 454 /** Gather indicator 1=gather*/ 455 u64 gather:1; 456 457 /** Data length OR no. of entries in gather list */ 458 u64 dlengsz:14; 459 460 /** Front Data size */ 461 u64 fsz:6; 462 463 /** Packet Order / Work Unit selection (1 of 8)*/ 464 u64 qos:3; 465 466 /** Core group selection (1 of 16) */ 467 u64 grp:4; 468 469 /** Short Raw Packet Indicator 1=short raw pkt */ 470 u64 rs:1; 471 472 /** Tag type */ 473 u64 tagtype:2; 474 475 /** Tag Value */ 476 u64 tag:32; 477 #else 478 /** Tag Value */ 479 u64 tag:32; 480 481 /** Tag type */ 482 u64 tagtype:2; 483 484 /** Short Raw Packet Indicator 1=short raw pkt */ 485 u64 rs:1; 486 487 /** Core group selection (1 of 16) */ 488 u64 grp:4; 489 490 /** Packet Order / Work Unit selection (1 of 8)*/ 491 u64 qos:3; 492 493 /** Front Data size */ 494 u64 fsz:6; 495 496 /** Data length OR no. of entries in gather list */ 497 u64 dlengsz:14; 498 499 /** Gather indicator 1=gather*/ 500 u64 gather:1; 501 502 /** Raw mode indicator 1 = RAW */ 503 u64 raw:1; 504 #endif 505 }; 506 507 /** Input Request Header */ 508 struct octeon_instr_irh { 509 #ifdef __BIG_ENDIAN_BITFIELD 510 u64 opcode:4; 511 u64 rflag:1; 512 u64 subcode:7; 513 u64 vlan:12; 514 u64 priority:3; 515 u64 reserved:5; 516 u64 ossp:32; /* opcode/subcode specific parameters */ 517 #else 518 u64 ossp:32; /* opcode/subcode specific parameters */ 519 u64 reserved:5; 520 u64 priority:3; 521 u64 vlan:12; 522 u64 subcode:7; 523 u64 rflag:1; 524 u64 opcode:4; 525 #endif 526 }; 527 528 /** Return Data Parameters */ 529 struct octeon_instr_rdp { 530 #ifdef __BIG_ENDIAN_BITFIELD 531 u64 reserved:49; 532 u64 pcie_port:3; 533 u64 rlen:12; 534 #else 535 u64 rlen:12; 536 u64 pcie_port:3; 537 u64 reserved:49; 538 #endif 539 }; 540 541 /** Receive Header */ 542 union octeon_rh { 543 #ifdef __BIG_ENDIAN_BITFIELD 544 u64 u64; 545 struct { 546 u64 opcode:4; 547 u64 subcode:8; 548 u64 len:3; /** additional 64-bit words */ 549 u64 reserved:17; 550 u64 ossp:32; /** opcode/subcode specific parameters */ 551 } r; 552 struct { 553 u64 opcode:4; 554 u64 subcode:8; 555 u64 len:3; /** additional 64-bit words */ 556 u64 extra:28; 557 u64 vlan:12; 558 u64 priority:3; 559 u64 csum_verified:3; /** checksum verified. */ 560 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 561 u64 encap_on:1; 562 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 563 } r_dh; 564 struct { 565 u64 opcode:4; 566 u64 subcode:8; 567 u64 len:3; /** additional 64-bit words */ 568 u64 reserved:11; 569 u64 num_gmx_ports:8; 570 u64 max_nic_ports:10; 571 u64 app_cap_flags:4; 572 u64 app_mode:8; 573 u64 pkind:8; 574 } r_core_drv_init; 575 struct { 576 u64 opcode:4; 577 u64 subcode:8; 578 u64 len:3; /** additional 64-bit words */ 579 u64 reserved:8; 580 u64 extra:25; 581 u64 gmxport:16; 582 } r_nic_info; 583 #else 584 u64 u64; 585 struct { 586 u64 ossp:32; /** opcode/subcode specific parameters */ 587 u64 reserved:17; 588 u64 len:3; /** additional 64-bit words */ 589 u64 subcode:8; 590 u64 opcode:4; 591 } r; 592 struct { 593 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 594 u64 encap_on:1; 595 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 596 u64 csum_verified:3; /** checksum verified. */ 597 u64 priority:3; 598 u64 vlan:12; 599 u64 extra:28; 600 u64 len:3; /** additional 64-bit words */ 601 u64 subcode:8; 602 u64 opcode:4; 603 } r_dh; 604 struct { 605 u64 pkind:8; 606 u64 app_mode:8; 607 u64 app_cap_flags:4; 608 u64 max_nic_ports:10; 609 u64 num_gmx_ports:8; 610 u64 reserved:11; 611 u64 len:3; /** additional 64-bit words */ 612 u64 subcode:8; 613 u64 opcode:4; 614 } r_core_drv_init; 615 struct { 616 u64 gmxport:16; 617 u64 extra:25; 618 u64 reserved:8; 619 u64 len:3; /** additional 64-bit words */ 620 u64 subcode:8; 621 u64 opcode:4; 622 } r_nic_info; 623 #endif 624 }; 625 626 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 627 628 union octnic_packet_params { 629 u32 u32; 630 struct { 631 #ifdef __BIG_ENDIAN_BITFIELD 632 u32 reserved:24; 633 u32 ip_csum:1; /* Perform IP header checksum(s) */ 634 /* Perform Outer transport header checksum */ 635 u32 transport_csum:1; 636 /* Find tunnel, and perform transport csum. */ 637 u32 tnl_csum:1; 638 u32 tsflag:1; /* Timestamp this packet */ 639 u32 ipsec_ops:4; /* IPsec operation */ 640 #else 641 u32 ipsec_ops:4; 642 u32 tsflag:1; 643 u32 tnl_csum:1; 644 u32 transport_csum:1; 645 u32 ip_csum:1; 646 u32 reserved:24; 647 #endif 648 } s; 649 }; 650 651 /** Status of a RGMII Link on Octeon as seen by core driver. */ 652 union oct_link_status { 653 u64 u64; 654 655 struct { 656 #ifdef __BIG_ENDIAN_BITFIELD 657 u64 duplex:8; 658 u64 mtu:16; 659 u64 speed:16; 660 u64 link_up:1; 661 u64 autoneg:1; 662 u64 if_mode:5; 663 u64 pause:1; 664 u64 flashing:1; 665 u64 reserved:15; 666 #else 667 u64 reserved:15; 668 u64 flashing:1; 669 u64 pause:1; 670 u64 if_mode:5; 671 u64 autoneg:1; 672 u64 link_up:1; 673 u64 speed:16; 674 u64 mtu:16; 675 u64 duplex:8; 676 #endif 677 } s; 678 }; 679 680 /** The txpciq info passed to host from the firmware */ 681 682 union oct_txpciq { 683 u64 u64; 684 685 struct { 686 #ifdef __BIG_ENDIAN_BITFIELD 687 u64 q_no:8; 688 u64 port:8; 689 u64 pkind:6; 690 u64 use_qpg:1; 691 u64 qpg:11; 692 u64 reserved:30; 693 #else 694 u64 reserved:30; 695 u64 qpg:11; 696 u64 use_qpg:1; 697 u64 pkind:6; 698 u64 port:8; 699 u64 q_no:8; 700 #endif 701 } s; 702 }; 703 704 /** The rxpciq info passed to host from the firmware */ 705 706 union oct_rxpciq { 707 u64 u64; 708 709 struct { 710 #ifdef __BIG_ENDIAN_BITFIELD 711 u64 q_no:8; 712 u64 reserved:56; 713 #else 714 u64 reserved:56; 715 u64 q_no:8; 716 #endif 717 } s; 718 }; 719 720 /** Information for a OCTEON ethernet interface shared between core & host. */ 721 struct oct_link_info { 722 union oct_link_status link; 723 u64 hw_addr; 724 725 #ifdef __BIG_ENDIAN_BITFIELD 726 u64 gmxport:16; 727 u64 macaddr_is_admin_asgnd:1; 728 u64 rsvd:31; 729 u64 num_txpciq:8; 730 u64 num_rxpciq:8; 731 #else 732 u64 num_rxpciq:8; 733 u64 num_txpciq:8; 734 u64 rsvd:31; 735 u64 macaddr_is_admin_asgnd:1; 736 u64 gmxport:16; 737 #endif 738 739 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 740 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 741 }; 742 743 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 744 745 struct liquidio_if_cfg_info { 746 u64 iqmask; /** mask for IQs enabled for the port */ 747 u64 oqmask; /** mask for OQs enabled for the port */ 748 struct oct_link_info linfo; /** initial link information */ 749 char liquidio_firmware_version[32]; 750 }; 751 752 /** Stats for each NIC port in RX direction. */ 753 struct nic_rx_stats { 754 /* link-level stats */ 755 u64 total_rcvd; 756 u64 bytes_rcvd; 757 u64 total_bcst; 758 u64 total_mcst; 759 u64 runts; 760 u64 ctl_rcvd; 761 u64 fifo_err; /* Accounts for over/under-run of buffers */ 762 u64 dmac_drop; 763 u64 fcs_err; 764 u64 jabber_err; 765 u64 l2_err; 766 u64 frame_err; 767 768 /* firmware stats */ 769 u64 fw_total_rcvd; 770 u64 fw_total_fwd; 771 u64 fw_err_pko; 772 u64 fw_err_link; 773 u64 fw_err_drop; 774 u64 fw_rx_vxlan; 775 u64 fw_rx_vxlan_err; 776 777 /* LRO */ 778 u64 fw_lro_pkts; /* Number of packets that are LROed */ 779 u64 fw_lro_octs; /* Number of octets that are LROed */ 780 u64 fw_total_lro; /* Number of LRO packets formed */ 781 u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 782 u64 fw_lro_aborts_port; 783 u64 fw_lro_aborts_seq; 784 u64 fw_lro_aborts_tsval; 785 u64 fw_lro_aborts_timer; 786 /* intrmod: packet forward rate */ 787 u64 fwd_rate; 788 }; 789 790 /** Stats for each NIC port in RX direction. */ 791 struct nic_tx_stats { 792 /* link-level stats */ 793 u64 total_pkts_sent; 794 u64 total_bytes_sent; 795 u64 mcast_pkts_sent; 796 u64 bcast_pkts_sent; 797 u64 ctl_sent; 798 u64 one_collision_sent; /* Packets sent after one collision*/ 799 u64 multi_collision_sent; /* Packets sent after multiple collision*/ 800 u64 max_collision_fail; /* Packets not sent due to max collisions */ 801 u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 802 u64 fifo_err; /* Accounts for over/under-run of buffers */ 803 u64 runts; 804 u64 total_collisions; /* Total number of collisions detected */ 805 806 /* firmware stats */ 807 u64 fw_total_sent; 808 u64 fw_total_fwd; 809 u64 fw_total_fwd_bytes; 810 u64 fw_err_pko; 811 u64 fw_err_link; 812 u64 fw_err_drop; 813 u64 fw_err_tso; 814 u64 fw_tso; /* number of tso requests */ 815 u64 fw_tso_fwd; /* number of packets segmented in tso */ 816 u64 fw_tx_vxlan; 817 }; 818 819 struct oct_link_stats { 820 struct nic_rx_stats fromwire; 821 struct nic_tx_stats fromhost; 822 823 }; 824 825 static inline int opcode_slow_path(union octeon_rh *rh) 826 { 827 u16 subcode1, subcode2; 828 829 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 830 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 831 832 return (subcode2 != subcode1); 833 } 834 835 #define LIO68XX_LED_CTRL_ADDR 0x3501 836 #define LIO68XX_LED_CTRL_CFGON 0x1f 837 #define LIO68XX_LED_CTRL_CFGOFF 0x100 838 #define LIO68XX_LED_BEACON_ADDR 0x3508 839 #define LIO68XX_LED_BEACON_CFGON 0x47fd 840 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 841 #define VITESSE_PHY_GPIO_DRIVEON 0x1 842 #define VITESSE_PHY_GPIO_CFG 0x8 843 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 844 #define VITESSE_PHY_GPIO_HIGH 0x2 845 #define VITESSE_PHY_GPIO_LOW 0x3 846 #define LED_IDENTIFICATION_ON 0x1 847 #define LED_IDENTIFICATION_OFF 0x0 848 849 struct oct_mdio_cmd { 850 u64 op; 851 u64 mdio_addr; 852 u64 value1; 853 u64 value2; 854 u64 value3; 855 }; 856 857 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 858 859 struct oct_intrmod_cfg { 860 u64 rx_enable; 861 u64 tx_enable; 862 u64 check_intrvl; 863 u64 maxpkt_ratethr; 864 u64 minpkt_ratethr; 865 u64 rx_maxcnt_trigger; 866 u64 rx_mincnt_trigger; 867 u64 rx_maxtmr_trigger; 868 u64 rx_mintmr_trigger; 869 u64 tx_mincnt_trigger; 870 u64 tx_maxcnt_trigger; 871 u64 rx_frames; 872 u64 tx_frames; 873 u64 rx_usecs; 874 }; 875 876 #define BASE_QUEUE_NOT_REQUESTED 65535 877 878 union oct_nic_if_cfg { 879 u64 u64; 880 struct { 881 #ifdef __BIG_ENDIAN_BITFIELD 882 u64 base_queue:16; 883 u64 num_iqueues:16; 884 u64 num_oqueues:16; 885 u64 gmx_port_id:8; 886 u64 vf_id:8; 887 #else 888 u64 vf_id:8; 889 u64 gmx_port_id:8; 890 u64 num_oqueues:16; 891 u64 num_iqueues:16; 892 u64 base_queue:16; 893 #endif 894 } s; 895 }; 896 897 #endif 898