1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 /*! \file liquidio_common.h 19 * \brief Common: Structures and macros used in PCI-NIC package by core and 20 * host driver. 21 */ 22 23 #ifndef __LIQUIDIO_COMMON_H__ 24 #define __LIQUIDIO_COMMON_H__ 25 26 #include "octeon_config.h" 27 28 #define LIQUIDIO_PACKAGE "" 29 #define LIQUIDIO_BASE_MAJOR_VERSION 1 30 #define LIQUIDIO_BASE_MINOR_VERSION 7 31 #define LIQUIDIO_BASE_MICRO_VERSION 2 32 #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 33 __stringify(LIQUIDIO_BASE_MINOR_VERSION) 34 #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 35 #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 36 __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 37 __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 38 "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 39 40 struct lio_version { 41 u16 major; 42 u16 minor; 43 u16 micro; 44 u16 reserved; 45 }; 46 47 #define CONTROL_IQ 0 48 /** Tag types used by Octeon cores in its work. */ 49 enum octeon_tag_type { 50 ORDERED_TAG = 0, 51 ATOMIC_TAG = 1, 52 NULL_TAG = 2, 53 NULL_NULL_TAG = 3 54 }; 55 56 /* pre-defined host->NIC tag values */ 57 #define LIO_CONTROL (0x11111110) 58 #define LIO_DATA(i) (0x11111111 + (i)) 59 60 /* Opcodes used by host driver/apps to perform operations on the core. 61 * These are used to identify the major subsystem that the operation 62 * is for. 63 */ 64 #define OPCODE_CORE 0 /* used for generic core operations */ 65 #define OPCODE_NIC 1 /* used for NIC operations */ 66 /* Subcodes are used by host driver/apps to identify the sub-operation 67 * for the core. They only need to by unique for a given subsystem. 68 */ 69 #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70 71 /** OPCODE_CORE subcodes. For future use. */ 72 73 /** OPCODE_NIC subcodes */ 74 75 /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76 #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77 #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78 #define OPCODE_NIC_CMD 0x03 79 #define OPCODE_NIC_INFO 0x04 80 #define OPCODE_NIC_PORT_STATS 0x05 81 #define OPCODE_NIC_MDIO45 0x06 82 #define OPCODE_NIC_TIMESTAMP 0x07 83 #define OPCODE_NIC_INTRMOD_CFG 0x08 84 #define OPCODE_NIC_IF_CFG 0x09 85 #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 86 #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87 #define OPCODE_NIC_QCOUNT_UPDATE 0x12 88 #define OPCODE_NIC_SET_TRUSTED_VF 0x13 89 #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 90 #define VF_DRV_LOADED 1 91 #define VF_DRV_REMOVED -1 92 #define VF_DRV_MACADDR_CHANGED 2 93 94 #define OPCODE_NIC_VF_REP_PKT 0x15 95 #define OPCODE_NIC_VF_REP_CMD 0x16 96 #define OPCODE_NIC_UBOOT_CTL 0x17 97 98 #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 99 100 /* Application codes advertised by the core driver initialization packet. */ 101 #define CVM_DRV_APP_START 0x0 102 #define CVM_DRV_NO_APP 0 103 #define CVM_DRV_APP_COUNT 0x2 104 #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 105 #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 106 #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 107 #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 108 109 #define BYTES_PER_DHLEN_UNIT 8 110 #define MAX_REG_CNT 2000000U 111 #define INTRNAMSIZ 32 112 #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 113 #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 114 #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 115 116 #define SCR2_BIT_FW_LOADED 63 117 118 /* App specific capabilities from firmware to pf driver */ 119 #define LIQUIDIO_TIME_SYNC_CAP 0x1 120 #define LIQUIDIO_SWITCHDEV_CAP 0x2 121 #define LIQUIDIO_SPOOFCHK_CAP 0x4 122 123 /* error status return from firmware */ 124 #define OCTEON_REQUEST_NO_PERMISSION 0xc 125 126 static inline u32 incr_index(u32 index, u32 count, u32 max) 127 { 128 if ((index + count) >= max) 129 index = index + count - max; 130 else 131 index += count; 132 133 return index; 134 } 135 136 #define OCT_BOARD_NAME 32 137 #define OCT_SERIAL_LEN 64 138 139 /* Structure used by core driver to send indication that the Octeon 140 * application is ready. 141 */ 142 struct octeon_core_setup { 143 u64 corefreq; 144 145 char boardname[OCT_BOARD_NAME]; 146 147 char board_serial_number[OCT_SERIAL_LEN]; 148 149 u64 board_rev_major; 150 151 u64 board_rev_minor; 152 153 }; 154 155 /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 156 157 /* The Scatter-Gather List Entry. The scatter or gather component used with 158 * a Octeon input instruction has this format. 159 */ 160 struct octeon_sg_entry { 161 /** The first 64 bit gives the size of data in each dptr.*/ 162 union { 163 u16 size[4]; 164 u64 size64; 165 } u; 166 167 /** The 4 dptr pointers for this entry. */ 168 u64 ptr[4]; 169 170 }; 171 172 #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 173 174 /* \brief Add size to gather list 175 * @param sg_entry scatter/gather entry 176 * @param size size to add 177 * @param pos position to add it. 178 */ 179 static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 180 u16 size, 181 u32 pos) 182 { 183 #ifdef __BIG_ENDIAN_BITFIELD 184 sg_entry->u.size[pos] = size; 185 #else 186 sg_entry->u.size[3 - pos] = size; 187 #endif 188 } 189 190 /*------------------------- End Scatter/Gather ---------------------------*/ 191 192 #define OCTNET_FRM_LENGTH_SIZE 8 193 194 #define OCTNET_FRM_PTP_HEADER_SIZE 8 195 196 #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 197 198 #define OCTNET_MIN_FRM_SIZE 64 199 200 #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 201 202 #define OCTNET_DEFAULT_MTU (1500) 203 #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE) 204 205 /** NIC Commands are sent using this Octeon Input Queue */ 206 #define OCTNET_CMD_Q 0 207 208 /* NIC Command types */ 209 #define OCTNET_CMD_CHANGE_MTU 0x1 210 #define OCTNET_CMD_CHANGE_MACADDR 0x2 211 #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 212 #define OCTNET_CMD_RX_CTL 0x4 213 214 #define OCTNET_CMD_SET_MULTI_LIST 0x5 215 #define OCTNET_CMD_CLEAR_STATS 0x6 216 217 /* command for setting the speed, duplex & autoneg */ 218 #define OCTNET_CMD_SET_SETTINGS 0x7 219 #define OCTNET_CMD_SET_FLOW_CTL 0x8 220 221 #define OCTNET_CMD_MDIO_READ_WRITE 0x9 222 #define OCTNET_CMD_GPIO_ACCESS 0xA 223 #define OCTNET_CMD_LRO_ENABLE 0xB 224 #define OCTNET_CMD_LRO_DISABLE 0xC 225 #define OCTNET_CMD_SET_RSS 0xD 226 #define OCTNET_CMD_WRITE_SA 0xE 227 #define OCTNET_CMD_DELETE_SA 0xF 228 #define OCTNET_CMD_UPDATE_SA 0x12 229 230 #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 231 #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 232 #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 233 #define OCTNET_CMD_VERBOSE_ENABLE 0x14 234 #define OCTNET_CMD_VERBOSE_DISABLE 0x15 235 236 #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 237 #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 238 #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 239 #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 240 241 #define OCTNET_CMD_ID_ACTIVE 0x1a 242 243 #define OCTNET_CMD_SET_UC_LIST 0x1b 244 #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 245 246 #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 247 248 #define OCTNET_CMD_GROUP1 1 249 #define OCTNET_CMD_SET_VF_SPOOFCHK 0x1 250 #define OCTNET_GROUP1_LAST_CMD OCTNET_CMD_SET_VF_SPOOFCHK 251 252 #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 253 #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 254 #define OCTNET_CMD_RXCSUM_ENABLE 0x0 255 #define OCTNET_CMD_RXCSUM_DISABLE 0x1 256 #define OCTNET_CMD_TXCSUM_ENABLE 0x0 257 #define OCTNET_CMD_TXCSUM_DISABLE 0x1 258 #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 259 #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 260 261 #define OCTNET_CMD_FAIL 0x1 262 263 #define SEAPI_CMD_SPEED_SET 0x2 264 #define SEAPI_CMD_SPEED_GET 0x3 265 266 #define OPCODE_NIC_VF_PORT_STATS 0x22 267 268 #define LIO_CMD_WAIT_TM 100 269 270 /* RX(packets coming from wire) Checksum verification flags */ 271 /* TCP/UDP csum */ 272 #define CNNIC_L4SUM_VERIFIED 0x1 273 #define CNNIC_IPSUM_VERIFIED 0x2 274 #define CNNIC_TUN_CSUM_VERIFIED 0x4 275 #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 276 277 /*LROIPV4 and LROIPV6 Flags*/ 278 #define OCTNIC_LROIPV4 0x1 279 #define OCTNIC_LROIPV6 0x2 280 281 /* Interface flags communicated between host driver and core app. */ 282 enum octnet_ifflags { 283 OCTNET_IFFLAG_PROMISC = 0x01, 284 OCTNET_IFFLAG_ALLMULTI = 0x02, 285 OCTNET_IFFLAG_MULTICAST = 0x04, 286 OCTNET_IFFLAG_BROADCAST = 0x08, 287 OCTNET_IFFLAG_UNICAST = 0x10 288 }; 289 290 /* wqe 291 * --------------- 0 292 * | wqe word0-3 | 293 * --------------- 32 294 * | PCI IH | 295 * --------------- 40 296 * | RPTR | 297 * --------------- 48 298 * | PCI IRH | 299 * --------------- 56 300 * | OCT_NET_CMD | 301 * --------------- 64 302 * | Addtl 8-BData | 303 * | | 304 * --------------- 305 */ 306 307 union octnet_cmd { 308 u64 u64; 309 310 struct { 311 #ifdef __BIG_ENDIAN_BITFIELD 312 u64 cmd:5; 313 314 u64 more:6; /* How many udd words follow the command */ 315 316 u64 cmdgroup:8; 317 u64 reserved:21; 318 319 u64 param1:16; 320 321 u64 param2:8; 322 323 #else 324 325 u64 param2:8; 326 327 u64 param1:16; 328 329 u64 reserved:21; 330 u64 cmdgroup:8; 331 332 u64 more:6; 333 334 u64 cmd:5; 335 336 #endif 337 } s; 338 339 }; 340 341 #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 342 343 /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 344 #define LIO_SOFTCMDRESP_IH2 40 345 #define LIO_SOFTCMDRESP_IH3 (40 + 8) 346 347 #define LIO_PCICMD_O2 24 348 #define LIO_PCICMD_O3 (24 + 8) 349 350 /* Instruction Header(DPI) - for OCTEON-III models */ 351 struct octeon_instr_ih3 { 352 #ifdef __BIG_ENDIAN_BITFIELD 353 354 /** Reserved3 */ 355 u64 reserved3:1; 356 357 /** Gather indicator 1=gather*/ 358 u64 gather:1; 359 360 /** Data length OR no. of entries in gather list */ 361 u64 dlengsz:14; 362 363 /** Front Data size */ 364 u64 fsz:6; 365 366 /** Reserved2 */ 367 u64 reserved2:4; 368 369 /** PKI port kind - PKIND */ 370 u64 pkind:6; 371 372 /** Reserved1 */ 373 u64 reserved1:32; 374 375 #else 376 /** Reserved1 */ 377 u64 reserved1:32; 378 379 /** PKI port kind - PKIND */ 380 u64 pkind:6; 381 382 /** Reserved2 */ 383 u64 reserved2:4; 384 385 /** Front Data size */ 386 u64 fsz:6; 387 388 /** Data length OR no. of entries in gather list */ 389 u64 dlengsz:14; 390 391 /** Gather indicator 1=gather*/ 392 u64 gather:1; 393 394 /** Reserved3 */ 395 u64 reserved3:1; 396 397 #endif 398 }; 399 400 /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 401 /** BIG ENDIAN format. */ 402 struct octeon_instr_pki_ih3 { 403 #ifdef __BIG_ENDIAN_BITFIELD 404 405 /** Wider bit */ 406 u64 w:1; 407 408 /** Raw mode indicator 1 = RAW */ 409 u64 raw:1; 410 411 /** Use Tag */ 412 u64 utag:1; 413 414 /** Use QPG */ 415 u64 uqpg:1; 416 417 /** Reserved2 */ 418 u64 reserved2:1; 419 420 /** Parse Mode */ 421 u64 pm:3; 422 423 /** Skip Length */ 424 u64 sl:8; 425 426 /** Use Tag Type */ 427 u64 utt:1; 428 429 /** Tag type */ 430 u64 tagtype:2; 431 432 /** Reserved1 */ 433 u64 reserved1:2; 434 435 /** QPG Value */ 436 u64 qpg:11; 437 438 /** Tag Value */ 439 u64 tag:32; 440 441 #else 442 443 /** Tag Value */ 444 u64 tag:32; 445 446 /** QPG Value */ 447 u64 qpg:11; 448 449 /** Reserved1 */ 450 u64 reserved1:2; 451 452 /** Tag type */ 453 u64 tagtype:2; 454 455 /** Use Tag Type */ 456 u64 utt:1; 457 458 /** Skip Length */ 459 u64 sl:8; 460 461 /** Parse Mode */ 462 u64 pm:3; 463 464 /** Reserved2 */ 465 u64 reserved2:1; 466 467 /** Use QPG */ 468 u64 uqpg:1; 469 470 /** Use Tag */ 471 u64 utag:1; 472 473 /** Raw mode indicator 1 = RAW */ 474 u64 raw:1; 475 476 /** Wider bit */ 477 u64 w:1; 478 #endif 479 480 }; 481 482 /** Instruction Header */ 483 struct octeon_instr_ih2 { 484 #ifdef __BIG_ENDIAN_BITFIELD 485 /** Raw mode indicator 1 = RAW */ 486 u64 raw:1; 487 488 /** Gather indicator 1=gather*/ 489 u64 gather:1; 490 491 /** Data length OR no. of entries in gather list */ 492 u64 dlengsz:14; 493 494 /** Front Data size */ 495 u64 fsz:6; 496 497 /** Packet Order / Work Unit selection (1 of 8)*/ 498 u64 qos:3; 499 500 /** Core group selection (1 of 16) */ 501 u64 grp:4; 502 503 /** Short Raw Packet Indicator 1=short raw pkt */ 504 u64 rs:1; 505 506 /** Tag type */ 507 u64 tagtype:2; 508 509 /** Tag Value */ 510 u64 tag:32; 511 #else 512 /** Tag Value */ 513 u64 tag:32; 514 515 /** Tag type */ 516 u64 tagtype:2; 517 518 /** Short Raw Packet Indicator 1=short raw pkt */ 519 u64 rs:1; 520 521 /** Core group selection (1 of 16) */ 522 u64 grp:4; 523 524 /** Packet Order / Work Unit selection (1 of 8)*/ 525 u64 qos:3; 526 527 /** Front Data size */ 528 u64 fsz:6; 529 530 /** Data length OR no. of entries in gather list */ 531 u64 dlengsz:14; 532 533 /** Gather indicator 1=gather*/ 534 u64 gather:1; 535 536 /** Raw mode indicator 1 = RAW */ 537 u64 raw:1; 538 #endif 539 }; 540 541 /** Input Request Header */ 542 struct octeon_instr_irh { 543 #ifdef __BIG_ENDIAN_BITFIELD 544 u64 opcode:4; 545 u64 rflag:1; 546 u64 subcode:7; 547 u64 vlan:12; 548 u64 priority:3; 549 u64 reserved:5; 550 u64 ossp:32; /* opcode/subcode specific parameters */ 551 #else 552 u64 ossp:32; /* opcode/subcode specific parameters */ 553 u64 reserved:5; 554 u64 priority:3; 555 u64 vlan:12; 556 u64 subcode:7; 557 u64 rflag:1; 558 u64 opcode:4; 559 #endif 560 }; 561 562 /** Return Data Parameters */ 563 struct octeon_instr_rdp { 564 #ifdef __BIG_ENDIAN_BITFIELD 565 u64 reserved:49; 566 u64 pcie_port:3; 567 u64 rlen:12; 568 #else 569 u64 rlen:12; 570 u64 pcie_port:3; 571 u64 reserved:49; 572 #endif 573 }; 574 575 /** Receive Header */ 576 union octeon_rh { 577 #ifdef __BIG_ENDIAN_BITFIELD 578 u64 u64; 579 struct { 580 u64 opcode:4; 581 u64 subcode:8; 582 u64 len:3; /** additional 64-bit words */ 583 u64 reserved:17; 584 u64 ossp:32; /** opcode/subcode specific parameters */ 585 } r; 586 struct { 587 u64 opcode:4; 588 u64 subcode:8; 589 u64 len:3; /** additional 64-bit words */ 590 u64 extra:28; 591 u64 vlan:12; 592 u64 priority:3; 593 u64 csum_verified:3; /** checksum verified. */ 594 u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 595 u64 encap_on:1; 596 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 597 } r_dh; 598 struct { 599 u64 opcode:4; 600 u64 subcode:8; 601 u64 len:3; /** additional 64-bit words */ 602 u64 reserved:11; 603 u64 num_gmx_ports:8; 604 u64 max_nic_ports:10; 605 u64 app_cap_flags:4; 606 u64 app_mode:8; 607 u64 pkind:8; 608 } r_core_drv_init; 609 struct { 610 u64 opcode:4; 611 u64 subcode:8; 612 u64 len:3; /** additional 64-bit words */ 613 u64 reserved:8; 614 u64 extra:25; 615 u64 gmxport:16; 616 } r_nic_info; 617 #else 618 u64 u64; 619 struct { 620 u64 ossp:32; /** opcode/subcode specific parameters */ 621 u64 reserved:17; 622 u64 len:3; /** additional 64-bit words */ 623 u64 subcode:8; 624 u64 opcode:4; 625 } r; 626 struct { 627 u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 628 u64 encap_on:1; 629 u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 630 u64 csum_verified:3; /** checksum verified. */ 631 u64 priority:3; 632 u64 vlan:12; 633 u64 extra:28; 634 u64 len:3; /** additional 64-bit words */ 635 u64 subcode:8; 636 u64 opcode:4; 637 } r_dh; 638 struct { 639 u64 pkind:8; 640 u64 app_mode:8; 641 u64 app_cap_flags:4; 642 u64 max_nic_ports:10; 643 u64 num_gmx_ports:8; 644 u64 reserved:11; 645 u64 len:3; /** additional 64-bit words */ 646 u64 subcode:8; 647 u64 opcode:4; 648 } r_core_drv_init; 649 struct { 650 u64 gmxport:16; 651 u64 extra:25; 652 u64 reserved:8; 653 u64 len:3; /** additional 64-bit words */ 654 u64 subcode:8; 655 u64 opcode:4; 656 } r_nic_info; 657 #endif 658 }; 659 660 #define OCT_RH_SIZE (sizeof(union octeon_rh)) 661 662 union octnic_packet_params { 663 u32 u32; 664 struct { 665 #ifdef __BIG_ENDIAN_BITFIELD 666 u32 reserved:24; 667 u32 ip_csum:1; /* Perform IP header checksum(s) */ 668 /* Perform Outer transport header checksum */ 669 u32 transport_csum:1; 670 /* Find tunnel, and perform transport csum. */ 671 u32 tnl_csum:1; 672 u32 tsflag:1; /* Timestamp this packet */ 673 u32 ipsec_ops:4; /* IPsec operation */ 674 #else 675 u32 ipsec_ops:4; 676 u32 tsflag:1; 677 u32 tnl_csum:1; 678 u32 transport_csum:1; 679 u32 ip_csum:1; 680 u32 reserved:24; 681 #endif 682 } s; 683 }; 684 685 /** Status of a RGMII Link on Octeon as seen by core driver. */ 686 union oct_link_status { 687 u64 u64; 688 689 struct { 690 #ifdef __BIG_ENDIAN_BITFIELD 691 u64 duplex:8; 692 u64 mtu:16; 693 u64 speed:16; 694 u64 link_up:1; 695 u64 autoneg:1; 696 u64 if_mode:5; 697 u64 pause:1; 698 u64 flashing:1; 699 u64 phy_type:5; 700 u64 reserved:10; 701 #else 702 u64 reserved:10; 703 u64 phy_type:5; 704 u64 flashing:1; 705 u64 pause:1; 706 u64 if_mode:5; 707 u64 autoneg:1; 708 u64 link_up:1; 709 u64 speed:16; 710 u64 mtu:16; 711 u64 duplex:8; 712 #endif 713 } s; 714 }; 715 716 enum lio_phy_type { 717 LIO_PHY_PORT_TP = 0x0, 718 LIO_PHY_PORT_FIBRE = 0x1, 719 LIO_PHY_PORT_UNKNOWN, 720 }; 721 722 /** The txpciq info passed to host from the firmware */ 723 724 union oct_txpciq { 725 u64 u64; 726 727 struct { 728 #ifdef __BIG_ENDIAN_BITFIELD 729 u64 q_no:8; 730 u64 port:8; 731 u64 pkind:6; 732 u64 use_qpg:1; 733 u64 qpg:11; 734 u64 reserved0:10; 735 u64 ctrl_qpg:11; 736 u64 reserved:9; 737 #else 738 u64 reserved:9; 739 u64 ctrl_qpg:11; 740 u64 reserved0:10; 741 u64 qpg:11; 742 u64 use_qpg:1; 743 u64 pkind:6; 744 u64 port:8; 745 u64 q_no:8; 746 #endif 747 } s; 748 }; 749 750 /** The rxpciq info passed to host from the firmware */ 751 752 union oct_rxpciq { 753 u64 u64; 754 755 struct { 756 #ifdef __BIG_ENDIAN_BITFIELD 757 u64 q_no:8; 758 u64 reserved:56; 759 #else 760 u64 reserved:56; 761 u64 q_no:8; 762 #endif 763 } s; 764 }; 765 766 /** Information for a OCTEON ethernet interface shared between core & host. */ 767 struct oct_link_info { 768 union oct_link_status link; 769 u64 hw_addr; 770 771 #ifdef __BIG_ENDIAN_BITFIELD 772 u64 gmxport:16; 773 u64 macaddr_is_admin_asgnd:1; 774 u64 rsvd:13; 775 u64 macaddr_spoofchk:1; 776 u64 rsvd1:17; 777 u64 num_txpciq:8; 778 u64 num_rxpciq:8; 779 #else 780 u64 num_rxpciq:8; 781 u64 num_txpciq:8; 782 u64 rsvd1:17; 783 u64 macaddr_spoofchk:1; 784 u64 rsvd:13; 785 u64 macaddr_is_admin_asgnd:1; 786 u64 gmxport:16; 787 #endif 788 789 union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 790 union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 791 }; 792 793 #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 794 795 struct liquidio_if_cfg_info { 796 u64 iqmask; /** mask for IQs enabled for the port */ 797 u64 oqmask; /** mask for OQs enabled for the port */ 798 struct oct_link_info linfo; /** initial link information */ 799 char liquidio_firmware_version[32]; 800 }; 801 802 /** Stats for each NIC port in RX direction. */ 803 struct nic_rx_stats { 804 /* link-level stats */ 805 u64 total_rcvd; /* Received packets */ 806 u64 bytes_rcvd; /* Octets of received packets */ 807 u64 total_bcst; /* Number of non-dropped L2 broadcast packets */ 808 u64 total_mcst; /* Number of non-dropped L2 multicast packets */ 809 u64 runts; /* Packets shorter than allowed */ 810 u64 ctl_rcvd; /* Received PAUSE packets */ 811 u64 fifo_err; /* Packets dropped due to RX FIFO full */ 812 u64 dmac_drop; /* Packets dropped by the DMAC filter */ 813 u64 fcs_err; /* Sum of fragment, overrun, and FCS errors */ 814 u64 jabber_err; /* Packets larger than allowed */ 815 u64 l2_err; /* Sum of DMA, parity, PCAM access, no memory, 816 * buffer overflow, malformed L2 header or 817 * length, oversize errors 818 **/ 819 u64 frame_err; /* Sum of IPv4 and L4 checksum errors */ 820 u64 red_drops; /* Packets dropped by RED due to buffer 821 * exhaustion 822 **/ 823 824 /* firmware stats */ 825 u64 fw_total_rcvd; 826 u64 fw_total_fwd; 827 u64 fw_total_fwd_bytes; 828 u64 fw_total_mcast; 829 u64 fw_total_bcast; 830 831 u64 fw_err_pko; 832 u64 fw_err_link; 833 u64 fw_err_drop; 834 u64 fw_rx_vxlan; 835 u64 fw_rx_vxlan_err; 836 837 /* LRO */ 838 u64 fw_lro_pkts; /* Number of packets that are LROed */ 839 u64 fw_lro_octs; /* Number of octets that are LROed */ 840 u64 fw_total_lro; /* Number of LRO packets formed */ 841 u64 fw_lro_aborts; /* Number of times LRO of packet aborted */ 842 u64 fw_lro_aborts_port; 843 u64 fw_lro_aborts_seq; 844 u64 fw_lro_aborts_tsval; 845 u64 fw_lro_aborts_timer; /* Timer setting error */ 846 /* intrmod: packet forward rate */ 847 u64 fwd_rate; 848 }; 849 850 /** Stats for each NIC port in RX direction. */ 851 struct nic_tx_stats { 852 /* link-level stats */ 853 u64 total_pkts_sent; /* Total frames sent on the interface */ 854 u64 total_bytes_sent; /* Total octets sent on the interface */ 855 u64 mcast_pkts_sent; /* Packets sent to the multicast DMAC */ 856 u64 bcast_pkts_sent; /* Packets sent to a broadcast DMAC */ 857 u64 ctl_sent; /* Control/PAUSE packets sent */ 858 u64 one_collision_sent; /* Packets sent that experienced a 859 * single collision before successful 860 * transmission 861 **/ 862 u64 multi_collision_sent; /* Packets sent that experienced 863 * multiple collisions before successful 864 * transmission 865 **/ 866 u64 max_collision_fail; /* Packets dropped due to excessive 867 * collisions 868 **/ 869 u64 max_deferral_fail; /* Packets not sent due to max 870 * deferrals 871 **/ 872 u64 fifo_err; /* Packets sent that experienced a 873 * transmit underflow and were 874 * truncated 875 **/ 876 u64 runts; /* Packets sent with an octet count 877 * lessthan 64 878 **/ 879 u64 total_collisions; /* Packets dropped due to excessive 880 * collisions 881 **/ 882 883 /* firmware stats */ 884 u64 fw_total_sent; 885 u64 fw_total_fwd; 886 u64 fw_total_fwd_bytes; 887 u64 fw_total_mcast_sent; 888 u64 fw_total_bcast_sent; 889 u64 fw_err_pko; 890 u64 fw_err_link; 891 u64 fw_err_drop; 892 u64 fw_err_tso; 893 u64 fw_tso; /* number of tso requests */ 894 u64 fw_tso_fwd; /* number of packets segmented in tso */ 895 u64 fw_tx_vxlan; 896 u64 fw_err_pki; 897 }; 898 899 struct oct_link_stats { 900 struct nic_rx_stats fromwire; 901 struct nic_tx_stats fromhost; 902 903 }; 904 905 static inline int opcode_slow_path(union octeon_rh *rh) 906 { 907 u16 subcode1, subcode2; 908 909 subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 910 subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 911 912 return (subcode2 != subcode1); 913 } 914 915 #define LIO68XX_LED_CTRL_ADDR 0x3501 916 #define LIO68XX_LED_CTRL_CFGON 0x1f 917 #define LIO68XX_LED_CTRL_CFGOFF 0x100 918 #define LIO68XX_LED_BEACON_ADDR 0x3508 919 #define LIO68XX_LED_BEACON_CFGON 0x47fd 920 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 921 #define VITESSE_PHY_GPIO_DRIVEON 0x1 922 #define VITESSE_PHY_GPIO_CFG 0x8 923 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 924 #define VITESSE_PHY_GPIO_HIGH 0x2 925 #define VITESSE_PHY_GPIO_LOW 0x3 926 #define LED_IDENTIFICATION_ON 0x1 927 #define LED_IDENTIFICATION_OFF 0x0 928 #define LIO23XX_COPPERHEAD_LED_GPIO 0x2 929 930 struct oct_mdio_cmd { 931 u64 op; 932 u64 mdio_addr; 933 u64 value1; 934 u64 value2; 935 u64 value3; 936 }; 937 938 #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 939 940 struct oct_intrmod_cfg { 941 u64 rx_enable; 942 u64 tx_enable; 943 u64 check_intrvl; 944 u64 maxpkt_ratethr; 945 u64 minpkt_ratethr; 946 u64 rx_maxcnt_trigger; 947 u64 rx_mincnt_trigger; 948 u64 rx_maxtmr_trigger; 949 u64 rx_mintmr_trigger; 950 u64 tx_mincnt_trigger; 951 u64 tx_maxcnt_trigger; 952 u64 rx_frames; 953 u64 tx_frames; 954 u64 rx_usecs; 955 }; 956 957 #define BASE_QUEUE_NOT_REQUESTED 65535 958 959 union oct_nic_if_cfg { 960 u64 u64; 961 struct { 962 #ifdef __BIG_ENDIAN_BITFIELD 963 u64 base_queue:16; 964 u64 num_iqueues:16; 965 u64 num_oqueues:16; 966 u64 gmx_port_id:8; 967 u64 vf_id:8; 968 #else 969 u64 vf_id:8; 970 u64 gmx_port_id:8; 971 u64 num_oqueues:16; 972 u64 num_iqueues:16; 973 u64 base_queue:16; 974 #endif 975 } s; 976 }; 977 978 struct lio_trusted_vf { 979 uint64_t active: 1; 980 uint64_t id : 8; 981 uint64_t reserved: 55; 982 }; 983 984 struct lio_time { 985 s64 sec; /* seconds */ 986 s64 nsec; /* nanoseconds */ 987 }; 988 989 struct lio_vf_rep_stats { 990 u64 tx_packets; 991 u64 tx_bytes; 992 u64 tx_dropped; 993 994 u64 rx_packets; 995 u64 rx_bytes; 996 u64 rx_dropped; 997 }; 998 999 enum lio_vf_rep_req_type { 1000 LIO_VF_REP_REQ_NONE, 1001 LIO_VF_REP_REQ_STATE, 1002 LIO_VF_REP_REQ_MTU, 1003 LIO_VF_REP_REQ_STATS, 1004 LIO_VF_REP_REQ_DEVNAME 1005 }; 1006 1007 enum { 1008 LIO_VF_REP_STATE_DOWN, 1009 LIO_VF_REP_STATE_UP 1010 }; 1011 1012 #define LIO_IF_NAME_SIZE 16 1013 struct lio_vf_rep_req { 1014 u8 req_type; 1015 u8 ifidx; 1016 u8 rsvd[6]; 1017 1018 union { 1019 struct lio_vf_rep_name { 1020 char name[LIO_IF_NAME_SIZE]; 1021 } rep_name; 1022 1023 struct lio_vf_rep_mtu { 1024 u32 mtu; 1025 u32 rsvd; 1026 } rep_mtu; 1027 1028 struct lio_vf_rep_state { 1029 u8 state; 1030 u8 rsvd[7]; 1031 } rep_state; 1032 }; 1033 }; 1034 1035 struct lio_vf_rep_resp { 1036 u64 rh; 1037 u8 status; 1038 u8 rsvd[7]; 1039 }; 1040 #endif 1041