1f21fb3edSRaghu Vatsavayi /********************************************************************** 2f21fb3edSRaghu Vatsavayi * Author: Cavium, Inc. 3f21fb3edSRaghu Vatsavayi * 4f21fb3edSRaghu Vatsavayi * Contact: support@cavium.com 5f21fb3edSRaghu Vatsavayi * Please include "LiquidIO" in the subject. 6f21fb3edSRaghu Vatsavayi * 7f21fb3edSRaghu Vatsavayi * Copyright (c) 2003-2015 Cavium, Inc. 8f21fb3edSRaghu Vatsavayi * 9f21fb3edSRaghu Vatsavayi * This file is free software; you can redistribute it and/or modify 10f21fb3edSRaghu Vatsavayi * it under the terms of the GNU General Public License, Version 2, as 11f21fb3edSRaghu Vatsavayi * published by the Free Software Foundation. 12f21fb3edSRaghu Vatsavayi * 13f21fb3edSRaghu Vatsavayi * This file is distributed in the hope that it will be useful, but 14f21fb3edSRaghu Vatsavayi * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15f21fb3edSRaghu Vatsavayi * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16f21fb3edSRaghu Vatsavayi * NONINFRINGEMENT. See the GNU General Public License for more 17f21fb3edSRaghu Vatsavayi * details. 18f21fb3edSRaghu Vatsavayi * 19f21fb3edSRaghu Vatsavayi * This file may also be available under a different license from Cavium. 20f21fb3edSRaghu Vatsavayi * Contact Cavium, Inc. for more information 21f21fb3edSRaghu Vatsavayi **********************************************************************/ 22f21fb3edSRaghu Vatsavayi 23f21fb3edSRaghu Vatsavayi /*! \file liquidio_common.h 24f21fb3edSRaghu Vatsavayi * \brief Common: Structures and macros used in PCI-NIC package by core and 25f21fb3edSRaghu Vatsavayi * host driver. 26f21fb3edSRaghu Vatsavayi */ 27f21fb3edSRaghu Vatsavayi 28f21fb3edSRaghu Vatsavayi #ifndef __LIQUIDIO_COMMON_H__ 29f21fb3edSRaghu Vatsavayi #define __LIQUIDIO_COMMON_H__ 30f21fb3edSRaghu Vatsavayi 31f21fb3edSRaghu Vatsavayi #include "octeon_config.h" 32f21fb3edSRaghu Vatsavayi 33d3d7e6c6SRaghu Vatsavayi #define LIQUIDIO_BASE_VERSION "1.4" 34d3d7e6c6SRaghu Vatsavayi #define LIQUIDIO_MICRO_VERSION ".1" 35d3d7e6c6SRaghu Vatsavayi #define LIQUIDIO_PACKAGE "" 36d3d7e6c6SRaghu Vatsavayi #define LIQUIDIO_VERSION "1.4.1" 37f21fb3edSRaghu Vatsavayi #define CONTROL_IQ 0 38f21fb3edSRaghu Vatsavayi /** Tag types used by Octeon cores in its work. */ 39f21fb3edSRaghu Vatsavayi enum octeon_tag_type { 40f21fb3edSRaghu Vatsavayi ORDERED_TAG = 0, 41f21fb3edSRaghu Vatsavayi ATOMIC_TAG = 1, 42f21fb3edSRaghu Vatsavayi NULL_TAG = 2, 43f21fb3edSRaghu Vatsavayi NULL_NULL_TAG = 3 44f21fb3edSRaghu Vatsavayi }; 45f21fb3edSRaghu Vatsavayi 46f21fb3edSRaghu Vatsavayi /* pre-defined host->NIC tag values */ 47f21fb3edSRaghu Vatsavayi #define LIO_CONTROL (0x11111110) 48f21fb3edSRaghu Vatsavayi #define LIO_DATA(i) (0x11111111 + (i)) 49f21fb3edSRaghu Vatsavayi 50f21fb3edSRaghu Vatsavayi /* Opcodes used by host driver/apps to perform operations on the core. 51f21fb3edSRaghu Vatsavayi * These are used to identify the major subsystem that the operation 52f21fb3edSRaghu Vatsavayi * is for. 53f21fb3edSRaghu Vatsavayi */ 54f21fb3edSRaghu Vatsavayi #define OPCODE_CORE 0 /* used for generic core operations */ 55f21fb3edSRaghu Vatsavayi #define OPCODE_NIC 1 /* used for NIC operations */ 56f21fb3edSRaghu Vatsavayi #define OPCODE_LAST OPCODE_NIC 57f21fb3edSRaghu Vatsavayi 58f21fb3edSRaghu Vatsavayi /* Subcodes are used by host driver/apps to identify the sub-operation 59f21fb3edSRaghu Vatsavayi * for the core. They only need to by unique for a given subsystem. 60f21fb3edSRaghu Vatsavayi */ 61f21fb3edSRaghu Vatsavayi #define OPCODE_SUBCODE(op, sub) (((op & 0x0f) << 8) | ((sub) & 0x7f)) 62f21fb3edSRaghu Vatsavayi 63f21fb3edSRaghu Vatsavayi /** OPCODE_CORE subcodes. For future use. */ 64f21fb3edSRaghu Vatsavayi 65f21fb3edSRaghu Vatsavayi /** OPCODE_NIC subcodes */ 66f21fb3edSRaghu Vatsavayi 67f21fb3edSRaghu Vatsavayi /* This subcode is sent by core PCI driver to indicate cores are ready. */ 68f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 69f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 70f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_CMD 0x03 71f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_INFO 0x04 72f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_PORT_STATS 0x05 73f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_MDIO45 0x06 74f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_TIMESTAMP 0x07 75f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_INTRMOD_CFG 0x08 76f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_IF_CFG 0x09 77f21fb3edSRaghu Vatsavayi 78f21fb3edSRaghu Vatsavayi #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 79f21fb3edSRaghu Vatsavayi 80f21fb3edSRaghu Vatsavayi #define OPCODE_SLOW_PATH(rh) \ 81f21fb3edSRaghu Vatsavayi (OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \ 82f21fb3edSRaghu Vatsavayi OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA)) 83f21fb3edSRaghu Vatsavayi 84f21fb3edSRaghu Vatsavayi /* Application codes advertised by the core driver initialization packet. */ 85f21fb3edSRaghu Vatsavayi #define CVM_DRV_APP_START 0x0 86f21fb3edSRaghu Vatsavayi #define CVM_DRV_NO_APP 0 87f21fb3edSRaghu Vatsavayi #define CVM_DRV_APP_COUNT 0x2 88f21fb3edSRaghu Vatsavayi #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 89f21fb3edSRaghu Vatsavayi #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 90f21fb3edSRaghu Vatsavayi #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 91f21fb3edSRaghu Vatsavayi #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 92f21fb3edSRaghu Vatsavayi 93f21fb3edSRaghu Vatsavayi /* Macro to increment index. 94f21fb3edSRaghu Vatsavayi * Index is incremented by count; if the sum exceeds 95f21fb3edSRaghu Vatsavayi * max, index is wrapped-around to the start. 96f21fb3edSRaghu Vatsavayi */ 97f21fb3edSRaghu Vatsavayi #define INCR_INDEX(index, count, max) \ 98f21fb3edSRaghu Vatsavayi do { \ 99f21fb3edSRaghu Vatsavayi if (((index) + (count)) >= (max)) \ 100f21fb3edSRaghu Vatsavayi index = ((index) + (count)) - (max); \ 101f21fb3edSRaghu Vatsavayi else \ 102f21fb3edSRaghu Vatsavayi index += (count); \ 103f21fb3edSRaghu Vatsavayi } while (0) 104f21fb3edSRaghu Vatsavayi 105f21fb3edSRaghu Vatsavayi #define INCR_INDEX_BY1(index, max) \ 106f21fb3edSRaghu Vatsavayi do { \ 107f21fb3edSRaghu Vatsavayi if ((++(index)) == (max)) \ 108f21fb3edSRaghu Vatsavayi index = 0; \ 109f21fb3edSRaghu Vatsavayi } while (0) 110f21fb3edSRaghu Vatsavayi 111f21fb3edSRaghu Vatsavayi #define DECR_INDEX(index, count, max) \ 112f21fb3edSRaghu Vatsavayi do { \ 113f21fb3edSRaghu Vatsavayi if ((count) > (index)) \ 114f21fb3edSRaghu Vatsavayi index = ((max) - ((count - index))); \ 115f21fb3edSRaghu Vatsavayi else \ 116f21fb3edSRaghu Vatsavayi index -= count; \ 117f21fb3edSRaghu Vatsavayi } while (0) 118f21fb3edSRaghu Vatsavayi 119f21fb3edSRaghu Vatsavayi #define OCT_BOARD_NAME 32 120f21fb3edSRaghu Vatsavayi #define OCT_SERIAL_LEN 64 121f21fb3edSRaghu Vatsavayi 122f21fb3edSRaghu Vatsavayi /* Structure used by core driver to send indication that the Octeon 123f21fb3edSRaghu Vatsavayi * application is ready. 124f21fb3edSRaghu Vatsavayi */ 125f21fb3edSRaghu Vatsavayi struct octeon_core_setup { 126f21fb3edSRaghu Vatsavayi u64 corefreq; 127f21fb3edSRaghu Vatsavayi 128f21fb3edSRaghu Vatsavayi char boardname[OCT_BOARD_NAME]; 129f21fb3edSRaghu Vatsavayi 130f21fb3edSRaghu Vatsavayi char board_serial_number[OCT_SERIAL_LEN]; 131f21fb3edSRaghu Vatsavayi 132f21fb3edSRaghu Vatsavayi u64 board_rev_major; 133f21fb3edSRaghu Vatsavayi 134f21fb3edSRaghu Vatsavayi u64 board_rev_minor; 135f21fb3edSRaghu Vatsavayi 136f21fb3edSRaghu Vatsavayi }; 137f21fb3edSRaghu Vatsavayi 138f21fb3edSRaghu Vatsavayi /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 139f21fb3edSRaghu Vatsavayi 140f21fb3edSRaghu Vatsavayi /* The Scatter-Gather List Entry. The scatter or gather component used with 141f21fb3edSRaghu Vatsavayi * a Octeon input instruction has this format. 142f21fb3edSRaghu Vatsavayi */ 143f21fb3edSRaghu Vatsavayi struct octeon_sg_entry { 144f21fb3edSRaghu Vatsavayi /** The first 64 bit gives the size of data in each dptr.*/ 145f21fb3edSRaghu Vatsavayi union { 146f21fb3edSRaghu Vatsavayi u16 size[4]; 147f21fb3edSRaghu Vatsavayi u64 size64; 148f21fb3edSRaghu Vatsavayi } u; 149f21fb3edSRaghu Vatsavayi 150f21fb3edSRaghu Vatsavayi /** The 4 dptr pointers for this entry. */ 151f21fb3edSRaghu Vatsavayi u64 ptr[4]; 152f21fb3edSRaghu Vatsavayi 153f21fb3edSRaghu Vatsavayi }; 154f21fb3edSRaghu Vatsavayi 155f21fb3edSRaghu Vatsavayi #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 156f21fb3edSRaghu Vatsavayi 157f21fb3edSRaghu Vatsavayi /* \brief Add size to gather list 158f21fb3edSRaghu Vatsavayi * @param sg_entry scatter/gather entry 159f21fb3edSRaghu Vatsavayi * @param size size to add 160f21fb3edSRaghu Vatsavayi * @param pos position to add it. 161f21fb3edSRaghu Vatsavayi */ 162f21fb3edSRaghu Vatsavayi static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 163f21fb3edSRaghu Vatsavayi u16 size, 164f21fb3edSRaghu Vatsavayi u32 pos) 165f21fb3edSRaghu Vatsavayi { 166f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 167f21fb3edSRaghu Vatsavayi sg_entry->u.size[pos] = size; 168f21fb3edSRaghu Vatsavayi #else 169f21fb3edSRaghu Vatsavayi sg_entry->u.size[3 - pos] = size; 170f21fb3edSRaghu Vatsavayi #endif 171f21fb3edSRaghu Vatsavayi } 172f21fb3edSRaghu Vatsavayi 173f21fb3edSRaghu Vatsavayi /*------------------------- End Scatter/Gather ---------------------------*/ 174f21fb3edSRaghu Vatsavayi 175f21fb3edSRaghu Vatsavayi #define OCTNET_FRM_PTP_HEADER_SIZE 8 176f21fb3edSRaghu Vatsavayi 177a5b37888SRaghu Vatsavayi #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 178a5b37888SRaghu Vatsavayi 179a5b37888SRaghu Vatsavayi #define OCTNET_MIN_FRM_SIZE 64 180a5b37888SRaghu Vatsavayi 181f21fb3edSRaghu Vatsavayi #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 182f21fb3edSRaghu Vatsavayi 183f21fb3edSRaghu Vatsavayi #define OCTNET_DEFAULT_FRM_SIZE (1500 + OCTNET_FRM_HEADER_SIZE) 184f21fb3edSRaghu Vatsavayi 185f21fb3edSRaghu Vatsavayi /** NIC Commands are sent using this Octeon Input Queue */ 186f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_Q 0 187f21fb3edSRaghu Vatsavayi 188f21fb3edSRaghu Vatsavayi /* NIC Command types */ 189f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CHANGE_MTU 0x1 190f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CHANGE_MACADDR 0x2 191f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 192f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_RX_CTL 0x4 193f21fb3edSRaghu Vatsavayi 194f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_MULTI_LIST 0x5 195f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CLEAR_STATS 0x6 196f21fb3edSRaghu Vatsavayi 197f21fb3edSRaghu Vatsavayi /* command for setting the speed, duplex & autoneg */ 198f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_SETTINGS 0x7 199f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_FLOW_CTL 0x8 200f21fb3edSRaghu Vatsavayi 201f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_MDIO_READ_WRITE 0x9 202f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_GPIO_ACCESS 0xA 203f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_LRO_ENABLE 0xB 204f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_LRO_DISABLE 0xC 205f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_RSS 0xD 206f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_WRITE_SA 0xE 207f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_DELETE_SA 0xF 208f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_UPDATE_SA 0x12 209f21fb3edSRaghu Vatsavayi 210f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 211f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 212f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 213f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_VERBOSE_ENABLE 0x14 214f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_VERBOSE_DISABLE 0x15 215f21fb3edSRaghu Vatsavayi 21663245f25SRaghu Vatsavayi #define OCTNET_CMD_ENABLE_VLAN_FILTER 0x16 21763245f25SRaghu Vatsavayi #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 21863245f25SRaghu Vatsavayi #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 21963245f25SRaghu Vatsavayi 220f21fb3edSRaghu Vatsavayi /* RX(packets coming from wire) Checksum verification flags */ 221f21fb3edSRaghu Vatsavayi /* TCP/UDP csum */ 222f21fb3edSRaghu Vatsavayi #define CNNIC_L4SUM_VERIFIED 0x1 223f21fb3edSRaghu Vatsavayi #define CNNIC_IPSUM_VERIFIED 0x2 224f21fb3edSRaghu Vatsavayi #define CNNIC_TUN_CSUM_VERIFIED 0x4 225f21fb3edSRaghu Vatsavayi #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 226f21fb3edSRaghu Vatsavayi 227f21fb3edSRaghu Vatsavayi /*LROIPV4 and LROIPV6 Flags*/ 228f21fb3edSRaghu Vatsavayi #define OCTNIC_LROIPV4 0x1 229f21fb3edSRaghu Vatsavayi #define OCTNIC_LROIPV6 0x2 230f21fb3edSRaghu Vatsavayi 231f21fb3edSRaghu Vatsavayi /* Interface flags communicated between host driver and core app. */ 232f21fb3edSRaghu Vatsavayi enum octnet_ifflags { 233f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_PROMISC = 0x01, 234f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_ALLMULTI = 0x02, 235f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_MULTICAST = 0x04, 236f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_BROADCAST = 0x08, 237f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_UNICAST = 0x10 238f21fb3edSRaghu Vatsavayi }; 239f21fb3edSRaghu Vatsavayi 240f21fb3edSRaghu Vatsavayi /* wqe 241f21fb3edSRaghu Vatsavayi * --------------- 0 242f21fb3edSRaghu Vatsavayi * | wqe word0-3 | 243f21fb3edSRaghu Vatsavayi * --------------- 32 244f21fb3edSRaghu Vatsavayi * | PCI IH | 245f21fb3edSRaghu Vatsavayi * --------------- 40 246f21fb3edSRaghu Vatsavayi * | RPTR | 247f21fb3edSRaghu Vatsavayi * --------------- 48 248f21fb3edSRaghu Vatsavayi * | PCI IRH | 249f21fb3edSRaghu Vatsavayi * --------------- 56 250f21fb3edSRaghu Vatsavayi * | OCT_NET_CMD | 251f21fb3edSRaghu Vatsavayi * --------------- 64 252f21fb3edSRaghu Vatsavayi * | Addtl 8-BData | 253f21fb3edSRaghu Vatsavayi * | | 254f21fb3edSRaghu Vatsavayi * --------------- 255f21fb3edSRaghu Vatsavayi */ 256f21fb3edSRaghu Vatsavayi 257f21fb3edSRaghu Vatsavayi union octnet_cmd { 258f21fb3edSRaghu Vatsavayi u64 u64; 259f21fb3edSRaghu Vatsavayi 260f21fb3edSRaghu Vatsavayi struct { 261f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 262f21fb3edSRaghu Vatsavayi u64 cmd:5; 263f21fb3edSRaghu Vatsavayi 264f21fb3edSRaghu Vatsavayi u64 more:6; /* How many udd words follow the command */ 265f21fb3edSRaghu Vatsavayi 2660cece6c5SRaghu Vatsavayi u64 reserved:29; 267f21fb3edSRaghu Vatsavayi 2680cece6c5SRaghu Vatsavayi u64 param1:16; 269f21fb3edSRaghu Vatsavayi 2700cece6c5SRaghu Vatsavayi u64 param2:8; 271f21fb3edSRaghu Vatsavayi 272f21fb3edSRaghu Vatsavayi #else 273f21fb3edSRaghu Vatsavayi 2740cece6c5SRaghu Vatsavayi u64 param2:8; 275f21fb3edSRaghu Vatsavayi 2760cece6c5SRaghu Vatsavayi u64 param1:16; 277f21fb3edSRaghu Vatsavayi 2780cece6c5SRaghu Vatsavayi u64 reserved:29; 279f21fb3edSRaghu Vatsavayi 280f21fb3edSRaghu Vatsavayi u64 more:6; 281f21fb3edSRaghu Vatsavayi 282f21fb3edSRaghu Vatsavayi u64 cmd:5; 283f21fb3edSRaghu Vatsavayi 284f21fb3edSRaghu Vatsavayi #endif 285f21fb3edSRaghu Vatsavayi } s; 286f21fb3edSRaghu Vatsavayi 287f21fb3edSRaghu Vatsavayi }; 288f21fb3edSRaghu Vatsavayi 289f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 290f21fb3edSRaghu Vatsavayi 2916a885b60SRaghu Vatsavayi /* Instruction Header (DPI - CN23xx) - for OCTEON-III models */ 2926a885b60SRaghu Vatsavayi struct octeon_instr_ih3 { 2936a885b60SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 2946a885b60SRaghu Vatsavayi 2956a885b60SRaghu Vatsavayi /** Reserved3 */ 2966a885b60SRaghu Vatsavayi u64 reserved3:1; 2976a885b60SRaghu Vatsavayi 2986a885b60SRaghu Vatsavayi /** Gather indicator 1=gather*/ 2996a885b60SRaghu Vatsavayi u64 gather:1; 3006a885b60SRaghu Vatsavayi 3016a885b60SRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 3026a885b60SRaghu Vatsavayi u64 dlengsz:14; 3036a885b60SRaghu Vatsavayi 3046a885b60SRaghu Vatsavayi /** Front Data size */ 3056a885b60SRaghu Vatsavayi u64 fsz:6; 3066a885b60SRaghu Vatsavayi 3076a885b60SRaghu Vatsavayi /** Reserved2 */ 3086a885b60SRaghu Vatsavayi u64 reserved2:4; 3096a885b60SRaghu Vatsavayi 3106a885b60SRaghu Vatsavayi /** PKI port kind - PKIND */ 3116a885b60SRaghu Vatsavayi u64 pkind:6; 3126a885b60SRaghu Vatsavayi 3136a885b60SRaghu Vatsavayi /** Reserved1 */ 3146a885b60SRaghu Vatsavayi u64 reserved1:32; 3156a885b60SRaghu Vatsavayi 3166a885b60SRaghu Vatsavayi #else 3176a885b60SRaghu Vatsavayi /** Reserved1 */ 3186a885b60SRaghu Vatsavayi u64 reserved1:32; 3196a885b60SRaghu Vatsavayi 3206a885b60SRaghu Vatsavayi /** PKI port kind - PKIND */ 3216a885b60SRaghu Vatsavayi u64 pkind:6; 3226a885b60SRaghu Vatsavayi 3236a885b60SRaghu Vatsavayi /** Reserved2 */ 3246a885b60SRaghu Vatsavayi u64 reserved2:4; 3256a885b60SRaghu Vatsavayi 3266a885b60SRaghu Vatsavayi /** Front Data size */ 3276a885b60SRaghu Vatsavayi u64 fsz:6; 3286a885b60SRaghu Vatsavayi 3296a885b60SRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 3306a885b60SRaghu Vatsavayi u64 dlengsz:14; 3316a885b60SRaghu Vatsavayi 3326a885b60SRaghu Vatsavayi /** Gather indicator 1=gather*/ 3336a885b60SRaghu Vatsavayi u64 gather:1; 3346a885b60SRaghu Vatsavayi 3356a885b60SRaghu Vatsavayi /** Reserved3 */ 3366a885b60SRaghu Vatsavayi u64 reserved3:1; 3376a885b60SRaghu Vatsavayi 3386a885b60SRaghu Vatsavayi #endif 3396a885b60SRaghu Vatsavayi }; 3406a885b60SRaghu Vatsavayi 3416a885b60SRaghu Vatsavayi /* Optional PKI Instruction Header(PKI IH) - for OCTEON CN23XX models */ 3426a885b60SRaghu Vatsavayi /** BIG ENDIAN format. */ 3436a885b60SRaghu Vatsavayi struct octeon_instr_pki_ih3 { 3446a885b60SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 3456a885b60SRaghu Vatsavayi 3466a885b60SRaghu Vatsavayi /** Wider bit */ 3476a885b60SRaghu Vatsavayi u64 w:1; 3486a885b60SRaghu Vatsavayi 3496a885b60SRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 3506a885b60SRaghu Vatsavayi u64 raw:1; 3516a885b60SRaghu Vatsavayi 3526a885b60SRaghu Vatsavayi /** Use Tag */ 3536a885b60SRaghu Vatsavayi u64 utag:1; 3546a885b60SRaghu Vatsavayi 3556a885b60SRaghu Vatsavayi /** Use QPG */ 3566a885b60SRaghu Vatsavayi u64 uqpg:1; 3576a885b60SRaghu Vatsavayi 3586a885b60SRaghu Vatsavayi /** Reserved2 */ 3596a885b60SRaghu Vatsavayi u64 reserved2:1; 3606a885b60SRaghu Vatsavayi 3616a885b60SRaghu Vatsavayi /** Parse Mode */ 3626a885b60SRaghu Vatsavayi u64 pm:3; 3636a885b60SRaghu Vatsavayi 3646a885b60SRaghu Vatsavayi /** Skip Length */ 3656a885b60SRaghu Vatsavayi u64 sl:8; 3666a885b60SRaghu Vatsavayi 3676a885b60SRaghu Vatsavayi /** Use Tag Type */ 3686a885b60SRaghu Vatsavayi u64 utt:1; 3696a885b60SRaghu Vatsavayi 3706a885b60SRaghu Vatsavayi /** Tag type */ 3716a885b60SRaghu Vatsavayi u64 tagtype:2; 3726a885b60SRaghu Vatsavayi 3736a885b60SRaghu Vatsavayi /** Reserved1 */ 3746a885b60SRaghu Vatsavayi u64 reserved1:2; 3756a885b60SRaghu Vatsavayi 3766a885b60SRaghu Vatsavayi /** QPG Value */ 3776a885b60SRaghu Vatsavayi u64 qpg:11; 3786a885b60SRaghu Vatsavayi 3796a885b60SRaghu Vatsavayi /** Tag Value */ 3806a885b60SRaghu Vatsavayi u64 tag:32; 3816a885b60SRaghu Vatsavayi 3826a885b60SRaghu Vatsavayi #else 3836a885b60SRaghu Vatsavayi 3846a885b60SRaghu Vatsavayi /** Tag Value */ 3856a885b60SRaghu Vatsavayi u64 tag:32; 3866a885b60SRaghu Vatsavayi 3876a885b60SRaghu Vatsavayi /** QPG Value */ 3886a885b60SRaghu Vatsavayi u64 qpg:11; 3896a885b60SRaghu Vatsavayi 3906a885b60SRaghu Vatsavayi /** Reserved1 */ 3916a885b60SRaghu Vatsavayi u64 reserved1:2; 3926a885b60SRaghu Vatsavayi 3936a885b60SRaghu Vatsavayi /** Tag type */ 3946a885b60SRaghu Vatsavayi u64 tagtype:2; 3956a885b60SRaghu Vatsavayi 3966a885b60SRaghu Vatsavayi /** Use Tag Type */ 3976a885b60SRaghu Vatsavayi u64 utt:1; 3986a885b60SRaghu Vatsavayi 3996a885b60SRaghu Vatsavayi /** Skip Length */ 4006a885b60SRaghu Vatsavayi u64 sl:8; 4016a885b60SRaghu Vatsavayi 4026a885b60SRaghu Vatsavayi /** Parse Mode */ 4036a885b60SRaghu Vatsavayi u64 pm:3; 4046a885b60SRaghu Vatsavayi 4056a885b60SRaghu Vatsavayi /** Reserved2 */ 4066a885b60SRaghu Vatsavayi u64 reserved2:1; 4076a885b60SRaghu Vatsavayi 4086a885b60SRaghu Vatsavayi /** Use QPG */ 4096a885b60SRaghu Vatsavayi u64 uqpg:1; 4106a885b60SRaghu Vatsavayi 4116a885b60SRaghu Vatsavayi /** Use Tag */ 4126a885b60SRaghu Vatsavayi u64 utag:1; 4136a885b60SRaghu Vatsavayi 4146a885b60SRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 4156a885b60SRaghu Vatsavayi u64 raw:1; 4166a885b60SRaghu Vatsavayi 4176a885b60SRaghu Vatsavayi /** Wider bit */ 4186a885b60SRaghu Vatsavayi u64 w:1; 4196a885b60SRaghu Vatsavayi #endif 4206a885b60SRaghu Vatsavayi 4216a885b60SRaghu Vatsavayi }; 4226a885b60SRaghu Vatsavayi 423f21fb3edSRaghu Vatsavayi /** Instruction Header */ 4246a885b60SRaghu Vatsavayi struct octeon_instr_ih2 { 425f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 426f21fb3edSRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 427f21fb3edSRaghu Vatsavayi u64 raw:1; 428f21fb3edSRaghu Vatsavayi 429f21fb3edSRaghu Vatsavayi /** Gather indicator 1=gather*/ 430f21fb3edSRaghu Vatsavayi u64 gather:1; 431f21fb3edSRaghu Vatsavayi 432f21fb3edSRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 433f21fb3edSRaghu Vatsavayi u64 dlengsz:14; 434f21fb3edSRaghu Vatsavayi 435f21fb3edSRaghu Vatsavayi /** Front Data size */ 436f21fb3edSRaghu Vatsavayi u64 fsz:6; 437f21fb3edSRaghu Vatsavayi 438f21fb3edSRaghu Vatsavayi /** Packet Order / Work Unit selection (1 of 8)*/ 439f21fb3edSRaghu Vatsavayi u64 qos:3; 440f21fb3edSRaghu Vatsavayi 441f21fb3edSRaghu Vatsavayi /** Core group selection (1 of 16) */ 442f21fb3edSRaghu Vatsavayi u64 grp:4; 443f21fb3edSRaghu Vatsavayi 444f21fb3edSRaghu Vatsavayi /** Short Raw Packet Indicator 1=short raw pkt */ 445f21fb3edSRaghu Vatsavayi u64 rs:1; 446f21fb3edSRaghu Vatsavayi 447f21fb3edSRaghu Vatsavayi /** Tag type */ 448f21fb3edSRaghu Vatsavayi u64 tagtype:2; 449f21fb3edSRaghu Vatsavayi 450f21fb3edSRaghu Vatsavayi /** Tag Value */ 451f21fb3edSRaghu Vatsavayi u64 tag:32; 452f21fb3edSRaghu Vatsavayi #else 453f21fb3edSRaghu Vatsavayi /** Tag Value */ 454f21fb3edSRaghu Vatsavayi u64 tag:32; 455f21fb3edSRaghu Vatsavayi 456f21fb3edSRaghu Vatsavayi /** Tag type */ 457f21fb3edSRaghu Vatsavayi u64 tagtype:2; 458f21fb3edSRaghu Vatsavayi 459f21fb3edSRaghu Vatsavayi /** Short Raw Packet Indicator 1=short raw pkt */ 460f21fb3edSRaghu Vatsavayi u64 rs:1; 461f21fb3edSRaghu Vatsavayi 462f21fb3edSRaghu Vatsavayi /** Core group selection (1 of 16) */ 463f21fb3edSRaghu Vatsavayi u64 grp:4; 464f21fb3edSRaghu Vatsavayi 465f21fb3edSRaghu Vatsavayi /** Packet Order / Work Unit selection (1 of 8)*/ 466f21fb3edSRaghu Vatsavayi u64 qos:3; 467f21fb3edSRaghu Vatsavayi 468f21fb3edSRaghu Vatsavayi /** Front Data size */ 469f21fb3edSRaghu Vatsavayi u64 fsz:6; 470f21fb3edSRaghu Vatsavayi 471f21fb3edSRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 472f21fb3edSRaghu Vatsavayi u64 dlengsz:14; 473f21fb3edSRaghu Vatsavayi 474f21fb3edSRaghu Vatsavayi /** Gather indicator 1=gather*/ 475f21fb3edSRaghu Vatsavayi u64 gather:1; 476f21fb3edSRaghu Vatsavayi 477f21fb3edSRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 478f21fb3edSRaghu Vatsavayi u64 raw:1; 479f21fb3edSRaghu Vatsavayi #endif 480f21fb3edSRaghu Vatsavayi }; 481f21fb3edSRaghu Vatsavayi 482f21fb3edSRaghu Vatsavayi /** Input Request Header */ 483f21fb3edSRaghu Vatsavayi struct octeon_instr_irh { 484f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 485f21fb3edSRaghu Vatsavayi u64 opcode:4; 486f21fb3edSRaghu Vatsavayi u64 rflag:1; 487f21fb3edSRaghu Vatsavayi u64 subcode:7; 4880da0b77cSRaghu Vatsavayi u64 vlan:12; 4890da0b77cSRaghu Vatsavayi u64 priority:3; 4900da0b77cSRaghu Vatsavayi u64 reserved:5; 491f21fb3edSRaghu Vatsavayi u64 ossp:32; /* opcode/subcode specific parameters */ 492f21fb3edSRaghu Vatsavayi #else 493f21fb3edSRaghu Vatsavayi u64 ossp:32; /* opcode/subcode specific parameters */ 4940da0b77cSRaghu Vatsavayi u64 reserved:5; 4950da0b77cSRaghu Vatsavayi u64 priority:3; 4960da0b77cSRaghu Vatsavayi u64 vlan:12; 497f21fb3edSRaghu Vatsavayi u64 subcode:7; 498f21fb3edSRaghu Vatsavayi u64 rflag:1; 499f21fb3edSRaghu Vatsavayi u64 opcode:4; 500f21fb3edSRaghu Vatsavayi #endif 501f21fb3edSRaghu Vatsavayi }; 502f21fb3edSRaghu Vatsavayi 503f21fb3edSRaghu Vatsavayi /** Return Data Parameters */ 504f21fb3edSRaghu Vatsavayi struct octeon_instr_rdp { 505f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 506f21fb3edSRaghu Vatsavayi u64 reserved:49; 507f21fb3edSRaghu Vatsavayi u64 pcie_port:3; 508f21fb3edSRaghu Vatsavayi u64 rlen:12; 509f21fb3edSRaghu Vatsavayi #else 510f21fb3edSRaghu Vatsavayi u64 rlen:12; 511f21fb3edSRaghu Vatsavayi u64 pcie_port:3; 512f21fb3edSRaghu Vatsavayi u64 reserved:49; 513f21fb3edSRaghu Vatsavayi #endif 514f21fb3edSRaghu Vatsavayi }; 515f21fb3edSRaghu Vatsavayi 516f21fb3edSRaghu Vatsavayi /** Receive Header */ 517f21fb3edSRaghu Vatsavayi union octeon_rh { 518f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 519f21fb3edSRaghu Vatsavayi u64 u64; 520f21fb3edSRaghu Vatsavayi struct { 521f21fb3edSRaghu Vatsavayi u64 opcode:4; 522f21fb3edSRaghu Vatsavayi u64 subcode:8; 523f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5240da0b77cSRaghu Vatsavayi u64 reserved:17; 525f21fb3edSRaghu Vatsavayi u64 ossp:32; /** opcode/subcode specific parameters */ 526f21fb3edSRaghu Vatsavayi } r; 527f21fb3edSRaghu Vatsavayi struct { 528f21fb3edSRaghu Vatsavayi u64 opcode:4; 529f21fb3edSRaghu Vatsavayi u64 subcode:8; 530f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5310da0b77cSRaghu Vatsavayi u64 extra:28; 5320da0b77cSRaghu Vatsavayi u64 vlan:12; 5330da0b77cSRaghu Vatsavayi u64 priority:3; 534f21fb3edSRaghu Vatsavayi u64 csum_verified:3; /** checksum verified. */ 535f21fb3edSRaghu Vatsavayi u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 536f21fb3edSRaghu Vatsavayi } r_dh; 537f21fb3edSRaghu Vatsavayi struct { 538f21fb3edSRaghu Vatsavayi u64 opcode:4; 539f21fb3edSRaghu Vatsavayi u64 subcode:8; 540f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5410da0b77cSRaghu Vatsavayi u64 reserved:11; 542f21fb3edSRaghu Vatsavayi u64 num_gmx_ports:8; 5430da0b77cSRaghu Vatsavayi u64 max_nic_ports:10; 544f21fb3edSRaghu Vatsavayi u64 app_cap_flags:4; 545f21fb3edSRaghu Vatsavayi u64 app_mode:16; 546f21fb3edSRaghu Vatsavayi } r_core_drv_init; 547f21fb3edSRaghu Vatsavayi struct { 548f21fb3edSRaghu Vatsavayi u64 opcode:4; 549f21fb3edSRaghu Vatsavayi u64 subcode:8; 550f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5510cece6c5SRaghu Vatsavayi u64 reserved:8; 552f21fb3edSRaghu Vatsavayi u64 extra:25; 5530cece6c5SRaghu Vatsavayi u64 gmxport:16; 554f21fb3edSRaghu Vatsavayi } r_nic_info; 555f21fb3edSRaghu Vatsavayi #else 556f21fb3edSRaghu Vatsavayi u64 u64; 557f21fb3edSRaghu Vatsavayi struct { 558f21fb3edSRaghu Vatsavayi u64 ossp:32; /** opcode/subcode specific parameters */ 5590da0b77cSRaghu Vatsavayi u64 reserved:17; 560f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 561f21fb3edSRaghu Vatsavayi u64 subcode:8; 562f21fb3edSRaghu Vatsavayi u64 opcode:4; 563f21fb3edSRaghu Vatsavayi } r; 564f21fb3edSRaghu Vatsavayi struct { 565f21fb3edSRaghu Vatsavayi u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 566f21fb3edSRaghu Vatsavayi u64 csum_verified:3; /** checksum verified. */ 5670da0b77cSRaghu Vatsavayi u64 priority:3; 5680da0b77cSRaghu Vatsavayi u64 vlan:12; 5690da0b77cSRaghu Vatsavayi u64 extra:28; 570f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 571f21fb3edSRaghu Vatsavayi u64 subcode:8; 572f21fb3edSRaghu Vatsavayi u64 opcode:4; 573f21fb3edSRaghu Vatsavayi } r_dh; 574f21fb3edSRaghu Vatsavayi struct { 575f21fb3edSRaghu Vatsavayi u64 app_mode:16; 576f21fb3edSRaghu Vatsavayi u64 app_cap_flags:4; 5770da0b77cSRaghu Vatsavayi u64 max_nic_ports:10; 578f21fb3edSRaghu Vatsavayi u64 num_gmx_ports:8; 5790da0b77cSRaghu Vatsavayi u64 reserved:11; 580f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 581f21fb3edSRaghu Vatsavayi u64 subcode:8; 582f21fb3edSRaghu Vatsavayi u64 opcode:4; 583f21fb3edSRaghu Vatsavayi } r_core_drv_init; 584f21fb3edSRaghu Vatsavayi struct { 5850cece6c5SRaghu Vatsavayi u64 gmxport:16; 586f21fb3edSRaghu Vatsavayi u64 extra:25; 5870cece6c5SRaghu Vatsavayi u64 reserved:8; 588f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 589f21fb3edSRaghu Vatsavayi u64 subcode:8; 590f21fb3edSRaghu Vatsavayi u64 opcode:4; 591f21fb3edSRaghu Vatsavayi } r_nic_info; 592f21fb3edSRaghu Vatsavayi #endif 593f21fb3edSRaghu Vatsavayi }; 594f21fb3edSRaghu Vatsavayi 595f21fb3edSRaghu Vatsavayi #define OCT_RH_SIZE (sizeof(union octeon_rh)) 596f21fb3edSRaghu Vatsavayi 597f21fb3edSRaghu Vatsavayi union octnic_packet_params { 598f21fb3edSRaghu Vatsavayi u32 u32; 599f21fb3edSRaghu Vatsavayi struct { 600f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 6010cece6c5SRaghu Vatsavayi u32 reserved:24; 6027275ebfcSRaghu Vatsavayi u32 ip_csum:1; /* Perform IP header checksum(s) */ 6037275ebfcSRaghu Vatsavayi /* Perform Outer transport header checksum */ 6047275ebfcSRaghu Vatsavayi u32 transport_csum:1; 6057275ebfcSRaghu Vatsavayi /* Find tunnel, and perform transport csum. */ 606f21fb3edSRaghu Vatsavayi u32 tnl_csum:1; 6077275ebfcSRaghu Vatsavayi u32 tsflag:1; /* Timestamp this packet */ 6087275ebfcSRaghu Vatsavayi u32 ipsec_ops:4; /* IPsec operation */ 609f21fb3edSRaghu Vatsavayi #else 610f21fb3edSRaghu Vatsavayi u32 ipsec_ops:4; 6117275ebfcSRaghu Vatsavayi u32 tsflag:1; 612f21fb3edSRaghu Vatsavayi u32 tnl_csum:1; 6137275ebfcSRaghu Vatsavayi u32 transport_csum:1; 6147275ebfcSRaghu Vatsavayi u32 ip_csum:1; 6150cece6c5SRaghu Vatsavayi u32 reserved:24; 616f21fb3edSRaghu Vatsavayi #endif 617f21fb3edSRaghu Vatsavayi } s; 618f21fb3edSRaghu Vatsavayi }; 619f21fb3edSRaghu Vatsavayi 620f21fb3edSRaghu Vatsavayi /** Status of a RGMII Link on Octeon as seen by core driver. */ 621f21fb3edSRaghu Vatsavayi union oct_link_status { 622f21fb3edSRaghu Vatsavayi u64 u64; 623f21fb3edSRaghu Vatsavayi 624f21fb3edSRaghu Vatsavayi struct { 625f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 626f21fb3edSRaghu Vatsavayi u64 duplex:8; 627f21fb3edSRaghu Vatsavayi u64 mtu:16; 628f21fb3edSRaghu Vatsavayi u64 speed:16; 6290cece6c5SRaghu Vatsavayi u64 link_up:1; 630f21fb3edSRaghu Vatsavayi u64 autoneg:1; 631f21fb3edSRaghu Vatsavayi u64 interface:4; 632f21fb3edSRaghu Vatsavayi u64 pause:1; 6330cece6c5SRaghu Vatsavayi u64 reserved:17; 634f21fb3edSRaghu Vatsavayi #else 6350cece6c5SRaghu Vatsavayi u64 reserved:17; 636f21fb3edSRaghu Vatsavayi u64 pause:1; 637f21fb3edSRaghu Vatsavayi u64 interface:4; 638f21fb3edSRaghu Vatsavayi u64 autoneg:1; 6390cece6c5SRaghu Vatsavayi u64 link_up:1; 640f21fb3edSRaghu Vatsavayi u64 speed:16; 641f21fb3edSRaghu Vatsavayi u64 mtu:16; 642f21fb3edSRaghu Vatsavayi u64 duplex:8; 643f21fb3edSRaghu Vatsavayi #endif 644f21fb3edSRaghu Vatsavayi } s; 645f21fb3edSRaghu Vatsavayi }; 646f21fb3edSRaghu Vatsavayi 64726236fa9SRaghu Vatsavayi /** The txpciq info passed to host from the firmware */ 64826236fa9SRaghu Vatsavayi 64926236fa9SRaghu Vatsavayi union oct_txpciq { 65026236fa9SRaghu Vatsavayi u64 u64; 65126236fa9SRaghu Vatsavayi 65226236fa9SRaghu Vatsavayi struct { 65326236fa9SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 65426236fa9SRaghu Vatsavayi u64 q_no:8; 65526236fa9SRaghu Vatsavayi u64 port:8; 65626236fa9SRaghu Vatsavayi u64 pkind:6; 65726236fa9SRaghu Vatsavayi u64 use_qpg:1; 65826236fa9SRaghu Vatsavayi u64 qpg:11; 65926236fa9SRaghu Vatsavayi u64 reserved:30; 66026236fa9SRaghu Vatsavayi #else 66126236fa9SRaghu Vatsavayi u64 reserved:30; 66226236fa9SRaghu Vatsavayi u64 qpg:11; 66326236fa9SRaghu Vatsavayi u64 use_qpg:1; 66426236fa9SRaghu Vatsavayi u64 pkind:6; 66526236fa9SRaghu Vatsavayi u64 port:8; 66626236fa9SRaghu Vatsavayi u64 q_no:8; 66726236fa9SRaghu Vatsavayi #endif 66826236fa9SRaghu Vatsavayi } s; 66926236fa9SRaghu Vatsavayi }; 67026236fa9SRaghu Vatsavayi 67126236fa9SRaghu Vatsavayi /** The rxpciq info passed to host from the firmware */ 67226236fa9SRaghu Vatsavayi 67326236fa9SRaghu Vatsavayi union oct_rxpciq { 67426236fa9SRaghu Vatsavayi u64 u64; 67526236fa9SRaghu Vatsavayi 67626236fa9SRaghu Vatsavayi struct { 67726236fa9SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 67826236fa9SRaghu Vatsavayi u64 q_no:8; 67926236fa9SRaghu Vatsavayi u64 reserved:56; 68026236fa9SRaghu Vatsavayi #else 68126236fa9SRaghu Vatsavayi u64 reserved:56; 68226236fa9SRaghu Vatsavayi u64 q_no:8; 68326236fa9SRaghu Vatsavayi #endif 68426236fa9SRaghu Vatsavayi } s; 68526236fa9SRaghu Vatsavayi }; 68626236fa9SRaghu Vatsavayi 687f21fb3edSRaghu Vatsavayi /** Information for a OCTEON ethernet interface shared between core & host. */ 688f21fb3edSRaghu Vatsavayi struct oct_link_info { 689f21fb3edSRaghu Vatsavayi union oct_link_status link; 690f21fb3edSRaghu Vatsavayi u64 hw_addr; 691f21fb3edSRaghu Vatsavayi 692f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 6930cece6c5SRaghu Vatsavayi u64 gmxport:16; 6940cece6c5SRaghu Vatsavayi u64 rsvd:32; 6950cece6c5SRaghu Vatsavayi u64 num_txpciq:8; 6960cece6c5SRaghu Vatsavayi u64 num_rxpciq:8; 697f21fb3edSRaghu Vatsavayi #else 6980cece6c5SRaghu Vatsavayi u64 num_rxpciq:8; 6990cece6c5SRaghu Vatsavayi u64 num_txpciq:8; 7000cece6c5SRaghu Vatsavayi u64 rsvd:32; 7010cece6c5SRaghu Vatsavayi u64 gmxport:16; 702f21fb3edSRaghu Vatsavayi #endif 703f21fb3edSRaghu Vatsavayi 70426236fa9SRaghu Vatsavayi union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 70526236fa9SRaghu Vatsavayi union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 706f21fb3edSRaghu Vatsavayi }; 707f21fb3edSRaghu Vatsavayi 708f21fb3edSRaghu Vatsavayi #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 709f21fb3edSRaghu Vatsavayi 710f21fb3edSRaghu Vatsavayi struct liquidio_if_cfg_info { 711f21fb3edSRaghu Vatsavayi u64 iqmask; /** mask for IQs enabled for the port */ 712f21fb3edSRaghu Vatsavayi u64 oqmask; /** mask for OQs enabled for the port */ 713f21fb3edSRaghu Vatsavayi struct oct_link_info linfo; /** initial link information */ 714d3d7e6c6SRaghu Vatsavayi char liquidio_firmware_version[32]; 715f21fb3edSRaghu Vatsavayi }; 716f21fb3edSRaghu Vatsavayi 717f21fb3edSRaghu Vatsavayi /** Stats for each NIC port in RX direction. */ 718f21fb3edSRaghu Vatsavayi struct nic_rx_stats { 719f21fb3edSRaghu Vatsavayi /* link-level stats */ 720f21fb3edSRaghu Vatsavayi u64 total_rcvd; 721f21fb3edSRaghu Vatsavayi u64 bytes_rcvd; 722f21fb3edSRaghu Vatsavayi u64 total_bcst; 723f21fb3edSRaghu Vatsavayi u64 total_mcst; 724f21fb3edSRaghu Vatsavayi u64 runts; 725f21fb3edSRaghu Vatsavayi u64 ctl_rcvd; 726f21fb3edSRaghu Vatsavayi u64 fifo_err; /* Accounts for over/under-run of buffers */ 727f21fb3edSRaghu Vatsavayi u64 dmac_drop; 728f21fb3edSRaghu Vatsavayi u64 fcs_err; 729f21fb3edSRaghu Vatsavayi u64 jabber_err; 730f21fb3edSRaghu Vatsavayi u64 l2_err; 731f21fb3edSRaghu Vatsavayi u64 frame_err; 732f21fb3edSRaghu Vatsavayi 733f21fb3edSRaghu Vatsavayi /* firmware stats */ 734f21fb3edSRaghu Vatsavayi u64 fw_total_rcvd; 735f21fb3edSRaghu Vatsavayi u64 fw_total_fwd; 736f21fb3edSRaghu Vatsavayi u64 fw_err_pko; 737f21fb3edSRaghu Vatsavayi u64 fw_err_link; 738f21fb3edSRaghu Vatsavayi u64 fw_err_drop; 739f21fb3edSRaghu Vatsavayi u64 fw_lro_pkts; /* Number of packets that are LROed */ 740f21fb3edSRaghu Vatsavayi u64 fw_lro_octs; /* Number of octets that are LROed */ 741f21fb3edSRaghu Vatsavayi u64 fw_total_lro; /* Number of LRO packets formed */ 742f21fb3edSRaghu Vatsavayi u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 743f21fb3edSRaghu Vatsavayi /* intrmod: packet forward rate */ 744f21fb3edSRaghu Vatsavayi u64 fwd_rate; 745f21fb3edSRaghu Vatsavayi }; 746f21fb3edSRaghu Vatsavayi 747f21fb3edSRaghu Vatsavayi /** Stats for each NIC port in RX direction. */ 748f21fb3edSRaghu Vatsavayi struct nic_tx_stats { 749f21fb3edSRaghu Vatsavayi /* link-level stats */ 750f21fb3edSRaghu Vatsavayi u64 total_pkts_sent; 751f21fb3edSRaghu Vatsavayi u64 total_bytes_sent; 752f21fb3edSRaghu Vatsavayi u64 mcast_pkts_sent; 753f21fb3edSRaghu Vatsavayi u64 bcast_pkts_sent; 754f21fb3edSRaghu Vatsavayi u64 ctl_sent; 755f21fb3edSRaghu Vatsavayi u64 one_collision_sent; /* Packets sent after one collision*/ 756f21fb3edSRaghu Vatsavayi u64 multi_collision_sent; /* Packets sent after multiple collision*/ 757f21fb3edSRaghu Vatsavayi u64 max_collision_fail; /* Packets not sent due to max collisions */ 758f21fb3edSRaghu Vatsavayi u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 759f21fb3edSRaghu Vatsavayi u64 fifo_err; /* Accounts for over/under-run of buffers */ 760f21fb3edSRaghu Vatsavayi u64 runts; 761f21fb3edSRaghu Vatsavayi u64 total_collisions; /* Total number of collisions detected */ 762f21fb3edSRaghu Vatsavayi 763f21fb3edSRaghu Vatsavayi /* firmware stats */ 764f21fb3edSRaghu Vatsavayi u64 fw_total_sent; 765f21fb3edSRaghu Vatsavayi u64 fw_total_fwd; 766f21fb3edSRaghu Vatsavayi u64 fw_err_pko; 767f21fb3edSRaghu Vatsavayi u64 fw_err_link; 768f21fb3edSRaghu Vatsavayi u64 fw_err_drop; 769f21fb3edSRaghu Vatsavayi }; 770f21fb3edSRaghu Vatsavayi 771f21fb3edSRaghu Vatsavayi struct oct_link_stats { 772f21fb3edSRaghu Vatsavayi struct nic_rx_stats fromwire; 773f21fb3edSRaghu Vatsavayi struct nic_tx_stats fromhost; 774f21fb3edSRaghu Vatsavayi 775f21fb3edSRaghu Vatsavayi }; 776f21fb3edSRaghu Vatsavayi 777f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_CTRL_ADDR 0x3501 778f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_CTRL_CFGON 0x1f 779f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_CTRL_CFGOFF 0x100 780f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_BEACON_ADDR 0x3508 781f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_BEACON_CFGON 0x47fd 782f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 783f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_DRIVEON 0x1 784f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_CFG 0x8 785f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 786f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_HIGH 0x2 787f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_LOW 0x3 788f21fb3edSRaghu Vatsavayi 789f21fb3edSRaghu Vatsavayi struct oct_mdio_cmd { 790f21fb3edSRaghu Vatsavayi u64 op; 791f21fb3edSRaghu Vatsavayi u64 mdio_addr; 792f21fb3edSRaghu Vatsavayi u64 value1; 793f21fb3edSRaghu Vatsavayi u64 value2; 794f21fb3edSRaghu Vatsavayi u64 value3; 795f21fb3edSRaghu Vatsavayi }; 796f21fb3edSRaghu Vatsavayi 797f21fb3edSRaghu Vatsavayi #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 798f21fb3edSRaghu Vatsavayi 799f21fb3edSRaghu Vatsavayi #define LIO_INTRMOD_CHECK_INTERVAL 1 800f21fb3edSRaghu Vatsavayi #define LIO_INTRMOD_MAXPKT_RATETHR 196608 /* max pkt rate threshold */ 801f21fb3edSRaghu Vatsavayi #define LIO_INTRMOD_MINPKT_RATETHR 9216 /* min pkt rate threshold */ 802f21fb3edSRaghu Vatsavayi #define LIO_INTRMOD_MAXCNT_TRIGGER 384 /* max pkts to trigger interrupt */ 803f21fb3edSRaghu Vatsavayi #define LIO_INTRMOD_MINCNT_TRIGGER 1 /* min pkts to trigger interrupt */ 804f21fb3edSRaghu Vatsavayi #define LIO_INTRMOD_MAXTMR_TRIGGER 128 /* max time to trigger interrupt */ 805f21fb3edSRaghu Vatsavayi #define LIO_INTRMOD_MINTMR_TRIGGER 32 /* min time to trigger interrupt */ 806f21fb3edSRaghu Vatsavayi 807f21fb3edSRaghu Vatsavayi struct oct_intrmod_cfg { 808f21fb3edSRaghu Vatsavayi u64 intrmod_enable; 809f21fb3edSRaghu Vatsavayi u64 intrmod_check_intrvl; 810f21fb3edSRaghu Vatsavayi u64 intrmod_maxpkt_ratethr; 811f21fb3edSRaghu Vatsavayi u64 intrmod_minpkt_ratethr; 812f21fb3edSRaghu Vatsavayi u64 intrmod_maxcnt_trigger; 813f21fb3edSRaghu Vatsavayi u64 intrmod_maxtmr_trigger; 814f21fb3edSRaghu Vatsavayi u64 intrmod_mincnt_trigger; 815f21fb3edSRaghu Vatsavayi u64 intrmod_mintmr_trigger; 816f21fb3edSRaghu Vatsavayi }; 817f21fb3edSRaghu Vatsavayi 818f21fb3edSRaghu Vatsavayi #define BASE_QUEUE_NOT_REQUESTED 65535 819f21fb3edSRaghu Vatsavayi 820f21fb3edSRaghu Vatsavayi union oct_nic_if_cfg { 821f21fb3edSRaghu Vatsavayi u64 u64; 822f21fb3edSRaghu Vatsavayi struct { 823f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 824f21fb3edSRaghu Vatsavayi u64 base_queue:16; 825f21fb3edSRaghu Vatsavayi u64 num_iqueues:16; 826f21fb3edSRaghu Vatsavayi u64 num_oqueues:16; 827f21fb3edSRaghu Vatsavayi u64 gmx_port_id:8; 828f21fb3edSRaghu Vatsavayi u64 reserved:8; 829f21fb3edSRaghu Vatsavayi #else 830f21fb3edSRaghu Vatsavayi u64 reserved:8; 831f21fb3edSRaghu Vatsavayi u64 gmx_port_id:8; 832f21fb3edSRaghu Vatsavayi u64 num_oqueues:16; 833f21fb3edSRaghu Vatsavayi u64 num_iqueues:16; 834f21fb3edSRaghu Vatsavayi u64 base_queue:16; 835f21fb3edSRaghu Vatsavayi #endif 836f21fb3edSRaghu Vatsavayi } s; 837f21fb3edSRaghu Vatsavayi }; 838f21fb3edSRaghu Vatsavayi 839f21fb3edSRaghu Vatsavayi #endif 840