1f21fb3edSRaghu Vatsavayi /********************************************************************** 2f21fb3edSRaghu Vatsavayi * Author: Cavium, Inc. 3f21fb3edSRaghu Vatsavayi * 4f21fb3edSRaghu Vatsavayi * Contact: support@cavium.com 5f21fb3edSRaghu Vatsavayi * Please include "LiquidIO" in the subject. 6f21fb3edSRaghu Vatsavayi * 750579d3dSRaghu Vatsavayi * Copyright (c) 2003-2016 Cavium, Inc. 8f21fb3edSRaghu Vatsavayi * 9f21fb3edSRaghu Vatsavayi * This file is free software; you can redistribute it and/or modify 10f21fb3edSRaghu Vatsavayi * it under the terms of the GNU General Public License, Version 2, as 11f21fb3edSRaghu Vatsavayi * published by the Free Software Foundation. 12f21fb3edSRaghu Vatsavayi * 13f21fb3edSRaghu Vatsavayi * This file is distributed in the hope that it will be useful, but 14f21fb3edSRaghu Vatsavayi * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15f21fb3edSRaghu Vatsavayi * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 1650579d3dSRaghu Vatsavayi * NONINFRINGEMENT. See the GNU General Public License for more details. 1750579d3dSRaghu Vatsavayi ***********************************************************************/ 18f21fb3edSRaghu Vatsavayi /*! \file liquidio_common.h 19f21fb3edSRaghu Vatsavayi * \brief Common: Structures and macros used in PCI-NIC package by core and 20f21fb3edSRaghu Vatsavayi * host driver. 21f21fb3edSRaghu Vatsavayi */ 22f21fb3edSRaghu Vatsavayi 23f21fb3edSRaghu Vatsavayi #ifndef __LIQUIDIO_COMMON_H__ 24f21fb3edSRaghu Vatsavayi #define __LIQUIDIO_COMMON_H__ 25f21fb3edSRaghu Vatsavayi 26f21fb3edSRaghu Vatsavayi #include "octeon_config.h" 27f21fb3edSRaghu Vatsavayi 28d3d7e6c6SRaghu Vatsavayi #define LIQUIDIO_PACKAGE "" 2983101ce3SRaghu Vatsavayi #define LIQUIDIO_BASE_MAJOR_VERSION 1 3025c5f715SFelix Manlunas #define LIQUIDIO_BASE_MINOR_VERSION 7 3125c5f715SFelix Manlunas #define LIQUIDIO_BASE_MICRO_VERSION 0 3283101ce3SRaghu Vatsavayi #define LIQUIDIO_BASE_VERSION __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 3383101ce3SRaghu Vatsavayi __stringify(LIQUIDIO_BASE_MINOR_VERSION) 3483101ce3SRaghu Vatsavayi #define LIQUIDIO_MICRO_VERSION "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 3583101ce3SRaghu Vatsavayi #define LIQUIDIO_VERSION LIQUIDIO_PACKAGE \ 3683101ce3SRaghu Vatsavayi __stringify(LIQUIDIO_BASE_MAJOR_VERSION) "." \ 3783101ce3SRaghu Vatsavayi __stringify(LIQUIDIO_BASE_MINOR_VERSION) \ 3883101ce3SRaghu Vatsavayi "." __stringify(LIQUIDIO_BASE_MICRO_VERSION) 3983101ce3SRaghu Vatsavayi 4083101ce3SRaghu Vatsavayi struct lio_version { 4183101ce3SRaghu Vatsavayi u16 major; 4283101ce3SRaghu Vatsavayi u16 minor; 4383101ce3SRaghu Vatsavayi u16 micro; 4483101ce3SRaghu Vatsavayi u16 reserved; 4583101ce3SRaghu Vatsavayi }; 46a2c64b67SRaghu Vatsavayi 47f21fb3edSRaghu Vatsavayi #define CONTROL_IQ 0 48f21fb3edSRaghu Vatsavayi /** Tag types used by Octeon cores in its work. */ 49f21fb3edSRaghu Vatsavayi enum octeon_tag_type { 50f21fb3edSRaghu Vatsavayi ORDERED_TAG = 0, 51f21fb3edSRaghu Vatsavayi ATOMIC_TAG = 1, 52f21fb3edSRaghu Vatsavayi NULL_TAG = 2, 53f21fb3edSRaghu Vatsavayi NULL_NULL_TAG = 3 54f21fb3edSRaghu Vatsavayi }; 55f21fb3edSRaghu Vatsavayi 56f21fb3edSRaghu Vatsavayi /* pre-defined host->NIC tag values */ 57f21fb3edSRaghu Vatsavayi #define LIO_CONTROL (0x11111110) 58f21fb3edSRaghu Vatsavayi #define LIO_DATA(i) (0x11111111 + (i)) 59f21fb3edSRaghu Vatsavayi 60f21fb3edSRaghu Vatsavayi /* Opcodes used by host driver/apps to perform operations on the core. 61f21fb3edSRaghu Vatsavayi * These are used to identify the major subsystem that the operation 62f21fb3edSRaghu Vatsavayi * is for. 63f21fb3edSRaghu Vatsavayi */ 64f21fb3edSRaghu Vatsavayi #define OPCODE_CORE 0 /* used for generic core operations */ 65f21fb3edSRaghu Vatsavayi #define OPCODE_NIC 1 /* used for NIC operations */ 66f21fb3edSRaghu Vatsavayi /* Subcodes are used by host driver/apps to identify the sub-operation 67f21fb3edSRaghu Vatsavayi * for the core. They only need to by unique for a given subsystem. 68f21fb3edSRaghu Vatsavayi */ 6997a25326SRaghu Vatsavayi #define OPCODE_SUBCODE(op, sub) ((((op) & 0x0f) << 8) | ((sub) & 0x7f)) 70f21fb3edSRaghu Vatsavayi 71f21fb3edSRaghu Vatsavayi /** OPCODE_CORE subcodes. For future use. */ 72f21fb3edSRaghu Vatsavayi 73f21fb3edSRaghu Vatsavayi /** OPCODE_NIC subcodes */ 74f21fb3edSRaghu Vatsavayi 75f21fb3edSRaghu Vatsavayi /* This subcode is sent by core PCI driver to indicate cores are ready. */ 76f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_CORE_DRV_ACTIVE 0x01 77f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_NW_DATA 0x02 /* network packet data */ 78f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_CMD 0x03 79f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_INFO 0x04 80f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_PORT_STATS 0x05 81f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_MDIO45 0x06 82f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_TIMESTAMP 0x07 83f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_INTRMOD_CFG 0x08 84f21fb3edSRaghu Vatsavayi #define OPCODE_NIC_IF_CFG 0x09 8586dea55bSRaghu Vatsavayi #define OPCODE_NIC_VF_DRV_NOTICE 0x0A 8650c0add5SPrasad Kanneganti #define OPCODE_NIC_INTRMOD_PARAMS 0x0B 87f2d254faSIntiyaz Basha #define OPCODE_NIC_SET_TRUSTED_VF 0x13 88907aaa6bSVeerasenareddy Burru #define OPCODE_NIC_SYNC_OCTEON_TIME 0x14 8986dea55bSRaghu Vatsavayi #define VF_DRV_LOADED 1 9086dea55bSRaghu Vatsavayi #define VF_DRV_REMOVED -1 9186dea55bSRaghu Vatsavayi #define VF_DRV_MACADDR_CHANGED 2 92f21fb3edSRaghu Vatsavayi 931f233f32SVijaya Mohan Guvva #define OPCODE_NIC_VF_REP_PKT 0x15 941f233f32SVijaya Mohan Guvva #define OPCODE_NIC_VF_REP_CMD 0x16 951f233f32SVijaya Mohan Guvva 96f21fb3edSRaghu Vatsavayi #define CORE_DRV_TEST_SCATTER_OP 0xFFF5 97f21fb3edSRaghu Vatsavayi 98f21fb3edSRaghu Vatsavayi /* Application codes advertised by the core driver initialization packet. */ 99f21fb3edSRaghu Vatsavayi #define CVM_DRV_APP_START 0x0 100f21fb3edSRaghu Vatsavayi #define CVM_DRV_NO_APP 0 101f21fb3edSRaghu Vatsavayi #define CVM_DRV_APP_COUNT 0x2 102f21fb3edSRaghu Vatsavayi #define CVM_DRV_BASE_APP (CVM_DRV_APP_START + 0x0) 103f21fb3edSRaghu Vatsavayi #define CVM_DRV_NIC_APP (CVM_DRV_APP_START + 0x1) 104f21fb3edSRaghu Vatsavayi #define CVM_DRV_INVALID_APP (CVM_DRV_APP_START + 0x2) 105f21fb3edSRaghu Vatsavayi #define CVM_DRV_APP_END (CVM_DRV_INVALID_APP - 1) 106f21fb3edSRaghu Vatsavayi 107de28c99dSPrasad Kanneganti #define BYTES_PER_DHLEN_UNIT 8 108cdb478e5SSatanand Burla #define MAX_REG_CNT 2000000U 1090c88a761SRick Farrington #define INTRNAMSIZ 32 1100c88a761SRick Farrington #define IRQ_NAME_OFF(i) ((i) * INTRNAMSIZ) 1110c88a761SRick Farrington #define MAX_IOQ_INTERRUPTS_PER_PF (64 * 2) 1120c88a761SRick Farrington #define MAX_IOQ_INTERRUPTS_PER_VF (8 * 2) 1130c88a761SRick Farrington 114b2854772SFelix Manlunas #define SCR2_BIT_FW_LOADED 63 115de28c99dSPrasad Kanneganti 116907aaa6bSVeerasenareddy Burru /* App specific capabilities from firmware to pf driver */ 117907aaa6bSVeerasenareddy Burru #define LIQUIDIO_TIME_SYNC_CAP 0x1 118d4be8ebeSVijaya Mohan Guvva #define LIQUIDIO_SWITCHDEV_CAP 0x2 119907aaa6bSVeerasenareddy Burru 12097a25326SRaghu Vatsavayi static inline u32 incr_index(u32 index, u32 count, u32 max) 12197a25326SRaghu Vatsavayi { 12297a25326SRaghu Vatsavayi if ((index + count) >= max) 12397a25326SRaghu Vatsavayi index = index + count - max; 12497a25326SRaghu Vatsavayi else 12597a25326SRaghu Vatsavayi index += count; 126f21fb3edSRaghu Vatsavayi 12797a25326SRaghu Vatsavayi return index; 12897a25326SRaghu Vatsavayi } 129f21fb3edSRaghu Vatsavayi 130f21fb3edSRaghu Vatsavayi #define OCT_BOARD_NAME 32 131f21fb3edSRaghu Vatsavayi #define OCT_SERIAL_LEN 64 132f21fb3edSRaghu Vatsavayi 133f21fb3edSRaghu Vatsavayi /* Structure used by core driver to send indication that the Octeon 134f21fb3edSRaghu Vatsavayi * application is ready. 135f21fb3edSRaghu Vatsavayi */ 136f21fb3edSRaghu Vatsavayi struct octeon_core_setup { 137f21fb3edSRaghu Vatsavayi u64 corefreq; 138f21fb3edSRaghu Vatsavayi 139f21fb3edSRaghu Vatsavayi char boardname[OCT_BOARD_NAME]; 140f21fb3edSRaghu Vatsavayi 141f21fb3edSRaghu Vatsavayi char board_serial_number[OCT_SERIAL_LEN]; 142f21fb3edSRaghu Vatsavayi 143f21fb3edSRaghu Vatsavayi u64 board_rev_major; 144f21fb3edSRaghu Vatsavayi 145f21fb3edSRaghu Vatsavayi u64 board_rev_minor; 146f21fb3edSRaghu Vatsavayi 147f21fb3edSRaghu Vatsavayi }; 148f21fb3edSRaghu Vatsavayi 149f21fb3edSRaghu Vatsavayi /*--------------------------- SCATTER GATHER ENTRY -----------------------*/ 150f21fb3edSRaghu Vatsavayi 151f21fb3edSRaghu Vatsavayi /* The Scatter-Gather List Entry. The scatter or gather component used with 152f21fb3edSRaghu Vatsavayi * a Octeon input instruction has this format. 153f21fb3edSRaghu Vatsavayi */ 154f21fb3edSRaghu Vatsavayi struct octeon_sg_entry { 155f21fb3edSRaghu Vatsavayi /** The first 64 bit gives the size of data in each dptr.*/ 156f21fb3edSRaghu Vatsavayi union { 157f21fb3edSRaghu Vatsavayi u16 size[4]; 158f21fb3edSRaghu Vatsavayi u64 size64; 159f21fb3edSRaghu Vatsavayi } u; 160f21fb3edSRaghu Vatsavayi 161f21fb3edSRaghu Vatsavayi /** The 4 dptr pointers for this entry. */ 162f21fb3edSRaghu Vatsavayi u64 ptr[4]; 163f21fb3edSRaghu Vatsavayi 164f21fb3edSRaghu Vatsavayi }; 165f21fb3edSRaghu Vatsavayi 166f21fb3edSRaghu Vatsavayi #define OCT_SG_ENTRY_SIZE (sizeof(struct octeon_sg_entry)) 167f21fb3edSRaghu Vatsavayi 168f21fb3edSRaghu Vatsavayi /* \brief Add size to gather list 169f21fb3edSRaghu Vatsavayi * @param sg_entry scatter/gather entry 170f21fb3edSRaghu Vatsavayi * @param size size to add 171f21fb3edSRaghu Vatsavayi * @param pos position to add it. 172f21fb3edSRaghu Vatsavayi */ 173f21fb3edSRaghu Vatsavayi static inline void add_sg_size(struct octeon_sg_entry *sg_entry, 174f21fb3edSRaghu Vatsavayi u16 size, 175f21fb3edSRaghu Vatsavayi u32 pos) 176f21fb3edSRaghu Vatsavayi { 177f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 178f21fb3edSRaghu Vatsavayi sg_entry->u.size[pos] = size; 179f21fb3edSRaghu Vatsavayi #else 180f21fb3edSRaghu Vatsavayi sg_entry->u.size[3 - pos] = size; 181f21fb3edSRaghu Vatsavayi #endif 182f21fb3edSRaghu Vatsavayi } 183f21fb3edSRaghu Vatsavayi 184f21fb3edSRaghu Vatsavayi /*------------------------- End Scatter/Gather ---------------------------*/ 185f21fb3edSRaghu Vatsavayi 186c4ee5d81SPrasad Kanneganti #define OCTNET_FRM_LENGTH_SIZE 8 187c4ee5d81SPrasad Kanneganti 188f21fb3edSRaghu Vatsavayi #define OCTNET_FRM_PTP_HEADER_SIZE 8 189f21fb3edSRaghu Vatsavayi 190a5b37888SRaghu Vatsavayi #define OCTNET_FRM_HEADER_SIZE 22 /* VLAN + Ethernet */ 191a5b37888SRaghu Vatsavayi 192a5b37888SRaghu Vatsavayi #define OCTNET_MIN_FRM_SIZE 64 193a5b37888SRaghu Vatsavayi 194f21fb3edSRaghu Vatsavayi #define OCTNET_MAX_FRM_SIZE (16000 + OCTNET_FRM_HEADER_SIZE) 195f21fb3edSRaghu Vatsavayi 19687a7c4b3SVeerasenareddy Burru #define OCTNET_DEFAULT_MTU (1500) 19787a7c4b3SVeerasenareddy Burru #define OCTNET_DEFAULT_FRM_SIZE (OCTNET_DEFAULT_MTU + OCTNET_FRM_HEADER_SIZE) 198f21fb3edSRaghu Vatsavayi 199f21fb3edSRaghu Vatsavayi /** NIC Commands are sent using this Octeon Input Queue */ 200f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_Q 0 201f21fb3edSRaghu Vatsavayi 202f21fb3edSRaghu Vatsavayi /* NIC Command types */ 203f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CHANGE_MTU 0x1 204f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CHANGE_MACADDR 0x2 205f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CHANGE_DEVFLAGS 0x3 206f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_RX_CTL 0x4 207f21fb3edSRaghu Vatsavayi 208f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_MULTI_LIST 0x5 209f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_CLEAR_STATS 0x6 210f21fb3edSRaghu Vatsavayi 211f21fb3edSRaghu Vatsavayi /* command for setting the speed, duplex & autoneg */ 212f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_SETTINGS 0x7 213f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_FLOW_CTL 0x8 214f21fb3edSRaghu Vatsavayi 215f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_MDIO_READ_WRITE 0x9 216f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_GPIO_ACCESS 0xA 217f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_LRO_ENABLE 0xB 218f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_LRO_DISABLE 0xC 219f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SET_RSS 0xD 220f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_WRITE_SA 0xE 221f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_DELETE_SA 0xF 222f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_UPDATE_SA 0x12 223f21fb3edSRaghu Vatsavayi 224f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_TNL_RX_CSUM_CTL 0x10 225f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_TNL_TX_CSUM_CTL 0x11 226f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13 227f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_VERBOSE_ENABLE 0x14 228f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_VERBOSE_DISABLE 0x15 229f21fb3edSRaghu Vatsavayi 230836d57e5SPrasad Kanneganti #define OCTNET_CMD_VLAN_FILTER_CTL 0x16 23163245f25SRaghu Vatsavayi #define OCTNET_CMD_ADD_VLAN_FILTER 0x17 23263245f25SRaghu Vatsavayi #define OCTNET_CMD_DEL_VLAN_FILTER 0x18 23301fb237aSRaghu Vatsavayi #define OCTNET_CMD_VXLAN_PORT_CONFIG 0x19 234dc3abcbeSRaghu Vatsavayi 235dc3abcbeSRaghu Vatsavayi #define OCTNET_CMD_ID_ACTIVE 0x1a 236dc3abcbeSRaghu Vatsavayi 23750f7f94bSRaghu Vatsavayi #define OCTNET_CMD_SET_UC_LIST 0x1b 23886dea55bSRaghu Vatsavayi #define OCTNET_CMD_SET_VF_LINKSTATE 0x1c 239a82457f1SIntiyaz Basha 240a82457f1SIntiyaz Basha #define OCTNET_CMD_QUEUE_COUNT_CTL 0x1f 241a82457f1SIntiyaz Basha 24201fb237aSRaghu Vatsavayi #define OCTNET_CMD_VXLAN_PORT_ADD 0x0 24301fb237aSRaghu Vatsavayi #define OCTNET_CMD_VXLAN_PORT_DEL 0x1 24401fb237aSRaghu Vatsavayi #define OCTNET_CMD_RXCSUM_ENABLE 0x0 24501fb237aSRaghu Vatsavayi #define OCTNET_CMD_RXCSUM_DISABLE 0x1 24601fb237aSRaghu Vatsavayi #define OCTNET_CMD_TXCSUM_ENABLE 0x0 24701fb237aSRaghu Vatsavayi #define OCTNET_CMD_TXCSUM_DISABLE 0x1 248836d57e5SPrasad Kanneganti #define OCTNET_CMD_VLAN_FILTER_ENABLE 0x1 249836d57e5SPrasad Kanneganti #define OCTNET_CMD_VLAN_FILTER_DISABLE 0x0 25063245f25SRaghu Vatsavayi 251ad530a1dSVeerasenareddy Burru #define LIO_CMD_WAIT_TM 100 252ad530a1dSVeerasenareddy Burru 253f21fb3edSRaghu Vatsavayi /* RX(packets coming from wire) Checksum verification flags */ 254f21fb3edSRaghu Vatsavayi /* TCP/UDP csum */ 255f21fb3edSRaghu Vatsavayi #define CNNIC_L4SUM_VERIFIED 0x1 256f21fb3edSRaghu Vatsavayi #define CNNIC_IPSUM_VERIFIED 0x2 257f21fb3edSRaghu Vatsavayi #define CNNIC_TUN_CSUM_VERIFIED 0x4 258f21fb3edSRaghu Vatsavayi #define CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED) 259f21fb3edSRaghu Vatsavayi 260f21fb3edSRaghu Vatsavayi /*LROIPV4 and LROIPV6 Flags*/ 261f21fb3edSRaghu Vatsavayi #define OCTNIC_LROIPV4 0x1 262f21fb3edSRaghu Vatsavayi #define OCTNIC_LROIPV6 0x2 263f21fb3edSRaghu Vatsavayi 264f21fb3edSRaghu Vatsavayi /* Interface flags communicated between host driver and core app. */ 265f21fb3edSRaghu Vatsavayi enum octnet_ifflags { 266f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_PROMISC = 0x01, 267f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_ALLMULTI = 0x02, 268f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_MULTICAST = 0x04, 269f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_BROADCAST = 0x08, 270f21fb3edSRaghu Vatsavayi OCTNET_IFFLAG_UNICAST = 0x10 271f21fb3edSRaghu Vatsavayi }; 272f21fb3edSRaghu Vatsavayi 273f21fb3edSRaghu Vatsavayi /* wqe 274f21fb3edSRaghu Vatsavayi * --------------- 0 275f21fb3edSRaghu Vatsavayi * | wqe word0-3 | 276f21fb3edSRaghu Vatsavayi * --------------- 32 277f21fb3edSRaghu Vatsavayi * | PCI IH | 278f21fb3edSRaghu Vatsavayi * --------------- 40 279f21fb3edSRaghu Vatsavayi * | RPTR | 280f21fb3edSRaghu Vatsavayi * --------------- 48 281f21fb3edSRaghu Vatsavayi * | PCI IRH | 282f21fb3edSRaghu Vatsavayi * --------------- 56 283f21fb3edSRaghu Vatsavayi * | OCT_NET_CMD | 284f21fb3edSRaghu Vatsavayi * --------------- 64 285f21fb3edSRaghu Vatsavayi * | Addtl 8-BData | 286f21fb3edSRaghu Vatsavayi * | | 287f21fb3edSRaghu Vatsavayi * --------------- 288f21fb3edSRaghu Vatsavayi */ 289f21fb3edSRaghu Vatsavayi 290f21fb3edSRaghu Vatsavayi union octnet_cmd { 291f21fb3edSRaghu Vatsavayi u64 u64; 292f21fb3edSRaghu Vatsavayi 293f21fb3edSRaghu Vatsavayi struct { 294f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 295f21fb3edSRaghu Vatsavayi u64 cmd:5; 296f21fb3edSRaghu Vatsavayi 297f21fb3edSRaghu Vatsavayi u64 more:6; /* How many udd words follow the command */ 298f21fb3edSRaghu Vatsavayi 2990cece6c5SRaghu Vatsavayi u64 reserved:29; 300f21fb3edSRaghu Vatsavayi 3010cece6c5SRaghu Vatsavayi u64 param1:16; 302f21fb3edSRaghu Vatsavayi 3030cece6c5SRaghu Vatsavayi u64 param2:8; 304f21fb3edSRaghu Vatsavayi 305f21fb3edSRaghu Vatsavayi #else 306f21fb3edSRaghu Vatsavayi 3070cece6c5SRaghu Vatsavayi u64 param2:8; 308f21fb3edSRaghu Vatsavayi 3090cece6c5SRaghu Vatsavayi u64 param1:16; 310f21fb3edSRaghu Vatsavayi 3110cece6c5SRaghu Vatsavayi u64 reserved:29; 312f21fb3edSRaghu Vatsavayi 313f21fb3edSRaghu Vatsavayi u64 more:6; 314f21fb3edSRaghu Vatsavayi 315f21fb3edSRaghu Vatsavayi u64 cmd:5; 316f21fb3edSRaghu Vatsavayi 317f21fb3edSRaghu Vatsavayi #endif 318f21fb3edSRaghu Vatsavayi } s; 319f21fb3edSRaghu Vatsavayi 320f21fb3edSRaghu Vatsavayi }; 321f21fb3edSRaghu Vatsavayi 322f21fb3edSRaghu Vatsavayi #define OCTNET_CMD_SIZE (sizeof(union octnet_cmd)) 323f21fb3edSRaghu Vatsavayi 3245b823514SRaghu Vatsavayi /*pkiih3 + irh + ossp[0] + ossp[1] + rdp + rptr = 40 bytes */ 3255b823514SRaghu Vatsavayi #define LIO_SOFTCMDRESP_IH2 40 3265b823514SRaghu Vatsavayi #define LIO_SOFTCMDRESP_IH3 (40 + 8) 3275b823514SRaghu Vatsavayi 3285b823514SRaghu Vatsavayi #define LIO_PCICMD_O2 24 3295b823514SRaghu Vatsavayi #define LIO_PCICMD_O3 (24 + 8) 3305b823514SRaghu Vatsavayi 331a2c64b67SRaghu Vatsavayi /* Instruction Header(DPI) - for OCTEON-III models */ 3326a885b60SRaghu Vatsavayi struct octeon_instr_ih3 { 3336a885b60SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 3346a885b60SRaghu Vatsavayi 3356a885b60SRaghu Vatsavayi /** Reserved3 */ 3366a885b60SRaghu Vatsavayi u64 reserved3:1; 3376a885b60SRaghu Vatsavayi 3386a885b60SRaghu Vatsavayi /** Gather indicator 1=gather*/ 3396a885b60SRaghu Vatsavayi u64 gather:1; 3406a885b60SRaghu Vatsavayi 3416a885b60SRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 3426a885b60SRaghu Vatsavayi u64 dlengsz:14; 3436a885b60SRaghu Vatsavayi 3446a885b60SRaghu Vatsavayi /** Front Data size */ 3456a885b60SRaghu Vatsavayi u64 fsz:6; 3466a885b60SRaghu Vatsavayi 3476a885b60SRaghu Vatsavayi /** Reserved2 */ 3486a885b60SRaghu Vatsavayi u64 reserved2:4; 3496a885b60SRaghu Vatsavayi 3506a885b60SRaghu Vatsavayi /** PKI port kind - PKIND */ 3516a885b60SRaghu Vatsavayi u64 pkind:6; 3526a885b60SRaghu Vatsavayi 3536a885b60SRaghu Vatsavayi /** Reserved1 */ 3546a885b60SRaghu Vatsavayi u64 reserved1:32; 3556a885b60SRaghu Vatsavayi 3566a885b60SRaghu Vatsavayi #else 3576a885b60SRaghu Vatsavayi /** Reserved1 */ 3586a885b60SRaghu Vatsavayi u64 reserved1:32; 3596a885b60SRaghu Vatsavayi 3606a885b60SRaghu Vatsavayi /** PKI port kind - PKIND */ 3616a885b60SRaghu Vatsavayi u64 pkind:6; 3626a885b60SRaghu Vatsavayi 3636a885b60SRaghu Vatsavayi /** Reserved2 */ 3646a885b60SRaghu Vatsavayi u64 reserved2:4; 3656a885b60SRaghu Vatsavayi 3666a885b60SRaghu Vatsavayi /** Front Data size */ 3676a885b60SRaghu Vatsavayi u64 fsz:6; 3686a885b60SRaghu Vatsavayi 3696a885b60SRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 3706a885b60SRaghu Vatsavayi u64 dlengsz:14; 3716a885b60SRaghu Vatsavayi 3726a885b60SRaghu Vatsavayi /** Gather indicator 1=gather*/ 3736a885b60SRaghu Vatsavayi u64 gather:1; 3746a885b60SRaghu Vatsavayi 3756a885b60SRaghu Vatsavayi /** Reserved3 */ 3766a885b60SRaghu Vatsavayi u64 reserved3:1; 3776a885b60SRaghu Vatsavayi 3786a885b60SRaghu Vatsavayi #endif 3796a885b60SRaghu Vatsavayi }; 3806a885b60SRaghu Vatsavayi 381a2c64b67SRaghu Vatsavayi /* Optional PKI Instruction Header(PKI IH) - for OCTEON-III models */ 3826a885b60SRaghu Vatsavayi /** BIG ENDIAN format. */ 3836a885b60SRaghu Vatsavayi struct octeon_instr_pki_ih3 { 3846a885b60SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 3856a885b60SRaghu Vatsavayi 3866a885b60SRaghu Vatsavayi /** Wider bit */ 3876a885b60SRaghu Vatsavayi u64 w:1; 3886a885b60SRaghu Vatsavayi 3896a885b60SRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 3906a885b60SRaghu Vatsavayi u64 raw:1; 3916a885b60SRaghu Vatsavayi 3926a885b60SRaghu Vatsavayi /** Use Tag */ 3936a885b60SRaghu Vatsavayi u64 utag:1; 3946a885b60SRaghu Vatsavayi 3956a885b60SRaghu Vatsavayi /** Use QPG */ 3966a885b60SRaghu Vatsavayi u64 uqpg:1; 3976a885b60SRaghu Vatsavayi 3986a885b60SRaghu Vatsavayi /** Reserved2 */ 3996a885b60SRaghu Vatsavayi u64 reserved2:1; 4006a885b60SRaghu Vatsavayi 4016a885b60SRaghu Vatsavayi /** Parse Mode */ 4026a885b60SRaghu Vatsavayi u64 pm:3; 4036a885b60SRaghu Vatsavayi 4046a885b60SRaghu Vatsavayi /** Skip Length */ 4056a885b60SRaghu Vatsavayi u64 sl:8; 4066a885b60SRaghu Vatsavayi 4076a885b60SRaghu Vatsavayi /** Use Tag Type */ 4086a885b60SRaghu Vatsavayi u64 utt:1; 4096a885b60SRaghu Vatsavayi 4106a885b60SRaghu Vatsavayi /** Tag type */ 4116a885b60SRaghu Vatsavayi u64 tagtype:2; 4126a885b60SRaghu Vatsavayi 4136a885b60SRaghu Vatsavayi /** Reserved1 */ 4146a885b60SRaghu Vatsavayi u64 reserved1:2; 4156a885b60SRaghu Vatsavayi 4166a885b60SRaghu Vatsavayi /** QPG Value */ 4176a885b60SRaghu Vatsavayi u64 qpg:11; 4186a885b60SRaghu Vatsavayi 4196a885b60SRaghu Vatsavayi /** Tag Value */ 4206a885b60SRaghu Vatsavayi u64 tag:32; 4216a885b60SRaghu Vatsavayi 4226a885b60SRaghu Vatsavayi #else 4236a885b60SRaghu Vatsavayi 4246a885b60SRaghu Vatsavayi /** Tag Value */ 4256a885b60SRaghu Vatsavayi u64 tag:32; 4266a885b60SRaghu Vatsavayi 4276a885b60SRaghu Vatsavayi /** QPG Value */ 4286a885b60SRaghu Vatsavayi u64 qpg:11; 4296a885b60SRaghu Vatsavayi 4306a885b60SRaghu Vatsavayi /** Reserved1 */ 4316a885b60SRaghu Vatsavayi u64 reserved1:2; 4326a885b60SRaghu Vatsavayi 4336a885b60SRaghu Vatsavayi /** Tag type */ 4346a885b60SRaghu Vatsavayi u64 tagtype:2; 4356a885b60SRaghu Vatsavayi 4366a885b60SRaghu Vatsavayi /** Use Tag Type */ 4376a885b60SRaghu Vatsavayi u64 utt:1; 4386a885b60SRaghu Vatsavayi 4396a885b60SRaghu Vatsavayi /** Skip Length */ 4406a885b60SRaghu Vatsavayi u64 sl:8; 4416a885b60SRaghu Vatsavayi 4426a885b60SRaghu Vatsavayi /** Parse Mode */ 4436a885b60SRaghu Vatsavayi u64 pm:3; 4446a885b60SRaghu Vatsavayi 4456a885b60SRaghu Vatsavayi /** Reserved2 */ 4466a885b60SRaghu Vatsavayi u64 reserved2:1; 4476a885b60SRaghu Vatsavayi 4486a885b60SRaghu Vatsavayi /** Use QPG */ 4496a885b60SRaghu Vatsavayi u64 uqpg:1; 4506a885b60SRaghu Vatsavayi 4516a885b60SRaghu Vatsavayi /** Use Tag */ 4526a885b60SRaghu Vatsavayi u64 utag:1; 4536a885b60SRaghu Vatsavayi 4546a885b60SRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 4556a885b60SRaghu Vatsavayi u64 raw:1; 4566a885b60SRaghu Vatsavayi 4576a885b60SRaghu Vatsavayi /** Wider bit */ 4586a885b60SRaghu Vatsavayi u64 w:1; 4596a885b60SRaghu Vatsavayi #endif 4606a885b60SRaghu Vatsavayi 4616a885b60SRaghu Vatsavayi }; 4626a885b60SRaghu Vatsavayi 463f21fb3edSRaghu Vatsavayi /** Instruction Header */ 4646a885b60SRaghu Vatsavayi struct octeon_instr_ih2 { 465f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 466f21fb3edSRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 467f21fb3edSRaghu Vatsavayi u64 raw:1; 468f21fb3edSRaghu Vatsavayi 469f21fb3edSRaghu Vatsavayi /** Gather indicator 1=gather*/ 470f21fb3edSRaghu Vatsavayi u64 gather:1; 471f21fb3edSRaghu Vatsavayi 472f21fb3edSRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 473f21fb3edSRaghu Vatsavayi u64 dlengsz:14; 474f21fb3edSRaghu Vatsavayi 475f21fb3edSRaghu Vatsavayi /** Front Data size */ 476f21fb3edSRaghu Vatsavayi u64 fsz:6; 477f21fb3edSRaghu Vatsavayi 478f21fb3edSRaghu Vatsavayi /** Packet Order / Work Unit selection (1 of 8)*/ 479f21fb3edSRaghu Vatsavayi u64 qos:3; 480f21fb3edSRaghu Vatsavayi 481f21fb3edSRaghu Vatsavayi /** Core group selection (1 of 16) */ 482f21fb3edSRaghu Vatsavayi u64 grp:4; 483f21fb3edSRaghu Vatsavayi 484f21fb3edSRaghu Vatsavayi /** Short Raw Packet Indicator 1=short raw pkt */ 485f21fb3edSRaghu Vatsavayi u64 rs:1; 486f21fb3edSRaghu Vatsavayi 487f21fb3edSRaghu Vatsavayi /** Tag type */ 488f21fb3edSRaghu Vatsavayi u64 tagtype:2; 489f21fb3edSRaghu Vatsavayi 490f21fb3edSRaghu Vatsavayi /** Tag Value */ 491f21fb3edSRaghu Vatsavayi u64 tag:32; 492f21fb3edSRaghu Vatsavayi #else 493f21fb3edSRaghu Vatsavayi /** Tag Value */ 494f21fb3edSRaghu Vatsavayi u64 tag:32; 495f21fb3edSRaghu Vatsavayi 496f21fb3edSRaghu Vatsavayi /** Tag type */ 497f21fb3edSRaghu Vatsavayi u64 tagtype:2; 498f21fb3edSRaghu Vatsavayi 499f21fb3edSRaghu Vatsavayi /** Short Raw Packet Indicator 1=short raw pkt */ 500f21fb3edSRaghu Vatsavayi u64 rs:1; 501f21fb3edSRaghu Vatsavayi 502f21fb3edSRaghu Vatsavayi /** Core group selection (1 of 16) */ 503f21fb3edSRaghu Vatsavayi u64 grp:4; 504f21fb3edSRaghu Vatsavayi 505f21fb3edSRaghu Vatsavayi /** Packet Order / Work Unit selection (1 of 8)*/ 506f21fb3edSRaghu Vatsavayi u64 qos:3; 507f21fb3edSRaghu Vatsavayi 508f21fb3edSRaghu Vatsavayi /** Front Data size */ 509f21fb3edSRaghu Vatsavayi u64 fsz:6; 510f21fb3edSRaghu Vatsavayi 511f21fb3edSRaghu Vatsavayi /** Data length OR no. of entries in gather list */ 512f21fb3edSRaghu Vatsavayi u64 dlengsz:14; 513f21fb3edSRaghu Vatsavayi 514f21fb3edSRaghu Vatsavayi /** Gather indicator 1=gather*/ 515f21fb3edSRaghu Vatsavayi u64 gather:1; 516f21fb3edSRaghu Vatsavayi 517f21fb3edSRaghu Vatsavayi /** Raw mode indicator 1 = RAW */ 518f21fb3edSRaghu Vatsavayi u64 raw:1; 519f21fb3edSRaghu Vatsavayi #endif 520f21fb3edSRaghu Vatsavayi }; 521f21fb3edSRaghu Vatsavayi 522f21fb3edSRaghu Vatsavayi /** Input Request Header */ 523f21fb3edSRaghu Vatsavayi struct octeon_instr_irh { 524f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 525f21fb3edSRaghu Vatsavayi u64 opcode:4; 526f21fb3edSRaghu Vatsavayi u64 rflag:1; 527f21fb3edSRaghu Vatsavayi u64 subcode:7; 5280da0b77cSRaghu Vatsavayi u64 vlan:12; 5290da0b77cSRaghu Vatsavayi u64 priority:3; 5300da0b77cSRaghu Vatsavayi u64 reserved:5; 531f21fb3edSRaghu Vatsavayi u64 ossp:32; /* opcode/subcode specific parameters */ 532f21fb3edSRaghu Vatsavayi #else 533f21fb3edSRaghu Vatsavayi u64 ossp:32; /* opcode/subcode specific parameters */ 5340da0b77cSRaghu Vatsavayi u64 reserved:5; 5350da0b77cSRaghu Vatsavayi u64 priority:3; 5360da0b77cSRaghu Vatsavayi u64 vlan:12; 537f21fb3edSRaghu Vatsavayi u64 subcode:7; 538f21fb3edSRaghu Vatsavayi u64 rflag:1; 539f21fb3edSRaghu Vatsavayi u64 opcode:4; 540f21fb3edSRaghu Vatsavayi #endif 541f21fb3edSRaghu Vatsavayi }; 542f21fb3edSRaghu Vatsavayi 543f21fb3edSRaghu Vatsavayi /** Return Data Parameters */ 544f21fb3edSRaghu Vatsavayi struct octeon_instr_rdp { 545f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 546f21fb3edSRaghu Vatsavayi u64 reserved:49; 547f21fb3edSRaghu Vatsavayi u64 pcie_port:3; 548f21fb3edSRaghu Vatsavayi u64 rlen:12; 549f21fb3edSRaghu Vatsavayi #else 550f21fb3edSRaghu Vatsavayi u64 rlen:12; 551f21fb3edSRaghu Vatsavayi u64 pcie_port:3; 552f21fb3edSRaghu Vatsavayi u64 reserved:49; 553f21fb3edSRaghu Vatsavayi #endif 554f21fb3edSRaghu Vatsavayi }; 555f21fb3edSRaghu Vatsavayi 556f21fb3edSRaghu Vatsavayi /** Receive Header */ 557f21fb3edSRaghu Vatsavayi union octeon_rh { 558f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 559f21fb3edSRaghu Vatsavayi u64 u64; 560f21fb3edSRaghu Vatsavayi struct { 561f21fb3edSRaghu Vatsavayi u64 opcode:4; 562f21fb3edSRaghu Vatsavayi u64 subcode:8; 563f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5640da0b77cSRaghu Vatsavayi u64 reserved:17; 565f21fb3edSRaghu Vatsavayi u64 ossp:32; /** opcode/subcode specific parameters */ 566f21fb3edSRaghu Vatsavayi } r; 567f21fb3edSRaghu Vatsavayi struct { 568f21fb3edSRaghu Vatsavayi u64 opcode:4; 569f21fb3edSRaghu Vatsavayi u64 subcode:8; 570f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5710da0b77cSRaghu Vatsavayi u64 extra:28; 5720da0b77cSRaghu Vatsavayi u64 vlan:12; 5730da0b77cSRaghu Vatsavayi u64 priority:3; 574f21fb3edSRaghu Vatsavayi u64 csum_verified:3; /** checksum verified. */ 575f21fb3edSRaghu Vatsavayi u64 has_hwtstamp:1; /** Has hardware timestamp. 1 = yes. */ 57601fb237aSRaghu Vatsavayi u64 encap_on:1; 5779fbc48f6SRaghu Vatsavayi u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 578f21fb3edSRaghu Vatsavayi } r_dh; 579f21fb3edSRaghu Vatsavayi struct { 580f21fb3edSRaghu Vatsavayi u64 opcode:4; 581f21fb3edSRaghu Vatsavayi u64 subcode:8; 582f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5830da0b77cSRaghu Vatsavayi u64 reserved:11; 584f21fb3edSRaghu Vatsavayi u64 num_gmx_ports:8; 5850da0b77cSRaghu Vatsavayi u64 max_nic_ports:10; 586f21fb3edSRaghu Vatsavayi u64 app_cap_flags:4; 5879fbc48f6SRaghu Vatsavayi u64 app_mode:8; 5889fbc48f6SRaghu Vatsavayi u64 pkind:8; 589f21fb3edSRaghu Vatsavayi } r_core_drv_init; 590f21fb3edSRaghu Vatsavayi struct { 591f21fb3edSRaghu Vatsavayi u64 opcode:4; 592f21fb3edSRaghu Vatsavayi u64 subcode:8; 593f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 5940cece6c5SRaghu Vatsavayi u64 reserved:8; 595f21fb3edSRaghu Vatsavayi u64 extra:25; 5960cece6c5SRaghu Vatsavayi u64 gmxport:16; 597f21fb3edSRaghu Vatsavayi } r_nic_info; 598f21fb3edSRaghu Vatsavayi #else 599f21fb3edSRaghu Vatsavayi u64 u64; 600f21fb3edSRaghu Vatsavayi struct { 601f21fb3edSRaghu Vatsavayi u64 ossp:32; /** opcode/subcode specific parameters */ 6020da0b77cSRaghu Vatsavayi u64 reserved:17; 603f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 604f21fb3edSRaghu Vatsavayi u64 subcode:8; 605f21fb3edSRaghu Vatsavayi u64 opcode:4; 606f21fb3edSRaghu Vatsavayi } r; 607f21fb3edSRaghu Vatsavayi struct { 6089fbc48f6SRaghu Vatsavayi u64 has_hash:1; /** Has hash (rth or rss). 1 = yes. */ 60901fb237aSRaghu Vatsavayi u64 encap_on:1; 610f21fb3edSRaghu Vatsavayi u64 has_hwtstamp:1; /** 1 = has hwtstamp */ 611f21fb3edSRaghu Vatsavayi u64 csum_verified:3; /** checksum verified. */ 6120da0b77cSRaghu Vatsavayi u64 priority:3; 6130da0b77cSRaghu Vatsavayi u64 vlan:12; 6140da0b77cSRaghu Vatsavayi u64 extra:28; 615f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 616f21fb3edSRaghu Vatsavayi u64 subcode:8; 617f21fb3edSRaghu Vatsavayi u64 opcode:4; 618f21fb3edSRaghu Vatsavayi } r_dh; 619f21fb3edSRaghu Vatsavayi struct { 6209fbc48f6SRaghu Vatsavayi u64 pkind:8; 6219fbc48f6SRaghu Vatsavayi u64 app_mode:8; 622f21fb3edSRaghu Vatsavayi u64 app_cap_flags:4; 6230da0b77cSRaghu Vatsavayi u64 max_nic_ports:10; 624f21fb3edSRaghu Vatsavayi u64 num_gmx_ports:8; 6250da0b77cSRaghu Vatsavayi u64 reserved:11; 626f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 627f21fb3edSRaghu Vatsavayi u64 subcode:8; 628f21fb3edSRaghu Vatsavayi u64 opcode:4; 629f21fb3edSRaghu Vatsavayi } r_core_drv_init; 630f21fb3edSRaghu Vatsavayi struct { 6310cece6c5SRaghu Vatsavayi u64 gmxport:16; 632f21fb3edSRaghu Vatsavayi u64 extra:25; 6330cece6c5SRaghu Vatsavayi u64 reserved:8; 634f21fb3edSRaghu Vatsavayi u64 len:3; /** additional 64-bit words */ 635f21fb3edSRaghu Vatsavayi u64 subcode:8; 636f21fb3edSRaghu Vatsavayi u64 opcode:4; 637f21fb3edSRaghu Vatsavayi } r_nic_info; 638f21fb3edSRaghu Vatsavayi #endif 639f21fb3edSRaghu Vatsavayi }; 640f21fb3edSRaghu Vatsavayi 641f21fb3edSRaghu Vatsavayi #define OCT_RH_SIZE (sizeof(union octeon_rh)) 642f21fb3edSRaghu Vatsavayi 643f21fb3edSRaghu Vatsavayi union octnic_packet_params { 644f21fb3edSRaghu Vatsavayi u32 u32; 645f21fb3edSRaghu Vatsavayi struct { 646f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 6470cece6c5SRaghu Vatsavayi u32 reserved:24; 6487275ebfcSRaghu Vatsavayi u32 ip_csum:1; /* Perform IP header checksum(s) */ 6497275ebfcSRaghu Vatsavayi /* Perform Outer transport header checksum */ 6507275ebfcSRaghu Vatsavayi u32 transport_csum:1; 6517275ebfcSRaghu Vatsavayi /* Find tunnel, and perform transport csum. */ 652f21fb3edSRaghu Vatsavayi u32 tnl_csum:1; 6537275ebfcSRaghu Vatsavayi u32 tsflag:1; /* Timestamp this packet */ 6547275ebfcSRaghu Vatsavayi u32 ipsec_ops:4; /* IPsec operation */ 655f21fb3edSRaghu Vatsavayi #else 656f21fb3edSRaghu Vatsavayi u32 ipsec_ops:4; 6577275ebfcSRaghu Vatsavayi u32 tsflag:1; 658f21fb3edSRaghu Vatsavayi u32 tnl_csum:1; 6597275ebfcSRaghu Vatsavayi u32 transport_csum:1; 6607275ebfcSRaghu Vatsavayi u32 ip_csum:1; 6610cece6c5SRaghu Vatsavayi u32 reserved:24; 662f21fb3edSRaghu Vatsavayi #endif 663f21fb3edSRaghu Vatsavayi } s; 664f21fb3edSRaghu Vatsavayi }; 665f21fb3edSRaghu Vatsavayi 666f21fb3edSRaghu Vatsavayi /** Status of a RGMII Link on Octeon as seen by core driver. */ 667f21fb3edSRaghu Vatsavayi union oct_link_status { 668f21fb3edSRaghu Vatsavayi u64 u64; 669f21fb3edSRaghu Vatsavayi 670f21fb3edSRaghu Vatsavayi struct { 671f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 672f21fb3edSRaghu Vatsavayi u64 duplex:8; 673f21fb3edSRaghu Vatsavayi u64 mtu:16; 674f21fb3edSRaghu Vatsavayi u64 speed:16; 6750cece6c5SRaghu Vatsavayi u64 link_up:1; 676f21fb3edSRaghu Vatsavayi u64 autoneg:1; 6779eb60844SRaghu Vatsavayi u64 if_mode:5; 678f21fb3edSRaghu Vatsavayi u64 pause:1; 6799fbc48f6SRaghu Vatsavayi u64 flashing:1; 6805677629aSVeerasenareddy Burru u64 phy_type:5; 6815677629aSVeerasenareddy Burru u64 reserved:10; 682f21fb3edSRaghu Vatsavayi #else 6835677629aSVeerasenareddy Burru u64 reserved:10; 6845677629aSVeerasenareddy Burru u64 phy_type:5; 6859fbc48f6SRaghu Vatsavayi u64 flashing:1; 686f21fb3edSRaghu Vatsavayi u64 pause:1; 6879eb60844SRaghu Vatsavayi u64 if_mode:5; 688f21fb3edSRaghu Vatsavayi u64 autoneg:1; 6890cece6c5SRaghu Vatsavayi u64 link_up:1; 690f21fb3edSRaghu Vatsavayi u64 speed:16; 691f21fb3edSRaghu Vatsavayi u64 mtu:16; 692f21fb3edSRaghu Vatsavayi u64 duplex:8; 693f21fb3edSRaghu Vatsavayi #endif 694f21fb3edSRaghu Vatsavayi } s; 695f21fb3edSRaghu Vatsavayi }; 696f21fb3edSRaghu Vatsavayi 6975677629aSVeerasenareddy Burru enum lio_phy_type { 6985677629aSVeerasenareddy Burru LIO_PHY_PORT_TP = 0x0, 6995677629aSVeerasenareddy Burru LIO_PHY_PORT_FIBRE = 0x1, 7005677629aSVeerasenareddy Burru LIO_PHY_PORT_UNKNOWN, 7015677629aSVeerasenareddy Burru }; 7025677629aSVeerasenareddy Burru 70326236fa9SRaghu Vatsavayi /** The txpciq info passed to host from the firmware */ 70426236fa9SRaghu Vatsavayi 70526236fa9SRaghu Vatsavayi union oct_txpciq { 70626236fa9SRaghu Vatsavayi u64 u64; 70726236fa9SRaghu Vatsavayi 70826236fa9SRaghu Vatsavayi struct { 70926236fa9SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 71026236fa9SRaghu Vatsavayi u64 q_no:8; 71126236fa9SRaghu Vatsavayi u64 port:8; 71226236fa9SRaghu Vatsavayi u64 pkind:6; 71326236fa9SRaghu Vatsavayi u64 use_qpg:1; 71426236fa9SRaghu Vatsavayi u64 qpg:11; 715697fefc7SIntiyaz Basha u64 reserved0:10; 716697fefc7SIntiyaz Basha u64 ctrl_qpg:11; 717697fefc7SIntiyaz Basha u64 reserved:9; 71826236fa9SRaghu Vatsavayi #else 719697fefc7SIntiyaz Basha u64 reserved:9; 720697fefc7SIntiyaz Basha u64 ctrl_qpg:11; 721697fefc7SIntiyaz Basha u64 reserved0:10; 72226236fa9SRaghu Vatsavayi u64 qpg:11; 72326236fa9SRaghu Vatsavayi u64 use_qpg:1; 72426236fa9SRaghu Vatsavayi u64 pkind:6; 72526236fa9SRaghu Vatsavayi u64 port:8; 72626236fa9SRaghu Vatsavayi u64 q_no:8; 72726236fa9SRaghu Vatsavayi #endif 72826236fa9SRaghu Vatsavayi } s; 72926236fa9SRaghu Vatsavayi }; 73026236fa9SRaghu Vatsavayi 73126236fa9SRaghu Vatsavayi /** The rxpciq info passed to host from the firmware */ 73226236fa9SRaghu Vatsavayi 73326236fa9SRaghu Vatsavayi union oct_rxpciq { 73426236fa9SRaghu Vatsavayi u64 u64; 73526236fa9SRaghu Vatsavayi 73626236fa9SRaghu Vatsavayi struct { 73726236fa9SRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 73826236fa9SRaghu Vatsavayi u64 q_no:8; 73926236fa9SRaghu Vatsavayi u64 reserved:56; 74026236fa9SRaghu Vatsavayi #else 74126236fa9SRaghu Vatsavayi u64 reserved:56; 74226236fa9SRaghu Vatsavayi u64 q_no:8; 74326236fa9SRaghu Vatsavayi #endif 74426236fa9SRaghu Vatsavayi } s; 74526236fa9SRaghu Vatsavayi }; 74626236fa9SRaghu Vatsavayi 747f21fb3edSRaghu Vatsavayi /** Information for a OCTEON ethernet interface shared between core & host. */ 748f21fb3edSRaghu Vatsavayi struct oct_link_info { 749f21fb3edSRaghu Vatsavayi union oct_link_status link; 750f21fb3edSRaghu Vatsavayi u64 hw_addr; 751f21fb3edSRaghu Vatsavayi 752f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 7530cece6c5SRaghu Vatsavayi u64 gmxport:16; 7548c978d05SRaghu Vatsavayi u64 macaddr_is_admin_asgnd:1; 7558c978d05SRaghu Vatsavayi u64 rsvd:31; 7560cece6c5SRaghu Vatsavayi u64 num_txpciq:8; 7570cece6c5SRaghu Vatsavayi u64 num_rxpciq:8; 758f21fb3edSRaghu Vatsavayi #else 7590cece6c5SRaghu Vatsavayi u64 num_rxpciq:8; 7600cece6c5SRaghu Vatsavayi u64 num_txpciq:8; 7618c978d05SRaghu Vatsavayi u64 rsvd:31; 7628c978d05SRaghu Vatsavayi u64 macaddr_is_admin_asgnd:1; 7630cece6c5SRaghu Vatsavayi u64 gmxport:16; 764f21fb3edSRaghu Vatsavayi #endif 765f21fb3edSRaghu Vatsavayi 76626236fa9SRaghu Vatsavayi union oct_txpciq txpciq[MAX_IOQS_PER_NICIF]; 76726236fa9SRaghu Vatsavayi union oct_rxpciq rxpciq[MAX_IOQS_PER_NICIF]; 768f21fb3edSRaghu Vatsavayi }; 769f21fb3edSRaghu Vatsavayi 770f21fb3edSRaghu Vatsavayi #define OCT_LINK_INFO_SIZE (sizeof(struct oct_link_info)) 771f21fb3edSRaghu Vatsavayi 772f21fb3edSRaghu Vatsavayi struct liquidio_if_cfg_info { 773f21fb3edSRaghu Vatsavayi u64 iqmask; /** mask for IQs enabled for the port */ 774f21fb3edSRaghu Vatsavayi u64 oqmask; /** mask for OQs enabled for the port */ 775f21fb3edSRaghu Vatsavayi struct oct_link_info linfo; /** initial link information */ 776d3d7e6c6SRaghu Vatsavayi char liquidio_firmware_version[32]; 777f21fb3edSRaghu Vatsavayi }; 778f21fb3edSRaghu Vatsavayi 779f21fb3edSRaghu Vatsavayi /** Stats for each NIC port in RX direction. */ 780f21fb3edSRaghu Vatsavayi struct nic_rx_stats { 781f21fb3edSRaghu Vatsavayi /* link-level stats */ 782f21fb3edSRaghu Vatsavayi u64 total_rcvd; 783f21fb3edSRaghu Vatsavayi u64 bytes_rcvd; 784f21fb3edSRaghu Vatsavayi u64 total_bcst; 785f21fb3edSRaghu Vatsavayi u64 total_mcst; 786f21fb3edSRaghu Vatsavayi u64 runts; 787f21fb3edSRaghu Vatsavayi u64 ctl_rcvd; 788f21fb3edSRaghu Vatsavayi u64 fifo_err; /* Accounts for over/under-run of buffers */ 789f21fb3edSRaghu Vatsavayi u64 dmac_drop; 790f21fb3edSRaghu Vatsavayi u64 fcs_err; 791f21fb3edSRaghu Vatsavayi u64 jabber_err; 792f21fb3edSRaghu Vatsavayi u64 l2_err; 793f21fb3edSRaghu Vatsavayi u64 frame_err; 794f21fb3edSRaghu Vatsavayi 795f21fb3edSRaghu Vatsavayi /* firmware stats */ 796f21fb3edSRaghu Vatsavayi u64 fw_total_rcvd; 797f21fb3edSRaghu Vatsavayi u64 fw_total_fwd; 798a847135aSFelix Manlunas u64 fw_total_fwd_bytes; 799f21fb3edSRaghu Vatsavayi u64 fw_err_pko; 800f21fb3edSRaghu Vatsavayi u64 fw_err_link; 801f21fb3edSRaghu Vatsavayi u64 fw_err_drop; 80201fb237aSRaghu Vatsavayi u64 fw_rx_vxlan; 80301fb237aSRaghu Vatsavayi u64 fw_rx_vxlan_err; 8041f164717SRaghu Vatsavayi 8051f164717SRaghu Vatsavayi /* LRO */ 806f21fb3edSRaghu Vatsavayi u64 fw_lro_pkts; /* Number of packets that are LROed */ 807f21fb3edSRaghu Vatsavayi u64 fw_lro_octs; /* Number of octets that are LROed */ 808f21fb3edSRaghu Vatsavayi u64 fw_total_lro; /* Number of LRO packets formed */ 809f21fb3edSRaghu Vatsavayi u64 fw_lro_aborts; /* Number of times lRO of packet aborted */ 8101f164717SRaghu Vatsavayi u64 fw_lro_aborts_port; 8111f164717SRaghu Vatsavayi u64 fw_lro_aborts_seq; 8121f164717SRaghu Vatsavayi u64 fw_lro_aborts_tsval; 8131f164717SRaghu Vatsavayi u64 fw_lro_aborts_timer; 814f21fb3edSRaghu Vatsavayi /* intrmod: packet forward rate */ 815f21fb3edSRaghu Vatsavayi u64 fwd_rate; 816f21fb3edSRaghu Vatsavayi }; 817f21fb3edSRaghu Vatsavayi 818f21fb3edSRaghu Vatsavayi /** Stats for each NIC port in RX direction. */ 819f21fb3edSRaghu Vatsavayi struct nic_tx_stats { 820f21fb3edSRaghu Vatsavayi /* link-level stats */ 821f21fb3edSRaghu Vatsavayi u64 total_pkts_sent; 822f21fb3edSRaghu Vatsavayi u64 total_bytes_sent; 823f21fb3edSRaghu Vatsavayi u64 mcast_pkts_sent; 824f21fb3edSRaghu Vatsavayi u64 bcast_pkts_sent; 825f21fb3edSRaghu Vatsavayi u64 ctl_sent; 826f21fb3edSRaghu Vatsavayi u64 one_collision_sent; /* Packets sent after one collision*/ 827f21fb3edSRaghu Vatsavayi u64 multi_collision_sent; /* Packets sent after multiple collision*/ 828f21fb3edSRaghu Vatsavayi u64 max_collision_fail; /* Packets not sent due to max collisions */ 829f21fb3edSRaghu Vatsavayi u64 max_deferral_fail; /* Packets not sent due to max deferrals */ 830f21fb3edSRaghu Vatsavayi u64 fifo_err; /* Accounts for over/under-run of buffers */ 831f21fb3edSRaghu Vatsavayi u64 runts; 832f21fb3edSRaghu Vatsavayi u64 total_collisions; /* Total number of collisions detected */ 833f21fb3edSRaghu Vatsavayi 834f21fb3edSRaghu Vatsavayi /* firmware stats */ 835f21fb3edSRaghu Vatsavayi u64 fw_total_sent; 836f21fb3edSRaghu Vatsavayi u64 fw_total_fwd; 8371f164717SRaghu Vatsavayi u64 fw_total_fwd_bytes; 838f21fb3edSRaghu Vatsavayi u64 fw_err_pko; 839f21fb3edSRaghu Vatsavayi u64 fw_err_link; 840f21fb3edSRaghu Vatsavayi u64 fw_err_drop; 8411f164717SRaghu Vatsavayi u64 fw_err_tso; 8421f164717SRaghu Vatsavayi u64 fw_tso; /* number of tso requests */ 8431f164717SRaghu Vatsavayi u64 fw_tso_fwd; /* number of packets segmented in tso */ 84401fb237aSRaghu Vatsavayi u64 fw_tx_vxlan; 845741912c5SRick Farrington u64 fw_err_pki; 846f21fb3edSRaghu Vatsavayi }; 847f21fb3edSRaghu Vatsavayi 848f21fb3edSRaghu Vatsavayi struct oct_link_stats { 849f21fb3edSRaghu Vatsavayi struct nic_rx_stats fromwire; 850f21fb3edSRaghu Vatsavayi struct nic_tx_stats fromhost; 851f21fb3edSRaghu Vatsavayi 852f21fb3edSRaghu Vatsavayi }; 853f21fb3edSRaghu Vatsavayi 85497a25326SRaghu Vatsavayi static inline int opcode_slow_path(union octeon_rh *rh) 85597a25326SRaghu Vatsavayi { 85697a25326SRaghu Vatsavayi u16 subcode1, subcode2; 85797a25326SRaghu Vatsavayi 85897a25326SRaghu Vatsavayi subcode1 = OPCODE_SUBCODE((rh)->r.opcode, (rh)->r.subcode); 85997a25326SRaghu Vatsavayi subcode2 = OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA); 86097a25326SRaghu Vatsavayi 86197a25326SRaghu Vatsavayi return (subcode2 != subcode1); 86297a25326SRaghu Vatsavayi } 86397a25326SRaghu Vatsavayi 864f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_CTRL_ADDR 0x3501 865f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_CTRL_CFGON 0x1f 866f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_CTRL_CFGOFF 0x100 867f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_BEACON_ADDR 0x3508 868f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_BEACON_CFGON 0x47fd 869f21fb3edSRaghu Vatsavayi #define LIO68XX_LED_BEACON_CFGOFF 0x11fc 870f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_DRIVEON 0x1 871f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_CFG 0x8 872f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_DRIVEOFF 0x4 873f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_HIGH 0x2 874f21fb3edSRaghu Vatsavayi #define VITESSE_PHY_GPIO_LOW 0x3 875dc3abcbeSRaghu Vatsavayi #define LED_IDENTIFICATION_ON 0x1 876dc3abcbeSRaghu Vatsavayi #define LED_IDENTIFICATION_OFF 0x0 877f21fb3edSRaghu Vatsavayi 878f21fb3edSRaghu Vatsavayi struct oct_mdio_cmd { 879f21fb3edSRaghu Vatsavayi u64 op; 880f21fb3edSRaghu Vatsavayi u64 mdio_addr; 881f21fb3edSRaghu Vatsavayi u64 value1; 882f21fb3edSRaghu Vatsavayi u64 value2; 883f21fb3edSRaghu Vatsavayi u64 value3; 884f21fb3edSRaghu Vatsavayi }; 885f21fb3edSRaghu Vatsavayi 886f21fb3edSRaghu Vatsavayi #define OCT_LINK_STATS_SIZE (sizeof(struct oct_link_stats)) 887f21fb3edSRaghu Vatsavayi 888f21fb3edSRaghu Vatsavayi struct oct_intrmod_cfg { 88978e6a9b4SRaghu Vatsavayi u64 rx_enable; 89078e6a9b4SRaghu Vatsavayi u64 tx_enable; 89178e6a9b4SRaghu Vatsavayi u64 check_intrvl; 89278e6a9b4SRaghu Vatsavayi u64 maxpkt_ratethr; 89378e6a9b4SRaghu Vatsavayi u64 minpkt_ratethr; 89478e6a9b4SRaghu Vatsavayi u64 rx_maxcnt_trigger; 89578e6a9b4SRaghu Vatsavayi u64 rx_mincnt_trigger; 89678e6a9b4SRaghu Vatsavayi u64 rx_maxtmr_trigger; 89778e6a9b4SRaghu Vatsavayi u64 rx_mintmr_trigger; 89878e6a9b4SRaghu Vatsavayi u64 tx_mincnt_trigger; 89978e6a9b4SRaghu Vatsavayi u64 tx_maxcnt_trigger; 90078e6a9b4SRaghu Vatsavayi u64 rx_frames; 90178e6a9b4SRaghu Vatsavayi u64 tx_frames; 90278e6a9b4SRaghu Vatsavayi u64 rx_usecs; 903f21fb3edSRaghu Vatsavayi }; 904f21fb3edSRaghu Vatsavayi 905f21fb3edSRaghu Vatsavayi #define BASE_QUEUE_NOT_REQUESTED 65535 906f21fb3edSRaghu Vatsavayi 907f21fb3edSRaghu Vatsavayi union oct_nic_if_cfg { 908f21fb3edSRaghu Vatsavayi u64 u64; 909f21fb3edSRaghu Vatsavayi struct { 910f21fb3edSRaghu Vatsavayi #ifdef __BIG_ENDIAN_BITFIELD 911f21fb3edSRaghu Vatsavayi u64 base_queue:16; 912f21fb3edSRaghu Vatsavayi u64 num_iqueues:16; 913f21fb3edSRaghu Vatsavayi u64 num_oqueues:16; 914f21fb3edSRaghu Vatsavayi u64 gmx_port_id:8; 9159fbc48f6SRaghu Vatsavayi u64 vf_id:8; 916f21fb3edSRaghu Vatsavayi #else 9179fbc48f6SRaghu Vatsavayi u64 vf_id:8; 918f21fb3edSRaghu Vatsavayi u64 gmx_port_id:8; 919f21fb3edSRaghu Vatsavayi u64 num_oqueues:16; 920f21fb3edSRaghu Vatsavayi u64 num_iqueues:16; 921f21fb3edSRaghu Vatsavayi u64 base_queue:16; 922f21fb3edSRaghu Vatsavayi #endif 923f21fb3edSRaghu Vatsavayi } s; 924f21fb3edSRaghu Vatsavayi }; 925f21fb3edSRaghu Vatsavayi 926f2d254faSIntiyaz Basha struct lio_trusted_vf { 927f2d254faSIntiyaz Basha uint64_t active: 1; 928f2d254faSIntiyaz Basha uint64_t id : 8; 929f2d254faSIntiyaz Basha uint64_t reserved: 55; 930f2d254faSIntiyaz Basha }; 931f2d254faSIntiyaz Basha 932907aaa6bSVeerasenareddy Burru struct lio_time { 933907aaa6bSVeerasenareddy Burru s64 sec; /* seconds */ 934907aaa6bSVeerasenareddy Burru s64 nsec; /* nanoseconds */ 935907aaa6bSVeerasenareddy Burru }; 9361f233f32SVijaya Mohan Guvva 9371f233f32SVijaya Mohan Guvva struct lio_vf_rep_stats { 9381f233f32SVijaya Mohan Guvva u64 tx_packets; 9391f233f32SVijaya Mohan Guvva u64 tx_bytes; 9401f233f32SVijaya Mohan Guvva u64 tx_dropped; 9411f233f32SVijaya Mohan Guvva 9421f233f32SVijaya Mohan Guvva u64 rx_packets; 9431f233f32SVijaya Mohan Guvva u64 rx_bytes; 9441f233f32SVijaya Mohan Guvva u64 rx_dropped; 9451f233f32SVijaya Mohan Guvva }; 9461f233f32SVijaya Mohan Guvva 9471f233f32SVijaya Mohan Guvva enum lio_vf_rep_req_type { 9481f233f32SVijaya Mohan Guvva LIO_VF_REP_REQ_NONE, 9491f233f32SVijaya Mohan Guvva LIO_VF_REP_REQ_STATE, 9501f233f32SVijaya Mohan Guvva LIO_VF_REP_REQ_MTU, 951e20f4696SVijaya Mohan Guvva LIO_VF_REP_REQ_STATS, 952e20f4696SVijaya Mohan Guvva LIO_VF_REP_REQ_DEVNAME 9531f233f32SVijaya Mohan Guvva }; 9541f233f32SVijaya Mohan Guvva 9551f233f32SVijaya Mohan Guvva enum { 9561f233f32SVijaya Mohan Guvva LIO_VF_REP_STATE_DOWN, 9571f233f32SVijaya Mohan Guvva LIO_VF_REP_STATE_UP 9581f233f32SVijaya Mohan Guvva }; 9591f233f32SVijaya Mohan Guvva 960e20f4696SVijaya Mohan Guvva #define LIO_IF_NAME_SIZE 16 9611f233f32SVijaya Mohan Guvva struct lio_vf_rep_req { 9621f233f32SVijaya Mohan Guvva u8 req_type; 9631f233f32SVijaya Mohan Guvva u8 ifidx; 9641f233f32SVijaya Mohan Guvva u8 rsvd[6]; 9651f233f32SVijaya Mohan Guvva 9661f233f32SVijaya Mohan Guvva union { 967e20f4696SVijaya Mohan Guvva struct lio_vf_rep_name { 968e20f4696SVijaya Mohan Guvva char name[LIO_IF_NAME_SIZE]; 969e20f4696SVijaya Mohan Guvva } rep_name; 970e20f4696SVijaya Mohan Guvva 9711f233f32SVijaya Mohan Guvva struct lio_vf_rep_mtu { 9721f233f32SVijaya Mohan Guvva u32 mtu; 9731f233f32SVijaya Mohan Guvva u32 rsvd; 9741f233f32SVijaya Mohan Guvva } rep_mtu; 9751f233f32SVijaya Mohan Guvva 9761f233f32SVijaya Mohan Guvva struct lio_vf_rep_state { 9771f233f32SVijaya Mohan Guvva u8 state; 9781f233f32SVijaya Mohan Guvva u8 rsvd[7]; 9791f233f32SVijaya Mohan Guvva } rep_state; 9801f233f32SVijaya Mohan Guvva }; 9811f233f32SVijaya Mohan Guvva }; 9821f233f32SVijaya Mohan Guvva 9831f233f32SVijaya Mohan Guvva struct lio_vf_rep_resp { 9841f233f32SVijaya Mohan Guvva u64 rh; 9851f233f32SVijaya Mohan Guvva u8 status; 9861f233f32SVijaya Mohan Guvva u8 rsvd[7]; 9871f233f32SVijaya Mohan Guvva }; 988f21fb3edSRaghu Vatsavayi #endif 989