1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 #include <linux/netdevice.h> 19 #include <linux/net_tstamp.h> 20 #include <linux/pci.h> 21 #include "liquidio_common.h" 22 #include "octeon_droq.h" 23 #include "octeon_iq.h" 24 #include "response_manager.h" 25 #include "octeon_device.h" 26 #include "octeon_nic.h" 27 #include "octeon_main.h" 28 #include "octeon_network.h" 29 #include "cn66xx_regs.h" 30 #include "cn66xx_device.h" 31 #include "cn23xx_pf_device.h" 32 #include "cn23xx_vf_device.h" 33 34 static int octnet_get_link_stats(struct net_device *netdev); 35 36 struct oct_mdio_cmd_context { 37 int octeon_id; 38 wait_queue_head_t wc; 39 int cond; 40 }; 41 42 struct oct_mdio_cmd_resp { 43 u64 rh; 44 struct oct_mdio_cmd resp; 45 u64 status; 46 }; 47 48 #define OCT_MDIO45_RESP_SIZE (sizeof(struct oct_mdio_cmd_resp)) 49 50 /* Octeon's interface mode of operation */ 51 enum { 52 INTERFACE_MODE_DISABLED, 53 INTERFACE_MODE_RGMII, 54 INTERFACE_MODE_GMII, 55 INTERFACE_MODE_SPI, 56 INTERFACE_MODE_PCIE, 57 INTERFACE_MODE_XAUI, 58 INTERFACE_MODE_SGMII, 59 INTERFACE_MODE_PICMG, 60 INTERFACE_MODE_NPI, 61 INTERFACE_MODE_LOOP, 62 INTERFACE_MODE_SRIO, 63 INTERFACE_MODE_ILK, 64 INTERFACE_MODE_RXAUI, 65 INTERFACE_MODE_QSGMII, 66 INTERFACE_MODE_AGL, 67 INTERFACE_MODE_XLAUI, 68 INTERFACE_MODE_XFI, 69 INTERFACE_MODE_10G_KR, 70 INTERFACE_MODE_40G_KR4, 71 INTERFACE_MODE_MIXED, 72 }; 73 74 #define OCT_ETHTOOL_REGDUMP_LEN 4096 75 #define OCT_ETHTOOL_REGDUMP_LEN_23XX (4096 * 11) 76 #define OCT_ETHTOOL_REGDUMP_LEN_23XX_VF (4096 * 2) 77 #define OCT_ETHTOOL_REGSVER 1 78 79 /* statistics of PF */ 80 static const char oct_stats_strings[][ETH_GSTRING_LEN] = { 81 "rx_packets", 82 "tx_packets", 83 "rx_bytes", 84 "tx_bytes", 85 "rx_errors", /*jabber_err+l2_err+frame_err */ 86 "tx_errors", /*fw_err_pko+fw_err_link+fw_err_drop */ 87 "rx_dropped", /*st->fromwire.total_rcvd - st->fromwire.fw_total_rcvd + 88 *st->fromwire.dmac_drop + st->fromwire.fw_err_drop 89 */ 90 "tx_dropped", 91 92 "tx_total_sent", 93 "tx_total_fwd", 94 "tx_err_pko", 95 "tx_err_link", 96 "tx_err_drop", 97 98 "tx_tso", 99 "tx_tso_packets", 100 "tx_tso_err", 101 "tx_vxlan", 102 103 "mac_tx_total_pkts", 104 "mac_tx_total_bytes", 105 "mac_tx_mcast_pkts", 106 "mac_tx_bcast_pkts", 107 "mac_tx_ctl_packets", /*oct->link_stats.fromhost.ctl_sent */ 108 "mac_tx_total_collisions", 109 "mac_tx_one_collision", 110 "mac_tx_multi_collison", 111 "mac_tx_max_collision_fail", 112 "mac_tx_max_deferal_fail", 113 "mac_tx_fifo_err", 114 "mac_tx_runts", 115 116 "rx_total_rcvd", 117 "rx_total_fwd", 118 "rx_jabber_err", 119 "rx_l2_err", 120 "rx_frame_err", 121 "rx_err_pko", 122 "rx_err_link", 123 "rx_err_drop", 124 125 "rx_vxlan", 126 "rx_vxlan_err", 127 128 "rx_lro_pkts", 129 "rx_lro_bytes", 130 "rx_total_lro", 131 132 "rx_lro_aborts", 133 "rx_lro_aborts_port", 134 "rx_lro_aborts_seq", 135 "rx_lro_aborts_tsval", 136 "rx_lro_aborts_timer", 137 "rx_fwd_rate", 138 139 "mac_rx_total_rcvd", 140 "mac_rx_bytes", 141 "mac_rx_total_bcst", 142 "mac_rx_total_mcst", 143 "mac_rx_runts", 144 "mac_rx_ctl_packets", 145 "mac_rx_fifo_err", 146 "mac_rx_dma_drop", 147 "mac_rx_fcs_err", 148 149 "link_state_changes", 150 }; 151 152 /* statistics of VF */ 153 static const char oct_vf_stats_strings[][ETH_GSTRING_LEN] = { 154 "rx_packets", 155 "tx_packets", 156 "rx_bytes", 157 "tx_bytes", 158 "rx_errors", /* jabber_err + l2_err+frame_err */ 159 "tx_errors", /* fw_err_pko + fw_err_link+fw_err_drop */ 160 "rx_dropped", /* total_rcvd - fw_total_rcvd + dmac_drop + fw_err_drop */ 161 "tx_dropped", 162 "link_state_changes", 163 }; 164 165 /* statistics of host tx queue */ 166 static const char oct_iq_stats_strings[][ETH_GSTRING_LEN] = { 167 "packets", /*oct->instr_queue[iq_no]->stats.tx_done*/ 168 "bytes", /*oct->instr_queue[iq_no]->stats.tx_tot_bytes*/ 169 "dropped", 170 "iq_busy", 171 "sgentry_sent", 172 173 "fw_instr_posted", 174 "fw_instr_processed", 175 "fw_instr_dropped", 176 "fw_bytes_sent", 177 178 "tso", 179 "vxlan", 180 "txq_restart", 181 }; 182 183 /* statistics of host rx queue */ 184 static const char oct_droq_stats_strings[][ETH_GSTRING_LEN] = { 185 "packets", /*oct->droq[oq_no]->stats.rx_pkts_received */ 186 "bytes", /*oct->droq[oq_no]->stats.rx_bytes_received */ 187 "dropped", /*oct->droq[oq_no]->stats.rx_dropped+ 188 *oct->droq[oq_no]->stats.dropped_nodispatch+ 189 *oct->droq[oq_no]->stats.dropped_toomany+ 190 *oct->droq[oq_no]->stats.dropped_nomem 191 */ 192 "dropped_nomem", 193 "dropped_toomany", 194 "fw_dropped", 195 "fw_pkts_received", 196 "fw_bytes_received", 197 "fw_dropped_nodispatch", 198 199 "vxlan", 200 "buffer_alloc_failure", 201 }; 202 203 /* LiquidIO driver private flags */ 204 static const char oct_priv_flags_strings[][ETH_GSTRING_LEN] = { 205 }; 206 207 #define OCTNIC_NCMD_AUTONEG_ON 0x1 208 #define OCTNIC_NCMD_PHY_ON 0x2 209 210 static int lio_get_link_ksettings(struct net_device *netdev, 211 struct ethtool_link_ksettings *ecmd) 212 { 213 struct lio *lio = GET_LIO(netdev); 214 struct octeon_device *oct = lio->oct_dev; 215 struct oct_link_info *linfo; 216 u32 supported, advertising; 217 218 linfo = &lio->linfo; 219 220 if (linfo->link.s.if_mode == INTERFACE_MODE_XAUI || 221 linfo->link.s.if_mode == INTERFACE_MODE_RXAUI || 222 linfo->link.s.if_mode == INTERFACE_MODE_XFI) { 223 ecmd->base.port = PORT_FIBRE; 224 supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE | 225 SUPPORTED_Pause); 226 advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_Pause); 227 ethtool_convert_legacy_u32_to_link_mode( 228 ecmd->link_modes.supported, supported); 229 ethtool_convert_legacy_u32_to_link_mode( 230 ecmd->link_modes.advertising, advertising); 231 ecmd->base.autoneg = AUTONEG_DISABLE; 232 233 } else { 234 dev_err(&oct->pci_dev->dev, "Unknown link interface reported %d\n", 235 linfo->link.s.if_mode); 236 } 237 238 if (linfo->link.s.link_up) { 239 ecmd->base.speed = linfo->link.s.speed; 240 ecmd->base.duplex = linfo->link.s.duplex; 241 } else { 242 ecmd->base.speed = SPEED_UNKNOWN; 243 ecmd->base.duplex = DUPLEX_UNKNOWN; 244 } 245 246 return 0; 247 } 248 249 static void 250 lio_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) 251 { 252 struct lio *lio; 253 struct octeon_device *oct; 254 255 lio = GET_LIO(netdev); 256 oct = lio->oct_dev; 257 258 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); 259 strcpy(drvinfo->driver, "liquidio"); 260 strcpy(drvinfo->version, LIQUIDIO_VERSION); 261 strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version, 262 ETHTOOL_FWVERS_LEN); 263 strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32); 264 } 265 266 static void 267 lio_get_vf_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) 268 { 269 struct octeon_device *oct; 270 struct lio *lio; 271 272 lio = GET_LIO(netdev); 273 oct = lio->oct_dev; 274 275 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); 276 strcpy(drvinfo->driver, "liquidio_vf"); 277 strcpy(drvinfo->version, LIQUIDIO_VERSION); 278 strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version, 279 ETHTOOL_FWVERS_LEN); 280 strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32); 281 } 282 283 static void 284 lio_ethtool_get_channels(struct net_device *dev, 285 struct ethtool_channels *channel) 286 { 287 struct lio *lio = GET_LIO(dev); 288 struct octeon_device *oct = lio->oct_dev; 289 u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0; 290 291 if (OCTEON_CN6XXX(oct)) { 292 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); 293 294 max_rx = CFG_GET_OQ_MAX_Q(conf6x); 295 max_tx = CFG_GET_IQ_MAX_Q(conf6x); 296 rx_count = CFG_GET_NUM_RXQS_NIC_IF(conf6x, lio->ifidx); 297 tx_count = CFG_GET_NUM_TXQS_NIC_IF(conf6x, lio->ifidx); 298 } else if (OCTEON_CN23XX_PF(oct)) { 299 struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_pf); 300 301 max_rx = CFG_GET_OQ_MAX_Q(conf23); 302 max_tx = CFG_GET_IQ_MAX_Q(conf23); 303 rx_count = CFG_GET_NUM_RXQS_NIC_IF(conf23, lio->ifidx); 304 tx_count = CFG_GET_NUM_TXQS_NIC_IF(conf23, lio->ifidx); 305 } 306 307 channel->max_rx = max_rx; 308 channel->max_tx = max_tx; 309 channel->rx_count = rx_count; 310 channel->tx_count = tx_count; 311 } 312 313 static int lio_get_eeprom_len(struct net_device *netdev) 314 { 315 u8 buf[128]; 316 struct lio *lio = GET_LIO(netdev); 317 struct octeon_device *oct_dev = lio->oct_dev; 318 struct octeon_board_info *board_info; 319 int len; 320 321 board_info = (struct octeon_board_info *)(&oct_dev->boardinfo); 322 len = sprintf(buf, "boardname:%s serialnum:%s maj:%lld min:%lld\n", 323 board_info->name, board_info->serial_number, 324 board_info->major, board_info->minor); 325 326 return len; 327 } 328 329 static int 330 lio_get_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, 331 u8 *bytes) 332 { 333 struct lio *lio = GET_LIO(netdev); 334 struct octeon_device *oct_dev = lio->oct_dev; 335 struct octeon_board_info *board_info; 336 337 if (eeprom->offset) 338 return -EINVAL; 339 340 eeprom->magic = oct_dev->pci_dev->vendor; 341 board_info = (struct octeon_board_info *)(&oct_dev->boardinfo); 342 sprintf((char *)bytes, 343 "boardname:%s serialnum:%s maj:%lld min:%lld\n", 344 board_info->name, board_info->serial_number, 345 board_info->major, board_info->minor); 346 347 return 0; 348 } 349 350 static int octnet_gpio_access(struct net_device *netdev, int addr, int val) 351 { 352 struct lio *lio = GET_LIO(netdev); 353 struct octeon_device *oct = lio->oct_dev; 354 struct octnic_ctrl_pkt nctrl; 355 int ret = 0; 356 357 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 358 359 nctrl.ncmd.u64 = 0; 360 nctrl.ncmd.s.cmd = OCTNET_CMD_GPIO_ACCESS; 361 nctrl.ncmd.s.param1 = addr; 362 nctrl.ncmd.s.param2 = val; 363 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 364 nctrl.wait_time = 100; 365 nctrl.netpndev = (u64)netdev; 366 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 367 368 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 369 if (ret < 0) { 370 dev_err(&oct->pci_dev->dev, "Failed to configure gpio value\n"); 371 return -EINVAL; 372 } 373 374 return 0; 375 } 376 377 static int octnet_id_active(struct net_device *netdev, int val) 378 { 379 struct lio *lio = GET_LIO(netdev); 380 struct octeon_device *oct = lio->oct_dev; 381 struct octnic_ctrl_pkt nctrl; 382 int ret = 0; 383 384 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 385 386 nctrl.ncmd.u64 = 0; 387 nctrl.ncmd.s.cmd = OCTNET_CMD_ID_ACTIVE; 388 nctrl.ncmd.s.param1 = val; 389 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 390 nctrl.wait_time = 100; 391 nctrl.netpndev = (u64)netdev; 392 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 393 394 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 395 if (ret < 0) { 396 dev_err(&oct->pci_dev->dev, "Failed to configure gpio value\n"); 397 return -EINVAL; 398 } 399 400 return 0; 401 } 402 403 /* Callback for when mdio command response arrives 404 */ 405 static void octnet_mdio_resp_callback(struct octeon_device *oct, 406 u32 status, 407 void *buf) 408 { 409 struct oct_mdio_cmd_context *mdio_cmd_ctx; 410 struct octeon_soft_command *sc = (struct octeon_soft_command *)buf; 411 412 mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr; 413 414 oct = lio_get_device(mdio_cmd_ctx->octeon_id); 415 if (status) { 416 dev_err(&oct->pci_dev->dev, "MIDO instruction failed. Status: %llx\n", 417 CVM_CAST64(status)); 418 WRITE_ONCE(mdio_cmd_ctx->cond, -1); 419 } else { 420 WRITE_ONCE(mdio_cmd_ctx->cond, 1); 421 } 422 wake_up_interruptible(&mdio_cmd_ctx->wc); 423 } 424 425 /* This routine provides PHY access routines for 426 * mdio clause45 . 427 */ 428 static int 429 octnet_mdio45_access(struct lio *lio, int op, int loc, int *value) 430 { 431 struct octeon_device *oct_dev = lio->oct_dev; 432 struct octeon_soft_command *sc; 433 struct oct_mdio_cmd_resp *mdio_cmd_rsp; 434 struct oct_mdio_cmd_context *mdio_cmd_ctx; 435 struct oct_mdio_cmd *mdio_cmd; 436 int retval = 0; 437 438 sc = (struct octeon_soft_command *) 439 octeon_alloc_soft_command(oct_dev, 440 sizeof(struct oct_mdio_cmd), 441 sizeof(struct oct_mdio_cmd_resp), 442 sizeof(struct oct_mdio_cmd_context)); 443 444 if (!sc) 445 return -ENOMEM; 446 447 mdio_cmd_ctx = (struct oct_mdio_cmd_context *)sc->ctxptr; 448 mdio_cmd_rsp = (struct oct_mdio_cmd_resp *)sc->virtrptr; 449 mdio_cmd = (struct oct_mdio_cmd *)sc->virtdptr; 450 451 WRITE_ONCE(mdio_cmd_ctx->cond, 0); 452 mdio_cmd_ctx->octeon_id = lio_get_device_id(oct_dev); 453 mdio_cmd->op = op; 454 mdio_cmd->mdio_addr = loc; 455 if (op) 456 mdio_cmd->value1 = *value; 457 octeon_swap_8B_data((u64 *)mdio_cmd, sizeof(struct oct_mdio_cmd) / 8); 458 459 sc->iq_no = lio->linfo.txpciq[0].s.q_no; 460 461 octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC, OPCODE_NIC_MDIO45, 462 0, 0, 0); 463 464 sc->wait_time = 1000; 465 sc->callback = octnet_mdio_resp_callback; 466 sc->callback_arg = sc; 467 468 init_waitqueue_head(&mdio_cmd_ctx->wc); 469 470 retval = octeon_send_soft_command(oct_dev, sc); 471 472 if (retval == IQ_SEND_FAILED) { 473 dev_err(&oct_dev->pci_dev->dev, 474 "octnet_mdio45_access instruction failed status: %x\n", 475 retval); 476 retval = -EBUSY; 477 } else { 478 /* Sleep on a wait queue till the cond flag indicates that the 479 * response arrived 480 */ 481 sleep_cond(&mdio_cmd_ctx->wc, &mdio_cmd_ctx->cond); 482 retval = mdio_cmd_rsp->status; 483 if (retval) { 484 dev_err(&oct_dev->pci_dev->dev, "octnet mdio45 access failed\n"); 485 retval = -EBUSY; 486 } else { 487 octeon_swap_8B_data((u64 *)(&mdio_cmd_rsp->resp), 488 sizeof(struct oct_mdio_cmd) / 8); 489 490 if (READ_ONCE(mdio_cmd_ctx->cond) == 1) { 491 if (!op) 492 *value = mdio_cmd_rsp->resp.value1; 493 } else { 494 retval = -EINVAL; 495 } 496 } 497 } 498 499 octeon_free_soft_command(oct_dev, sc); 500 501 return retval; 502 } 503 504 static int lio_set_phys_id(struct net_device *netdev, 505 enum ethtool_phys_id_state state) 506 { 507 struct lio *lio = GET_LIO(netdev); 508 struct octeon_device *oct = lio->oct_dev; 509 int value, ret; 510 511 switch (state) { 512 case ETHTOOL_ID_ACTIVE: 513 if (oct->chip_id == OCTEON_CN66XX) { 514 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG, 515 VITESSE_PHY_GPIO_DRIVEON); 516 return 2; 517 518 } else if (oct->chip_id == OCTEON_CN68XX) { 519 /* Save the current LED settings */ 520 ret = octnet_mdio45_access(lio, 0, 521 LIO68XX_LED_BEACON_ADDR, 522 &lio->phy_beacon_val); 523 if (ret) 524 return ret; 525 526 ret = octnet_mdio45_access(lio, 0, 527 LIO68XX_LED_CTRL_ADDR, 528 &lio->led_ctrl_val); 529 if (ret) 530 return ret; 531 532 /* Configure Beacon values */ 533 value = LIO68XX_LED_BEACON_CFGON; 534 ret = octnet_mdio45_access(lio, 1, 535 LIO68XX_LED_BEACON_ADDR, 536 &value); 537 if (ret) 538 return ret; 539 540 value = LIO68XX_LED_CTRL_CFGON; 541 ret = octnet_mdio45_access(lio, 1, 542 LIO68XX_LED_CTRL_ADDR, 543 &value); 544 if (ret) 545 return ret; 546 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) { 547 octnet_id_active(netdev, LED_IDENTIFICATION_ON); 548 549 /* returns 0 since updates are asynchronous */ 550 return 0; 551 } else { 552 return -EINVAL; 553 } 554 break; 555 556 case ETHTOOL_ID_ON: 557 if (oct->chip_id == OCTEON_CN66XX) { 558 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG, 559 VITESSE_PHY_GPIO_HIGH); 560 561 } else if (oct->chip_id == OCTEON_CN68XX) { 562 return -EINVAL; 563 } else { 564 return -EINVAL; 565 } 566 break; 567 568 case ETHTOOL_ID_OFF: 569 if (oct->chip_id == OCTEON_CN66XX) 570 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG, 571 VITESSE_PHY_GPIO_LOW); 572 else if (oct->chip_id == OCTEON_CN68XX) 573 return -EINVAL; 574 else 575 return -EINVAL; 576 577 break; 578 579 case ETHTOOL_ID_INACTIVE: 580 if (oct->chip_id == OCTEON_CN66XX) { 581 octnet_gpio_access(netdev, VITESSE_PHY_GPIO_CFG, 582 VITESSE_PHY_GPIO_DRIVEOFF); 583 } else if (oct->chip_id == OCTEON_CN68XX) { 584 /* Restore LED settings */ 585 ret = octnet_mdio45_access(lio, 1, 586 LIO68XX_LED_CTRL_ADDR, 587 &lio->led_ctrl_val); 588 if (ret) 589 return ret; 590 591 ret = octnet_mdio45_access(lio, 1, 592 LIO68XX_LED_BEACON_ADDR, 593 &lio->phy_beacon_val); 594 if (ret) 595 return ret; 596 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) { 597 octnet_id_active(netdev, LED_IDENTIFICATION_OFF); 598 599 return 0; 600 } else { 601 return -EINVAL; 602 } 603 break; 604 605 default: 606 return -EINVAL; 607 } 608 609 return 0; 610 } 611 612 static void 613 lio_ethtool_get_ringparam(struct net_device *netdev, 614 struct ethtool_ringparam *ering) 615 { 616 struct lio *lio = GET_LIO(netdev); 617 struct octeon_device *oct = lio->oct_dev; 618 u32 tx_max_pending = 0, rx_max_pending = 0, tx_pending = 0, 619 rx_pending = 0; 620 621 if (OCTEON_CN6XXX(oct)) { 622 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); 623 624 tx_max_pending = CN6XXX_MAX_IQ_DESCRIPTORS; 625 rx_max_pending = CN6XXX_MAX_OQ_DESCRIPTORS; 626 rx_pending = CFG_GET_NUM_RX_DESCS_NIC_IF(conf6x, lio->ifidx); 627 tx_pending = CFG_GET_NUM_TX_DESCS_NIC_IF(conf6x, lio->ifidx); 628 } else if (OCTEON_CN23XX_PF(oct)) { 629 struct octeon_config *conf23 = CHIP_CONF(oct, cn23xx_pf); 630 631 tx_max_pending = CN23XX_MAX_IQ_DESCRIPTORS; 632 rx_max_pending = CN23XX_MAX_OQ_DESCRIPTORS; 633 rx_pending = CFG_GET_NUM_RX_DESCS_NIC_IF(conf23, lio->ifidx); 634 tx_pending = CFG_GET_NUM_TX_DESCS_NIC_IF(conf23, lio->ifidx); 635 } 636 637 if (lio->mtu > OCTNET_DEFAULT_FRM_SIZE - OCTNET_FRM_HEADER_SIZE) { 638 ering->rx_pending = 0; 639 ering->rx_max_pending = 0; 640 ering->rx_mini_pending = 0; 641 ering->rx_jumbo_pending = rx_pending; 642 ering->rx_mini_max_pending = 0; 643 ering->rx_jumbo_max_pending = rx_max_pending; 644 } else { 645 ering->rx_pending = rx_pending; 646 ering->rx_max_pending = rx_max_pending; 647 ering->rx_mini_pending = 0; 648 ering->rx_jumbo_pending = 0; 649 ering->rx_mini_max_pending = 0; 650 ering->rx_jumbo_max_pending = 0; 651 } 652 653 ering->tx_pending = tx_pending; 654 ering->tx_max_pending = tx_max_pending; 655 } 656 657 static u32 lio_get_msglevel(struct net_device *netdev) 658 { 659 struct lio *lio = GET_LIO(netdev); 660 661 return lio->msg_enable; 662 } 663 664 static void lio_set_msglevel(struct net_device *netdev, u32 msglvl) 665 { 666 struct lio *lio = GET_LIO(netdev); 667 668 if ((msglvl ^ lio->msg_enable) & NETIF_MSG_HW) { 669 if (msglvl & NETIF_MSG_HW) 670 liquidio_set_feature(netdev, 671 OCTNET_CMD_VERBOSE_ENABLE, 0); 672 else 673 liquidio_set_feature(netdev, 674 OCTNET_CMD_VERBOSE_DISABLE, 0); 675 } 676 677 lio->msg_enable = msglvl; 678 } 679 680 static void 681 lio_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) 682 { 683 /* Notes: Not supporting any auto negotiation in these 684 * drivers. Just report pause frame support. 685 */ 686 struct lio *lio = GET_LIO(netdev); 687 struct octeon_device *oct = lio->oct_dev; 688 689 pause->autoneg = 0; 690 691 pause->tx_pause = oct->tx_pause; 692 pause->rx_pause = oct->rx_pause; 693 } 694 695 static int 696 lio_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) 697 { 698 /* Notes: Not supporting any auto negotiation in these 699 * drivers. 700 */ 701 struct lio *lio = GET_LIO(netdev); 702 struct octeon_device *oct = lio->oct_dev; 703 struct octnic_ctrl_pkt nctrl; 704 struct oct_link_info *linfo = &lio->linfo; 705 706 int ret = 0; 707 708 if (oct->chip_id != OCTEON_CN23XX_PF_VID) 709 return -EINVAL; 710 711 if (linfo->link.s.duplex == 0) { 712 /*no flow control for half duplex*/ 713 if (pause->rx_pause || pause->tx_pause) 714 return -EINVAL; 715 } 716 717 /*do not support autoneg of link flow control*/ 718 if (pause->autoneg == AUTONEG_ENABLE) 719 return -EINVAL; 720 721 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); 722 723 nctrl.ncmd.u64 = 0; 724 nctrl.ncmd.s.cmd = OCTNET_CMD_SET_FLOW_CTL; 725 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; 726 nctrl.wait_time = 100; 727 nctrl.netpndev = (u64)netdev; 728 nctrl.cb_fn = liquidio_link_ctrl_cmd_completion; 729 730 if (pause->rx_pause) { 731 /*enable rx pause*/ 732 nctrl.ncmd.s.param1 = 1; 733 } else { 734 /*disable rx pause*/ 735 nctrl.ncmd.s.param1 = 0; 736 } 737 738 if (pause->tx_pause) { 739 /*enable tx pause*/ 740 nctrl.ncmd.s.param2 = 1; 741 } else { 742 /*disable tx pause*/ 743 nctrl.ncmd.s.param2 = 0; 744 } 745 746 ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl); 747 if (ret < 0) { 748 dev_err(&oct->pci_dev->dev, "Failed to set pause parameter\n"); 749 return -EINVAL; 750 } 751 752 oct->rx_pause = pause->rx_pause; 753 oct->tx_pause = pause->tx_pause; 754 755 return 0; 756 } 757 758 static void 759 lio_get_ethtool_stats(struct net_device *netdev, 760 struct ethtool_stats *stats __attribute__((unused)), 761 u64 *data) 762 { 763 struct lio *lio = GET_LIO(netdev); 764 struct octeon_device *oct_dev = lio->oct_dev; 765 struct net_device_stats *netstats = &netdev->stats; 766 int i = 0, j; 767 768 netdev->netdev_ops->ndo_get_stats(netdev); 769 octnet_get_link_stats(netdev); 770 771 /*sum of oct->droq[oq_no]->stats->rx_pkts_received */ 772 data[i++] = CVM_CAST64(netstats->rx_packets); 773 /*sum of oct->instr_queue[iq_no]->stats.tx_done */ 774 data[i++] = CVM_CAST64(netstats->tx_packets); 775 /*sum of oct->droq[oq_no]->stats->rx_bytes_received */ 776 data[i++] = CVM_CAST64(netstats->rx_bytes); 777 /*sum of oct->instr_queue[iq_no]->stats.tx_tot_bytes */ 778 data[i++] = CVM_CAST64(netstats->tx_bytes); 779 data[i++] = CVM_CAST64(netstats->rx_errors); 780 data[i++] = CVM_CAST64(netstats->tx_errors); 781 /*sum of oct->droq[oq_no]->stats->rx_dropped + 782 *oct->droq[oq_no]->stats->dropped_nodispatch + 783 *oct->droq[oq_no]->stats->dropped_toomany + 784 *oct->droq[oq_no]->stats->dropped_nomem 785 */ 786 data[i++] = CVM_CAST64(netstats->rx_dropped); 787 /*sum of oct->instr_queue[iq_no]->stats.tx_dropped */ 788 data[i++] = CVM_CAST64(netstats->tx_dropped); 789 790 /* firmware tx stats */ 791 /*per_core_stats[cvmx_get_core_num()].link_stats[mdata->from_ifidx]. 792 *fromhost.fw_total_sent 793 */ 794 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_total_sent); 795 /*per_core_stats[i].link_stats[port].fromwire.fw_total_fwd */ 796 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_total_fwd); 797 /*per_core_stats[j].link_stats[i].fromhost.fw_err_pko */ 798 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_pko); 799 /*per_core_stats[j].link_stats[i].fromhost.fw_err_link */ 800 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_link); 801 /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost. 802 *fw_err_drop 803 */ 804 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_drop); 805 806 /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost.fw_tso */ 807 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tso); 808 /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost. 809 *fw_tso_fwd 810 */ 811 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tso_fwd); 812 /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost. 813 *fw_err_tso 814 */ 815 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_err_tso); 816 /*per_core_stats[cvmx_get_core_num()].link_stats[idx].fromhost. 817 *fw_tx_vxlan 818 */ 819 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fw_tx_vxlan); 820 821 /* mac tx statistics */ 822 /*CVMX_BGXX_CMRX_TX_STAT5 */ 823 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_pkts_sent); 824 /*CVMX_BGXX_CMRX_TX_STAT4 */ 825 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_bytes_sent); 826 /*CVMX_BGXX_CMRX_TX_STAT15 */ 827 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.mcast_pkts_sent); 828 /*CVMX_BGXX_CMRX_TX_STAT14 */ 829 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.bcast_pkts_sent); 830 /*CVMX_BGXX_CMRX_TX_STAT17 */ 831 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.ctl_sent); 832 /*CVMX_BGXX_CMRX_TX_STAT0 */ 833 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.total_collisions); 834 /*CVMX_BGXX_CMRX_TX_STAT3 */ 835 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.one_collision_sent); 836 /*CVMX_BGXX_CMRX_TX_STAT2 */ 837 data[i++] = 838 CVM_CAST64(oct_dev->link_stats.fromhost.multi_collision_sent); 839 /*CVMX_BGXX_CMRX_TX_STAT0 */ 840 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.max_collision_fail); 841 /*CVMX_BGXX_CMRX_TX_STAT1 */ 842 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.max_deferral_fail); 843 /*CVMX_BGXX_CMRX_TX_STAT16 */ 844 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.fifo_err); 845 /*CVMX_BGXX_CMRX_TX_STAT6 */ 846 data[i++] = CVM_CAST64(oct_dev->link_stats.fromhost.runts); 847 848 /* RX firmware stats */ 849 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 850 *fw_total_rcvd 851 */ 852 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_rcvd); 853 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 854 *fw_total_fwd 855 */ 856 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_fwd); 857 /*per_core_stats[core_id].link_stats[ifidx].fromwire.jabber_err */ 858 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.jabber_err); 859 /*per_core_stats[core_id].link_stats[ifidx].fromwire.l2_err */ 860 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.l2_err); 861 /*per_core_stats[core_id].link_stats[ifidx].fromwire.frame_err */ 862 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.frame_err); 863 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 864 *fw_err_pko 865 */ 866 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_pko); 867 /*per_core_stats[j].link_stats[i].fromwire.fw_err_link */ 868 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_link); 869 /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx]. 870 *fromwire.fw_err_drop 871 */ 872 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_err_drop); 873 874 /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx]. 875 *fromwire.fw_rx_vxlan 876 */ 877 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_rx_vxlan); 878 /*per_core_stats[cvmx_get_core_num()].link_stats[lro_ctx->ifidx]. 879 *fromwire.fw_rx_vxlan_err 880 */ 881 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_rx_vxlan_err); 882 883 /* LRO */ 884 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 885 *fw_lro_pkts 886 */ 887 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_pkts); 888 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 889 *fw_lro_octs 890 */ 891 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_octs); 892 /*per_core_stats[j].link_stats[i].fromwire.fw_total_lro */ 893 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_total_lro); 894 /*per_core_stats[j].link_stats[i].fromwire.fw_lro_aborts */ 895 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts); 896 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 897 *fw_lro_aborts_port 898 */ 899 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_port); 900 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 901 *fw_lro_aborts_seq 902 */ 903 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_seq); 904 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 905 *fw_lro_aborts_tsval 906 */ 907 data[i++] = 908 CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_tsval); 909 /*per_core_stats[cvmx_get_core_num()].link_stats[ifidx].fromwire. 910 *fw_lro_aborts_timer 911 */ 912 /* intrmod: packet forward rate */ 913 data[i++] = 914 CVM_CAST64(oct_dev->link_stats.fromwire.fw_lro_aborts_timer); 915 /*per_core_stats[j].link_stats[i].fromwire.fw_lro_aborts */ 916 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fwd_rate); 917 918 /* mac: link-level stats */ 919 /*CVMX_BGXX_CMRX_RX_STAT0 */ 920 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_rcvd); 921 /*CVMX_BGXX_CMRX_RX_STAT1 */ 922 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.bytes_rcvd); 923 /*CVMX_PKI_STATX_STAT5 */ 924 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_bcst); 925 /*CVMX_PKI_STATX_STAT5 */ 926 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.total_mcst); 927 /*wqe->word2.err_code or wqe->word2.err_level */ 928 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.runts); 929 /*CVMX_BGXX_CMRX_RX_STAT2 */ 930 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.ctl_rcvd); 931 /*CVMX_BGXX_CMRX_RX_STAT6 */ 932 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fifo_err); 933 /*CVMX_BGXX_CMRX_RX_STAT4 */ 934 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.dmac_drop); 935 /*wqe->word2.err_code or wqe->word2.err_level */ 936 data[i++] = CVM_CAST64(oct_dev->link_stats.fromwire.fcs_err); 937 /*lio->link_changes*/ 938 data[i++] = CVM_CAST64(lio->link_changes); 939 940 for (j = 0; j < MAX_OCTEON_INSTR_QUEUES(oct_dev); j++) { 941 if (!(oct_dev->io_qmask.iq & BIT_ULL(j))) 942 continue; 943 /*packets to network port*/ 944 /*# of packets tx to network */ 945 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_done); 946 /*# of bytes tx to network */ 947 data[i++] = 948 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_tot_bytes); 949 /*# of packets dropped */ 950 data[i++] = 951 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_dropped); 952 /*# of tx fails due to queue full */ 953 data[i++] = 954 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_iq_busy); 955 /*XXX gather entries sent */ 956 data[i++] = 957 CVM_CAST64(oct_dev->instr_queue[j]->stats.sgentry_sent); 958 959 /*instruction to firmware: data and control */ 960 /*# of instructions to the queue */ 961 data[i++] = 962 CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_posted); 963 /*# of instructions processed */ 964 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]-> 965 stats.instr_processed); 966 /*# of instructions could not be processed */ 967 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]-> 968 stats.instr_dropped); 969 /*bytes sent through the queue */ 970 data[i++] = 971 CVM_CAST64(oct_dev->instr_queue[j]->stats.bytes_sent); 972 973 /*tso request*/ 974 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_gso); 975 /*vxlan request*/ 976 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_vxlan); 977 /*txq restart*/ 978 data[i++] = 979 CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_restart); 980 } 981 982 /* RX */ 983 for (j = 0; j < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); j++) { 984 if (!(oct_dev->io_qmask.oq & BIT_ULL(j))) 985 continue; 986 987 /*packets send to TCP/IP network stack */ 988 /*# of packets to network stack */ 989 data[i++] = 990 CVM_CAST64(oct_dev->droq[j]->stats.rx_pkts_received); 991 /*# of bytes to network stack */ 992 data[i++] = 993 CVM_CAST64(oct_dev->droq[j]->stats.rx_bytes_received); 994 /*# of packets dropped */ 995 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem + 996 oct_dev->droq[j]->stats.dropped_toomany + 997 oct_dev->droq[j]->stats.rx_dropped); 998 data[i++] = 999 CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem); 1000 data[i++] = 1001 CVM_CAST64(oct_dev->droq[j]->stats.dropped_toomany); 1002 data[i++] = 1003 CVM_CAST64(oct_dev->droq[j]->stats.rx_dropped); 1004 1005 /*control and data path*/ 1006 data[i++] = 1007 CVM_CAST64(oct_dev->droq[j]->stats.pkts_received); 1008 data[i++] = 1009 CVM_CAST64(oct_dev->droq[j]->stats.bytes_received); 1010 data[i++] = 1011 CVM_CAST64(oct_dev->droq[j]->stats.dropped_nodispatch); 1012 1013 data[i++] = 1014 CVM_CAST64(oct_dev->droq[j]->stats.rx_vxlan); 1015 data[i++] = 1016 CVM_CAST64(oct_dev->droq[j]->stats.rx_alloc_failure); 1017 } 1018 } 1019 1020 static void lio_vf_get_ethtool_stats(struct net_device *netdev, 1021 struct ethtool_stats *stats 1022 __attribute__((unused)), 1023 u64 *data) 1024 { 1025 struct net_device_stats *netstats = &netdev->stats; 1026 struct lio *lio = GET_LIO(netdev); 1027 struct octeon_device *oct_dev = lio->oct_dev; 1028 int i = 0, j, vj; 1029 1030 netdev->netdev_ops->ndo_get_stats(netdev); 1031 /* sum of oct->droq[oq_no]->stats->rx_pkts_received */ 1032 data[i++] = CVM_CAST64(netstats->rx_packets); 1033 /* sum of oct->instr_queue[iq_no]->stats.tx_done */ 1034 data[i++] = CVM_CAST64(netstats->tx_packets); 1035 /* sum of oct->droq[oq_no]->stats->rx_bytes_received */ 1036 data[i++] = CVM_CAST64(netstats->rx_bytes); 1037 /* sum of oct->instr_queue[iq_no]->stats.tx_tot_bytes */ 1038 data[i++] = CVM_CAST64(netstats->tx_bytes); 1039 data[i++] = CVM_CAST64(netstats->rx_errors); 1040 data[i++] = CVM_CAST64(netstats->tx_errors); 1041 /* sum of oct->droq[oq_no]->stats->rx_dropped + 1042 * oct->droq[oq_no]->stats->dropped_nodispatch + 1043 * oct->droq[oq_no]->stats->dropped_toomany + 1044 * oct->droq[oq_no]->stats->dropped_nomem 1045 */ 1046 data[i++] = CVM_CAST64(netstats->rx_dropped); 1047 /* sum of oct->instr_queue[iq_no]->stats.tx_dropped */ 1048 data[i++] = CVM_CAST64(netstats->tx_dropped); 1049 /* lio->link_changes */ 1050 data[i++] = CVM_CAST64(lio->link_changes); 1051 1052 for (vj = 0; vj < lio->linfo.num_txpciq; vj++) { 1053 j = lio->linfo.txpciq[vj].s.q_no; 1054 1055 /* packets to network port */ 1056 /* # of packets tx to network */ 1057 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_done); 1058 /* # of bytes tx to network */ 1059 data[i++] = CVM_CAST64( 1060 oct_dev->instr_queue[j]->stats.tx_tot_bytes); 1061 /* # of packets dropped */ 1062 data[i++] = CVM_CAST64( 1063 oct_dev->instr_queue[j]->stats.tx_dropped); 1064 /* # of tx fails due to queue full */ 1065 data[i++] = CVM_CAST64( 1066 oct_dev->instr_queue[j]->stats.tx_iq_busy); 1067 /* XXX gather entries sent */ 1068 data[i++] = CVM_CAST64( 1069 oct_dev->instr_queue[j]->stats.sgentry_sent); 1070 1071 /* instruction to firmware: data and control */ 1072 /* # of instructions to the queue */ 1073 data[i++] = CVM_CAST64( 1074 oct_dev->instr_queue[j]->stats.instr_posted); 1075 /* # of instructions processed */ 1076 data[i++] = 1077 CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_processed); 1078 /* # of instructions could not be processed */ 1079 data[i++] = 1080 CVM_CAST64(oct_dev->instr_queue[j]->stats.instr_dropped); 1081 /* bytes sent through the queue */ 1082 data[i++] = CVM_CAST64( 1083 oct_dev->instr_queue[j]->stats.bytes_sent); 1084 /* tso request */ 1085 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_gso); 1086 /* vxlan request */ 1087 data[i++] = CVM_CAST64(oct_dev->instr_queue[j]->stats.tx_vxlan); 1088 /* txq restart */ 1089 data[i++] = CVM_CAST64( 1090 oct_dev->instr_queue[j]->stats.tx_restart); 1091 } 1092 1093 /* RX */ 1094 for (vj = 0; vj < lio->linfo.num_rxpciq; vj++) { 1095 j = lio->linfo.rxpciq[vj].s.q_no; 1096 1097 /* packets send to TCP/IP network stack */ 1098 /* # of packets to network stack */ 1099 data[i++] = CVM_CAST64( 1100 oct_dev->droq[j]->stats.rx_pkts_received); 1101 /* # of bytes to network stack */ 1102 data[i++] = CVM_CAST64( 1103 oct_dev->droq[j]->stats.rx_bytes_received); 1104 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem + 1105 oct_dev->droq[j]->stats.dropped_toomany + 1106 oct_dev->droq[j]->stats.rx_dropped); 1107 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_nomem); 1108 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.dropped_toomany); 1109 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.rx_dropped); 1110 1111 /* control and data path */ 1112 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.pkts_received); 1113 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.bytes_received); 1114 data[i++] = 1115 CVM_CAST64(oct_dev->droq[j]->stats.dropped_nodispatch); 1116 1117 data[i++] = CVM_CAST64(oct_dev->droq[j]->stats.rx_vxlan); 1118 data[i++] = 1119 CVM_CAST64(oct_dev->droq[j]->stats.rx_alloc_failure); 1120 } 1121 } 1122 1123 static void lio_get_priv_flags_strings(struct lio *lio, u8 *data) 1124 { 1125 struct octeon_device *oct_dev = lio->oct_dev; 1126 int i; 1127 1128 switch (oct_dev->chip_id) { 1129 case OCTEON_CN23XX_PF_VID: 1130 case OCTEON_CN23XX_VF_VID: 1131 for (i = 0; i < ARRAY_SIZE(oct_priv_flags_strings); i++) { 1132 sprintf(data, "%s", oct_priv_flags_strings[i]); 1133 data += ETH_GSTRING_LEN; 1134 } 1135 break; 1136 case OCTEON_CN68XX: 1137 case OCTEON_CN66XX: 1138 break; 1139 default: 1140 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n"); 1141 break; 1142 } 1143 } 1144 1145 static void lio_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 1146 { 1147 struct lio *lio = GET_LIO(netdev); 1148 struct octeon_device *oct_dev = lio->oct_dev; 1149 int num_iq_stats, num_oq_stats, i, j; 1150 int num_stats; 1151 1152 switch (stringset) { 1153 case ETH_SS_STATS: 1154 num_stats = ARRAY_SIZE(oct_stats_strings); 1155 for (j = 0; j < num_stats; j++) { 1156 sprintf(data, "%s", oct_stats_strings[j]); 1157 data += ETH_GSTRING_LEN; 1158 } 1159 1160 num_iq_stats = ARRAY_SIZE(oct_iq_stats_strings); 1161 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { 1162 if (!(oct_dev->io_qmask.iq & BIT_ULL(i))) 1163 continue; 1164 for (j = 0; j < num_iq_stats; j++) { 1165 sprintf(data, "tx-%d-%s", i, 1166 oct_iq_stats_strings[j]); 1167 data += ETH_GSTRING_LEN; 1168 } 1169 } 1170 1171 num_oq_stats = ARRAY_SIZE(oct_droq_stats_strings); 1172 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { 1173 if (!(oct_dev->io_qmask.oq & BIT_ULL(i))) 1174 continue; 1175 for (j = 0; j < num_oq_stats; j++) { 1176 sprintf(data, "rx-%d-%s", i, 1177 oct_droq_stats_strings[j]); 1178 data += ETH_GSTRING_LEN; 1179 } 1180 } 1181 break; 1182 1183 case ETH_SS_PRIV_FLAGS: 1184 lio_get_priv_flags_strings(lio, data); 1185 break; 1186 default: 1187 netif_info(lio, drv, lio->netdev, "Unknown Stringset !!\n"); 1188 break; 1189 } 1190 } 1191 1192 static void lio_vf_get_strings(struct net_device *netdev, u32 stringset, 1193 u8 *data) 1194 { 1195 int num_iq_stats, num_oq_stats, i, j; 1196 struct lio *lio = GET_LIO(netdev); 1197 struct octeon_device *oct_dev = lio->oct_dev; 1198 int num_stats; 1199 1200 switch (stringset) { 1201 case ETH_SS_STATS: 1202 num_stats = ARRAY_SIZE(oct_vf_stats_strings); 1203 for (j = 0; j < num_stats; j++) { 1204 sprintf(data, "%s", oct_vf_stats_strings[j]); 1205 data += ETH_GSTRING_LEN; 1206 } 1207 1208 num_iq_stats = ARRAY_SIZE(oct_iq_stats_strings); 1209 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { 1210 if (!(oct_dev->io_qmask.iq & BIT_ULL(i))) 1211 continue; 1212 for (j = 0; j < num_iq_stats; j++) { 1213 sprintf(data, "tx-%d-%s", i, 1214 oct_iq_stats_strings[j]); 1215 data += ETH_GSTRING_LEN; 1216 } 1217 } 1218 1219 num_oq_stats = ARRAY_SIZE(oct_droq_stats_strings); 1220 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { 1221 if (!(oct_dev->io_qmask.oq & BIT_ULL(i))) 1222 continue; 1223 for (j = 0; j < num_oq_stats; j++) { 1224 sprintf(data, "rx-%d-%s", i, 1225 oct_droq_stats_strings[j]); 1226 data += ETH_GSTRING_LEN; 1227 } 1228 } 1229 break; 1230 1231 case ETH_SS_PRIV_FLAGS: 1232 lio_get_priv_flags_strings(lio, data); 1233 break; 1234 default: 1235 netif_info(lio, drv, lio->netdev, "Unknown Stringset !!\n"); 1236 break; 1237 } 1238 } 1239 1240 static int lio_get_priv_flags_ss_count(struct lio *lio) 1241 { 1242 struct octeon_device *oct_dev = lio->oct_dev; 1243 1244 switch (oct_dev->chip_id) { 1245 case OCTEON_CN23XX_PF_VID: 1246 case OCTEON_CN23XX_VF_VID: 1247 return ARRAY_SIZE(oct_priv_flags_strings); 1248 case OCTEON_CN68XX: 1249 case OCTEON_CN66XX: 1250 return -EOPNOTSUPP; 1251 default: 1252 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n"); 1253 return -EOPNOTSUPP; 1254 } 1255 } 1256 1257 static int lio_get_sset_count(struct net_device *netdev, int sset) 1258 { 1259 struct lio *lio = GET_LIO(netdev); 1260 struct octeon_device *oct_dev = lio->oct_dev; 1261 1262 switch (sset) { 1263 case ETH_SS_STATS: 1264 return (ARRAY_SIZE(oct_stats_strings) + 1265 ARRAY_SIZE(oct_iq_stats_strings) * oct_dev->num_iqs + 1266 ARRAY_SIZE(oct_droq_stats_strings) * oct_dev->num_oqs); 1267 case ETH_SS_PRIV_FLAGS: 1268 return lio_get_priv_flags_ss_count(lio); 1269 default: 1270 return -EOPNOTSUPP; 1271 } 1272 } 1273 1274 static int lio_vf_get_sset_count(struct net_device *netdev, int sset) 1275 { 1276 struct lio *lio = GET_LIO(netdev); 1277 struct octeon_device *oct_dev = lio->oct_dev; 1278 1279 switch (sset) { 1280 case ETH_SS_STATS: 1281 return (ARRAY_SIZE(oct_vf_stats_strings) + 1282 ARRAY_SIZE(oct_iq_stats_strings) * oct_dev->num_iqs + 1283 ARRAY_SIZE(oct_droq_stats_strings) * oct_dev->num_oqs); 1284 case ETH_SS_PRIV_FLAGS: 1285 return lio_get_priv_flags_ss_count(lio); 1286 default: 1287 return -EOPNOTSUPP; 1288 } 1289 } 1290 1291 static int lio_get_intr_coalesce(struct net_device *netdev, 1292 struct ethtool_coalesce *intr_coal) 1293 { 1294 struct lio *lio = GET_LIO(netdev); 1295 struct octeon_device *oct = lio->oct_dev; 1296 struct octeon_instr_queue *iq; 1297 struct oct_intrmod_cfg *intrmod_cfg; 1298 1299 intrmod_cfg = &oct->intrmod; 1300 1301 switch (oct->chip_id) { 1302 case OCTEON_CN23XX_PF_VID: 1303 case OCTEON_CN23XX_VF_VID: 1304 if (!intrmod_cfg->rx_enable) { 1305 intr_coal->rx_coalesce_usecs = intrmod_cfg->rx_usecs; 1306 intr_coal->rx_max_coalesced_frames = 1307 intrmod_cfg->rx_frames; 1308 } 1309 if (!intrmod_cfg->tx_enable) 1310 intr_coal->tx_max_coalesced_frames = 1311 intrmod_cfg->tx_frames; 1312 break; 1313 case OCTEON_CN68XX: 1314 case OCTEON_CN66XX: { 1315 struct octeon_cn6xxx *cn6xxx = 1316 (struct octeon_cn6xxx *)oct->chip; 1317 1318 if (!intrmod_cfg->rx_enable) { 1319 intr_coal->rx_coalesce_usecs = 1320 CFG_GET_OQ_INTR_TIME(cn6xxx->conf); 1321 intr_coal->rx_max_coalesced_frames = 1322 CFG_GET_OQ_INTR_PKT(cn6xxx->conf); 1323 } 1324 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no]; 1325 intr_coal->tx_max_coalesced_frames = iq->fill_threshold; 1326 break; 1327 } 1328 default: 1329 netif_info(lio, drv, lio->netdev, "Unknown Chip !!\n"); 1330 return -EINVAL; 1331 } 1332 if (intrmod_cfg->rx_enable) { 1333 intr_coal->use_adaptive_rx_coalesce = 1334 intrmod_cfg->rx_enable; 1335 intr_coal->rate_sample_interval = 1336 intrmod_cfg->check_intrvl; 1337 intr_coal->pkt_rate_high = 1338 intrmod_cfg->maxpkt_ratethr; 1339 intr_coal->pkt_rate_low = 1340 intrmod_cfg->minpkt_ratethr; 1341 intr_coal->rx_max_coalesced_frames_high = 1342 intrmod_cfg->rx_maxcnt_trigger; 1343 intr_coal->rx_coalesce_usecs_high = 1344 intrmod_cfg->rx_maxtmr_trigger; 1345 intr_coal->rx_coalesce_usecs_low = 1346 intrmod_cfg->rx_mintmr_trigger; 1347 intr_coal->rx_max_coalesced_frames_low = 1348 intrmod_cfg->rx_mincnt_trigger; 1349 } 1350 if ((OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) && 1351 (intrmod_cfg->tx_enable)) { 1352 intr_coal->use_adaptive_tx_coalesce = intrmod_cfg->tx_enable; 1353 intr_coal->tx_max_coalesced_frames_high = 1354 intrmod_cfg->tx_maxcnt_trigger; 1355 intr_coal->tx_max_coalesced_frames_low = 1356 intrmod_cfg->tx_mincnt_trigger; 1357 } 1358 return 0; 1359 } 1360 1361 /* Callback function for intrmod */ 1362 static void octnet_intrmod_callback(struct octeon_device *oct_dev, 1363 u32 status, 1364 void *ptr) 1365 { 1366 struct oct_intrmod_cmd *cmd = ptr; 1367 struct octeon_soft_command *sc = cmd->sc; 1368 1369 oct_dev = cmd->oct_dev; 1370 1371 if (status) 1372 dev_err(&oct_dev->pci_dev->dev, "intrmod config failed. Status: %llx\n", 1373 CVM_CAST64(status)); 1374 else 1375 dev_info(&oct_dev->pci_dev->dev, 1376 "Rx-Adaptive Interrupt moderation enabled:%llx\n", 1377 oct_dev->intrmod.rx_enable); 1378 1379 octeon_free_soft_command(oct_dev, sc); 1380 } 1381 1382 /* Configure interrupt moderation parameters */ 1383 static int octnet_set_intrmod_cfg(struct lio *lio, 1384 struct oct_intrmod_cfg *intr_cfg) 1385 { 1386 struct octeon_soft_command *sc; 1387 struct oct_intrmod_cmd *cmd; 1388 struct oct_intrmod_cfg *cfg; 1389 int retval; 1390 struct octeon_device *oct_dev = lio->oct_dev; 1391 1392 /* Alloc soft command */ 1393 sc = (struct octeon_soft_command *) 1394 octeon_alloc_soft_command(oct_dev, 1395 sizeof(struct oct_intrmod_cfg), 1396 0, 1397 sizeof(struct oct_intrmod_cmd)); 1398 1399 if (!sc) 1400 return -ENOMEM; 1401 1402 cmd = (struct oct_intrmod_cmd *)sc->ctxptr; 1403 cfg = (struct oct_intrmod_cfg *)sc->virtdptr; 1404 1405 memcpy(cfg, intr_cfg, sizeof(struct oct_intrmod_cfg)); 1406 octeon_swap_8B_data((u64 *)cfg, (sizeof(struct oct_intrmod_cfg)) / 8); 1407 cmd->sc = sc; 1408 cmd->cfg = cfg; 1409 cmd->oct_dev = oct_dev; 1410 1411 sc->iq_no = lio->linfo.txpciq[0].s.q_no; 1412 1413 octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC, 1414 OPCODE_NIC_INTRMOD_CFG, 0, 0, 0); 1415 1416 sc->callback = octnet_intrmod_callback; 1417 sc->callback_arg = cmd; 1418 sc->wait_time = 1000; 1419 1420 retval = octeon_send_soft_command(oct_dev, sc); 1421 if (retval == IQ_SEND_FAILED) { 1422 octeon_free_soft_command(oct_dev, sc); 1423 return -EINVAL; 1424 } 1425 1426 return 0; 1427 } 1428 1429 static void 1430 octnet_nic_stats_callback(struct octeon_device *oct_dev, 1431 u32 status, void *ptr) 1432 { 1433 struct octeon_soft_command *sc = (struct octeon_soft_command *)ptr; 1434 struct oct_nic_stats_resp *resp = 1435 (struct oct_nic_stats_resp *)sc->virtrptr; 1436 struct oct_nic_stats_ctrl *ctrl = 1437 (struct oct_nic_stats_ctrl *)sc->ctxptr; 1438 struct nic_rx_stats *rsp_rstats = &resp->stats.fromwire; 1439 struct nic_tx_stats *rsp_tstats = &resp->stats.fromhost; 1440 1441 struct nic_rx_stats *rstats = &oct_dev->link_stats.fromwire; 1442 struct nic_tx_stats *tstats = &oct_dev->link_stats.fromhost; 1443 1444 if ((status != OCTEON_REQUEST_TIMEOUT) && !resp->status) { 1445 octeon_swap_8B_data((u64 *)&resp->stats, 1446 (sizeof(struct oct_link_stats)) >> 3); 1447 1448 /* RX link-level stats */ 1449 rstats->total_rcvd = rsp_rstats->total_rcvd; 1450 rstats->bytes_rcvd = rsp_rstats->bytes_rcvd; 1451 rstats->total_bcst = rsp_rstats->total_bcst; 1452 rstats->total_mcst = rsp_rstats->total_mcst; 1453 rstats->runts = rsp_rstats->runts; 1454 rstats->ctl_rcvd = rsp_rstats->ctl_rcvd; 1455 /* Accounts for over/under-run of buffers */ 1456 rstats->fifo_err = rsp_rstats->fifo_err; 1457 rstats->dmac_drop = rsp_rstats->dmac_drop; 1458 rstats->fcs_err = rsp_rstats->fcs_err; 1459 rstats->jabber_err = rsp_rstats->jabber_err; 1460 rstats->l2_err = rsp_rstats->l2_err; 1461 rstats->frame_err = rsp_rstats->frame_err; 1462 1463 /* RX firmware stats */ 1464 rstats->fw_total_rcvd = rsp_rstats->fw_total_rcvd; 1465 rstats->fw_total_fwd = rsp_rstats->fw_total_fwd; 1466 rstats->fw_err_pko = rsp_rstats->fw_err_pko; 1467 rstats->fw_err_link = rsp_rstats->fw_err_link; 1468 rstats->fw_err_drop = rsp_rstats->fw_err_drop; 1469 rstats->fw_rx_vxlan = rsp_rstats->fw_rx_vxlan; 1470 rstats->fw_rx_vxlan_err = rsp_rstats->fw_rx_vxlan_err; 1471 1472 /* Number of packets that are LROed */ 1473 rstats->fw_lro_pkts = rsp_rstats->fw_lro_pkts; 1474 /* Number of octets that are LROed */ 1475 rstats->fw_lro_octs = rsp_rstats->fw_lro_octs; 1476 /* Number of LRO packets formed */ 1477 rstats->fw_total_lro = rsp_rstats->fw_total_lro; 1478 /* Number of times lRO of packet aborted */ 1479 rstats->fw_lro_aborts = rsp_rstats->fw_lro_aborts; 1480 rstats->fw_lro_aborts_port = rsp_rstats->fw_lro_aborts_port; 1481 rstats->fw_lro_aborts_seq = rsp_rstats->fw_lro_aborts_seq; 1482 rstats->fw_lro_aborts_tsval = rsp_rstats->fw_lro_aborts_tsval; 1483 rstats->fw_lro_aborts_timer = rsp_rstats->fw_lro_aborts_timer; 1484 /* intrmod: packet forward rate */ 1485 rstats->fwd_rate = rsp_rstats->fwd_rate; 1486 1487 /* TX link-level stats */ 1488 tstats->total_pkts_sent = rsp_tstats->total_pkts_sent; 1489 tstats->total_bytes_sent = rsp_tstats->total_bytes_sent; 1490 tstats->mcast_pkts_sent = rsp_tstats->mcast_pkts_sent; 1491 tstats->bcast_pkts_sent = rsp_tstats->bcast_pkts_sent; 1492 tstats->ctl_sent = rsp_tstats->ctl_sent; 1493 /* Packets sent after one collision*/ 1494 tstats->one_collision_sent = rsp_tstats->one_collision_sent; 1495 /* Packets sent after multiple collision*/ 1496 tstats->multi_collision_sent = rsp_tstats->multi_collision_sent; 1497 /* Packets not sent due to max collisions */ 1498 tstats->max_collision_fail = rsp_tstats->max_collision_fail; 1499 /* Packets not sent due to max deferrals */ 1500 tstats->max_deferral_fail = rsp_tstats->max_deferral_fail; 1501 /* Accounts for over/under-run of buffers */ 1502 tstats->fifo_err = rsp_tstats->fifo_err; 1503 tstats->runts = rsp_tstats->runts; 1504 /* Total number of collisions detected */ 1505 tstats->total_collisions = rsp_tstats->total_collisions; 1506 1507 /* firmware stats */ 1508 tstats->fw_total_sent = rsp_tstats->fw_total_sent; 1509 tstats->fw_total_fwd = rsp_tstats->fw_total_fwd; 1510 tstats->fw_err_pko = rsp_tstats->fw_err_pko; 1511 tstats->fw_err_link = rsp_tstats->fw_err_link; 1512 tstats->fw_err_drop = rsp_tstats->fw_err_drop; 1513 tstats->fw_tso = rsp_tstats->fw_tso; 1514 tstats->fw_tso_fwd = rsp_tstats->fw_tso_fwd; 1515 tstats->fw_err_tso = rsp_tstats->fw_err_tso; 1516 tstats->fw_tx_vxlan = rsp_tstats->fw_tx_vxlan; 1517 1518 resp->status = 1; 1519 } else { 1520 resp->status = -1; 1521 } 1522 complete(&ctrl->complete); 1523 } 1524 1525 /* Configure interrupt moderation parameters */ 1526 static int octnet_get_link_stats(struct net_device *netdev) 1527 { 1528 struct lio *lio = GET_LIO(netdev); 1529 struct octeon_device *oct_dev = lio->oct_dev; 1530 1531 struct octeon_soft_command *sc; 1532 struct oct_nic_stats_ctrl *ctrl; 1533 struct oct_nic_stats_resp *resp; 1534 1535 int retval; 1536 1537 /* Alloc soft command */ 1538 sc = (struct octeon_soft_command *) 1539 octeon_alloc_soft_command(oct_dev, 1540 0, 1541 sizeof(struct oct_nic_stats_resp), 1542 sizeof(struct octnic_ctrl_pkt)); 1543 1544 if (!sc) 1545 return -ENOMEM; 1546 1547 resp = (struct oct_nic_stats_resp *)sc->virtrptr; 1548 memset(resp, 0, sizeof(struct oct_nic_stats_resp)); 1549 1550 ctrl = (struct oct_nic_stats_ctrl *)sc->ctxptr; 1551 memset(ctrl, 0, sizeof(struct oct_nic_stats_ctrl)); 1552 ctrl->netdev = netdev; 1553 init_completion(&ctrl->complete); 1554 1555 sc->iq_no = lio->linfo.txpciq[0].s.q_no; 1556 1557 octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC, 1558 OPCODE_NIC_PORT_STATS, 0, 0, 0); 1559 1560 sc->callback = octnet_nic_stats_callback; 1561 sc->callback_arg = sc; 1562 sc->wait_time = 500; /*in milli seconds*/ 1563 1564 retval = octeon_send_soft_command(oct_dev, sc); 1565 if (retval == IQ_SEND_FAILED) { 1566 octeon_free_soft_command(oct_dev, sc); 1567 return -EINVAL; 1568 } 1569 1570 wait_for_completion_timeout(&ctrl->complete, msecs_to_jiffies(1000)); 1571 1572 if (resp->status != 1) { 1573 octeon_free_soft_command(oct_dev, sc); 1574 1575 return -EINVAL; 1576 } 1577 1578 octeon_free_soft_command(oct_dev, sc); 1579 1580 return 0; 1581 } 1582 1583 /* Enable/Disable auto interrupt Moderation */ 1584 static int oct_cfg_adaptive_intr(struct lio *lio, struct ethtool_coalesce 1585 *intr_coal) 1586 { 1587 int ret = 0; 1588 struct octeon_device *oct = lio->oct_dev; 1589 struct oct_intrmod_cfg *intrmod_cfg; 1590 1591 intrmod_cfg = &oct->intrmod; 1592 1593 if (oct->intrmod.rx_enable || oct->intrmod.tx_enable) { 1594 if (intr_coal->rate_sample_interval) 1595 intrmod_cfg->check_intrvl = 1596 intr_coal->rate_sample_interval; 1597 else 1598 intrmod_cfg->check_intrvl = 1599 LIO_INTRMOD_CHECK_INTERVAL; 1600 1601 if (intr_coal->pkt_rate_high) 1602 intrmod_cfg->maxpkt_ratethr = 1603 intr_coal->pkt_rate_high; 1604 else 1605 intrmod_cfg->maxpkt_ratethr = 1606 LIO_INTRMOD_MAXPKT_RATETHR; 1607 1608 if (intr_coal->pkt_rate_low) 1609 intrmod_cfg->minpkt_ratethr = 1610 intr_coal->pkt_rate_low; 1611 else 1612 intrmod_cfg->minpkt_ratethr = 1613 LIO_INTRMOD_MINPKT_RATETHR; 1614 } 1615 if (oct->intrmod.rx_enable) { 1616 if (intr_coal->rx_max_coalesced_frames_high) 1617 intrmod_cfg->rx_maxcnt_trigger = 1618 intr_coal->rx_max_coalesced_frames_high; 1619 else 1620 intrmod_cfg->rx_maxcnt_trigger = 1621 LIO_INTRMOD_RXMAXCNT_TRIGGER; 1622 1623 if (intr_coal->rx_coalesce_usecs_high) 1624 intrmod_cfg->rx_maxtmr_trigger = 1625 intr_coal->rx_coalesce_usecs_high; 1626 else 1627 intrmod_cfg->rx_maxtmr_trigger = 1628 LIO_INTRMOD_RXMAXTMR_TRIGGER; 1629 1630 if (intr_coal->rx_coalesce_usecs_low) 1631 intrmod_cfg->rx_mintmr_trigger = 1632 intr_coal->rx_coalesce_usecs_low; 1633 else 1634 intrmod_cfg->rx_mintmr_trigger = 1635 LIO_INTRMOD_RXMINTMR_TRIGGER; 1636 1637 if (intr_coal->rx_max_coalesced_frames_low) 1638 intrmod_cfg->rx_mincnt_trigger = 1639 intr_coal->rx_max_coalesced_frames_low; 1640 else 1641 intrmod_cfg->rx_mincnt_trigger = 1642 LIO_INTRMOD_RXMINCNT_TRIGGER; 1643 } 1644 if (oct->intrmod.tx_enable) { 1645 if (intr_coal->tx_max_coalesced_frames_high) 1646 intrmod_cfg->tx_maxcnt_trigger = 1647 intr_coal->tx_max_coalesced_frames_high; 1648 else 1649 intrmod_cfg->tx_maxcnt_trigger = 1650 LIO_INTRMOD_TXMAXCNT_TRIGGER; 1651 if (intr_coal->tx_max_coalesced_frames_low) 1652 intrmod_cfg->tx_mincnt_trigger = 1653 intr_coal->tx_max_coalesced_frames_low; 1654 else 1655 intrmod_cfg->tx_mincnt_trigger = 1656 LIO_INTRMOD_TXMINCNT_TRIGGER; 1657 } 1658 1659 ret = octnet_set_intrmod_cfg(lio, intrmod_cfg); 1660 1661 return ret; 1662 } 1663 1664 static int 1665 oct_cfg_rx_intrcnt(struct lio *lio, struct ethtool_coalesce *intr_coal) 1666 { 1667 struct octeon_device *oct = lio->oct_dev; 1668 u32 rx_max_coalesced_frames; 1669 1670 /* Config Cnt based interrupt values */ 1671 switch (oct->chip_id) { 1672 case OCTEON_CN68XX: 1673 case OCTEON_CN66XX: { 1674 struct octeon_cn6xxx *cn6xxx = 1675 (struct octeon_cn6xxx *)oct->chip; 1676 1677 if (!intr_coal->rx_max_coalesced_frames) 1678 rx_max_coalesced_frames = CN6XXX_OQ_INTR_PKT; 1679 else 1680 rx_max_coalesced_frames = 1681 intr_coal->rx_max_coalesced_frames; 1682 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS, 1683 rx_max_coalesced_frames); 1684 CFG_SET_OQ_INTR_PKT(cn6xxx->conf, rx_max_coalesced_frames); 1685 break; 1686 } 1687 case OCTEON_CN23XX_PF_VID: { 1688 int q_no; 1689 1690 if (!intr_coal->rx_max_coalesced_frames) 1691 rx_max_coalesced_frames = oct->intrmod.rx_frames; 1692 else 1693 rx_max_coalesced_frames = 1694 intr_coal->rx_max_coalesced_frames; 1695 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 1696 q_no += oct->sriov_info.pf_srn; 1697 octeon_write_csr64( 1698 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no), 1699 (octeon_read_csr64( 1700 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no)) & 1701 (0x3fffff00000000UL)) | 1702 rx_max_coalesced_frames); 1703 /*consider setting resend bit*/ 1704 } 1705 oct->intrmod.rx_frames = rx_max_coalesced_frames; 1706 break; 1707 } 1708 case OCTEON_CN23XX_VF_VID: { 1709 int q_no; 1710 1711 if (!intr_coal->rx_max_coalesced_frames) 1712 rx_max_coalesced_frames = oct->intrmod.rx_frames; 1713 else 1714 rx_max_coalesced_frames = 1715 intr_coal->rx_max_coalesced_frames; 1716 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 1717 octeon_write_csr64( 1718 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), 1719 (octeon_read_csr64( 1720 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no)) & 1721 (0x3fffff00000000UL)) | 1722 rx_max_coalesced_frames); 1723 /* consider writing to resend bit here */ 1724 } 1725 oct->intrmod.rx_frames = rx_max_coalesced_frames; 1726 break; 1727 } 1728 default: 1729 return -EINVAL; 1730 } 1731 return 0; 1732 } 1733 1734 static int oct_cfg_rx_intrtime(struct lio *lio, 1735 struct ethtool_coalesce *intr_coal) 1736 { 1737 struct octeon_device *oct = lio->oct_dev; 1738 u32 time_threshold, rx_coalesce_usecs; 1739 1740 /* Config Time based interrupt values */ 1741 switch (oct->chip_id) { 1742 case OCTEON_CN68XX: 1743 case OCTEON_CN66XX: { 1744 struct octeon_cn6xxx *cn6xxx = 1745 (struct octeon_cn6xxx *)oct->chip; 1746 if (!intr_coal->rx_coalesce_usecs) 1747 rx_coalesce_usecs = CN6XXX_OQ_INTR_TIME; 1748 else 1749 rx_coalesce_usecs = intr_coal->rx_coalesce_usecs; 1750 1751 time_threshold = lio_cn6xxx_get_oq_ticks(oct, 1752 rx_coalesce_usecs); 1753 octeon_write_csr(oct, 1754 CN6XXX_SLI_OQ_INT_LEVEL_TIME, 1755 time_threshold); 1756 1757 CFG_SET_OQ_INTR_TIME(cn6xxx->conf, rx_coalesce_usecs); 1758 break; 1759 } 1760 case OCTEON_CN23XX_PF_VID: { 1761 u64 time_threshold; 1762 int q_no; 1763 1764 if (!intr_coal->rx_coalesce_usecs) 1765 rx_coalesce_usecs = oct->intrmod.rx_usecs; 1766 else 1767 rx_coalesce_usecs = intr_coal->rx_coalesce_usecs; 1768 time_threshold = 1769 cn23xx_pf_get_oq_ticks(oct, (u32)rx_coalesce_usecs); 1770 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 1771 q_no += oct->sriov_info.pf_srn; 1772 octeon_write_csr64(oct, 1773 CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no), 1774 (oct->intrmod.rx_frames | 1775 (time_threshold << 32))); 1776 /*consider writing to resend bit here*/ 1777 } 1778 oct->intrmod.rx_usecs = rx_coalesce_usecs; 1779 break; 1780 } 1781 case OCTEON_CN23XX_VF_VID: { 1782 u64 time_threshold; 1783 int q_no; 1784 1785 if (!intr_coal->rx_coalesce_usecs) 1786 rx_coalesce_usecs = oct->intrmod.rx_usecs; 1787 else 1788 rx_coalesce_usecs = intr_coal->rx_coalesce_usecs; 1789 1790 time_threshold = 1791 cn23xx_vf_get_oq_ticks(oct, (u32)rx_coalesce_usecs); 1792 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 1793 octeon_write_csr64( 1794 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), 1795 (oct->intrmod.rx_frames | 1796 (time_threshold << 32))); 1797 /* consider setting resend bit */ 1798 } 1799 oct->intrmod.rx_usecs = rx_coalesce_usecs; 1800 break; 1801 } 1802 default: 1803 return -EINVAL; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static int 1810 oct_cfg_tx_intrcnt(struct lio *lio, struct ethtool_coalesce *intr_coal 1811 __attribute__((unused))) 1812 { 1813 struct octeon_device *oct = lio->oct_dev; 1814 u32 iq_intr_pkt; 1815 void __iomem *inst_cnt_reg; 1816 u64 val; 1817 1818 /* Config Cnt based interrupt values */ 1819 switch (oct->chip_id) { 1820 case OCTEON_CN68XX: 1821 case OCTEON_CN66XX: 1822 break; 1823 case OCTEON_CN23XX_VF_VID: 1824 case OCTEON_CN23XX_PF_VID: { 1825 int q_no; 1826 1827 if (!intr_coal->tx_max_coalesced_frames) 1828 iq_intr_pkt = CN23XX_DEF_IQ_INTR_THRESHOLD & 1829 CN23XX_PKT_IN_DONE_WMARK_MASK; 1830 else 1831 iq_intr_pkt = intr_coal->tx_max_coalesced_frames & 1832 CN23XX_PKT_IN_DONE_WMARK_MASK; 1833 for (q_no = 0; q_no < oct->num_iqs; q_no++) { 1834 inst_cnt_reg = (oct->instr_queue[q_no])->inst_cnt_reg; 1835 val = readq(inst_cnt_reg); 1836 /*clear wmark and count.dont want to write count back*/ 1837 val = (val & 0xFFFF000000000000ULL) | 1838 ((u64)iq_intr_pkt 1839 << CN23XX_PKT_IN_DONE_WMARK_BIT_POS); 1840 writeq(val, inst_cnt_reg); 1841 /*consider setting resend bit*/ 1842 } 1843 oct->intrmod.tx_frames = iq_intr_pkt; 1844 break; 1845 } 1846 default: 1847 return -EINVAL; 1848 } 1849 return 0; 1850 } 1851 1852 static int lio_set_intr_coalesce(struct net_device *netdev, 1853 struct ethtool_coalesce *intr_coal) 1854 { 1855 struct lio *lio = GET_LIO(netdev); 1856 int ret; 1857 struct octeon_device *oct = lio->oct_dev; 1858 u32 j, q_no; 1859 int db_max, db_min; 1860 1861 switch (oct->chip_id) { 1862 case OCTEON_CN68XX: 1863 case OCTEON_CN66XX: 1864 db_min = CN6XXX_DB_MIN; 1865 db_max = CN6XXX_DB_MAX; 1866 if ((intr_coal->tx_max_coalesced_frames >= db_min) && 1867 (intr_coal->tx_max_coalesced_frames <= db_max)) { 1868 for (j = 0; j < lio->linfo.num_txpciq; j++) { 1869 q_no = lio->linfo.txpciq[j].s.q_no; 1870 oct->instr_queue[q_no]->fill_threshold = 1871 intr_coal->tx_max_coalesced_frames; 1872 } 1873 } else { 1874 dev_err(&oct->pci_dev->dev, 1875 "LIQUIDIO: Invalid tx-frames:%d. Range is min:%d max:%d\n", 1876 intr_coal->tx_max_coalesced_frames, db_min, 1877 db_max); 1878 return -EINVAL; 1879 } 1880 break; 1881 case OCTEON_CN23XX_PF_VID: 1882 case OCTEON_CN23XX_VF_VID: 1883 break; 1884 default: 1885 return -EINVAL; 1886 } 1887 1888 oct->intrmod.rx_enable = intr_coal->use_adaptive_rx_coalesce ? 1 : 0; 1889 oct->intrmod.tx_enable = intr_coal->use_adaptive_tx_coalesce ? 1 : 0; 1890 1891 ret = oct_cfg_adaptive_intr(lio, intr_coal); 1892 1893 if (!intr_coal->use_adaptive_rx_coalesce) { 1894 ret = oct_cfg_rx_intrtime(lio, intr_coal); 1895 if (ret) 1896 goto ret_intrmod; 1897 1898 ret = oct_cfg_rx_intrcnt(lio, intr_coal); 1899 if (ret) 1900 goto ret_intrmod; 1901 } 1902 if (!intr_coal->use_adaptive_tx_coalesce) { 1903 ret = oct_cfg_tx_intrcnt(lio, intr_coal); 1904 if (ret) 1905 goto ret_intrmod; 1906 } 1907 1908 return 0; 1909 ret_intrmod: 1910 return ret; 1911 } 1912 1913 static int lio_get_ts_info(struct net_device *netdev, 1914 struct ethtool_ts_info *info) 1915 { 1916 struct lio *lio = GET_LIO(netdev); 1917 1918 info->so_timestamping = 1919 #ifdef PTP_HARDWARE_TIMESTAMPING 1920 SOF_TIMESTAMPING_TX_HARDWARE | 1921 SOF_TIMESTAMPING_RX_HARDWARE | 1922 SOF_TIMESTAMPING_RAW_HARDWARE | 1923 SOF_TIMESTAMPING_TX_SOFTWARE | 1924 #endif 1925 SOF_TIMESTAMPING_RX_SOFTWARE | 1926 SOF_TIMESTAMPING_SOFTWARE; 1927 1928 if (lio->ptp_clock) 1929 info->phc_index = ptp_clock_index(lio->ptp_clock); 1930 else 1931 info->phc_index = -1; 1932 1933 #ifdef PTP_HARDWARE_TIMESTAMPING 1934 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1935 1936 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 1937 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 1938 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1939 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); 1940 #endif 1941 1942 return 0; 1943 } 1944 1945 /* Return register dump len. */ 1946 static int lio_get_regs_len(struct net_device *dev) 1947 { 1948 struct lio *lio = GET_LIO(dev); 1949 struct octeon_device *oct = lio->oct_dev; 1950 1951 switch (oct->chip_id) { 1952 case OCTEON_CN23XX_PF_VID: 1953 return OCT_ETHTOOL_REGDUMP_LEN_23XX; 1954 case OCTEON_CN23XX_VF_VID: 1955 return OCT_ETHTOOL_REGDUMP_LEN_23XX_VF; 1956 default: 1957 return OCT_ETHTOOL_REGDUMP_LEN; 1958 } 1959 } 1960 1961 static int cn23xx_read_csr_reg(char *s, struct octeon_device *oct) 1962 { 1963 u32 reg; 1964 u8 pf_num = oct->pf_num; 1965 int len = 0; 1966 int i; 1967 1968 /* PCI Window Registers */ 1969 1970 len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n"); 1971 1972 /*0x29030 or 0x29040*/ 1973 reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num); 1974 len += sprintf(s + len, 1975 "\n[%08x] (SLI_PKT_MAC%d_PF%d_RINFO): %016llx\n", 1976 reg, oct->pcie_port, oct->pf_num, 1977 (u64)octeon_read_csr64(oct, reg)); 1978 1979 /*0x27080 or 0x27090*/ 1980 reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); 1981 len += 1982 sprintf(s + len, "\n[%08x] (SLI_MAC%d_PF%d_INT_ENB): %016llx\n", 1983 reg, oct->pcie_port, oct->pf_num, 1984 (u64)octeon_read_csr64(oct, reg)); 1985 1986 /*0x27000 or 0x27010*/ 1987 reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); 1988 len += 1989 sprintf(s + len, "\n[%08x] (SLI_MAC%d_PF%d_INT_SUM): %016llx\n", 1990 reg, oct->pcie_port, oct->pf_num, 1991 (u64)octeon_read_csr64(oct, reg)); 1992 1993 /*0x29120*/ 1994 reg = 0x29120; 1995 len += sprintf(s + len, "\n[%08x] (SLI_PKT_MEM_CTL): %016llx\n", reg, 1996 (u64)octeon_read_csr64(oct, reg)); 1997 1998 /*0x27300*/ 1999 reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + 2000 (oct->pf_num) * CN23XX_PF_INT_OFFSET; 2001 len += sprintf( 2002 s + len, "\n[%08x] (SLI_MAC%d_PF%d_PKT_VF_INT): %016llx\n", reg, 2003 oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg)); 2004 2005 /*0x27200*/ 2006 reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + 2007 (oct->pf_num) * CN23XX_PF_INT_OFFSET; 2008 len += sprintf(s + len, 2009 "\n[%08x] (SLI_MAC%d_PF%d_PP_VF_INT): %016llx\n", 2010 reg, oct->pcie_port, oct->pf_num, 2011 (u64)octeon_read_csr64(oct, reg)); 2012 2013 /*29130*/ 2014 reg = CN23XX_SLI_PKT_CNT_INT; 2015 len += sprintf(s + len, "\n[%08x] (SLI_PKT_CNT_INT): %016llx\n", reg, 2016 (u64)octeon_read_csr64(oct, reg)); 2017 2018 /*0x29140*/ 2019 reg = CN23XX_SLI_PKT_TIME_INT; 2020 len += sprintf(s + len, "\n[%08x] (SLI_PKT_TIME_INT): %016llx\n", reg, 2021 (u64)octeon_read_csr64(oct, reg)); 2022 2023 /*0x29160*/ 2024 reg = 0x29160; 2025 len += sprintf(s + len, "\n[%08x] (SLI_PKT_INT): %016llx\n", reg, 2026 (u64)octeon_read_csr64(oct, reg)); 2027 2028 /*0x29180*/ 2029 reg = CN23XX_SLI_OQ_WMARK; 2030 len += sprintf(s + len, "\n[%08x] (SLI_PKT_OUTPUT_WMARK): %016llx\n", 2031 reg, (u64)octeon_read_csr64(oct, reg)); 2032 2033 /*0x291E0*/ 2034 reg = CN23XX_SLI_PKT_IOQ_RING_RST; 2035 len += sprintf(s + len, "\n[%08x] (SLI_PKT_RING_RST): %016llx\n", reg, 2036 (u64)octeon_read_csr64(oct, reg)); 2037 2038 /*0x29210*/ 2039 reg = CN23XX_SLI_GBL_CONTROL; 2040 len += sprintf(s + len, 2041 "\n[%08x] (SLI_PKT_GBL_CONTROL): %016llx\n", reg, 2042 (u64)octeon_read_csr64(oct, reg)); 2043 2044 /*0x29220*/ 2045 reg = 0x29220; 2046 len += sprintf(s + len, "\n[%08x] (SLI_PKT_BIST_STATUS): %016llx\n", 2047 reg, (u64)octeon_read_csr64(oct, reg)); 2048 2049 /*PF only*/ 2050 if (pf_num == 0) { 2051 /*0x29260*/ 2052 reg = CN23XX_SLI_OUT_BP_EN_W1S; 2053 len += sprintf(s + len, 2054 "\n[%08x] (SLI_PKT_OUT_BP_EN_W1S): %016llx\n", 2055 reg, (u64)octeon_read_csr64(oct, reg)); 2056 } else if (pf_num == 1) { 2057 /*0x29270*/ 2058 reg = CN23XX_SLI_OUT_BP_EN2_W1S; 2059 len += sprintf(s + len, 2060 "\n[%08x] (SLI_PKT_OUT_BP_EN2_W1S): %016llx\n", 2061 reg, (u64)octeon_read_csr64(oct, reg)); 2062 } 2063 2064 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2065 reg = CN23XX_SLI_OQ_BUFF_INFO_SIZE(i); 2066 len += 2067 sprintf(s + len, "\n[%08x] (SLI_PKT%d_OUT_SIZE): %016llx\n", 2068 reg, i, (u64)octeon_read_csr64(oct, reg)); 2069 } 2070 2071 /*0x10040*/ 2072 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { 2073 reg = CN23XX_SLI_IQ_INSTR_COUNT64(i); 2074 len += sprintf(s + len, 2075 "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n", 2076 reg, i, (u64)octeon_read_csr64(oct, reg)); 2077 } 2078 2079 /*0x10080*/ 2080 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2081 reg = CN23XX_SLI_OQ_PKTS_CREDIT(i); 2082 len += sprintf(s + len, 2083 "\n[%08x] (SLI_PKT%d_SLIST_BAOFF_DBELL): %016llx\n", 2084 reg, i, (u64)octeon_read_csr64(oct, reg)); 2085 } 2086 2087 /*0x10090*/ 2088 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2089 reg = CN23XX_SLI_OQ_SIZE(i); 2090 len += sprintf( 2091 s + len, "\n[%08x] (SLI_PKT%d_SLIST_FIFO_RSIZE): %016llx\n", 2092 reg, i, (u64)octeon_read_csr64(oct, reg)); 2093 } 2094 2095 /*0x10050*/ 2096 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2097 reg = CN23XX_SLI_OQ_PKT_CONTROL(i); 2098 len += sprintf( 2099 s + len, 2100 "\n[%08x] (SLI_PKT%d__OUTPUT_CONTROL): %016llx\n", 2101 reg, i, (u64)octeon_read_csr64(oct, reg)); 2102 } 2103 2104 /*0x10070*/ 2105 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2106 reg = CN23XX_SLI_OQ_BASE_ADDR64(i); 2107 len += sprintf(s + len, 2108 "\n[%08x] (SLI_PKT%d_SLIST_BADDR): %016llx\n", 2109 reg, i, (u64)octeon_read_csr64(oct, reg)); 2110 } 2111 2112 /*0x100a0*/ 2113 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2114 reg = CN23XX_SLI_OQ_PKT_INT_LEVELS(i); 2115 len += sprintf(s + len, 2116 "\n[%08x] (SLI_PKT%d_INT_LEVELS): %016llx\n", 2117 reg, i, (u64)octeon_read_csr64(oct, reg)); 2118 } 2119 2120 /*0x100b0*/ 2121 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2122 reg = CN23XX_SLI_OQ_PKTS_SENT(i); 2123 len += sprintf(s + len, "\n[%08x] (SLI_PKT%d_CNTS): %016llx\n", 2124 reg, i, (u64)octeon_read_csr64(oct, reg)); 2125 } 2126 2127 /*0x100c0*/ 2128 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { 2129 reg = 0x100c0 + i * CN23XX_OQ_OFFSET; 2130 len += sprintf(s + len, 2131 "\n[%08x] (SLI_PKT%d_ERROR_INFO): %016llx\n", 2132 reg, i, (u64)octeon_read_csr64(oct, reg)); 2133 2134 /*0x10000*/ 2135 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { 2136 reg = CN23XX_SLI_IQ_PKT_CONTROL64(i); 2137 len += sprintf( 2138 s + len, 2139 "\n[%08x] (SLI_PKT%d_INPUT_CONTROL): %016llx\n", 2140 reg, i, (u64)octeon_read_csr64(oct, reg)); 2141 } 2142 2143 /*0x10010*/ 2144 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { 2145 reg = CN23XX_SLI_IQ_BASE_ADDR64(i); 2146 len += sprintf( 2147 s + len, 2148 "\n[%08x] (SLI_PKT%d_INSTR_BADDR): %016llx\n", reg, 2149 i, (u64)octeon_read_csr64(oct, reg)); 2150 } 2151 2152 /*0x10020*/ 2153 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { 2154 reg = CN23XX_SLI_IQ_DOORBELL(i); 2155 len += sprintf( 2156 s + len, 2157 "\n[%08x] (SLI_PKT%d_INSTR_BAOFF_DBELL): %016llx\n", 2158 reg, i, (u64)octeon_read_csr64(oct, reg)); 2159 } 2160 2161 /*0x10030*/ 2162 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { 2163 reg = CN23XX_SLI_IQ_SIZE(i); 2164 len += sprintf( 2165 s + len, 2166 "\n[%08x] (SLI_PKT%d_INSTR_FIFO_RSIZE): %016llx\n", 2167 reg, i, (u64)octeon_read_csr64(oct, reg)); 2168 } 2169 2170 /*0x10040*/ 2171 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) 2172 reg = CN23XX_SLI_IQ_INSTR_COUNT64(i); 2173 len += sprintf(s + len, 2174 "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n", 2175 reg, i, (u64)octeon_read_csr64(oct, reg)); 2176 } 2177 2178 return len; 2179 } 2180 2181 static int cn23xx_vf_read_csr_reg(char *s, struct octeon_device *oct) 2182 { 2183 int len = 0; 2184 u32 reg; 2185 int i; 2186 2187 /* PCI Window Registers */ 2188 2189 len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n"); 2190 2191 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2192 reg = CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(i); 2193 len += sprintf(s + len, 2194 "\n[%08x] (SLI_PKT%d_OUT_SIZE): %016llx\n", 2195 reg, i, (u64)octeon_read_csr64(oct, reg)); 2196 } 2197 2198 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2199 reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i); 2200 len += sprintf(s + len, 2201 "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n", 2202 reg, i, (u64)octeon_read_csr64(oct, reg)); 2203 } 2204 2205 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2206 reg = CN23XX_VF_SLI_OQ_PKTS_CREDIT(i); 2207 len += sprintf(s + len, 2208 "\n[%08x] (SLI_PKT%d_SLIST_BAOFF_DBELL): %016llx\n", 2209 reg, i, (u64)octeon_read_csr64(oct, reg)); 2210 } 2211 2212 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2213 reg = CN23XX_VF_SLI_OQ_SIZE(i); 2214 len += sprintf(s + len, 2215 "\n[%08x] (SLI_PKT%d_SLIST_FIFO_RSIZE): %016llx\n", 2216 reg, i, (u64)octeon_read_csr64(oct, reg)); 2217 } 2218 2219 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2220 reg = CN23XX_VF_SLI_OQ_PKT_CONTROL(i); 2221 len += sprintf(s + len, 2222 "\n[%08x] (SLI_PKT%d__OUTPUT_CONTROL): %016llx\n", 2223 reg, i, (u64)octeon_read_csr64(oct, reg)); 2224 } 2225 2226 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2227 reg = CN23XX_VF_SLI_OQ_BASE_ADDR64(i); 2228 len += sprintf(s + len, 2229 "\n[%08x] (SLI_PKT%d_SLIST_BADDR): %016llx\n", 2230 reg, i, (u64)octeon_read_csr64(oct, reg)); 2231 } 2232 2233 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2234 reg = CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(i); 2235 len += sprintf(s + len, 2236 "\n[%08x] (SLI_PKT%d_INT_LEVELS): %016llx\n", 2237 reg, i, (u64)octeon_read_csr64(oct, reg)); 2238 } 2239 2240 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2241 reg = CN23XX_VF_SLI_OQ_PKTS_SENT(i); 2242 len += sprintf(s + len, "\n[%08x] (SLI_PKT%d_CNTS): %016llx\n", 2243 reg, i, (u64)octeon_read_csr64(oct, reg)); 2244 } 2245 2246 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2247 reg = 0x100c0 + i * CN23XX_VF_OQ_OFFSET; 2248 len += sprintf(s + len, 2249 "\n[%08x] (SLI_PKT%d_ERROR_INFO): %016llx\n", 2250 reg, i, (u64)octeon_read_csr64(oct, reg)); 2251 } 2252 2253 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2254 reg = 0x100d0 + i * CN23XX_VF_IQ_OFFSET; 2255 len += sprintf(s + len, 2256 "\n[%08x] (SLI_PKT%d_VF_INT_SUM): %016llx\n", 2257 reg, i, (u64)octeon_read_csr64(oct, reg)); 2258 } 2259 2260 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2261 reg = CN23XX_VF_SLI_IQ_PKT_CONTROL64(i); 2262 len += sprintf(s + len, 2263 "\n[%08x] (SLI_PKT%d_INPUT_CONTROL): %016llx\n", 2264 reg, i, (u64)octeon_read_csr64(oct, reg)); 2265 } 2266 2267 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2268 reg = CN23XX_VF_SLI_IQ_BASE_ADDR64(i); 2269 len += sprintf(s + len, 2270 "\n[%08x] (SLI_PKT%d_INSTR_BADDR): %016llx\n", 2271 reg, i, (u64)octeon_read_csr64(oct, reg)); 2272 } 2273 2274 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2275 reg = CN23XX_VF_SLI_IQ_DOORBELL(i); 2276 len += sprintf(s + len, 2277 "\n[%08x] (SLI_PKT%d_INSTR_BAOFF_DBELL): %016llx\n", 2278 reg, i, (u64)octeon_read_csr64(oct, reg)); 2279 } 2280 2281 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2282 reg = CN23XX_VF_SLI_IQ_SIZE(i); 2283 len += sprintf(s + len, 2284 "\n[%08x] (SLI_PKT%d_INSTR_FIFO_RSIZE): %016llx\n", 2285 reg, i, (u64)octeon_read_csr64(oct, reg)); 2286 } 2287 2288 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { 2289 reg = CN23XX_VF_SLI_IQ_INSTR_COUNT64(i); 2290 len += sprintf(s + len, 2291 "\n[%08x] (SLI_PKT_IN_DONE%d_CNTS): %016llx\n", 2292 reg, i, (u64)octeon_read_csr64(oct, reg)); 2293 } 2294 2295 return len; 2296 } 2297 2298 static int cn6xxx_read_csr_reg(char *s, struct octeon_device *oct) 2299 { 2300 u32 reg; 2301 int i, len = 0; 2302 2303 /* PCI Window Registers */ 2304 2305 len += sprintf(s + len, "\n\t Octeon CSR Registers\n\n"); 2306 reg = CN6XXX_WIN_WR_ADDR_LO; 2307 len += sprintf(s + len, "\n[%02x] (WIN_WR_ADDR_LO): %08x\n", 2308 CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg)); 2309 reg = CN6XXX_WIN_WR_ADDR_HI; 2310 len += sprintf(s + len, "[%02x] (WIN_WR_ADDR_HI): %08x\n", 2311 CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg)); 2312 reg = CN6XXX_WIN_RD_ADDR_LO; 2313 len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_LO): %08x\n", 2314 CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg)); 2315 reg = CN6XXX_WIN_RD_ADDR_HI; 2316 len += sprintf(s + len, "[%02x] (WIN_RD_ADDR_HI): %08x\n", 2317 CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg)); 2318 reg = CN6XXX_WIN_WR_DATA_LO; 2319 len += sprintf(s + len, "[%02x] (WIN_WR_DATA_LO): %08x\n", 2320 CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg)); 2321 reg = CN6XXX_WIN_WR_DATA_HI; 2322 len += sprintf(s + len, "[%02x] (WIN_WR_DATA_HI): %08x\n", 2323 CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg)); 2324 len += sprintf(s + len, "[%02x] (WIN_WR_MASK_REG): %08x\n", 2325 CN6XXX_WIN_WR_MASK_REG, 2326 octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG)); 2327 2328 /* PCI Interrupt Register */ 2329 len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n", 2330 CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct, 2331 CN6XXX_SLI_INT_ENB64_PORT0)); 2332 len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 1): %08x\n", 2333 CN6XXX_SLI_INT_ENB64_PORT1, 2334 octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1)); 2335 len += sprintf(s + len, "[%x] (INT_SUM): %08x\n", CN6XXX_SLI_INT_SUM64, 2336 octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64)); 2337 2338 /* PCI Output queue registers */ 2339 for (i = 0; i < oct->num_oqs; i++) { 2340 reg = CN6XXX_SLI_OQ_PKTS_SENT(i); 2341 len += sprintf(s + len, "\n[%x] (PKTS_SENT_%d): %08x\n", 2342 reg, i, octeon_read_csr(oct, reg)); 2343 reg = CN6XXX_SLI_OQ_PKTS_CREDIT(i); 2344 len += sprintf(s + len, "[%x] (PKT_CREDITS_%d): %08x\n", 2345 reg, i, octeon_read_csr(oct, reg)); 2346 } 2347 reg = CN6XXX_SLI_OQ_INT_LEVEL_PKTS; 2348 len += sprintf(s + len, "\n[%x] (PKTS_SENT_INT_LEVEL): %08x\n", 2349 reg, octeon_read_csr(oct, reg)); 2350 reg = CN6XXX_SLI_OQ_INT_LEVEL_TIME; 2351 len += sprintf(s + len, "[%x] (PKTS_SENT_TIME): %08x\n", 2352 reg, octeon_read_csr(oct, reg)); 2353 2354 /* PCI Input queue registers */ 2355 for (i = 0; i <= 3; i++) { 2356 u32 reg; 2357 2358 reg = CN6XXX_SLI_IQ_DOORBELL(i); 2359 len += sprintf(s + len, "\n[%x] (INSTR_DOORBELL_%d): %08x\n", 2360 reg, i, octeon_read_csr(oct, reg)); 2361 reg = CN6XXX_SLI_IQ_INSTR_COUNT(i); 2362 len += sprintf(s + len, "[%x] (INSTR_COUNT_%d): %08x\n", 2363 reg, i, octeon_read_csr(oct, reg)); 2364 } 2365 2366 /* PCI DMA registers */ 2367 2368 len += sprintf(s + len, "\n[%x] (DMA_CNT_0): %08x\n", 2369 CN6XXX_DMA_CNT(0), 2370 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); 2371 reg = CN6XXX_DMA_PKT_INT_LEVEL(0); 2372 len += sprintf(s + len, "[%x] (DMA_INT_LEV_0): %08x\n", 2373 CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); 2374 reg = CN6XXX_DMA_TIME_INT_LEVEL(0); 2375 len += sprintf(s + len, "[%x] (DMA_TIME_0): %08x\n", 2376 CN6XXX_DMA_TIME_INT_LEVEL(0), 2377 octeon_read_csr(oct, reg)); 2378 2379 len += sprintf(s + len, "\n[%x] (DMA_CNT_1): %08x\n", 2380 CN6XXX_DMA_CNT(1), 2381 octeon_read_csr(oct, CN6XXX_DMA_CNT(1))); 2382 reg = CN6XXX_DMA_PKT_INT_LEVEL(1); 2383 len += sprintf(s + len, "[%x] (DMA_INT_LEV_1): %08x\n", 2384 CN6XXX_DMA_PKT_INT_LEVEL(1), 2385 octeon_read_csr(oct, reg)); 2386 reg = CN6XXX_DMA_PKT_INT_LEVEL(1); 2387 len += sprintf(s + len, "[%x] (DMA_TIME_1): %08x\n", 2388 CN6XXX_DMA_TIME_INT_LEVEL(1), 2389 octeon_read_csr(oct, reg)); 2390 2391 /* PCI Index registers */ 2392 2393 len += sprintf(s + len, "\n"); 2394 2395 for (i = 0; i < 16; i++) { 2396 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port)); 2397 len += sprintf(s + len, "[%llx] (BAR1_INDEX_%02d): %08x\n", 2398 CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg); 2399 } 2400 2401 return len; 2402 } 2403 2404 static int cn6xxx_read_config_reg(char *s, struct octeon_device *oct) 2405 { 2406 u32 val; 2407 int i, len = 0; 2408 2409 /* PCI CONFIG Registers */ 2410 2411 len += sprintf(s + len, 2412 "\n\t Octeon Config space Registers\n\n"); 2413 2414 for (i = 0; i <= 13; i++) { 2415 pci_read_config_dword(oct->pci_dev, (i * 4), &val); 2416 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", 2417 (i * 4), i, val); 2418 } 2419 2420 for (i = 30; i <= 34; i++) { 2421 pci_read_config_dword(oct->pci_dev, (i * 4), &val); 2422 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", 2423 (i * 4), i, val); 2424 } 2425 2426 return len; 2427 } 2428 2429 /* Return register dump user app. */ 2430 static void lio_get_regs(struct net_device *dev, 2431 struct ethtool_regs *regs, void *regbuf) 2432 { 2433 struct lio *lio = GET_LIO(dev); 2434 int len = 0; 2435 struct octeon_device *oct = lio->oct_dev; 2436 2437 regs->version = OCT_ETHTOOL_REGSVER; 2438 2439 switch (oct->chip_id) { 2440 case OCTEON_CN23XX_PF_VID: 2441 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX); 2442 len += cn23xx_read_csr_reg(regbuf + len, oct); 2443 break; 2444 case OCTEON_CN23XX_VF_VID: 2445 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX_VF); 2446 len += cn23xx_vf_read_csr_reg(regbuf + len, oct); 2447 break; 2448 case OCTEON_CN68XX: 2449 case OCTEON_CN66XX: 2450 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN); 2451 len += cn6xxx_read_csr_reg(regbuf + len, oct); 2452 len += cn6xxx_read_config_reg(regbuf + len, oct); 2453 break; 2454 default: 2455 dev_err(&oct->pci_dev->dev, "%s Unknown chipid: %d\n", 2456 __func__, oct->chip_id); 2457 } 2458 } 2459 2460 static u32 lio_get_priv_flags(struct net_device *netdev) 2461 { 2462 struct lio *lio = GET_LIO(netdev); 2463 2464 return lio->oct_dev->priv_flags; 2465 } 2466 2467 static int lio_set_priv_flags(struct net_device *netdev, u32 flags) 2468 { 2469 struct lio *lio = GET_LIO(netdev); 2470 bool intr_by_tx_bytes = !!(flags & (0x1 << OCT_PRIV_FLAG_TX_BYTES)); 2471 2472 lio_set_priv_flag(lio->oct_dev, OCT_PRIV_FLAG_TX_BYTES, 2473 intr_by_tx_bytes); 2474 return 0; 2475 } 2476 2477 static const struct ethtool_ops lio_ethtool_ops = { 2478 .get_link_ksettings = lio_get_link_ksettings, 2479 .get_link = ethtool_op_get_link, 2480 .get_drvinfo = lio_get_drvinfo, 2481 .get_ringparam = lio_ethtool_get_ringparam, 2482 .get_channels = lio_ethtool_get_channels, 2483 .set_phys_id = lio_set_phys_id, 2484 .get_eeprom_len = lio_get_eeprom_len, 2485 .get_eeprom = lio_get_eeprom, 2486 .get_strings = lio_get_strings, 2487 .get_ethtool_stats = lio_get_ethtool_stats, 2488 .get_pauseparam = lio_get_pauseparam, 2489 .set_pauseparam = lio_set_pauseparam, 2490 .get_regs_len = lio_get_regs_len, 2491 .get_regs = lio_get_regs, 2492 .get_msglevel = lio_get_msglevel, 2493 .set_msglevel = lio_set_msglevel, 2494 .get_sset_count = lio_get_sset_count, 2495 .get_coalesce = lio_get_intr_coalesce, 2496 .set_coalesce = lio_set_intr_coalesce, 2497 .get_priv_flags = lio_get_priv_flags, 2498 .set_priv_flags = lio_set_priv_flags, 2499 .get_ts_info = lio_get_ts_info, 2500 }; 2501 2502 static const struct ethtool_ops lio_vf_ethtool_ops = { 2503 .get_link_ksettings = lio_get_link_ksettings, 2504 .get_link = ethtool_op_get_link, 2505 .get_drvinfo = lio_get_vf_drvinfo, 2506 .get_ringparam = lio_ethtool_get_ringparam, 2507 .get_channels = lio_ethtool_get_channels, 2508 .get_strings = lio_vf_get_strings, 2509 .get_ethtool_stats = lio_vf_get_ethtool_stats, 2510 .get_regs_len = lio_get_regs_len, 2511 .get_regs = lio_get_regs, 2512 .get_msglevel = lio_get_msglevel, 2513 .set_msglevel = lio_set_msglevel, 2514 .get_sset_count = lio_vf_get_sset_count, 2515 .get_coalesce = lio_get_intr_coalesce, 2516 .set_coalesce = lio_set_intr_coalesce, 2517 .get_priv_flags = lio_get_priv_flags, 2518 .set_priv_flags = lio_set_priv_flags, 2519 .get_ts_info = lio_get_ts_info, 2520 }; 2521 2522 void liquidio_set_ethtool_ops(struct net_device *netdev) 2523 { 2524 struct lio *lio = GET_LIO(netdev); 2525 struct octeon_device *oct = lio->oct_dev; 2526 2527 if (OCTEON_CN23XX_VF(oct)) 2528 netdev->ethtool_ops = &lio_vf_ethtool_ops; 2529 else 2530 netdev->ethtool_ops = &lio_ethtool_ops; 2531 } 2532