1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2015 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 #include <linux/version.h> 23 #include <linux/types.h> 24 #include <linux/list.h> 25 #include <linux/interrupt.h> 26 #include <linux/pci.h> 27 #include <linux/kthread.h> 28 #include <linux/netdevice.h> 29 #include "octeon_config.h" 30 #include "liquidio_common.h" 31 #include "octeon_droq.h" 32 #include "octeon_iq.h" 33 #include "response_manager.h" 34 #include "octeon_device.h" 35 #include "octeon_nic.h" 36 #include "octeon_main.h" 37 #include "octeon_network.h" 38 #include "cn66xx_regs.h" 39 #include "cn66xx_device.h" 40 #include "cn68xx_regs.h" 41 #include "cn68xx_device.h" 42 #include "liquidio_image.h" 43 #include "octeon_mem_ops.h" 44 45 static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct) 46 { 47 u32 i; 48 u32 fifo_sizes[6] = { 3, 3, 1, 1, 1, 8 }; 49 50 lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL); 51 dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n", 52 lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL)); 53 54 for (i = 0; i < 6; i++) { 55 /* Prevent service of instruction queue for all DMA engines 56 * Engine 5 will remain 0. Engines 0 - 4 will be setup by 57 * core. 58 */ 59 lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i)); 60 lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i)); 61 dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i, 62 lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i))); 63 } 64 65 /* DPI_SLI_PRT_CFG has MPS and MRRS settings that will be set 66 * separately. 67 */ 68 69 lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL); 70 dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n", 71 lio_pci_readq(oct, CN6XXX_DPI_CTL)); 72 } 73 74 static int lio_cn68xx_soft_reset(struct octeon_device *oct) 75 { 76 lio_cn6xxx_soft_reset(oct); 77 lio_cn68xx_set_dpi_regs(oct); 78 79 return 0; 80 } 81 82 static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct) 83 { 84 struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip; 85 u64 pktctl, tx_pipe, max_oqs; 86 87 pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL); 88 89 /* 68XX specific */ 90 max_oqs = CFG_GET_OQ_MAX_Q(CHIP_FIELD(oct, cn6xxx, conf)); 91 tx_pipe = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE); 92 tx_pipe &= 0xffffffffff00ffffULL; /* clear out NUMP field */ 93 tx_pipe |= max_oqs << 16; /* put max_oqs in NUMP field */ 94 octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe); 95 96 if (CFG_GET_IS_SLI_BP_ON(cn68xx->conf)) 97 pktctl |= 0xF; 98 else 99 /* Disable per-port backpressure. */ 100 pktctl &= ~0xF; 101 octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl); 102 } 103 104 static int lio_cn68xx_setup_device_regs(struct octeon_device *oct) 105 { 106 lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT); 107 lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B); 108 lio_cn6xxx_enable_error_reporting(oct); 109 110 lio_cn6xxx_setup_global_input_regs(oct); 111 lio_cn68xx_setup_pkt_ctl_regs(oct); 112 lio_cn6xxx_setup_global_output_regs(oct); 113 114 /* Default error timeout value should be 0x200000 to avoid host hang 115 * when reads invalid register 116 */ 117 octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL); 118 119 return 0; 120 } 121 122 static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct) 123 { 124 u32 val = 0; 125 126 /* Set M_VEND1_DRP and M_VEND0_DRP bits */ 127 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val); 128 val |= 0x3; 129 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val); 130 } 131 132 int lio_is_210nv(struct octeon_device *oct) 133 { 134 u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG); 135 136 return ((mio_qlm4_cfg & CN6XXX_MIO_QLM_CFG_MASK) == 0); 137 } 138 139 int lio_setup_cn68xx_octeon_device(struct octeon_device *oct) 140 { 141 struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip; 142 u16 card_type = LIO_410NV; 143 144 if (octeon_map_pci_barx(oct, 0, 0)) 145 return 1; 146 147 if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) { 148 dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n", 149 __func__); 150 octeon_unmap_pci_barx(oct, 0); 151 return 1; 152 } 153 154 spin_lock_init(&cn68xx->lock_for_droq_int_enb_reg); 155 156 oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs; 157 oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs; 158 159 oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs; 160 oct->fn_list.soft_reset = lio_cn68xx_soft_reset; 161 oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs; 162 oct->fn_list.reinit_regs = lio_cn6xxx_reinit_regs; 163 oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index; 164 165 oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup; 166 oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write; 167 oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read; 168 169 oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt; 170 oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt; 171 172 oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues; 173 oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues; 174 175 lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list); 176 177 /* Determine variant of card */ 178 if (lio_is_210nv(oct)) 179 card_type = LIO_210NV; 180 181 cn68xx->conf = (struct octeon_config *) 182 oct_get_config_info(oct, card_type); 183 if (!cn68xx->conf) { 184 dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n", 185 __func__, 186 (card_type == LIO_410NV) ? LIO_410NV_NAME : 187 LIO_210NV_NAME); 188 octeon_unmap_pci_barx(oct, 0); 189 octeon_unmap_pci_barx(oct, 1); 190 return 1; 191 } 192 193 oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct); 194 195 lio_cn68xx_vendor_message_fix(oct); 196 197 return 0; 198 } 199