1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2015 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * This file may also be available under a different license from Cavium. 20 * Contact Cavium, Inc. for more information 21 **********************************************************************/ 22 #include <linux/pci.h> 23 #include <linux/netdevice.h> 24 #include "liquidio_common.h" 25 #include "octeon_droq.h" 26 #include "octeon_iq.h" 27 #include "response_manager.h" 28 #include "octeon_device.h" 29 #include "octeon_main.h" 30 #include "cn66xx_regs.h" 31 #include "cn66xx_device.h" 32 #include "cn68xx_regs.h" 33 34 static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct) 35 { 36 u32 i; 37 u32 fifo_sizes[6] = { 3, 3, 1, 1, 1, 8 }; 38 39 lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL); 40 dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n", 41 lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL)); 42 43 for (i = 0; i < 6; i++) { 44 /* Prevent service of instruction queue for all DMA engines 45 * Engine 5 will remain 0. Engines 0 - 4 will be setup by 46 * core. 47 */ 48 lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i)); 49 lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i)); 50 dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i, 51 lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i))); 52 } 53 54 /* DPI_SLI_PRT_CFG has MPS and MRRS settings that will be set 55 * separately. 56 */ 57 58 lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL); 59 dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n", 60 lio_pci_readq(oct, CN6XXX_DPI_CTL)); 61 } 62 63 static int lio_cn68xx_soft_reset(struct octeon_device *oct) 64 { 65 lio_cn6xxx_soft_reset(oct); 66 lio_cn68xx_set_dpi_regs(oct); 67 68 return 0; 69 } 70 71 static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct) 72 { 73 struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip; 74 u64 pktctl, tx_pipe, max_oqs; 75 76 pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL); 77 78 /* 68XX specific */ 79 max_oqs = CFG_GET_OQ_MAX_Q(CHIP_FIELD(oct, cn6xxx, conf)); 80 tx_pipe = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE); 81 tx_pipe &= 0xffffffffff00ffffULL; /* clear out NUMP field */ 82 tx_pipe |= max_oqs << 16; /* put max_oqs in NUMP field */ 83 octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe); 84 85 if (CFG_GET_IS_SLI_BP_ON(cn68xx->conf)) 86 pktctl |= 0xF; 87 else 88 /* Disable per-port backpressure. */ 89 pktctl &= ~0xF; 90 octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl); 91 } 92 93 static int lio_cn68xx_setup_device_regs(struct octeon_device *oct) 94 { 95 lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT); 96 lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B); 97 lio_cn6xxx_enable_error_reporting(oct); 98 99 lio_cn6xxx_setup_global_input_regs(oct); 100 lio_cn68xx_setup_pkt_ctl_regs(oct); 101 lio_cn6xxx_setup_global_output_regs(oct); 102 103 /* Default error timeout value should be 0x200000 to avoid host hang 104 * when reads invalid register 105 */ 106 octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL); 107 108 return 0; 109 } 110 111 static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct) 112 { 113 u32 val = 0; 114 115 /* Set M_VEND1_DRP and M_VEND0_DRP bits */ 116 pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val); 117 val |= 0x3; 118 pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val); 119 } 120 121 static int lio_is_210nv(struct octeon_device *oct) 122 { 123 u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG); 124 125 return ((mio_qlm4_cfg & CN6XXX_MIO_QLM_CFG_MASK) == 0); 126 } 127 128 int lio_setup_cn68xx_octeon_device(struct octeon_device *oct) 129 { 130 struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip; 131 u16 card_type = LIO_410NV; 132 133 if (octeon_map_pci_barx(oct, 0, 0)) 134 return 1; 135 136 if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) { 137 dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n", 138 __func__); 139 octeon_unmap_pci_barx(oct, 0); 140 return 1; 141 } 142 143 spin_lock_init(&cn68xx->lock_for_droq_int_enb_reg); 144 145 oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs; 146 oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs; 147 148 oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs; 149 oct->fn_list.soft_reset = lio_cn68xx_soft_reset; 150 oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs; 151 oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index; 152 153 oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup; 154 oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write; 155 oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read; 156 157 oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt; 158 oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt; 159 160 oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues; 161 oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues; 162 163 lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list); 164 165 /* Determine variant of card */ 166 if (lio_is_210nv(oct)) 167 card_type = LIO_210NV; 168 169 cn68xx->conf = (struct octeon_config *) 170 oct_get_config_info(oct, card_type); 171 if (!cn68xx->conf) { 172 dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n", 173 __func__, 174 (card_type == LIO_410NV) ? LIO_410NV_NAME : 175 LIO_210NV_NAME); 176 octeon_unmap_pci_barx(oct, 0); 177 octeon_unmap_pci_barx(oct, 1); 178 return 1; 179 } 180 181 oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct); 182 183 lio_cn68xx_vendor_message_fix(oct); 184 185 return 0; 186 } 187