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22 
23 /*! \file  cn66xx_device.h
24  *  \brief Host Driver: Routines that perform CN66XX specific operations.
25  */
26 
27 #ifndef __CN66XX_DEVICE_H__
28 #define  __CN66XX_DEVICE_H__
29 
30 /* Register address and configuration for a CN6XXX devices.
31  * If device specific changes need to be made then add a struct to include
32  * device specific fields as shown in the commented section
33  */
34 struct octeon_cn6xxx {
35 	/** PCI interrupt summary register */
36 	u8 __iomem *intr_sum_reg64;
37 
38 	/** PCI interrupt enable register */
39 	u8 __iomem *intr_enb_reg64;
40 
41 	/** The PCI interrupt mask used by interrupt handler */
42 	u64 intr_mask64;
43 
44 	struct octeon_config *conf;
45 
46 	/* Example additional fields - not used currently
47 	 *  struct {
48 	 *  }cn6xyz;
49 	 */
50 
51 	/* For the purpose of atomic access to interrupt enable reg */
52 	spinlock_t lock_for_droq_int_enb_reg;
53 
54 };
55 
56 enum octeon_pcie_mps {
57 	PCIE_MPS_DEFAULT = -1,	/* Use the default setup by BIOS */
58 	PCIE_MPS_128B = 0,
59 	PCIE_MPS_256B = 1
60 };
61 
62 enum octeon_pcie_mrrs {
63 	PCIE_MRRS_DEFAULT = -1,	/* Use the default setup by BIOS */
64 	PCIE_MRRS_128B = 0,
65 	PCIE_MRRS_256B = 1,
66 	PCIE_MRRS_512B = 2,
67 	PCIE_MRRS_1024B = 3,
68 	PCIE_MRRS_2048B = 4,
69 	PCIE_MRRS_4096B = 5
70 };
71 
72 /* Common functions for 66xx and 68xx */
73 int lio_cn6xxx_soft_reset(struct octeon_device *oct);
74 void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct);
75 void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct,
76 			       enum octeon_pcie_mps mps);
77 void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct,
78 				enum octeon_pcie_mrrs mrrs);
79 void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct);
80 void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct);
81 void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no);
82 void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no);
83 void lio_cn6xxx_enable_io_queues(struct octeon_device *oct);
84 void lio_cn6xxx_disable_io_queues(struct octeon_device *oct);
85 void lio_cn6xxx_process_pcie_error_intr(struct octeon_device *oct, u64 intr64);
86 int lio_cn6xxx_process_droq_intr_regs(struct octeon_device *oct);
87 irqreturn_t lio_cn6xxx_process_interrupt_regs(void *dev);
88 void lio_cn6xxx_reinit_regs(struct octeon_device *oct);
89 void lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
90 			       u32 idx, int valid);
91 void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask);
92 u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx);
93 u32
94 lio_cn6xxx_update_read_index(struct octeon_device *oct __attribute__((unused)),
95 			     struct octeon_instr_queue *iq);
96 void lio_cn6xxx_enable_interrupt(void *chip);
97 void lio_cn6xxx_disable_interrupt(void *chip);
98 void cn6xxx_get_pcie_qlmport(struct octeon_device *oct);
99 void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, void *chip,
100 				  struct octeon_reg_list *reg_list);
101 u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct);
102 u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us);
103 int lio_setup_cn66xx_octeon_device(struct octeon_device *);
104 int lio_validate_cn6xxx_config_info(struct octeon_device *oct,
105 				    struct octeon_config *);
106 
107 #endif
108