1 /********************************************************************** 2 * Author: Cavium, Inc. 3 * 4 * Contact: support@cavium.com 5 * Please include "LiquidIO" in the subject. 6 * 7 * Copyright (c) 2003-2016 Cavium, Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more details. 17 ***********************************************************************/ 18 #include <linux/pci.h> 19 #include <linux/netdevice.h> 20 #include <linux/vmalloc.h> 21 #include "liquidio_common.h" 22 #include "octeon_droq.h" 23 #include "octeon_iq.h" 24 #include "response_manager.h" 25 #include "octeon_device.h" 26 #include "cn23xx_vf_device.h" 27 #include "octeon_main.h" 28 #include "octeon_mailbox.h" 29 30 u32 cn23xx_vf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us) 31 { 32 /* This gives the SLI clock per microsec */ 33 u32 oqticks_per_us = (u32)oct->pfvf_hsword.coproc_tics_per_us; 34 35 /* This gives the clock cycles per millisecond */ 36 oqticks_per_us *= 1000; 37 38 /* This gives the oq ticks (1024 core clock cycles) per millisecond */ 39 oqticks_per_us /= 1024; 40 41 /* time_intr is in microseconds. The next 2 steps gives the oq ticks 42 * corressponding to time_intr. 43 */ 44 oqticks_per_us *= time_intr_in_us; 45 oqticks_per_us /= 1000; 46 47 return oqticks_per_us; 48 } 49 50 static int cn23xx_vf_reset_io_queues(struct octeon_device *oct, u32 num_queues) 51 { 52 u32 loop = BUSY_READING_REG_VF_LOOP_COUNT; 53 int ret_val = 0; 54 u32 q_no; 55 u64 d64; 56 57 for (q_no = 0; q_no < num_queues; q_no++) { 58 /* set RST bit to 1. This bit applies to both IQ and OQ */ 59 d64 = octeon_read_csr64(oct, 60 CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); 61 d64 |= CN23XX_PKT_INPUT_CTL_RST; 62 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), 63 d64); 64 } 65 66 /* wait until the RST bit is clear or the RST and QUIET bits are set */ 67 for (q_no = 0; q_no < num_queues; q_no++) { 68 u64 reg_val = octeon_read_csr64(oct, 69 CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); 70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && 71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && 72 loop) { 73 WRITE_ONCE(reg_val, octeon_read_csr64( 74 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))); 75 loop--; 76 } 77 if (!loop) { 78 dev_err(&oct->pci_dev->dev, 79 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n", 80 q_no); 81 return -1; 82 } 83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & 84 ~CN23XX_PKT_INPUT_CTL_RST); 85 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), 86 READ_ONCE(reg_val)); 87 88 WRITE_ONCE(reg_val, octeon_read_csr64( 89 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))); 90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { 91 dev_err(&oct->pci_dev->dev, 92 "clearing the reset failed for qno: %u\n", 93 q_no); 94 ret_val = -1; 95 } 96 } 97 98 return ret_val; 99 } 100 101 static int cn23xx_vf_setup_global_input_regs(struct octeon_device *oct) 102 { 103 struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; 104 struct octeon_instr_queue *iq; 105 u64 q_no, intr_threshold; 106 u64 d64; 107 108 if (cn23xx_vf_reset_io_queues(oct, oct->sriov_info.rings_per_vf)) 109 return -1; 110 111 for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) { 112 void __iomem *inst_cnt_reg; 113 114 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_DOORBELL(q_no), 115 0xFFFFFFFF); 116 iq = oct->instr_queue[q_no]; 117 118 if (iq) 119 inst_cnt_reg = iq->inst_cnt_reg; 120 else 121 inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr + 122 CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no); 123 124 d64 = octeon_read_csr64(oct, 125 CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)); 126 127 d64 &= 0xEFFFFFFFFFFFFFFFL; 128 129 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), 130 d64); 131 132 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for 133 * the Input Queues 134 */ 135 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), 136 CN23XX_PKT_INPUT_CTL_MASK); 137 138 /* set the wmark level to trigger PI_INT */ 139 intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) & 140 CN23XX_PKT_IN_DONE_WMARK_MASK; 141 142 writeq((readq(inst_cnt_reg) & 143 ~(CN23XX_PKT_IN_DONE_WMARK_MASK << 144 CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) | 145 (intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS), 146 inst_cnt_reg); 147 } 148 return 0; 149 } 150 151 static void cn23xx_vf_setup_global_output_regs(struct octeon_device *oct) 152 { 153 u32 reg_val; 154 u32 q_no; 155 156 for (q_no = 0; q_no < (oct->sriov_info.rings_per_vf); q_no++) { 157 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKTS_CREDIT(q_no), 158 0xFFFFFFFF); 159 160 reg_val = 161 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKTS_SENT(q_no)); 162 163 reg_val &= 0xEFFFFFFFFFFFFFFFL; 164 165 reg_val = 166 octeon_read_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); 167 168 /* set DPTR */ 169 reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR; 170 171 /* reset BMODE */ 172 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE); 173 174 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap 175 * for Output Queue ScatterList reset ROR_P, NSR_P 176 */ 177 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P); 178 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P); 179 180 #ifdef __LITTLE_ENDIAN_BITFIELD 181 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P); 182 #else 183 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P); 184 #endif 185 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap 186 * for Output Queue Data reset ROR, NSR 187 */ 188 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR); 189 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR); 190 /* set the ES bit */ 191 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES); 192 193 /* write all the selected settings */ 194 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), 195 reg_val); 196 } 197 } 198 199 static int cn23xx_setup_vf_device_regs(struct octeon_device *oct) 200 { 201 if (cn23xx_vf_setup_global_input_regs(oct)) 202 return -1; 203 204 cn23xx_vf_setup_global_output_regs(oct); 205 206 return 0; 207 } 208 209 static void cn23xx_setup_vf_iq_regs(struct octeon_device *oct, u32 iq_no) 210 { 211 struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; 212 u64 pkt_in_done; 213 214 /* Write the start of the input queue's ring and its size */ 215 octeon_write_csr64(oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(iq_no), 216 iq->base_addr_dma); 217 octeon_write_csr(oct, CN23XX_VF_SLI_IQ_SIZE(iq_no), iq->max_count); 218 219 /* Remember the doorbell & instruction count register addr 220 * for this queue 221 */ 222 iq->doorbell_reg = 223 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_DOORBELL(iq_no); 224 iq->inst_cnt_reg = 225 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_IQ_INSTR_COUNT64(iq_no); 226 dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n", 227 iq_no, iq->doorbell_reg, iq->inst_cnt_reg); 228 229 /* Store the current instruction counter (used in flush_iq 230 * calculation) 231 */ 232 pkt_in_done = readq(iq->inst_cnt_reg); 233 234 if (oct->msix_on) { 235 /* Set CINT_ENB to enable IQ interrupt */ 236 writeq((pkt_in_done | CN23XX_INTR_CINT_ENB), 237 iq->inst_cnt_reg); 238 } 239 iq->reset_instr_cnt = 0; 240 } 241 242 static void cn23xx_setup_vf_oq_regs(struct octeon_device *oct, u32 oq_no) 243 { 244 struct octeon_droq *droq = oct->droq[oq_no]; 245 246 octeon_write_csr64(oct, CN23XX_VF_SLI_OQ_BASE_ADDR64(oq_no), 247 droq->desc_ring_dma); 248 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_SIZE(oq_no), droq->max_count); 249 250 octeon_write_csr(oct, CN23XX_VF_SLI_OQ_BUFF_INFO_SIZE(oq_no), 251 droq->buffer_size); 252 253 /* Get the mapped address of the pkt_sent and pkts_credit regs */ 254 droq->pkts_sent_reg = 255 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_SENT(oq_no); 256 droq->pkts_credit_reg = 257 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_OQ_PKTS_CREDIT(oq_no); 258 } 259 260 static void cn23xx_vf_mbox_thread(struct work_struct *work) 261 { 262 struct cavium_wk *wk = (struct cavium_wk *)work; 263 struct octeon_mbox *mbox = (struct octeon_mbox *)wk->ctxptr; 264 265 octeon_mbox_process_message(mbox); 266 } 267 268 static int cn23xx_free_vf_mbox(struct octeon_device *oct) 269 { 270 cancel_delayed_work_sync(&oct->mbox[0]->mbox_poll_wk.work); 271 vfree(oct->mbox[0]); 272 return 0; 273 } 274 275 static int cn23xx_setup_vf_mbox(struct octeon_device *oct) 276 { 277 struct octeon_mbox *mbox = NULL; 278 279 mbox = vmalloc(sizeof(*mbox)); 280 if (!mbox) 281 return 1; 282 283 memset(mbox, 0, sizeof(struct octeon_mbox)); 284 285 spin_lock_init(&mbox->lock); 286 287 mbox->oct_dev = oct; 288 289 mbox->q_no = 0; 290 291 mbox->state = OCTEON_MBOX_STATE_IDLE; 292 293 /* VF mbox interrupt reg */ 294 mbox->mbox_int_reg = 295 (u8 *)oct->mmio[0].hw_addr + CN23XX_VF_SLI_PKT_MBOX_INT(0); 296 /* VF reads from SIG0 reg */ 297 mbox->mbox_read_reg = 298 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 0); 299 /* VF writes into SIG1 reg */ 300 mbox->mbox_write_reg = 301 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_PKT_PF_VF_MBOX_SIG(0, 1); 302 303 INIT_DELAYED_WORK(&mbox->mbox_poll_wk.work, 304 cn23xx_vf_mbox_thread); 305 306 mbox->mbox_poll_wk.ctxptr = mbox; 307 308 oct->mbox[0] = mbox; 309 310 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg); 311 312 return 0; 313 } 314 315 static int cn23xx_enable_vf_io_queues(struct octeon_device *oct) 316 { 317 u32 q_no; 318 319 for (q_no = 0; q_no < oct->num_iqs; q_no++) { 320 u64 reg_val; 321 322 /* set the corresponding IQ IS_64B bit */ 323 if (oct->io_qmask.iq64B & BIT_ULL(q_no)) { 324 reg_val = octeon_read_csr64( 325 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); 326 reg_val |= CN23XX_PKT_INPUT_CTL_IS_64B; 327 octeon_write_csr64( 328 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); 329 } 330 331 /* set the corresponding IQ ENB bit */ 332 if (oct->io_qmask.iq & BIT_ULL(q_no)) { 333 reg_val = octeon_read_csr64( 334 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)); 335 reg_val |= CN23XX_PKT_INPUT_CTL_RING_ENB; 336 octeon_write_csr64( 337 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), reg_val); 338 } 339 } 340 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 341 u32 reg_val; 342 343 /* set the corresponding OQ ENB bit */ 344 if (oct->io_qmask.oq & BIT_ULL(q_no)) { 345 reg_val = octeon_read_csr( 346 oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no)); 347 reg_val |= CN23XX_PKT_OUTPUT_CTL_RING_ENB; 348 octeon_write_csr( 349 oct, CN23XX_VF_SLI_OQ_PKT_CONTROL(q_no), reg_val); 350 } 351 } 352 353 return 0; 354 } 355 356 static void cn23xx_disable_vf_io_queues(struct octeon_device *oct) 357 { 358 u32 num_queues = oct->num_iqs; 359 360 /* per HRM, rings can only be disabled via reset operation, 361 * NOT via SLI_PKT()_INPUT/OUTPUT_CONTROL[ENB] 362 */ 363 if (num_queues < oct->num_oqs) 364 num_queues = oct->num_oqs; 365 366 cn23xx_vf_reset_io_queues(oct, num_queues); 367 } 368 369 void cn23xx_vf_ask_pf_to_do_flr(struct octeon_device *oct) 370 { 371 struct octeon_mbox_cmd mbox_cmd; 372 373 mbox_cmd.msg.u64 = 0; 374 mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST; 375 mbox_cmd.msg.s.resp_needed = 0; 376 mbox_cmd.msg.s.cmd = OCTEON_VF_FLR_REQUEST; 377 mbox_cmd.msg.s.len = 1; 378 mbox_cmd.q_no = 0; 379 mbox_cmd.recv_len = 0; 380 mbox_cmd.recv_status = 0; 381 mbox_cmd.fn = NULL; 382 mbox_cmd.fn_arg = 0; 383 384 octeon_mbox_write(oct, &mbox_cmd); 385 } 386 387 static void octeon_pfvf_hs_callback(struct octeon_device *oct, 388 struct octeon_mbox_cmd *cmd, 389 void *arg) 390 { 391 u32 major = 0; 392 393 memcpy((uint8_t *)&oct->pfvf_hsword, cmd->msg.s.params, 394 CN23XX_MAILBOX_MSGPARAM_SIZE); 395 if (cmd->recv_len > 1) { 396 major = ((struct lio_version *)(cmd->data))->major; 397 major = major << 16; 398 } 399 400 atomic_set((atomic_t *)arg, major | 1); 401 } 402 403 int cn23xx_octeon_pfvf_handshake(struct octeon_device *oct) 404 { 405 struct octeon_mbox_cmd mbox_cmd; 406 u32 q_no, count = 0; 407 atomic_t status; 408 u32 pfmajor; 409 u32 vfmajor; 410 u32 ret; 411 412 /* Sending VF_ACTIVE indication to the PF driver */ 413 dev_dbg(&oct->pci_dev->dev, "requesting info from pf\n"); 414 415 mbox_cmd.msg.u64 = 0; 416 mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST; 417 mbox_cmd.msg.s.resp_needed = 1; 418 mbox_cmd.msg.s.cmd = OCTEON_VF_ACTIVE; 419 mbox_cmd.msg.s.len = 2; 420 mbox_cmd.data[0] = 0; 421 ((struct lio_version *)&mbox_cmd.data[0])->major = 422 LIQUIDIO_BASE_MAJOR_VERSION; 423 ((struct lio_version *)&mbox_cmd.data[0])->minor = 424 LIQUIDIO_BASE_MINOR_VERSION; 425 ((struct lio_version *)&mbox_cmd.data[0])->micro = 426 LIQUIDIO_BASE_MICRO_VERSION; 427 mbox_cmd.q_no = 0; 428 mbox_cmd.recv_len = 0; 429 mbox_cmd.recv_status = 0; 430 mbox_cmd.fn = (octeon_mbox_callback_t)octeon_pfvf_hs_callback; 431 mbox_cmd.fn_arg = &status; 432 433 octeon_mbox_write(oct, &mbox_cmd); 434 435 atomic_set(&status, 0); 436 437 do { 438 schedule_timeout_uninterruptible(1); 439 } while ((!atomic_read(&status)) && (count++ < 100000)); 440 441 ret = atomic_read(&status); 442 if (!ret) { 443 dev_err(&oct->pci_dev->dev, "octeon_pfvf_handshake timeout\n"); 444 return 1; 445 } 446 447 for (q_no = 0 ; q_no < oct->num_iqs ; q_no++) 448 oct->instr_queue[q_no]->txpciq.s.pkind = oct->pfvf_hsword.pkind; 449 450 vfmajor = LIQUIDIO_BASE_MAJOR_VERSION; 451 pfmajor = ret >> 16; 452 if (pfmajor != vfmajor) { 453 dev_err(&oct->pci_dev->dev, 454 "VF Liquidio driver (major version %d) is not compatible with Liquidio PF driver (major version %d)\n", 455 vfmajor, pfmajor); 456 return 1; 457 } 458 459 dev_dbg(&oct->pci_dev->dev, 460 "VF Liquidio driver (major version %d), Liquidio PF driver (major version %d)\n", 461 vfmajor, pfmajor); 462 463 dev_dbg(&oct->pci_dev->dev, "got data from pf pkind is %d\n", 464 oct->pfvf_hsword.pkind); 465 466 return 0; 467 } 468 469 static void cn23xx_handle_vf_mbox_intr(struct octeon_ioq_vector *ioq_vector) 470 { 471 struct octeon_device *oct = ioq_vector->oct_dev; 472 u64 mbox_int_val; 473 474 if (!ioq_vector->droq_index) { 475 /* read and clear by writing 1 */ 476 mbox_int_val = readq(oct->mbox[0]->mbox_int_reg); 477 writeq(mbox_int_val, oct->mbox[0]->mbox_int_reg); 478 if (octeon_mbox_read(oct->mbox[0])) 479 schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work, 480 msecs_to_jiffies(0)); 481 } 482 } 483 484 static u64 cn23xx_vf_msix_interrupt_handler(void *dev) 485 { 486 struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev; 487 struct octeon_device *oct = ioq_vector->oct_dev; 488 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index]; 489 u64 pkts_sent; 490 u64 ret = 0; 491 492 dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct); 493 pkts_sent = readq(droq->pkts_sent_reg); 494 495 /* If our device has interrupted, then proceed. Also check 496 * for all f's if interrupt was triggered on an error 497 * and the PCI read fails. 498 */ 499 if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL)) 500 return ret; 501 502 /* Write count reg in sli_pkt_cnts to clear these int. */ 503 if ((pkts_sent & CN23XX_INTR_PO_INT) || 504 (pkts_sent & CN23XX_INTR_PI_INT)) { 505 if (pkts_sent & CN23XX_INTR_PO_INT) 506 ret |= MSIX_PO_INT; 507 } 508 509 if (pkts_sent & CN23XX_INTR_PI_INT) 510 /* We will clear the count when we update the read_index. */ 511 ret |= MSIX_PI_INT; 512 513 if (pkts_sent & CN23XX_INTR_MBOX_INT) { 514 cn23xx_handle_vf_mbox_intr(ioq_vector); 515 ret |= MSIX_MBOX_INT; 516 } 517 518 return ret; 519 } 520 521 static u32 cn23xx_update_read_index(struct octeon_instr_queue *iq) 522 { 523 u32 pkt_in_done = readl(iq->inst_cnt_reg); 524 u32 last_done; 525 u32 new_idx; 526 527 last_done = pkt_in_done - iq->pkt_in_done; 528 iq->pkt_in_done = pkt_in_done; 529 530 /* Modulo of the new index with the IQ size will give us 531 * the new index. The iq->reset_instr_cnt is always zero for 532 * cn23xx, so no extra adjustments are needed. 533 */ 534 new_idx = (iq->octeon_read_index + 535 (u32)(last_done & CN23XX_PKT_IN_DONE_CNT_MASK)) % 536 iq->max_count; 537 538 return new_idx; 539 } 540 541 static void cn23xx_enable_vf_interrupt(struct octeon_device *oct, u8 intr_flag) 542 { 543 struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; 544 u32 q_no, time_threshold; 545 546 if (intr_flag & OCTEON_OUTPUT_INTR) { 547 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 548 /* Set up interrupt packet and time thresholds 549 * for all the OQs 550 */ 551 time_threshold = cn23xx_vf_get_oq_ticks( 552 oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf)); 553 554 octeon_write_csr64( 555 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), 556 (CFG_GET_OQ_INTR_PKT(cn23xx->conf) | 557 ((u64)time_threshold << 32))); 558 } 559 } 560 561 if (intr_flag & OCTEON_INPUT_INTR) { 562 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 563 /* Set CINT_ENB to enable IQ interrupt */ 564 octeon_write_csr64( 565 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), 566 ((octeon_read_csr64( 567 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) & 568 ~CN23XX_PKT_IN_DONE_CNT_MASK) | 569 CN23XX_INTR_CINT_ENB)); 570 } 571 } 572 573 /* Set queue-0 MBOX_ENB to enable VF mailbox interrupt */ 574 if (intr_flag & OCTEON_MBOX_INTR) { 575 octeon_write_csr64( 576 oct, CN23XX_VF_SLI_PKT_MBOX_INT(0), 577 (octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) | 578 CN23XX_INTR_MBOX_ENB)); 579 } 580 } 581 582 static void cn23xx_disable_vf_interrupt(struct octeon_device *oct, u8 intr_flag) 583 { 584 u32 q_no; 585 586 if (intr_flag & OCTEON_OUTPUT_INTR) { 587 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 588 /* Write all 1's in INT_LEVEL reg to disable PO_INT */ 589 octeon_write_csr64( 590 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), 591 0x3fffffffffffff); 592 } 593 } 594 if (intr_flag & OCTEON_INPUT_INTR) { 595 for (q_no = 0; q_no < oct->num_oqs; q_no++) { 596 octeon_write_csr64( 597 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no), 598 (octeon_read_csr64( 599 oct, CN23XX_VF_SLI_IQ_INSTR_COUNT64(q_no)) & 600 ~(CN23XX_INTR_CINT_ENB | 601 CN23XX_PKT_IN_DONE_CNT_MASK))); 602 } 603 } 604 605 if (intr_flag & OCTEON_MBOX_INTR) { 606 octeon_write_csr64( 607 oct, CN23XX_VF_SLI_PKT_MBOX_INT(0), 608 (octeon_read_csr64(oct, CN23XX_VF_SLI_PKT_MBOX_INT(0)) & 609 ~CN23XX_INTR_MBOX_ENB)); 610 } 611 } 612 613 int cn23xx_setup_octeon_vf_device(struct octeon_device *oct) 614 { 615 struct octeon_cn23xx_vf *cn23xx = (struct octeon_cn23xx_vf *)oct->chip; 616 u32 rings_per_vf, ring_flag; 617 u64 reg_val; 618 619 if (octeon_map_pci_barx(oct, 0, 0)) 620 return 1; 621 622 /* INPUT_CONTROL[RPVF] gives the VF IOq count */ 623 reg_val = octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(0)); 624 625 oct->pf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) & 626 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK; 627 oct->vf_num = (reg_val >> CN23XX_PKT_INPUT_CTL_VF_NUM_POS) & 628 CN23XX_PKT_INPUT_CTL_VF_NUM_MASK; 629 630 reg_val = reg_val >> CN23XX_PKT_INPUT_CTL_RPVF_POS; 631 632 rings_per_vf = reg_val & CN23XX_PKT_INPUT_CTL_RPVF_MASK; 633 634 ring_flag = 0; 635 636 cn23xx->conf = oct_get_config_info(oct, LIO_23XX); 637 if (!cn23xx->conf) { 638 dev_err(&oct->pci_dev->dev, "%s No Config found for CN23XX\n", 639 __func__); 640 octeon_unmap_pci_barx(oct, 0); 641 return 1; 642 } 643 644 if (oct->sriov_info.rings_per_vf > rings_per_vf) { 645 dev_warn(&oct->pci_dev->dev, 646 "num_queues:%d greater than PF configured rings_per_vf:%d. Reducing to %d.\n", 647 oct->sriov_info.rings_per_vf, rings_per_vf, 648 rings_per_vf); 649 oct->sriov_info.rings_per_vf = rings_per_vf; 650 } else { 651 if (rings_per_vf > num_present_cpus()) { 652 dev_warn(&oct->pci_dev->dev, 653 "PF configured rings_per_vf:%d greater than num_cpu:%d. Using rings_per_vf:%d equal to num cpus\n", 654 rings_per_vf, 655 num_present_cpus(), 656 num_present_cpus()); 657 oct->sriov_info.rings_per_vf = 658 num_present_cpus(); 659 } else { 660 oct->sriov_info.rings_per_vf = rings_per_vf; 661 } 662 } 663 664 oct->fn_list.setup_iq_regs = cn23xx_setup_vf_iq_regs; 665 oct->fn_list.setup_oq_regs = cn23xx_setup_vf_oq_regs; 666 oct->fn_list.setup_mbox = cn23xx_setup_vf_mbox; 667 oct->fn_list.free_mbox = cn23xx_free_vf_mbox; 668 669 oct->fn_list.msix_interrupt_handler = cn23xx_vf_msix_interrupt_handler; 670 671 oct->fn_list.setup_device_regs = cn23xx_setup_vf_device_regs; 672 oct->fn_list.update_iq_read_idx = cn23xx_update_read_index; 673 674 oct->fn_list.enable_interrupt = cn23xx_enable_vf_interrupt; 675 oct->fn_list.disable_interrupt = cn23xx_disable_vf_interrupt; 676 677 oct->fn_list.enable_io_queues = cn23xx_enable_vf_io_queues; 678 oct->fn_list.disable_io_queues = cn23xx_disable_vf_io_queues; 679 680 return 0; 681 } 682 683 void cn23xx_dump_vf_iq_regs(struct octeon_device *oct) 684 { 685 u32 regval, q_no; 686 687 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_DOORBELL_0 [0x%x]: 0x%016llx\n", 688 CN23XX_VF_SLI_IQ_DOORBELL(0), 689 CVM_CAST64(octeon_read_csr64( 690 oct, CN23XX_VF_SLI_IQ_DOORBELL(0)))); 691 692 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_BASEADDR_0 [0x%x]: 0x%016llx\n", 693 CN23XX_VF_SLI_IQ_BASE_ADDR64(0), 694 CVM_CAST64(octeon_read_csr64( 695 oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(0)))); 696 697 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_FIFO_RSIZE_0 [0x%x]: 0x%016llx\n", 698 CN23XX_VF_SLI_IQ_SIZE(0), 699 CVM_CAST64(octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_SIZE(0)))); 700 701 for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) { 702 dev_dbg(&oct->pci_dev->dev, "SLI_PKT[%d]_INPUT_CTL [0x%x]: 0x%016llx\n", 703 q_no, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no), 704 CVM_CAST64(octeon_read_csr64( 705 oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no)))); 706 } 707 708 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, ®val); 709 dev_dbg(&oct->pci_dev->dev, "Config DevCtl [0x%x]: 0x%08x\n", 710 CN23XX_CONFIG_PCIE_DEVCTL, regval); 711 } 712