1 /**********************************************************************
2  * Author: Cavium, Inc.
3  *
4  * Contact: support@cavium.com
5  *          Please include "LiquidIO" in the subject.
6  *
7  * Copyright (c) 2003-2016 Cavium, Inc.
8  *
9  * This file is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License, Version 2, as
11  * published by the Free Software Foundation.
12  *
13  * This file is distributed in the hope that it will be useful, but
14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16  * NONINFRINGEMENT.  See the GNU General Public License for more details.
17  ***********************************************************************/
18 /*! \file cn23xx_regs.h
19  * \brief Host Driver: Register Address and Register Mask values for
20  * Octeon CN23XX devices.
21  */
22 
23 #ifndef __CN23XX_PF_REGS_H__
24 #define __CN23XX_PF_REGS_H__
25 
26 #define     CN23XX_CONFIG_VENDOR_ID	0x00
27 #define     CN23XX_CONFIG_DEVICE_ID	0x02
28 
29 #define     CN23XX_CONFIG_XPANSION_BAR             0x38
30 
31 #define     CN23XX_CONFIG_MSIX_CAP		   0x50
32 #define     CN23XX_CONFIG_MSIX_LMSI		   0x54
33 #define     CN23XX_CONFIG_MSIX_UMSI		   0x58
34 #define     CN23XX_CONFIG_MSIX_MSIMD		   0x5C
35 #define     CN23XX_CONFIG_MSIX_MSIMM		   0x60
36 #define     CN23XX_CONFIG_MSIX_MSIMP		   0x64
37 
38 #define     CN23XX_CONFIG_PCIE_CAP                 0x70
39 #define     CN23XX_CONFIG_PCIE_DEVCAP              0x74
40 #define     CN23XX_CONFIG_PCIE_DEVCTL              0x78
41 #define     CN23XX_CONFIG_PCIE_LINKCAP             0x7C
42 #define     CN23XX_CONFIG_PCIE_LINKCTL             0x80
43 #define     CN23XX_CONFIG_PCIE_SLOTCAP             0x84
44 #define     CN23XX_CONFIG_PCIE_SLOTCTL             0x88
45 #define     CN23XX_CONFIG_PCIE_DEVCTL2             0x98
46 #define     CN23XX_CONFIG_PCIE_LINKCTL2            0xA0
47 #define     CN23XX_CONFIG_PCIE_UNCORRECT_ERR_MASK  0x108
48 #define     CN23XX_CONFIG_PCIE_CORRECT_ERR_STATUS  0x110
49 #define     CN23XX_CONFIG_PCIE_DEVCTL_MASK         0x00040000
50 
51 #define     CN23XX_PCIE_SRIOV_FDL		   0x188
52 #define     CN23XX_PCIE_SRIOV_FDL_BIT_POS	   0x10
53 #define     CN23XX_PCIE_SRIOV_FDL_MASK		   0xFF
54 
55 #define     CN23XX_CONFIG_PCIE_FLTMSK              0x720
56 
57 #define     CN23XX_CONFIG_SRIOV_VFDEVID            0x190
58 
59 #define     CN23XX_CONFIG_SRIOV_BAR_START	   0x19C
60 #define     CN23XX_CONFIG_SRIOV_BARX(i)		\
61 		(CN23XX_CONFIG_SRIOV_BAR_START + ((i) * 4))
62 #define     CN23XX_CONFIG_SRIOV_BAR_PF		   0x08
63 #define     CN23XX_CONFIG_SRIOV_BAR_64BIT	   0x04
64 #define     CN23XX_CONFIG_SRIOV_BAR_IO		   0x01
65 
66 /* ##############  BAR0 Registers ################ */
67 
68 #define    CN23XX_SLI_CTL_PORT_START               0x286E0
69 #define    CN23XX_PORT_OFFSET                      0x10
70 
71 #define    CN23XX_SLI_CTL_PORT(p)                  \
72 		(CN23XX_SLI_CTL_PORT_START + ((p) * CN23XX_PORT_OFFSET))
73 
74 /* 2 scatch registers (64-bit)  */
75 #define    CN23XX_SLI_WINDOW_CTL                   0x282E0
76 #define    CN23XX_SLI_SCRATCH1                     0x283C0
77 #define    CN23XX_SLI_SCRATCH2                     0x283D0
78 #define    CN23XX_SLI_WINDOW_CTL_DEFAULT           0x200000ULL
79 
80 /* 1 registers (64-bit)  - SLI_CTL_STATUS */
81 #define    CN23XX_SLI_CTL_STATUS                   0x28570
82 
83 /* SLI Packet Input Jabber Register (64 bit register)
84  * <31:0> for Byte count for limiting sizes of packet sizes
85  * that are allowed for sli packet inbound packets.
86  * the default value is 0xFA00(=64000).
87  */
88 #define    CN23XX_SLI_PKT_IN_JABBER                0x29170
89 /* The input jabber is used to determine the TSO max size.
90  * Due to H/W limitation, this need to be reduced to 60000
91  * in order to to H/W TSO and avoid the WQE malfarmation
92  * PKO_BUG_24989_WQE_LEN
93  */
94 #define    CN23XX_DEFAULT_INPUT_JABBER             0xEA60 /*60000*/
95 
96 #define    CN23XX_WIN_WR_ADDR_LO                   0x20000
97 #define    CN23XX_WIN_WR_ADDR_HI                   0x20004
98 #define    CN23XX_WIN_WR_ADDR64                    CN23XX_WIN_WR_ADDR_LO
99 
100 #define    CN23XX_WIN_RD_ADDR_LO                   0x20010
101 #define    CN23XX_WIN_RD_ADDR_HI                   0x20014
102 #define    CN23XX_WIN_RD_ADDR64                    CN23XX_WIN_RD_ADDR_LO
103 
104 #define    CN23XX_WIN_WR_DATA_LO                   0x20020
105 #define    CN23XX_WIN_WR_DATA_HI                   0x20024
106 #define    CN23XX_WIN_WR_DATA64                    CN23XX_WIN_WR_DATA_LO
107 
108 #define    CN23XX_WIN_RD_DATA_LO                   0x20040
109 #define    CN23XX_WIN_RD_DATA_HI                   0x20044
110 #define    CN23XX_WIN_RD_DATA64                    CN23XX_WIN_RD_DATA_LO
111 
112 #define    CN23XX_WIN_WR_MASK_LO                   0x20030
113 #define    CN23XX_WIN_WR_MASK_HI                   0x20034
114 #define    CN23XX_WIN_WR_MASK_REG                  CN23XX_WIN_WR_MASK_LO
115 #define    CN23XX_SLI_MAC_CREDIT_CNT               0x23D70
116 
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
118  * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO
119  */
120 #define    CN23XX_SLI_PKT_MAC_RINFO_START64       0x29030
121 
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
123 #define    CN23XX_SLI_PKT_IOQ_RING_RST            0x291E0
124 
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
126 #define    CN23XX_IQ_OFFSET                       0x20000
127 
128 #define    CN23XX_MAC_RINFO_OFFSET                0x20
129 #define    CN23XX_PF_RINFO_OFFSET                 0x10
130 
131 #define CN23XX_SLI_PKT_MAC_RINFO64(mac, pf)		\
132 		(CN23XX_SLI_PKT_MAC_RINFO_START64 +     \
133 		 ((mac) * CN23XX_MAC_RINFO_OFFSET) +	\
134 		 ((pf) * CN23XX_PF_RINFO_OFFSET))
135 
136 /** mask for total rings, setting TRS to base */
137 #define    CN23XX_PKT_MAC_CTL_RINFO_TRS               BIT_ULL(16)
138 /** mask for starting ring number: setting SRN <6:0> = 0x7F */
139 #define    CN23XX_PKT_MAC_CTL_RINFO_SRN               (0x7F)
140 
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
142 #define    CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS     16
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
144 #define    CN23XX_PKT_MAC_CTL_RINFO_SRN_BIT_POS     0
145 /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */
146 #define    CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS     32
147 /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
148 #define    CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS     48
149 
150 /*###################### REQUEST QUEUE #########################*/
151 
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
153 #define    CN23XX_SLI_IQ_INSTR_COUNT_START64     0x10040
154 
155 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
156 #define    CN23XX_SLI_IQ_BASE_ADDR_START64       0x10010
157 
158 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
159 #define    CN23XX_SLI_IQ_DOORBELL_START          0x10020
160 
161 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
162 #define    CN23XX_SLI_IQ_SIZE_START              0x10030
163 
164 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
165  * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL.
166  */
167 #define    CN23XX_SLI_IQ_PKT_CONTROL_START64    0x10000
168 
169 /*------- Request Queue Macros ---------*/
170 #define    CN23XX_SLI_IQ_PKT_CONTROL64(iq)          \
171 		(CN23XX_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET))
172 
173 #define    CN23XX_SLI_IQ_BASE_ADDR64(iq)          \
174 		(CN23XX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_IQ_OFFSET))
175 
176 #define    CN23XX_SLI_IQ_SIZE(iq)                 \
177 		(CN23XX_SLI_IQ_SIZE_START + ((iq) * CN23XX_IQ_OFFSET))
178 
179 #define    CN23XX_SLI_IQ_DOORBELL(iq)             \
180 		(CN23XX_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_IQ_OFFSET))
181 
182 #define    CN23XX_SLI_IQ_INSTR_COUNT64(iq)          \
183 		(CN23XX_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_IQ_OFFSET))
184 
185 /*------------------ Masks ----------------*/
186 #define    CN23XX_PKT_INPUT_CTL_VF_NUM                  BIT_ULL(32)
187 #define    CN23XX_PKT_INPUT_CTL_MAC_NUM                 BIT(29)
188 /* Number of instructions to be read in one MAC read request.
189  * setting to Max value(4)
190  */
191 #define    CN23XX_PKT_INPUT_CTL_RDSIZE                  (3 << 25)
192 #define    CN23XX_PKT_INPUT_CTL_IS_64B                  BIT(24)
193 #define    CN23XX_PKT_INPUT_CTL_RST                     BIT(23)
194 #define    CN23XX_PKT_INPUT_CTL_QUIET                   BIT(28)
195 #define    CN23XX_PKT_INPUT_CTL_RING_ENB                BIT(22)
196 #define    CN23XX_PKT_INPUT_CTL_DATA_NS                 BIT(8)
197 #define    CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP        BIT(6)
198 #define    CN23XX_PKT_INPUT_CTL_DATA_RO                 BIT(5)
199 #define    CN23XX_PKT_INPUT_CTL_USE_CSR                 BIT(4)
200 #define    CN23XX_PKT_INPUT_CTL_GATHER_NS               BIT(3)
201 #define    CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP      (2)
202 #define    CN23XX_PKT_INPUT_CTL_GATHER_RO               (1)
203 
204 /** Rings per Virtual Function **/
205 #define    CN23XX_PKT_INPUT_CTL_RPVF_MASK               (0x3F)
206 #define    CN23XX_PKT_INPUT_CTL_RPVF_POS                (48)
207 /** These bits[47:44] select the Physical function number within the MAC */
208 #define    CN23XX_PKT_INPUT_CTL_PF_NUM_MASK             (0x7)
209 #define    CN23XX_PKT_INPUT_CTL_PF_NUM_POS              (45)
210 /** These bits[43:32] select the function number within the PF */
211 #define    CN23XX_PKT_INPUT_CTL_VF_NUM_MASK             (0x1FFF)
212 #define    CN23XX_PKT_INPUT_CTL_VF_NUM_POS              (32)
213 #define    CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK            (0x3)
214 #define    CN23XX_PKT_INPUT_CTL_MAC_NUM_POS             (29)
215 #define    CN23XX_PKT_IN_DONE_WMARK_MASK                (0xFFFFULL)
216 #define    CN23XX_PKT_IN_DONE_WMARK_BIT_POS             (32)
217 #define    CN23XX_PKT_IN_DONE_CNT_MASK                  (0x00000000FFFFFFFFULL)
218 
219 #ifdef __LITTLE_ENDIAN_BITFIELD
220 #define    CN23XX_PKT_INPUT_CTL_MASK				\
221 		(CN23XX_PKT_INPUT_CTL_RDSIZE		|	\
222 		 CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP	|	\
223 		 CN23XX_PKT_INPUT_CTL_USE_CSR)
224 #else
225 #define    CN23XX_PKT_INPUT_CTL_MASK				\
226 		(CN23XX_PKT_INPUT_CTL_RDSIZE		|	\
227 		 CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP	|	\
228 		 CN23XX_PKT_INPUT_CTL_USE_CSR		|	\
229 		 CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP)
230 #endif
231 
232 /** Masks for SLI_PKT_IN_DONE(0..63)_CNTS Register */
233 #define    CN23XX_IN_DONE_CNTS_PI_INT               BIT_ULL(62)
234 #define    CN23XX_IN_DONE_CNTS_CINT_ENB             BIT_ULL(48)
235 
236 /*############################ OUTPUT QUEUE #########################*/
237 
238 /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */
239 #define    CN23XX_SLI_OQ_PKT_CONTROL_START       0x10050
240 
241 /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */
242 #define    CN23XX_SLI_OQ0_BUFF_INFO_SIZE         0x10060
243 
244 /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */
245 #define    CN23XX_SLI_OQ_BASE_ADDR_START64       0x10070
246 
247 /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */
248 #define    CN23XX_SLI_OQ_PKT_CREDITS_START       0x10080
249 
250 /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */
251 #define    CN23XX_SLI_OQ_SIZE_START              0x10090
252 
253 /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */
254 #define    CN23XX_SLI_OQ_PKT_SENT_START          0x100B0
255 
256 /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */
257 #define    CN23XX_SLI_OQ_PKT_INT_LEVELS_START64   0x100A0
258 
259 /* Each Output Queue register is at a 16-byte Offset in BAR0 */
260 #define    CN23XX_OQ_OFFSET                      0x20000
261 
262 /* 1 (64-bit register) for Output Queue backpressure across all rings. */
263 #define    CN23XX_SLI_OQ_WMARK                   0x29180
264 
265 /* Global pkt control register */
266 #define    CN23XX_SLI_GBL_CONTROL                0x29210
267 
268 /* Backpressure enable register for PF0  */
269 #define    CN23XX_SLI_OUT_BP_EN_W1S              0x29260
270 
271 /* Backpressure enable register for PF1  */
272 #define    CN23XX_SLI_OUT_BP_EN2_W1S             0x29270
273 
274 /* Backpressure disable register for PF0  */
275 #define    CN23XX_SLI_OUT_BP_EN_W1C              0x29280
276 
277 /* Backpressure disable register for PF1  */
278 #define    CN23XX_SLI_OUT_BP_EN2_W1C             0x29290
279 
280 /*------- Output Queue Macros ---------*/
281 
282 #define    CN23XX_SLI_OQ_PKT_CONTROL(oq)          \
283 		(CN23XX_SLI_OQ_PKT_CONTROL_START + ((oq) * CN23XX_OQ_OFFSET))
284 
285 #define    CN23XX_SLI_OQ_BASE_ADDR64(oq)          \
286 		(CN23XX_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN23XX_OQ_OFFSET))
287 
288 #define    CN23XX_SLI_OQ_SIZE(oq)                 \
289 		(CN23XX_SLI_OQ_SIZE_START + ((oq) * CN23XX_OQ_OFFSET))
290 
291 #define    CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq)                 \
292 		(CN23XX_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN23XX_OQ_OFFSET))
293 
294 #define    CN23XX_SLI_OQ_PKTS_SENT(oq)            \
295 		(CN23XX_SLI_OQ_PKT_SENT_START + ((oq) * CN23XX_OQ_OFFSET))
296 
297 #define    CN23XX_SLI_OQ_PKTS_CREDIT(oq)          \
298 		(CN23XX_SLI_OQ_PKT_CREDITS_START + ((oq) * CN23XX_OQ_OFFSET))
299 
300 #define    CN23XX_SLI_OQ_PKT_INT_LEVELS(oq)		\
301 		(CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 +	\
302 		 ((oq) * CN23XX_OQ_OFFSET))
303 
304 /*Macro's for accessing CNT and TIME separately from INT_LEVELS*/
305 #define    CN23XX_SLI_OQ_PKT_INT_LEVELS_CNT(oq)		\
306 		(CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 + \
307 		 ((oq) * CN23XX_OQ_OFFSET))
308 
309 #define    CN23XX_SLI_OQ_PKT_INT_LEVELS_TIME(oq)	\
310 		(CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 +	\
311 		 ((oq) * CN23XX_OQ_OFFSET) + 4)
312 
313 /*------------------ Masks ----------------*/
314 #define    CN23XX_PKT_OUTPUT_CTL_TENB                  BIT(13)
315 #define    CN23XX_PKT_OUTPUT_CTL_CENB                  BIT(12)
316 #define    CN23XX_PKT_OUTPUT_CTL_IPTR                  BIT(11)
317 #define    CN23XX_PKT_OUTPUT_CTL_ES                    BIT(9)
318 #define    CN23XX_PKT_OUTPUT_CTL_NSR                   BIT(8)
319 #define    CN23XX_PKT_OUTPUT_CTL_ROR                   BIT(7)
320 #define    CN23XX_PKT_OUTPUT_CTL_DPTR                  BIT(6)
321 #define    CN23XX_PKT_OUTPUT_CTL_BMODE                 BIT(5)
322 #define    CN23XX_PKT_OUTPUT_CTL_ES_P                  BIT(3)
323 #define    CN23XX_PKT_OUTPUT_CTL_NSR_P                 BIT(2)
324 #define    CN23XX_PKT_OUTPUT_CTL_ROR_P                 BIT(1)
325 #define    CN23XX_PKT_OUTPUT_CTL_RING_ENB              BIT(0)
326 
327 /*######################### Mailbox Reg Macros ########################*/
328 #define    CN23XX_SLI_PKT_MBOX_INT_START             0x10210
329 #define    CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START       0x10200
330 #define    CN23XX_SLI_MAC_PF_MBOX_INT_START          0x27380
331 
332 #define    CN23XX_SLI_MBOX_OFFSET		     0x20000
333 #define    CN23XX_SLI_MBOX_SIG_IDX_OFFSET	     0x8
334 
335 #define    CN23XX_SLI_PKT_MBOX_INT(q)          \
336 		(CN23XX_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET))
337 
338 #define    CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx)		\
339 		(CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START +		\
340 		 ((q) * CN23XX_SLI_MBOX_OFFSET +		\
341 		  (idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET))
342 
343 #define    CN23XX_SLI_MAC_PF_MBOX_INT(mac, pf)		\
344 		(CN23XX_SLI_MAC_PF_MBOX_INT_START +	\
345 		 ((mac) * CN23XX_MAC_INT_OFFSET +	\
346 		  (pf) * CN23XX_PF_INT_OFFSET))
347 
348 /*######################### DMA Counters #########################*/
349 
350 /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */
351 #define    CN23XX_DMA_CNT_START                   0x28400
352 
353 /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values */
354 /* SLI_DMA_0_TIM */
355 #define    CN23XX_DMA_TIM_START                   0x28420
356 
357 /* 2 registers (64-bit) - DMA count & Time Interrupt threshold -
358  * SLI_DMA_0_INT_LEVEL
359  */
360 #define    CN23XX_DMA_INT_LEVEL_START             0x283E0
361 
362 /* Each DMA register is at a 16-byte Offset in BAR0 */
363 #define    CN23XX_DMA_OFFSET                      0x10
364 
365 /*---------- DMA Counter Macros ---------*/
366 #define    CN23XX_DMA_CNT(dq)                      \
367 		(CN23XX_DMA_CNT_START + ((dq) * CN23XX_DMA_OFFSET))
368 
369 #define    CN23XX_DMA_INT_LEVEL(dq)                \
370 		(CN23XX_DMA_INT_LEVEL_START + ((dq) * CN23XX_DMA_OFFSET))
371 
372 #define    CN23XX_DMA_PKT_INT_LEVEL(dq)            \
373 		(CN23XX_DMA_INT_LEVEL_START + ((dq) * CN23XX_DMA_OFFSET))
374 
375 #define    CN23XX_DMA_TIME_INT_LEVEL(dq)           \
376 		(CN23XX_DMA_INT_LEVEL_START + 4 + ((dq) * CN23XX_DMA_OFFSET))
377 
378 #define    CN23XX_DMA_TIM(dq)                     \
379 		(CN23XX_DMA_TIM_START + ((dq) * CN23XX_DMA_OFFSET))
380 
381 /*######################## MSIX TABLE #########################*/
382 
383 #define	CN23XX_MSIX_TABLE_ADDR_START		0x0
384 #define	CN23XX_MSIX_TABLE_DATA_START		0x8
385 
386 #define	CN23XX_MSIX_TABLE_SIZE			0x10
387 #define	CN23XX_MSIX_TABLE_ENTRIES		0x41
388 
389 #define CN23XX_MSIX_ENTRY_VECTOR_CTL	BIT_ULL(32)
390 
391 #define	CN23XX_MSIX_TABLE_ADDR(idx)		\
392 	(CN23XX_MSIX_TABLE_ADDR_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
393 
394 #define	CN23XX_MSIX_TABLE_DATA(idx)		\
395 	(CN23XX_MSIX_TABLE_DATA_START + ((idx) * CN23XX_MSIX_TABLE_SIZE))
396 
397 /*######################## INTERRUPTS #########################*/
398 #define CN23XX_MAC_INT_OFFSET   0x20
399 #define CN23XX_PF_INT_OFFSET    0x10
400 
401 /* 1 register (64-bit) for Interrupt Summary */
402 #define    CN23XX_SLI_INT_SUM64            0x27000
403 
404 /* 4 registers (64-bit) for Interrupt Enable for each Port */
405 #define    CN23XX_SLI_INT_ENB64            0x27080
406 
407 #define    CN23XX_SLI_MAC_PF_INT_SUM64(mac, pf)			\
408 		(CN23XX_SLI_INT_SUM64 +				\
409 		 ((mac) * CN23XX_MAC_INT_OFFSET) +		\
410 		 ((pf) * CN23XX_PF_INT_OFFSET))
411 
412 #define    CN23XX_SLI_MAC_PF_INT_ENB64(mac, pf)		\
413 		(CN23XX_SLI_INT_ENB64 +			\
414 		 ((mac) * CN23XX_MAC_INT_OFFSET) +	\
415 		 ((pf) * CN23XX_PF_INT_OFFSET))
416 
417 /* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */
418 #define    CN23XX_SLI_PKT_CNT_INT                0x29130
419 
420 /* 1 register (64-bit) to indicate which Output Queue reached time threshold */
421 #define    CN23XX_SLI_PKT_TIME_INT               0x29140
422 
423 /*------------------ Interrupt Masks ----------------*/
424 
425 #define    CN23XX_INTR_PO_INT			BIT_ULL(63)
426 #define    CN23XX_INTR_PI_INT			BIT_ULL(62)
427 #define    CN23XX_INTR_MBOX_INT			BIT_ULL(61)
428 #define    CN23XX_INTR_RESEND			BIT_ULL(60)
429 
430 #define    CN23XX_INTR_CINT_ENB                 BIT_ULL(48)
431 #define    CN23XX_INTR_MBOX_ENB                 BIT(0)
432 
433 #define    CN23XX_INTR_RML_TIMEOUT_ERR           (1)
434 
435 #define    CN23XX_INTR_MIO_INT                   BIT(1)
436 
437 #define    CN23XX_INTR_RESERVED1                 (3 << 2)
438 
439 #define    CN23XX_INTR_PKT_COUNT                 BIT(4)
440 #define    CN23XX_INTR_PKT_TIME                  BIT(5)
441 
442 #define    CN23XX_INTR_RESERVED2                 (3 << 6)
443 
444 #define    CN23XX_INTR_M0UPB0_ERR                BIT(8)
445 #define    CN23XX_INTR_M0UPWI_ERR                BIT(9)
446 #define    CN23XX_INTR_M0UNB0_ERR                BIT(10)
447 #define    CN23XX_INTR_M0UNWI_ERR                BIT(11)
448 
449 #define    CN23XX_INTR_RESERVED3                 (0xFFFFFULL << 12)
450 
451 #define    CN23XX_INTR_DMA0_FORCE                BIT_ULL(32)
452 #define    CN23XX_INTR_DMA1_FORCE                BIT_ULL(33)
453 
454 #define    CN23XX_INTR_DMA0_COUNT                BIT_ULL(34)
455 #define    CN23XX_INTR_DMA1_COUNT                BIT_ULL(35)
456 
457 #define    CN23XX_INTR_DMA0_TIME                 BIT_ULL(36)
458 #define    CN23XX_INTR_DMA1_TIME                 BIT_ULL(37)
459 
460 #define    CN23XX_INTR_RESERVED4                 (0x7FFFFULL << 38)
461 
462 #define    CN23XX_INTR_VF_MBOX                   BIT_ULL(57)
463 #define    CN23XX_INTR_DMAVF_ERR                 BIT_ULL(58)
464 #define    CN23XX_INTR_DMAPF_ERR                 BIT_ULL(59)
465 
466 #define    CN23XX_INTR_PKTVF_ERR                 BIT_ULL(60)
467 #define    CN23XX_INTR_PKTPF_ERR                 BIT_ULL(61)
468 #define    CN23XX_INTR_PPVF_ERR                  BIT_ULL(62)
469 #define    CN23XX_INTR_PPPF_ERR                  BIT_ULL(63)
470 
471 #define    CN23XX_INTR_DMA0_DATA                 (CN23XX_INTR_DMA0_TIME)
472 #define    CN23XX_INTR_DMA1_DATA                 (CN23XX_INTR_DMA1_TIME)
473 
474 #define    CN23XX_INTR_DMA_DATA                  \
475 		(CN23XX_INTR_DMA0_DATA | CN23XX_INTR_DMA1_DATA)
476 
477 /* By fault only TIME based */
478 #define    CN23XX_INTR_PKT_DATA                  (CN23XX_INTR_PKT_TIME)
479 /* For both COUNT and TIME based */
480 /* #define    CN23XX_INTR_PKT_DATA                  \
481  * (CN23XX_INTR_PKT_COUNT | CN23XX_INTR_PKT_TIME)
482  */
483 
484 /* Sum of interrupts for all PCI-Express Data Interrupts */
485 #define    CN23XX_INTR_PCIE_DATA                 \
486 		(CN23XX_INTR_DMA_DATA | CN23XX_INTR_PKT_DAT)
487 
488 /* Sum of interrupts for error events */
489 #define    CN23XX_INTR_ERR			\
490 		(CN23XX_INTR_M0UPB0_ERR	|	\
491 		 CN23XX_INTR_M0UPWI_ERR	|	\
492 		 CN23XX_INTR_M0UNB0_ERR	|	\
493 		 CN23XX_INTR_M0UNWI_ERR	|	\
494 		 CN23XX_INTR_DMAVF_ERR	|	\
495 		 CN23XX_INTR_DMAPF_ERR	|	\
496 		 CN23XX_INTR_PKTPF_ERR	|	\
497 		 CN23XX_INTR_PPPF_ERR	|	\
498 		 CN23XX_INTR_PPVF_ERR)
499 
500 /* Programmed Mask for Interrupt Sum */
501 #define    CN23XX_INTR_MASK			\
502 		(CN23XX_INTR_DMA_DATA	|	\
503 		 CN23XX_INTR_DMA0_FORCE	|	\
504 		 CN23XX_INTR_DMA1_FORCE	|	\
505 		 CN23XX_INTR_MIO_INT	|	\
506 		 CN23XX_INTR_ERR)
507 
508 /* 4 Registers (64 - bit) */
509 #define    CN23XX_SLI_S2M_PORT_CTL_START         0x23D80
510 #define    CN23XX_SLI_S2M_PORTX_CTL(port)	\
511 		(CN23XX_SLI_S2M_PORT_CTL_START + ((port) * 0x10))
512 
513 #define    CN23XX_SLI_MAC_NUMBER                 0x20050
514 
515 /** PEM(0..3)_BAR1_INDEX(0..15)address is defined as
516  *  addr = (0x00011800C0000100  |port <<24 |idx <<3 )
517  *  Here, port is PEM(0..3) & idx is INDEX(0..15)
518  */
519 #define    CN23XX_PEM_BAR1_INDEX_START             0x00011800C0000100ULL
520 #define    CN23XX_PEM_OFFSET                       24
521 #define    CN23XX_BAR1_INDEX_OFFSET                3
522 
523 #define    CN23XX_PEM_BAR1_INDEX_REG(port, idx)		\
524 		(CN23XX_PEM_BAR1_INDEX_START + ((port) << CN23XX_PEM_OFFSET) + \
525 		 ((idx) << CN23XX_BAR1_INDEX_OFFSET))
526 
527 /*############################ DPI #########################*/
528 
529 /* 1 register (64-bit) - provides DMA Enable */
530 #define    CN23XX_DPI_CTL                 0x0001df0000000040ULL
531 
532 /* 1 register (64-bit) - Controls the DMA IO Operation */
533 #define    CN23XX_DPI_DMA_CONTROL         0x0001df0000000048ULL
534 
535 /* 1 register (64-bit) - Provides DMA Instr'n Queue Enable  */
536 #define    CN23XX_DPI_REQ_GBL_ENB         0x0001df0000000050ULL
537 
538 /* 1 register (64-bit) - DPI_REQ_ERR_RSP
539  * Indicates which Instr'n Queue received error response from the IO sub-system
540  */
541 #define    CN23XX_DPI_REQ_ERR_RSP         0x0001df0000000058ULL
542 
543 /* 1 register (64-bit) - DPI_REQ_ERR_RST
544  * Indicates which Instr'n Queue dropped an Instr'n
545  */
546 #define    CN23XX_DPI_REQ_ERR_RST         0x0001df0000000060ULL
547 
548 /* 6 register (64-bit) - DPI_DMA_ENG(0..5)_EN
549  * Provides DMA Engine Queue Enable
550  */
551 #define    CN23XX_DPI_DMA_ENG0_ENB        0x0001df0000000080ULL
552 #define    CN23XX_DPI_DMA_ENG_ENB(eng) (CN23XX_DPI_DMA_ENG0_ENB + ((eng) * 8))
553 
554 /* 8 register (64-bit) - DPI_DMA(0..7)_REQQ_CTL
555  * Provides control bits for transaction on 8 Queues
556  */
557 #define    CN23XX_DPI_DMA_REQQ0_CTL       0x0001df0000000180ULL
558 #define    CN23XX_DPI_DMA_REQQ_CTL(q_no)	\
559 		(CN23XX_DPI_DMA_REQQ0_CTL + ((q_no) * 8))
560 
561 /* 6 register (64-bit) - DPI_ENG(0..5)_BUF
562  * Provides DMA Engine FIFO (Queue) Size
563  */
564 #define    CN23XX_DPI_DMA_ENG0_BUF        0x0001df0000000880ULL
565 #define    CN23XX_DPI_DMA_ENG_BUF(eng)   \
566 		(CN23XX_DPI_DMA_ENG0_BUF + ((eng) * 8))
567 
568 /* 4 Registers (64-bit) */
569 #define    CN23XX_DPI_SLI_PRT_CFG_START   0x0001df0000000900ULL
570 #define    CN23XX_DPI_SLI_PRTX_CFG(port)        \
571 		(CN23XX_DPI_SLI_PRT_CFG_START + ((port) * 0x8))
572 
573 /* Masks for DPI_DMA_CONTROL Register */
574 #define    CN23XX_DPI_DMA_COMMIT_MODE     BIT_ULL(58)
575 #define    CN23XX_DPI_DMA_PKT_EN          BIT_ULL(56)
576 #define    CN23XX_DPI_DMA_ENB             (0x0FULL << 48)
577 /* Set the DMA Control, to update packet count not byte count sent by DMA,
578  * when we use Interrupt Coalescing (CA mode)
579  */
580 #define    CN23XX_DPI_DMA_O_ADD1          BIT(19)
581 /*selecting 64-bit Byte Swap Mode */
582 #define    CN23XX_DPI_DMA_O_ES            BIT(15)
583 #define    CN23XX_DPI_DMA_O_MODE          BIT(14)
584 
585 #define    CN23XX_DPI_DMA_CTL_MASK			\
586 		(CN23XX_DPI_DMA_COMMIT_MODE	|	\
587 		 CN23XX_DPI_DMA_PKT_EN		|	\
588 		 CN23XX_DPI_DMA_O_ES		|	\
589 		 CN23XX_DPI_DMA_O_MODE)
590 
591 /*############################ RST #########################*/
592 
593 #define    CN23XX_RST_BOOT            0x0001180006001600ULL
594 #define    CN23XX_RST_SOFT_RST        0x0001180006001680ULL
595 
596 #define    CN23XX_LMC0_RESET_CTL               0x0001180088000180ULL
597 #define    CN23XX_LMC0_RESET_CTL_DDR3RST_MASK  0x0000000000000001ULL
598 
599 #endif
600