15bc67f58SRaghu Vatsavayi /********************************************************************** 25bc67f58SRaghu Vatsavayi * Author: Cavium, Inc. 35bc67f58SRaghu Vatsavayi * 45bc67f58SRaghu Vatsavayi * Contact: support@cavium.com 55bc67f58SRaghu Vatsavayi * Please include "LiquidIO" in the subject. 65bc67f58SRaghu Vatsavayi * 750579d3dSRaghu Vatsavayi * Copyright (c) 2003-2016 Cavium, Inc. 85bc67f58SRaghu Vatsavayi * 95bc67f58SRaghu Vatsavayi * This file is free software; you can redistribute it and/or modify 105bc67f58SRaghu Vatsavayi * it under the terms of the GNU General Public License, Version 2, as 115bc67f58SRaghu Vatsavayi * published by the Free Software Foundation. 125bc67f58SRaghu Vatsavayi * 135bc67f58SRaghu Vatsavayi * This file is distributed in the hope that it will be useful, but 145bc67f58SRaghu Vatsavayi * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 155bc67f58SRaghu Vatsavayi * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 1650579d3dSRaghu Vatsavayi * NONINFRINGEMENT. See the GNU General Public License for more details. 1750579d3dSRaghu Vatsavayi ***********************************************************************/ 185bc67f58SRaghu Vatsavayi /*! \file cn23xx_regs.h 195bc67f58SRaghu Vatsavayi * \brief Host Driver: Register Address and Register Mask values for 205bc67f58SRaghu Vatsavayi * Octeon CN23XX devices. 215bc67f58SRaghu Vatsavayi */ 225bc67f58SRaghu Vatsavayi 235bc67f58SRaghu Vatsavayi #ifndef __CN23XX_PF_REGS_H__ 245bc67f58SRaghu Vatsavayi #define __CN23XX_PF_REGS_H__ 255bc67f58SRaghu Vatsavayi 265bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_VENDOR_ID 0x00 275bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_DEVICE_ID 0x02 285bc67f58SRaghu Vatsavayi 295bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_XPANSION_BAR 0x38 305bc67f58SRaghu Vatsavayi 315bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_MSIX_CAP 0x50 325bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_MSIX_LMSI 0x54 335bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_MSIX_UMSI 0x58 345bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_MSIX_MSIMD 0x5C 355bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_MSIX_MSIMM 0x60 365bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_MSIX_MSIMP 0x64 375bc67f58SRaghu Vatsavayi 385bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_CAP 0x70 395bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_DEVCAP 0x74 405bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_DEVCTL 0x78 415bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_LINKCAP 0x7C 425bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_LINKCTL 0x80 435bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_SLOTCAP 0x84 445bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_SLOTCTL 0x88 455bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_DEVCTL2 0x98 465bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_LINKCTL2 0xA0 475bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_UNCORRECT_ERR_MASK 0x108 485bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_CORRECT_ERR_STATUS 0x110 495bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_DEVCTL_MASK 0x00040000 505bc67f58SRaghu Vatsavayi 515bc67f58SRaghu Vatsavayi #define CN23XX_PCIE_SRIOV_FDL 0x188 525bc67f58SRaghu Vatsavayi #define CN23XX_PCIE_SRIOV_FDL_BIT_POS 0x10 535bc67f58SRaghu Vatsavayi #define CN23XX_PCIE_SRIOV_FDL_MASK 0xFF 545bc67f58SRaghu Vatsavayi 555bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_PCIE_FLTMSK 0x720 565bc67f58SRaghu Vatsavayi 575bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_SRIOV_VFDEVID 0x190 585bc67f58SRaghu Vatsavayi 595bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_SRIOV_BAR_START 0x19C 605bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_SRIOV_BARX(i) \ 6197a25326SRaghu Vatsavayi (CN23XX_CONFIG_SRIOV_BAR_START + ((i) * 4)) 625bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_SRIOV_BAR_PF 0x08 635bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_SRIOV_BAR_64BIT 0x04 645bc67f58SRaghu Vatsavayi #define CN23XX_CONFIG_SRIOV_BAR_IO 0x01 655bc67f58SRaghu Vatsavayi 665bc67f58SRaghu Vatsavayi /* ############## BAR0 Registers ################ */ 675bc67f58SRaghu Vatsavayi 685bc67f58SRaghu Vatsavayi #define CN23XX_SLI_CTL_PORT_START 0x286E0 695bc67f58SRaghu Vatsavayi #define CN23XX_PORT_OFFSET 0x10 705bc67f58SRaghu Vatsavayi 715bc67f58SRaghu Vatsavayi #define CN23XX_SLI_CTL_PORT(p) \ 725bc67f58SRaghu Vatsavayi (CN23XX_SLI_CTL_PORT_START + ((p) * CN23XX_PORT_OFFSET)) 735bc67f58SRaghu Vatsavayi 745bc67f58SRaghu Vatsavayi /* 2 scatch registers (64-bit) */ 755bc67f58SRaghu Vatsavayi #define CN23XX_SLI_WINDOW_CTL 0x282E0 765bc67f58SRaghu Vatsavayi #define CN23XX_SLI_SCRATCH1 0x283C0 775bc67f58SRaghu Vatsavayi #define CN23XX_SLI_SCRATCH2 0x283D0 785bc67f58SRaghu Vatsavayi #define CN23XX_SLI_WINDOW_CTL_DEFAULT 0x200000ULL 795bc67f58SRaghu Vatsavayi 805bc67f58SRaghu Vatsavayi /* 1 registers (64-bit) - SLI_CTL_STATUS */ 815bc67f58SRaghu Vatsavayi #define CN23XX_SLI_CTL_STATUS 0x28570 825bc67f58SRaghu Vatsavayi 835bc67f58SRaghu Vatsavayi /* SLI Packet Input Jabber Register (64 bit register) 845bc67f58SRaghu Vatsavayi * <31:0> for Byte count for limiting sizes of packet sizes 855bc67f58SRaghu Vatsavayi * that are allowed for sli packet inbound packets. 865bc67f58SRaghu Vatsavayi * the default value is 0xFA00(=64000). 875bc67f58SRaghu Vatsavayi */ 885bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_IN_JABBER 0x29170 895bc67f58SRaghu Vatsavayi /* The input jabber is used to determine the TSO max size. 905bc67f58SRaghu Vatsavayi * Due to H/W limitation, this need to be reduced to 60000 915bc67f58SRaghu Vatsavayi * in order to to H/W TSO and avoid the WQE malfarmation 925bc67f58SRaghu Vatsavayi * PKO_BUG_24989_WQE_LEN 935bc67f58SRaghu Vatsavayi */ 945bc67f58SRaghu Vatsavayi #define CN23XX_DEFAULT_INPUT_JABBER 0xEA60 /*60000*/ 955bc67f58SRaghu Vatsavayi 965bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_ADDR_LO 0x20000 975bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_ADDR_HI 0x20004 985bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_ADDR64 CN23XX_WIN_WR_ADDR_LO 995bc67f58SRaghu Vatsavayi 1005bc67f58SRaghu Vatsavayi #define CN23XX_WIN_RD_ADDR_LO 0x20010 1015bc67f58SRaghu Vatsavayi #define CN23XX_WIN_RD_ADDR_HI 0x20014 1025bc67f58SRaghu Vatsavayi #define CN23XX_WIN_RD_ADDR64 CN23XX_WIN_RD_ADDR_LO 1035bc67f58SRaghu Vatsavayi 1045bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_DATA_LO 0x20020 1055bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_DATA_HI 0x20024 1065bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_DATA64 CN23XX_WIN_WR_DATA_LO 1075bc67f58SRaghu Vatsavayi 1085bc67f58SRaghu Vatsavayi #define CN23XX_WIN_RD_DATA_LO 0x20040 1095bc67f58SRaghu Vatsavayi #define CN23XX_WIN_RD_DATA_HI 0x20044 1105bc67f58SRaghu Vatsavayi #define CN23XX_WIN_RD_DATA64 CN23XX_WIN_RD_DATA_LO 1115bc67f58SRaghu Vatsavayi 1125bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_MASK_LO 0x20030 1135bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_MASK_HI 0x20034 1145bc67f58SRaghu Vatsavayi #define CN23XX_WIN_WR_MASK_REG CN23XX_WIN_WR_MASK_LO 1155bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MAC_CREDIT_CNT 0x23D70 1165bc67f58SRaghu Vatsavayi 1175bc67f58SRaghu Vatsavayi /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)- 1185bc67f58SRaghu Vatsavayi * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO 1195bc67f58SRaghu Vatsavayi */ 1205bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_MAC_RINFO_START64 0x29030 1215bc67f58SRaghu Vatsavayi 1225bc67f58SRaghu Vatsavayi /*1 register (64-bit) to determine whether IOQs are in reset. */ 1235bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_IOQ_RING_RST 0x291E0 1245bc67f58SRaghu Vatsavayi 1255bc67f58SRaghu Vatsavayi /* Each Input Queue register is at a 16-byte Offset in BAR0 */ 1265bc67f58SRaghu Vatsavayi #define CN23XX_IQ_OFFSET 0x20000 1275bc67f58SRaghu Vatsavayi 1285bc67f58SRaghu Vatsavayi #define CN23XX_MAC_RINFO_OFFSET 0x20 1295bc67f58SRaghu Vatsavayi #define CN23XX_PF_RINFO_OFFSET 0x10 1305bc67f58SRaghu Vatsavayi 1315bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_MAC_RINFO64(mac, pf) \ 1325bc67f58SRaghu Vatsavayi (CN23XX_SLI_PKT_MAC_RINFO_START64 + \ 1335bc67f58SRaghu Vatsavayi ((mac) * CN23XX_MAC_RINFO_OFFSET) + \ 1345bc67f58SRaghu Vatsavayi ((pf) * CN23XX_PF_RINFO_OFFSET)) 1355bc67f58SRaghu Vatsavayi 1365bc67f58SRaghu Vatsavayi /** mask for total rings, setting TRS to base */ 1375bc67f58SRaghu Vatsavayi #define CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16) 1385bc67f58SRaghu Vatsavayi /** mask for starting ring number: setting SRN <6:0> = 0x7F */ 1395bc67f58SRaghu Vatsavayi #define CN23XX_PKT_MAC_CTL_RINFO_SRN (0x7F) 1405bc67f58SRaghu Vatsavayi 1415bc67f58SRaghu Vatsavayi /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */ 1425bc67f58SRaghu Vatsavayi #define CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS 16 1435bc67f58SRaghu Vatsavayi /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */ 1445bc67f58SRaghu Vatsavayi #define CN23XX_PKT_MAC_CTL_RINFO_SRN_BIT_POS 0 1455bc67f58SRaghu Vatsavayi /* Starting bit of RPVF field in CN23XX_SLI_PKT_MAC_RINFO64 register */ 1465bc67f58SRaghu Vatsavayi #define CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS 32 1475bc67f58SRaghu Vatsavayi /* Starting bit of NVFS field in CN23XX_SLI_PKT_MAC_RINFO64 register */ 1485bc67f58SRaghu Vatsavayi #define CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS 48 1495bc67f58SRaghu Vatsavayi 1505bc67f58SRaghu Vatsavayi /*###################### REQUEST QUEUE #########################*/ 1515bc67f58SRaghu Vatsavayi 1525bc67f58SRaghu Vatsavayi /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */ 1535bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_INSTR_COUNT_START64 0x10040 1545bc67f58SRaghu Vatsavayi 1555bc67f58SRaghu Vatsavayi /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */ 1565bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_BASE_ADDR_START64 0x10010 1575bc67f58SRaghu Vatsavayi 1585bc67f58SRaghu Vatsavayi /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */ 1595bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_DOORBELL_START 0x10020 1605bc67f58SRaghu Vatsavayi 1615bc67f58SRaghu Vatsavayi /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */ 1625bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_SIZE_START 0x10030 1635bc67f58SRaghu Vatsavayi 1645bc67f58SRaghu Vatsavayi /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data & 1655bc67f58SRaghu Vatsavayi * gather list fetches. SLI_PKT(0..63)_INPUT_CONTROL. 1665bc67f58SRaghu Vatsavayi */ 1675bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_PKT_CONTROL_START64 0x10000 1685bc67f58SRaghu Vatsavayi 1695bc67f58SRaghu Vatsavayi /*------- Request Queue Macros ---------*/ 1705bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_PKT_CONTROL64(iq) \ 1715bc67f58SRaghu Vatsavayi (CN23XX_SLI_IQ_PKT_CONTROL_START64 + ((iq) * CN23XX_IQ_OFFSET)) 1725bc67f58SRaghu Vatsavayi 1735bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_BASE_ADDR64(iq) \ 1745bc67f58SRaghu Vatsavayi (CN23XX_SLI_IQ_BASE_ADDR_START64 + ((iq) * CN23XX_IQ_OFFSET)) 1755bc67f58SRaghu Vatsavayi 1765bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_SIZE(iq) \ 1775bc67f58SRaghu Vatsavayi (CN23XX_SLI_IQ_SIZE_START + ((iq) * CN23XX_IQ_OFFSET)) 1785bc67f58SRaghu Vatsavayi 1795bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_DOORBELL(iq) \ 1805bc67f58SRaghu Vatsavayi (CN23XX_SLI_IQ_DOORBELL_START + ((iq) * CN23XX_IQ_OFFSET)) 1815bc67f58SRaghu Vatsavayi 1825bc67f58SRaghu Vatsavayi #define CN23XX_SLI_IQ_INSTR_COUNT64(iq) \ 1835bc67f58SRaghu Vatsavayi (CN23XX_SLI_IQ_INSTR_COUNT_START64 + ((iq) * CN23XX_IQ_OFFSET)) 1845bc67f58SRaghu Vatsavayi 1855bc67f58SRaghu Vatsavayi /*------------------ Masks ----------------*/ 1865bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32) 1875bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_MAC_NUM BIT(29) 1885bc67f58SRaghu Vatsavayi /* Number of instructions to be read in one MAC read request. 1895bc67f58SRaghu Vatsavayi * setting to Max value(4) 1905bc67f58SRaghu Vatsavayi */ 1915bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_RDSIZE (3 << 25) 1925bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_IS_64B BIT(24) 1935bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_RST BIT(23) 1945bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_QUIET BIT(28) 1955bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_RING_ENB BIT(22) 1965bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_DATA_NS BIT(8) 1975bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP BIT(6) 1985bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_DATA_RO BIT(5) 1995bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_USE_CSR BIT(4) 2005bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_GATHER_NS BIT(3) 2015bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP (2) 2025bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_GATHER_RO (1) 2035bc67f58SRaghu Vatsavayi 2045bc67f58SRaghu Vatsavayi /** Rings per Virtual Function **/ 2055bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_RPVF_MASK (0x3F) 2065bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_RPVF_POS (48) 2075bc67f58SRaghu Vatsavayi /** These bits[47:44] select the Physical function number within the MAC */ 2085bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_PF_NUM_MASK (0x7) 2095bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_PF_NUM_POS (45) 2105bc67f58SRaghu Vatsavayi /** These bits[43:32] select the function number within the PF */ 2115bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_VF_NUM_MASK (0x1FFF) 2125bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_VF_NUM_POS (32) 2135bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_MAC_NUM_MASK (0x3) 2145bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_MAC_NUM_POS (29) 2155bc67f58SRaghu Vatsavayi #define CN23XX_PKT_IN_DONE_WMARK_MASK (0xFFFFULL) 2165bc67f58SRaghu Vatsavayi #define CN23XX_PKT_IN_DONE_WMARK_BIT_POS (32) 2175bc67f58SRaghu Vatsavayi #define CN23XX_PKT_IN_DONE_CNT_MASK (0x00000000FFFFFFFFULL) 2185bc67f58SRaghu Vatsavayi 2195bc67f58SRaghu Vatsavayi #ifdef __LITTLE_ENDIAN_BITFIELD 2205bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_MASK \ 2215bc67f58SRaghu Vatsavayi (CN23XX_PKT_INPUT_CTL_RDSIZE | \ 2225bc67f58SRaghu Vatsavayi CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 2235bc67f58SRaghu Vatsavayi CN23XX_PKT_INPUT_CTL_USE_CSR) 2245bc67f58SRaghu Vatsavayi #else 2255bc67f58SRaghu Vatsavayi #define CN23XX_PKT_INPUT_CTL_MASK \ 2265bc67f58SRaghu Vatsavayi (CN23XX_PKT_INPUT_CTL_RDSIZE | \ 2275bc67f58SRaghu Vatsavayi CN23XX_PKT_INPUT_CTL_DATA_ES_64B_SWAP | \ 2285bc67f58SRaghu Vatsavayi CN23XX_PKT_INPUT_CTL_USE_CSR | \ 2295bc67f58SRaghu Vatsavayi CN23XX_PKT_INPUT_CTL_GATHER_ES_64B_SWAP) 2305bc67f58SRaghu Vatsavayi #endif 2315bc67f58SRaghu Vatsavayi 2325bc67f58SRaghu Vatsavayi /** Masks for SLI_PKT_IN_DONE(0..63)_CNTS Register */ 2335bc67f58SRaghu Vatsavayi #define CN23XX_IN_DONE_CNTS_PI_INT BIT_ULL(62) 2345bc67f58SRaghu Vatsavayi #define CN23XX_IN_DONE_CNTS_CINT_ENB BIT_ULL(48) 2355bc67f58SRaghu Vatsavayi 2365bc67f58SRaghu Vatsavayi /*############################ OUTPUT QUEUE #########################*/ 2375bc67f58SRaghu Vatsavayi 2385bc67f58SRaghu Vatsavayi /* 64 registers for Output queue control - SLI_PKT(0..63)_OUTPUT_CONTROL */ 2395bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_CONTROL_START 0x10050 2405bc67f58SRaghu Vatsavayi 2415bc67f58SRaghu Vatsavayi /* 64 registers for Output queue buffer and info size - SLI_PKT0_OUT_SIZE */ 2425bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ0_BUFF_INFO_SIZE 0x10060 2435bc67f58SRaghu Vatsavayi 2445bc67f58SRaghu Vatsavayi /* 64 registers for Output Queue Start Addr - SLI_PKT0_SLIST_BADDR */ 2455bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_BASE_ADDR_START64 0x10070 2465bc67f58SRaghu Vatsavayi 2475bc67f58SRaghu Vatsavayi /* 64 registers for Output Queue Packet Credits - SLI_PKT0_SLIST_BAOFF_DBELL */ 2485bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_CREDITS_START 0x10080 2495bc67f58SRaghu Vatsavayi 2505bc67f58SRaghu Vatsavayi /* 64 registers for Output Queue size - SLI_PKT0_SLIST_FIFO_RSIZE */ 2515bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_SIZE_START 0x10090 2525bc67f58SRaghu Vatsavayi 2535bc67f58SRaghu Vatsavayi /* 64 registers for Output Queue Packet Count - SLI_PKT0_CNTS */ 2545bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_SENT_START 0x100B0 2555bc67f58SRaghu Vatsavayi 2565bc67f58SRaghu Vatsavayi /* 64 registers for Output Queue INT Levels - SLI_PKT0_INT_LEVELS */ 2575bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 0x100A0 2585bc67f58SRaghu Vatsavayi 2595bc67f58SRaghu Vatsavayi /* Each Output Queue register is at a 16-byte Offset in BAR0 */ 2605bc67f58SRaghu Vatsavayi #define CN23XX_OQ_OFFSET 0x20000 2615bc67f58SRaghu Vatsavayi 2625bc67f58SRaghu Vatsavayi /* 1 (64-bit register) for Output Queue backpressure across all rings. */ 2635bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_WMARK 0x29180 2645bc67f58SRaghu Vatsavayi 2655bc67f58SRaghu Vatsavayi /* Global pkt control register */ 2665bc67f58SRaghu Vatsavayi #define CN23XX_SLI_GBL_CONTROL 0x29210 2675bc67f58SRaghu Vatsavayi 2685bc67f58SRaghu Vatsavayi /* Backpressure enable register for PF0 */ 2695bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OUT_BP_EN_W1S 0x29260 2705bc67f58SRaghu Vatsavayi 2715bc67f58SRaghu Vatsavayi /* Backpressure enable register for PF1 */ 2725bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OUT_BP_EN2_W1S 0x29270 2735bc67f58SRaghu Vatsavayi 2745bc67f58SRaghu Vatsavayi /* Backpressure disable register for PF0 */ 2755bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OUT_BP_EN_W1C 0x29280 2765bc67f58SRaghu Vatsavayi 2775bc67f58SRaghu Vatsavayi /* Backpressure disable register for PF1 */ 2785bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OUT_BP_EN2_W1C 0x29290 2795bc67f58SRaghu Vatsavayi 2805bc67f58SRaghu Vatsavayi /*------- Output Queue Macros ---------*/ 2815bc67f58SRaghu Vatsavayi 2825bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_CONTROL(oq) \ 2835bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_PKT_CONTROL_START + ((oq) * CN23XX_OQ_OFFSET)) 2845bc67f58SRaghu Vatsavayi 2855bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_BASE_ADDR64(oq) \ 2865bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_BASE_ADDR_START64 + ((oq) * CN23XX_OQ_OFFSET)) 2875bc67f58SRaghu Vatsavayi 2885bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_SIZE(oq) \ 2895bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_SIZE_START + ((oq) * CN23XX_OQ_OFFSET)) 2905bc67f58SRaghu Vatsavayi 2915bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq) \ 2925bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ0_BUFF_INFO_SIZE + ((oq) * CN23XX_OQ_OFFSET)) 2935bc67f58SRaghu Vatsavayi 2945bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKTS_SENT(oq) \ 2955bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_PKT_SENT_START + ((oq) * CN23XX_OQ_OFFSET)) 2965bc67f58SRaghu Vatsavayi 2975bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKTS_CREDIT(oq) \ 2985bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_PKT_CREDITS_START + ((oq) * CN23XX_OQ_OFFSET)) 2995bc67f58SRaghu Vatsavayi 3005bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_INT_LEVELS(oq) \ 3015bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 + \ 3025bc67f58SRaghu Vatsavayi ((oq) * CN23XX_OQ_OFFSET)) 3035bc67f58SRaghu Vatsavayi 3045bc67f58SRaghu Vatsavayi /*Macro's for accessing CNT and TIME separately from INT_LEVELS*/ 3055bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_INT_LEVELS_CNT(oq) \ 3065bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 + \ 3075bc67f58SRaghu Vatsavayi ((oq) * CN23XX_OQ_OFFSET)) 3085bc67f58SRaghu Vatsavayi 3095bc67f58SRaghu Vatsavayi #define CN23XX_SLI_OQ_PKT_INT_LEVELS_TIME(oq) \ 3105bc67f58SRaghu Vatsavayi (CN23XX_SLI_OQ_PKT_INT_LEVELS_START64 + \ 3115bc67f58SRaghu Vatsavayi ((oq) * CN23XX_OQ_OFFSET) + 4) 3125bc67f58SRaghu Vatsavayi 3135bc67f58SRaghu Vatsavayi /*------------------ Masks ----------------*/ 3145bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_TENB BIT(13) 3155bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_CENB BIT(12) 3165bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_IPTR BIT(11) 3175bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_ES BIT(9) 3185bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_NSR BIT(8) 3195bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_ROR BIT(7) 3205bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_DPTR BIT(6) 3215bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_BMODE BIT(5) 3225bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_ES_P BIT(3) 3235bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_NSR_P BIT(2) 3245bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_ROR_P BIT(1) 3255bc67f58SRaghu Vatsavayi #define CN23XX_PKT_OUTPUT_CTL_RING_ENB BIT(0) 3265bc67f58SRaghu Vatsavayi 3275bc67f58SRaghu Vatsavayi /*######################### Mailbox Reg Macros ########################*/ 3285bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_MBOX_INT_START 0x10210 3295bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START 0x10200 3305bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MAC_PF_MBOX_INT_START 0x27380 3315bc67f58SRaghu Vatsavayi 3325bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MBOX_OFFSET 0x20000 3335bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MBOX_SIG_IDX_OFFSET 0x8 3345bc67f58SRaghu Vatsavayi 3355bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_MBOX_INT(q) \ 3365bc67f58SRaghu Vatsavayi (CN23XX_SLI_PKT_MBOX_INT_START + ((q) * CN23XX_SLI_MBOX_OFFSET)) 3375bc67f58SRaghu Vatsavayi 3385bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q, idx) \ 3395bc67f58SRaghu Vatsavayi (CN23XX_SLI_PKT_PF_VF_MBOX_SIG_START + \ 3405bc67f58SRaghu Vatsavayi ((q) * CN23XX_SLI_MBOX_OFFSET + \ 3415bc67f58SRaghu Vatsavayi (idx) * CN23XX_SLI_MBOX_SIG_IDX_OFFSET)) 3425bc67f58SRaghu Vatsavayi 3435bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MAC_PF_MBOX_INT(mac, pf) \ 3445bc67f58SRaghu Vatsavayi (CN23XX_SLI_MAC_PF_MBOX_INT_START + \ 3455bc67f58SRaghu Vatsavayi ((mac) * CN23XX_MAC_INT_OFFSET + \ 3465bc67f58SRaghu Vatsavayi (pf) * CN23XX_PF_INT_OFFSET)) 3475bc67f58SRaghu Vatsavayi 3485bc67f58SRaghu Vatsavayi /*######################### DMA Counters #########################*/ 3495bc67f58SRaghu Vatsavayi 3505bc67f58SRaghu Vatsavayi /* 2 registers (64-bit) - DMA Count - 1 for each DMA counter 0/1. */ 3515bc67f58SRaghu Vatsavayi #define CN23XX_DMA_CNT_START 0x28400 3525bc67f58SRaghu Vatsavayi 3535bc67f58SRaghu Vatsavayi /* 2 registers (64-bit) - DMA Timer 0/1, contains DMA timer values */ 3545bc67f58SRaghu Vatsavayi /* SLI_DMA_0_TIM */ 3555bc67f58SRaghu Vatsavayi #define CN23XX_DMA_TIM_START 0x28420 3565bc67f58SRaghu Vatsavayi 3575bc67f58SRaghu Vatsavayi /* 2 registers (64-bit) - DMA count & Time Interrupt threshold - 3585bc67f58SRaghu Vatsavayi * SLI_DMA_0_INT_LEVEL 3595bc67f58SRaghu Vatsavayi */ 3605bc67f58SRaghu Vatsavayi #define CN23XX_DMA_INT_LEVEL_START 0x283E0 3615bc67f58SRaghu Vatsavayi 3625bc67f58SRaghu Vatsavayi /* Each DMA register is at a 16-byte Offset in BAR0 */ 3635bc67f58SRaghu Vatsavayi #define CN23XX_DMA_OFFSET 0x10 3645bc67f58SRaghu Vatsavayi 3655bc67f58SRaghu Vatsavayi /*---------- DMA Counter Macros ---------*/ 3665bc67f58SRaghu Vatsavayi #define CN23XX_DMA_CNT(dq) \ 3675bc67f58SRaghu Vatsavayi (CN23XX_DMA_CNT_START + ((dq) * CN23XX_DMA_OFFSET)) 3685bc67f58SRaghu Vatsavayi 3695bc67f58SRaghu Vatsavayi #define CN23XX_DMA_INT_LEVEL(dq) \ 3705bc67f58SRaghu Vatsavayi (CN23XX_DMA_INT_LEVEL_START + ((dq) * CN23XX_DMA_OFFSET)) 3715bc67f58SRaghu Vatsavayi 3725bc67f58SRaghu Vatsavayi #define CN23XX_DMA_PKT_INT_LEVEL(dq) \ 3735bc67f58SRaghu Vatsavayi (CN23XX_DMA_INT_LEVEL_START + ((dq) * CN23XX_DMA_OFFSET)) 3745bc67f58SRaghu Vatsavayi 3755bc67f58SRaghu Vatsavayi #define CN23XX_DMA_TIME_INT_LEVEL(dq) \ 3765bc67f58SRaghu Vatsavayi (CN23XX_DMA_INT_LEVEL_START + 4 + ((dq) * CN23XX_DMA_OFFSET)) 3775bc67f58SRaghu Vatsavayi 3785bc67f58SRaghu Vatsavayi #define CN23XX_DMA_TIM(dq) \ 3795bc67f58SRaghu Vatsavayi (CN23XX_DMA_TIM_START + ((dq) * CN23XX_DMA_OFFSET)) 3805bc67f58SRaghu Vatsavayi 3815bc67f58SRaghu Vatsavayi /*######################## MSIX TABLE #########################*/ 3825bc67f58SRaghu Vatsavayi 3835bc67f58SRaghu Vatsavayi #define CN23XX_MSIX_TABLE_ADDR_START 0x0 3845bc67f58SRaghu Vatsavayi #define CN23XX_MSIX_TABLE_DATA_START 0x8 3855bc67f58SRaghu Vatsavayi 3865bc67f58SRaghu Vatsavayi #define CN23XX_MSIX_TABLE_SIZE 0x10 3875bc67f58SRaghu Vatsavayi #define CN23XX_MSIX_TABLE_ENTRIES 0x41 3885bc67f58SRaghu Vatsavayi 3895bc67f58SRaghu Vatsavayi #define CN23XX_MSIX_ENTRY_VECTOR_CTL BIT_ULL(32) 3905bc67f58SRaghu Vatsavayi 3915bc67f58SRaghu Vatsavayi #define CN23XX_MSIX_TABLE_ADDR(idx) \ 3925bc67f58SRaghu Vatsavayi (CN23XX_MSIX_TABLE_ADDR_START + ((idx) * CN23XX_MSIX_TABLE_SIZE)) 3935bc67f58SRaghu Vatsavayi 3945bc67f58SRaghu Vatsavayi #define CN23XX_MSIX_TABLE_DATA(idx) \ 3955bc67f58SRaghu Vatsavayi (CN23XX_MSIX_TABLE_DATA_START + ((idx) * CN23XX_MSIX_TABLE_SIZE)) 3965bc67f58SRaghu Vatsavayi 3975bc67f58SRaghu Vatsavayi /*######################## INTERRUPTS #########################*/ 3985bc67f58SRaghu Vatsavayi #define CN23XX_MAC_INT_OFFSET 0x20 3995bc67f58SRaghu Vatsavayi #define CN23XX_PF_INT_OFFSET 0x10 4005bc67f58SRaghu Vatsavayi 4015bc67f58SRaghu Vatsavayi /* 1 register (64-bit) for Interrupt Summary */ 4025bc67f58SRaghu Vatsavayi #define CN23XX_SLI_INT_SUM64 0x27000 4035bc67f58SRaghu Vatsavayi 4045bc67f58SRaghu Vatsavayi /* 4 registers (64-bit) for Interrupt Enable for each Port */ 4055bc67f58SRaghu Vatsavayi #define CN23XX_SLI_INT_ENB64 0x27080 4065bc67f58SRaghu Vatsavayi 4075bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MAC_PF_INT_SUM64(mac, pf) \ 4085bc67f58SRaghu Vatsavayi (CN23XX_SLI_INT_SUM64 + \ 4095bc67f58SRaghu Vatsavayi ((mac) * CN23XX_MAC_INT_OFFSET) + \ 4105bc67f58SRaghu Vatsavayi ((pf) * CN23XX_PF_INT_OFFSET)) 4115bc67f58SRaghu Vatsavayi 4125bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MAC_PF_INT_ENB64(mac, pf) \ 4135bc67f58SRaghu Vatsavayi (CN23XX_SLI_INT_ENB64 + \ 4145bc67f58SRaghu Vatsavayi ((mac) * CN23XX_MAC_INT_OFFSET) + \ 4155bc67f58SRaghu Vatsavayi ((pf) * CN23XX_PF_INT_OFFSET)) 4165bc67f58SRaghu Vatsavayi 4175bc67f58SRaghu Vatsavayi /* 1 register (64-bit) to indicate which Output Queue reached pkt threshold */ 4185bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_CNT_INT 0x29130 4195bc67f58SRaghu Vatsavayi 4205bc67f58SRaghu Vatsavayi /* 1 register (64-bit) to indicate which Output Queue reached time threshold */ 4215bc67f58SRaghu Vatsavayi #define CN23XX_SLI_PKT_TIME_INT 0x29140 4225bc67f58SRaghu Vatsavayi 4235bc67f58SRaghu Vatsavayi /*------------------ Interrupt Masks ----------------*/ 4245bc67f58SRaghu Vatsavayi 4255bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PO_INT BIT_ULL(63) 4265bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PI_INT BIT_ULL(62) 4275bc67f58SRaghu Vatsavayi #define CN23XX_INTR_MBOX_INT BIT_ULL(61) 4285bc67f58SRaghu Vatsavayi #define CN23XX_INTR_RESEND BIT_ULL(60) 4295bc67f58SRaghu Vatsavayi 4305bc67f58SRaghu Vatsavayi #define CN23XX_INTR_CINT_ENB BIT_ULL(48) 4315bc67f58SRaghu Vatsavayi #define CN23XX_INTR_MBOX_ENB BIT(0) 4325bc67f58SRaghu Vatsavayi 4335bc67f58SRaghu Vatsavayi #define CN23XX_INTR_RML_TIMEOUT_ERR (1) 4345bc67f58SRaghu Vatsavayi 4355bc67f58SRaghu Vatsavayi #define CN23XX_INTR_MIO_INT BIT(1) 4365bc67f58SRaghu Vatsavayi 4375bc67f58SRaghu Vatsavayi #define CN23XX_INTR_RESERVED1 (3 << 2) 4385bc67f58SRaghu Vatsavayi 4395bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PKT_COUNT BIT(4) 4405bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PKT_TIME BIT(5) 4415bc67f58SRaghu Vatsavayi 4425bc67f58SRaghu Vatsavayi #define CN23XX_INTR_RESERVED2 (3 << 6) 4435bc67f58SRaghu Vatsavayi 4445bc67f58SRaghu Vatsavayi #define CN23XX_INTR_M0UPB0_ERR BIT(8) 4455bc67f58SRaghu Vatsavayi #define CN23XX_INTR_M0UPWI_ERR BIT(9) 4465bc67f58SRaghu Vatsavayi #define CN23XX_INTR_M0UNB0_ERR BIT(10) 4475bc67f58SRaghu Vatsavayi #define CN23XX_INTR_M0UNWI_ERR BIT(11) 4485bc67f58SRaghu Vatsavayi 4495bc67f58SRaghu Vatsavayi #define CN23XX_INTR_RESERVED3 (0xFFFFFULL << 12) 4505bc67f58SRaghu Vatsavayi 4515bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA0_FORCE BIT_ULL(32) 4525bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA1_FORCE BIT_ULL(33) 4535bc67f58SRaghu Vatsavayi 4545bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA0_COUNT BIT_ULL(34) 4555bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA1_COUNT BIT_ULL(35) 4565bc67f58SRaghu Vatsavayi 4575bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA0_TIME BIT_ULL(36) 4585bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA1_TIME BIT_ULL(37) 4595bc67f58SRaghu Vatsavayi 4605bc67f58SRaghu Vatsavayi #define CN23XX_INTR_RESERVED4 (0x7FFFFULL << 38) 4615bc67f58SRaghu Vatsavayi 4625bc67f58SRaghu Vatsavayi #define CN23XX_INTR_VF_MBOX BIT_ULL(57) 4635bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMAVF_ERR BIT_ULL(58) 4645bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMAPF_ERR BIT_ULL(59) 4655bc67f58SRaghu Vatsavayi 4665bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PKTVF_ERR BIT_ULL(60) 4675bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PKTPF_ERR BIT_ULL(61) 4685bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PPVF_ERR BIT_ULL(62) 4695bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PPPF_ERR BIT_ULL(63) 4705bc67f58SRaghu Vatsavayi 4715bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA0_DATA (CN23XX_INTR_DMA0_TIME) 4725bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA1_DATA (CN23XX_INTR_DMA1_TIME) 4735bc67f58SRaghu Vatsavayi 4745bc67f58SRaghu Vatsavayi #define CN23XX_INTR_DMA_DATA \ 4755bc67f58SRaghu Vatsavayi (CN23XX_INTR_DMA0_DATA | CN23XX_INTR_DMA1_DATA) 4765bc67f58SRaghu Vatsavayi 4775bc67f58SRaghu Vatsavayi /* By fault only TIME based */ 4785bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PKT_DATA (CN23XX_INTR_PKT_TIME) 4795bc67f58SRaghu Vatsavayi /* For both COUNT and TIME based */ 4805bc67f58SRaghu Vatsavayi /* #define CN23XX_INTR_PKT_DATA \ 4815bc67f58SRaghu Vatsavayi * (CN23XX_INTR_PKT_COUNT | CN23XX_INTR_PKT_TIME) 4825bc67f58SRaghu Vatsavayi */ 4835bc67f58SRaghu Vatsavayi 4845bc67f58SRaghu Vatsavayi /* Sum of interrupts for all PCI-Express Data Interrupts */ 4855bc67f58SRaghu Vatsavayi #define CN23XX_INTR_PCIE_DATA \ 4865bc67f58SRaghu Vatsavayi (CN23XX_INTR_DMA_DATA | CN23XX_INTR_PKT_DAT) 4875bc67f58SRaghu Vatsavayi 4885bc67f58SRaghu Vatsavayi /* Sum of interrupts for error events */ 4895bc67f58SRaghu Vatsavayi #define CN23XX_INTR_ERR \ 4905bc67f58SRaghu Vatsavayi (CN23XX_INTR_M0UPB0_ERR | \ 4915bc67f58SRaghu Vatsavayi CN23XX_INTR_M0UPWI_ERR | \ 4925bc67f58SRaghu Vatsavayi CN23XX_INTR_M0UNB0_ERR | \ 4935bc67f58SRaghu Vatsavayi CN23XX_INTR_M0UNWI_ERR | \ 4945bc67f58SRaghu Vatsavayi CN23XX_INTR_DMAVF_ERR | \ 4955bc67f58SRaghu Vatsavayi CN23XX_INTR_DMAPF_ERR | \ 4965bc67f58SRaghu Vatsavayi CN23XX_INTR_PKTPF_ERR | \ 4975bc67f58SRaghu Vatsavayi CN23XX_INTR_PPPF_ERR | \ 4985bc67f58SRaghu Vatsavayi CN23XX_INTR_PPVF_ERR) 4995bc67f58SRaghu Vatsavayi 5005bc67f58SRaghu Vatsavayi /* Programmed Mask for Interrupt Sum */ 5015bc67f58SRaghu Vatsavayi #define CN23XX_INTR_MASK \ 5025bc67f58SRaghu Vatsavayi (CN23XX_INTR_DMA_DATA | \ 5035bc67f58SRaghu Vatsavayi CN23XX_INTR_DMA0_FORCE | \ 5045bc67f58SRaghu Vatsavayi CN23XX_INTR_DMA1_FORCE | \ 5055bc67f58SRaghu Vatsavayi CN23XX_INTR_MIO_INT | \ 5065bc67f58SRaghu Vatsavayi CN23XX_INTR_ERR) 5075bc67f58SRaghu Vatsavayi 5085bc67f58SRaghu Vatsavayi /* 4 Registers (64 - bit) */ 5095bc67f58SRaghu Vatsavayi #define CN23XX_SLI_S2M_PORT_CTL_START 0x23D80 5105bc67f58SRaghu Vatsavayi #define CN23XX_SLI_S2M_PORTX_CTL(port) \ 51197a25326SRaghu Vatsavayi (CN23XX_SLI_S2M_PORT_CTL_START + ((port) * 0x10)) 5125bc67f58SRaghu Vatsavayi 5135bc67f58SRaghu Vatsavayi #define CN23XX_SLI_MAC_NUMBER 0x20050 5145bc67f58SRaghu Vatsavayi 5155bc67f58SRaghu Vatsavayi /** PEM(0..3)_BAR1_INDEX(0..15)address is defined as 5165bc67f58SRaghu Vatsavayi * addr = (0x00011800C0000100 |port <<24 |idx <<3 ) 5175bc67f58SRaghu Vatsavayi * Here, port is PEM(0..3) & idx is INDEX(0..15) 5185bc67f58SRaghu Vatsavayi */ 5195bc67f58SRaghu Vatsavayi #define CN23XX_PEM_BAR1_INDEX_START 0x00011800C0000100ULL 5205bc67f58SRaghu Vatsavayi #define CN23XX_PEM_OFFSET 24 5215bc67f58SRaghu Vatsavayi #define CN23XX_BAR1_INDEX_OFFSET 3 5225bc67f58SRaghu Vatsavayi 5235bc67f58SRaghu Vatsavayi #define CN23XX_PEM_BAR1_INDEX_REG(port, idx) \ 524*298b58f0SColin Ian King (CN23XX_PEM_BAR1_INDEX_START + (((u64)port) << CN23XX_PEM_OFFSET) + \ 5255bc67f58SRaghu Vatsavayi ((idx) << CN23XX_BAR1_INDEX_OFFSET)) 5265bc67f58SRaghu Vatsavayi 5275bc67f58SRaghu Vatsavayi /*############################ DPI #########################*/ 5285bc67f58SRaghu Vatsavayi 5295bc67f58SRaghu Vatsavayi /* 1 register (64-bit) - provides DMA Enable */ 5305bc67f58SRaghu Vatsavayi #define CN23XX_DPI_CTL 0x0001df0000000040ULL 5315bc67f58SRaghu Vatsavayi 5325bc67f58SRaghu Vatsavayi /* 1 register (64-bit) - Controls the DMA IO Operation */ 5335bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_CONTROL 0x0001df0000000048ULL 5345bc67f58SRaghu Vatsavayi 5355bc67f58SRaghu Vatsavayi /* 1 register (64-bit) - Provides DMA Instr'n Queue Enable */ 5365bc67f58SRaghu Vatsavayi #define CN23XX_DPI_REQ_GBL_ENB 0x0001df0000000050ULL 5375bc67f58SRaghu Vatsavayi 5385bc67f58SRaghu Vatsavayi /* 1 register (64-bit) - DPI_REQ_ERR_RSP 5395bc67f58SRaghu Vatsavayi * Indicates which Instr'n Queue received error response from the IO sub-system 5405bc67f58SRaghu Vatsavayi */ 5415bc67f58SRaghu Vatsavayi #define CN23XX_DPI_REQ_ERR_RSP 0x0001df0000000058ULL 5425bc67f58SRaghu Vatsavayi 5435bc67f58SRaghu Vatsavayi /* 1 register (64-bit) - DPI_REQ_ERR_RST 5445bc67f58SRaghu Vatsavayi * Indicates which Instr'n Queue dropped an Instr'n 5455bc67f58SRaghu Vatsavayi */ 5465bc67f58SRaghu Vatsavayi #define CN23XX_DPI_REQ_ERR_RST 0x0001df0000000060ULL 5475bc67f58SRaghu Vatsavayi 5485bc67f58SRaghu Vatsavayi /* 6 register (64-bit) - DPI_DMA_ENG(0..5)_EN 5495bc67f58SRaghu Vatsavayi * Provides DMA Engine Queue Enable 5505bc67f58SRaghu Vatsavayi */ 5515bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_ENG0_ENB 0x0001df0000000080ULL 55297a25326SRaghu Vatsavayi #define CN23XX_DPI_DMA_ENG_ENB(eng) (CN23XX_DPI_DMA_ENG0_ENB + ((eng) * 8)) 5535bc67f58SRaghu Vatsavayi 5545bc67f58SRaghu Vatsavayi /* 8 register (64-bit) - DPI_DMA(0..7)_REQQ_CTL 5555bc67f58SRaghu Vatsavayi * Provides control bits for transaction on 8 Queues 5565bc67f58SRaghu Vatsavayi */ 5575bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_REQQ0_CTL 0x0001df0000000180ULL 5585bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_REQQ_CTL(q_no) \ 55997a25326SRaghu Vatsavayi (CN23XX_DPI_DMA_REQQ0_CTL + ((q_no) * 8)) 5605bc67f58SRaghu Vatsavayi 5615bc67f58SRaghu Vatsavayi /* 6 register (64-bit) - DPI_ENG(0..5)_BUF 5625bc67f58SRaghu Vatsavayi * Provides DMA Engine FIFO (Queue) Size 5635bc67f58SRaghu Vatsavayi */ 5645bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_ENG0_BUF 0x0001df0000000880ULL 5655bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_ENG_BUF(eng) \ 56697a25326SRaghu Vatsavayi (CN23XX_DPI_DMA_ENG0_BUF + ((eng) * 8)) 5675bc67f58SRaghu Vatsavayi 5685bc67f58SRaghu Vatsavayi /* 4 Registers (64-bit) */ 5695bc67f58SRaghu Vatsavayi #define CN23XX_DPI_SLI_PRT_CFG_START 0x0001df0000000900ULL 5705bc67f58SRaghu Vatsavayi #define CN23XX_DPI_SLI_PRTX_CFG(port) \ 57197a25326SRaghu Vatsavayi (CN23XX_DPI_SLI_PRT_CFG_START + ((port) * 0x8)) 5725bc67f58SRaghu Vatsavayi 5735bc67f58SRaghu Vatsavayi /* Masks for DPI_DMA_CONTROL Register */ 5745bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_COMMIT_MODE BIT_ULL(58) 5755bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_PKT_EN BIT_ULL(56) 5765bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_ENB (0x0FULL << 48) 5775bc67f58SRaghu Vatsavayi /* Set the DMA Control, to update packet count not byte count sent by DMA, 5785bc67f58SRaghu Vatsavayi * when we use Interrupt Coalescing (CA mode) 5795bc67f58SRaghu Vatsavayi */ 5805bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_O_ADD1 BIT(19) 5815bc67f58SRaghu Vatsavayi /*selecting 64-bit Byte Swap Mode */ 5825bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_O_ES BIT(15) 5835bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_O_MODE BIT(14) 5845bc67f58SRaghu Vatsavayi 5855bc67f58SRaghu Vatsavayi #define CN23XX_DPI_DMA_CTL_MASK \ 5865bc67f58SRaghu Vatsavayi (CN23XX_DPI_DMA_COMMIT_MODE | \ 5875bc67f58SRaghu Vatsavayi CN23XX_DPI_DMA_PKT_EN | \ 5885bc67f58SRaghu Vatsavayi CN23XX_DPI_DMA_O_ES | \ 5895bc67f58SRaghu Vatsavayi CN23XX_DPI_DMA_O_MODE) 5905bc67f58SRaghu Vatsavayi 5915bc67f58SRaghu Vatsavayi /*############################ RST #########################*/ 5925bc67f58SRaghu Vatsavayi 5935bc67f58SRaghu Vatsavayi #define CN23XX_RST_BOOT 0x0001180006001600ULL 5945bc67f58SRaghu Vatsavayi #define CN23XX_RST_SOFT_RST 0x0001180006001680ULL 5955bc67f58SRaghu Vatsavayi 5965bc67f58SRaghu Vatsavayi #define CN23XX_LMC0_RESET_CTL 0x0001180088000180ULL 5975bc67f58SRaghu Vatsavayi #define CN23XX_LMC0_RESET_CTL_DDR3RST_MASK 0x0000000000000001ULL 5985bc67f58SRaghu Vatsavayi 5995bc67f58SRaghu Vatsavayi #endif 600