1 /* 2 * Copyright 2010-2011 Calxeda, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/circ_buf.h> 20 #include <linux/interrupt.h> 21 #include <linux/etherdevice.h> 22 #include <linux/platform_device.h> 23 #include <linux/skbuff.h> 24 #include <linux/ethtool.h> 25 #include <linux/if.h> 26 #include <linux/crc32.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/slab.h> 29 30 /* XGMAC Register definitions */ 31 #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */ 32 #define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */ 33 #define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */ 34 #define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */ 35 #define XGMAC_VERSION 0x00000020 /* Version */ 36 #define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */ 37 #define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */ 38 #define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */ 39 #define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */ 40 #define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */ 41 #define XGMAC_DEBUG 0x00000038 /* Debug */ 42 #define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */ 43 #define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8)) 44 #define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8)) 45 #define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */ 46 #define XGMAC_NUM_HASH 16 47 #define XGMAC_OMR 0x00000400 48 #define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */ 49 #define XGMAC_PMT 0x00000704 /* PMT Control and Status */ 50 #define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */ 51 #define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */ 52 #define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */ 53 #define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */ 54 #define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */ 55 56 /* Hardware TX Statistics Counters */ 57 #define XGMAC_MMC_TXOCTET_GB_LO 0x00000814 58 #define XGMAC_MMC_TXOCTET_GB_HI 0x00000818 59 #define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C 60 #define XGMAC_MMC_TXFRAME_GB_HI 0x00000820 61 #define XGMAC_MMC_TXBCFRAME_G 0x00000824 62 #define XGMAC_MMC_TXMCFRAME_G 0x0000082C 63 #define XGMAC_MMC_TXUCFRAME_GB 0x00000864 64 #define XGMAC_MMC_TXMCFRAME_GB 0x0000086C 65 #define XGMAC_MMC_TXBCFRAME_GB 0x00000874 66 #define XGMAC_MMC_TXUNDERFLOW 0x0000087C 67 #define XGMAC_MMC_TXOCTET_G_LO 0x00000884 68 #define XGMAC_MMC_TXOCTET_G_HI 0x00000888 69 #define XGMAC_MMC_TXFRAME_G_LO 0x0000088C 70 #define XGMAC_MMC_TXFRAME_G_HI 0x00000890 71 #define XGMAC_MMC_TXPAUSEFRAME 0x00000894 72 #define XGMAC_MMC_TXVLANFRAME 0x0000089C 73 74 /* Hardware RX Statistics Counters */ 75 #define XGMAC_MMC_RXFRAME_GB_LO 0x00000900 76 #define XGMAC_MMC_RXFRAME_GB_HI 0x00000904 77 #define XGMAC_MMC_RXOCTET_GB_LO 0x00000908 78 #define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C 79 #define XGMAC_MMC_RXOCTET_G_LO 0x00000910 80 #define XGMAC_MMC_RXOCTET_G_HI 0x00000914 81 #define XGMAC_MMC_RXBCFRAME_G 0x00000918 82 #define XGMAC_MMC_RXMCFRAME_G 0x00000920 83 #define XGMAC_MMC_RXCRCERR 0x00000928 84 #define XGMAC_MMC_RXRUNT 0x00000930 85 #define XGMAC_MMC_RXJABBER 0x00000934 86 #define XGMAC_MMC_RXUCFRAME_G 0x00000970 87 #define XGMAC_MMC_RXLENGTHERR 0x00000978 88 #define XGMAC_MMC_RXPAUSEFRAME 0x00000988 89 #define XGMAC_MMC_RXOVERFLOW 0x00000990 90 #define XGMAC_MMC_RXVLANFRAME 0x00000998 91 #define XGMAC_MMC_RXWATCHDOG 0x000009a0 92 93 /* DMA Control and Status Registers */ 94 #define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */ 95 #define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */ 96 #define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */ 97 #define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */ 98 #define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */ 99 #define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */ 100 #define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */ 101 #define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */ 102 #define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */ 103 #define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */ 104 #define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */ 105 #define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */ 106 #define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */ 107 108 #define XGMAC_ADDR_AE 0x80000000 109 #define XGMAC_MAX_FILTER_ADDR 31 110 111 /* PMT Control and Status */ 112 #define XGMAC_PMT_POINTER_RESET 0x80000000 113 #define XGMAC_PMT_GLBL_UNICAST 0x00000200 114 #define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040 115 #define XGMAC_PMT_MAGIC_PKT 0x00000020 116 #define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004 117 #define XGMAC_PMT_MAGIC_PKT_EN 0x00000002 118 #define XGMAC_PMT_POWERDOWN 0x00000001 119 120 #define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */ 121 #define XGMAC_CONTROL_SPD_MASK 0x60000000 122 #define XGMAC_CONTROL_SPD_1G 0x60000000 123 #define XGMAC_CONTROL_SPD_2_5G 0x40000000 124 #define XGMAC_CONTROL_SPD_10G 0x00000000 125 #define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */ 126 #define XGMAC_CONTROL_SARK_MASK 0x18000000 127 #define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */ 128 #define XGMAC_CONTROL_CAR_MASK 0x06000000 129 #define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */ 130 #define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */ 131 #define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */ 132 #define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ 133 #define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 134 #define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ 135 #define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */ 136 #define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */ 137 #define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ 138 #define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ 139 140 /* XGMAC Frame Filter defines */ 141 #define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ 142 #define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ 143 #define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ 144 #define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ 145 #define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ 146 #define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ 147 #define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ 148 #define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ 149 #define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ 150 #define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */ 151 #define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */ 152 #define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ 153 154 /* XGMAC FLOW CTRL defines */ 155 #define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ 156 #define XGMAC_FLOW_CTRL_PT_SHIFT 16 157 #define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */ 158 #define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */ 159 #define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */ 160 #define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */ 161 #define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ 162 #define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ 163 #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ 164 165 /* XGMAC_INT_STAT reg */ 166 #define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */ 167 #define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */ 168 169 /* DMA Bus Mode register defines */ 170 #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */ 171 #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ 172 #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ 173 #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */ 174 175 /* Programmable burst length */ 176 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ 177 #define DMA_BUS_MODE_PBL_SHIFT 8 178 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ 179 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ 180 #define DMA_BUS_MODE_RPBL_SHIFT 17 181 #define DMA_BUS_MODE_USP 0x00800000 182 #define DMA_BUS_MODE_8PBL 0x01000000 183 #define DMA_BUS_MODE_AAL 0x02000000 184 185 /* DMA Bus Mode register defines */ 186 #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ 187 #define DMA_BUS_PR_RATIO_SHIFT 14 188 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ 189 190 /* DMA Control register defines */ 191 #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */ 192 #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */ 193 #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */ 194 195 /* DMA Normal interrupt */ 196 #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */ 197 #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */ 198 #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */ 199 #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */ 200 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */ 201 #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */ 202 #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */ 203 #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */ 204 #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */ 205 #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */ 206 #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */ 207 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */ 208 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */ 209 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */ 210 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */ 211 212 #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \ 213 DMA_INTR_ENA_TUE) 214 215 #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \ 216 DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \ 217 DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \ 218 DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \ 219 DMA_INTR_ENA_TSE) 220 221 /* DMA default interrupt mask */ 222 #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL) 223 224 /* DMA Status register defines */ 225 #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */ 226 #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */ 227 #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */ 228 #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */ 229 #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */ 230 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */ 231 #define DMA_STATUS_TS_SHIFT 20 232 #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */ 233 #define DMA_STATUS_RS_SHIFT 17 234 #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */ 235 #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */ 236 #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */ 237 #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */ 238 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */ 239 #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */ 240 #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */ 241 #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */ 242 #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */ 243 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */ 244 #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */ 245 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */ 246 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */ 247 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */ 248 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ 249 250 /* Common MAC defines */ 251 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */ 252 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */ 253 254 /* XGMAC Operation Mode Register */ 255 #define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */ 256 #define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */ 257 #define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */ 258 #define XGMAC_OMR_TTC_MASK 0x00030000 259 #define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */ 260 #define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */ 261 #define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */ 262 #define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */ 263 #define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */ 264 #define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */ 265 #define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */ 266 #define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */ 267 #define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */ 268 #define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */ 269 270 /* XGMAC HW Features Register */ 271 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */ 272 273 #define XGMAC_MMC_CTRL_CNT_FRZ 0x00000008 274 275 /* XGMAC Descriptor Defines */ 276 #define MAX_DESC_BUF_SZ (0x2000 - 8) 277 278 #define RXDESC_EXT_STATUS 0x00000001 279 #define RXDESC_CRC_ERR 0x00000002 280 #define RXDESC_RX_ERR 0x00000008 281 #define RXDESC_RX_WDOG 0x00000010 282 #define RXDESC_FRAME_TYPE 0x00000020 283 #define RXDESC_GIANT_FRAME 0x00000080 284 #define RXDESC_LAST_SEG 0x00000100 285 #define RXDESC_FIRST_SEG 0x00000200 286 #define RXDESC_VLAN_FRAME 0x00000400 287 #define RXDESC_OVERFLOW_ERR 0x00000800 288 #define RXDESC_LENGTH_ERR 0x00001000 289 #define RXDESC_SA_FILTER_FAIL 0x00002000 290 #define RXDESC_DESCRIPTOR_ERR 0x00004000 291 #define RXDESC_ERROR_SUMMARY 0x00008000 292 #define RXDESC_FRAME_LEN_OFFSET 16 293 #define RXDESC_FRAME_LEN_MASK 0x3fff0000 294 #define RXDESC_DA_FILTER_FAIL 0x40000000 295 296 #define RXDESC1_END_RING 0x00008000 297 298 #define RXDESC_IP_PAYLOAD_MASK 0x00000003 299 #define RXDESC_IP_PAYLOAD_UDP 0x00000001 300 #define RXDESC_IP_PAYLOAD_TCP 0x00000002 301 #define RXDESC_IP_PAYLOAD_ICMP 0x00000003 302 #define RXDESC_IP_HEADER_ERR 0x00000008 303 #define RXDESC_IP_PAYLOAD_ERR 0x00000010 304 #define RXDESC_IPV4_PACKET 0x00000040 305 #define RXDESC_IPV6_PACKET 0x00000080 306 #define TXDESC_UNDERFLOW_ERR 0x00000001 307 #define TXDESC_JABBER_TIMEOUT 0x00000002 308 #define TXDESC_LOCAL_FAULT 0x00000004 309 #define TXDESC_REMOTE_FAULT 0x00000008 310 #define TXDESC_VLAN_FRAME 0x00000010 311 #define TXDESC_FRAME_FLUSHED 0x00000020 312 #define TXDESC_IP_HEADER_ERR 0x00000040 313 #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080 314 #define TXDESC_ERROR_SUMMARY 0x00008000 315 #define TXDESC_SA_CTRL_INSERT 0x00040000 316 #define TXDESC_SA_CTRL_REPLACE 0x00080000 317 #define TXDESC_2ND_ADDR_CHAINED 0x00100000 318 #define TXDESC_END_RING 0x00200000 319 #define TXDESC_CSUM_IP 0x00400000 320 #define TXDESC_CSUM_IP_PAYLD 0x00800000 321 #define TXDESC_CSUM_ALL 0x00C00000 322 #define TXDESC_CRC_EN_REPLACE 0x01000000 323 #define TXDESC_CRC_EN_APPEND 0x02000000 324 #define TXDESC_DISABLE_PAD 0x04000000 325 #define TXDESC_FIRST_SEG 0x10000000 326 #define TXDESC_LAST_SEG 0x20000000 327 #define TXDESC_INTERRUPT 0x40000000 328 329 #define DESC_OWN 0x80000000 330 #define DESC_BUFFER1_SZ_MASK 0x00001fff 331 #define DESC_BUFFER2_SZ_MASK 0x1fff0000 332 #define DESC_BUFFER2_SZ_OFFSET 16 333 334 struct xgmac_dma_desc { 335 __le32 flags; 336 __le32 buf_size; 337 __le32 buf1_addr; /* Buffer 1 Address Pointer */ 338 __le32 buf2_addr; /* Buffer 2 Address Pointer */ 339 __le32 ext_status; 340 __le32 res[3]; 341 }; 342 343 struct xgmac_extra_stats { 344 /* Transmit errors */ 345 unsigned long tx_jabber; 346 unsigned long tx_frame_flushed; 347 unsigned long tx_payload_error; 348 unsigned long tx_ip_header_error; 349 unsigned long tx_local_fault; 350 unsigned long tx_remote_fault; 351 /* Receive errors */ 352 unsigned long rx_watchdog; 353 unsigned long rx_da_filter_fail; 354 unsigned long rx_sa_filter_fail; 355 unsigned long rx_payload_error; 356 unsigned long rx_ip_header_error; 357 /* Tx/Rx IRQ errors */ 358 unsigned long tx_undeflow; 359 unsigned long tx_process_stopped; 360 unsigned long rx_buf_unav; 361 unsigned long rx_process_stopped; 362 unsigned long tx_early; 363 unsigned long fatal_bus_error; 364 }; 365 366 struct xgmac_priv { 367 struct xgmac_dma_desc *dma_rx; 368 struct sk_buff **rx_skbuff; 369 unsigned int rx_tail; 370 unsigned int rx_head; 371 372 struct xgmac_dma_desc *dma_tx; 373 struct sk_buff **tx_skbuff; 374 unsigned int tx_head; 375 unsigned int tx_tail; 376 377 void __iomem *base; 378 unsigned int dma_buf_sz; 379 dma_addr_t dma_rx_phy; 380 dma_addr_t dma_tx_phy; 381 382 struct net_device *dev; 383 struct device *device; 384 struct napi_struct napi; 385 386 struct xgmac_extra_stats xstats; 387 388 spinlock_t stats_lock; 389 int pmt_irq; 390 char rx_pause; 391 char tx_pause; 392 int wolopts; 393 }; 394 395 /* XGMAC Configuration Settings */ 396 #define MAX_MTU 9000 397 #define PAUSE_TIME 0x400 398 399 #define DMA_RX_RING_SZ 256 400 #define DMA_TX_RING_SZ 128 401 /* minimum number of free TX descriptors required to wake up TX process */ 402 #define TX_THRESH (DMA_TX_RING_SZ/4) 403 404 /* DMA descriptor ring helpers */ 405 #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1)) 406 #define dma_ring_space(h, t, s) CIRC_SPACE(h, t, s) 407 #define dma_ring_cnt(h, t, s) CIRC_CNT(h, t, s) 408 409 /* XGMAC Descriptor Access Helpers */ 410 static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz) 411 { 412 if (buf_sz > MAX_DESC_BUF_SZ) 413 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ | 414 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET); 415 else 416 p->buf_size = cpu_to_le32(buf_sz); 417 } 418 419 static inline int desc_get_buf_len(struct xgmac_dma_desc *p) 420 { 421 u32 len = cpu_to_le32(p->flags); 422 return (len & DESC_BUFFER1_SZ_MASK) + 423 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET); 424 } 425 426 static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size, 427 int buf_sz) 428 { 429 struct xgmac_dma_desc *end = p + ring_size - 1; 430 431 memset(p, 0, sizeof(*p) * ring_size); 432 433 for (; p <= end; p++) 434 desc_set_buf_len(p, buf_sz); 435 436 end->buf_size |= cpu_to_le32(RXDESC1_END_RING); 437 } 438 439 static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size) 440 { 441 memset(p, 0, sizeof(*p) * ring_size); 442 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING); 443 } 444 445 static inline int desc_get_owner(struct xgmac_dma_desc *p) 446 { 447 return le32_to_cpu(p->flags) & DESC_OWN; 448 } 449 450 static inline void desc_set_rx_owner(struct xgmac_dma_desc *p) 451 { 452 /* Clear all fields and set the owner */ 453 p->flags = cpu_to_le32(DESC_OWN); 454 } 455 456 static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags) 457 { 458 u32 tmpflags = le32_to_cpu(p->flags); 459 tmpflags &= TXDESC_END_RING; 460 tmpflags |= flags | DESC_OWN; 461 p->flags = cpu_to_le32(tmpflags); 462 } 463 464 static inline int desc_get_tx_ls(struct xgmac_dma_desc *p) 465 { 466 return le32_to_cpu(p->flags) & TXDESC_LAST_SEG; 467 } 468 469 static inline u32 desc_get_buf_addr(struct xgmac_dma_desc *p) 470 { 471 return le32_to_cpu(p->buf1_addr); 472 } 473 474 static inline void desc_set_buf_addr(struct xgmac_dma_desc *p, 475 u32 paddr, int len) 476 { 477 p->buf1_addr = cpu_to_le32(paddr); 478 if (len > MAX_DESC_BUF_SZ) 479 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ); 480 } 481 482 static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p, 483 u32 paddr, int len) 484 { 485 desc_set_buf_len(p, len); 486 desc_set_buf_addr(p, paddr, len); 487 } 488 489 static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p) 490 { 491 u32 data = le32_to_cpu(p->flags); 492 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET; 493 if (data & RXDESC_FRAME_TYPE) 494 len -= ETH_FCS_LEN; 495 496 return len; 497 } 498 499 static void xgmac_dma_flush_tx_fifo(void __iomem *ioaddr) 500 { 501 int timeout = 1000; 502 u32 reg = readl(ioaddr + XGMAC_OMR); 503 writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR); 504 505 while ((timeout-- > 0) && readl(ioaddr + XGMAC_OMR) & XGMAC_OMR_FTF) 506 udelay(1); 507 } 508 509 static int desc_get_tx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p) 510 { 511 struct xgmac_extra_stats *x = &priv->xstats; 512 u32 status = le32_to_cpu(p->flags); 513 514 if (!(status & TXDESC_ERROR_SUMMARY)) 515 return 0; 516 517 netdev_dbg(priv->dev, "tx desc error = 0x%08x\n", status); 518 if (status & TXDESC_JABBER_TIMEOUT) 519 x->tx_jabber++; 520 if (status & TXDESC_FRAME_FLUSHED) 521 x->tx_frame_flushed++; 522 if (status & TXDESC_UNDERFLOW_ERR) 523 xgmac_dma_flush_tx_fifo(priv->base); 524 if (status & TXDESC_IP_HEADER_ERR) 525 x->tx_ip_header_error++; 526 if (status & TXDESC_LOCAL_FAULT) 527 x->tx_local_fault++; 528 if (status & TXDESC_REMOTE_FAULT) 529 x->tx_remote_fault++; 530 if (status & TXDESC_PAYLOAD_CSUM_ERR) 531 x->tx_payload_error++; 532 533 return -1; 534 } 535 536 static int desc_get_rx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p) 537 { 538 struct xgmac_extra_stats *x = &priv->xstats; 539 int ret = CHECKSUM_UNNECESSARY; 540 u32 status = le32_to_cpu(p->flags); 541 u32 ext_status = le32_to_cpu(p->ext_status); 542 543 if (status & RXDESC_DA_FILTER_FAIL) { 544 netdev_dbg(priv->dev, "XGMAC RX : Dest Address filter fail\n"); 545 x->rx_da_filter_fail++; 546 return -1; 547 } 548 549 /* Check if packet has checksum already */ 550 if ((status & RXDESC_FRAME_TYPE) && (status & RXDESC_EXT_STATUS) && 551 !(ext_status & RXDESC_IP_PAYLOAD_MASK)) 552 ret = CHECKSUM_NONE; 553 554 netdev_dbg(priv->dev, "rx status - frame type=%d, csum = %d, ext stat %08x\n", 555 (status & RXDESC_FRAME_TYPE) ? 1 : 0, ret, ext_status); 556 557 if (!(status & RXDESC_ERROR_SUMMARY)) 558 return ret; 559 560 /* Handle any errors */ 561 if (status & (RXDESC_DESCRIPTOR_ERR | RXDESC_OVERFLOW_ERR | 562 RXDESC_GIANT_FRAME | RXDESC_LENGTH_ERR | RXDESC_CRC_ERR)) 563 return -1; 564 565 if (status & RXDESC_EXT_STATUS) { 566 if (ext_status & RXDESC_IP_HEADER_ERR) 567 x->rx_ip_header_error++; 568 if (ext_status & RXDESC_IP_PAYLOAD_ERR) 569 x->rx_payload_error++; 570 netdev_dbg(priv->dev, "IP checksum error - stat %08x\n", 571 ext_status); 572 return CHECKSUM_NONE; 573 } 574 575 return ret; 576 } 577 578 static inline void xgmac_mac_enable(void __iomem *ioaddr) 579 { 580 u32 value = readl(ioaddr + XGMAC_CONTROL); 581 value |= MAC_ENABLE_RX | MAC_ENABLE_TX; 582 writel(value, ioaddr + XGMAC_CONTROL); 583 584 value = readl(ioaddr + XGMAC_DMA_CONTROL); 585 value |= DMA_CONTROL_ST | DMA_CONTROL_SR; 586 writel(value, ioaddr + XGMAC_DMA_CONTROL); 587 } 588 589 static inline void xgmac_mac_disable(void __iomem *ioaddr) 590 { 591 u32 value = readl(ioaddr + XGMAC_DMA_CONTROL); 592 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR); 593 writel(value, ioaddr + XGMAC_DMA_CONTROL); 594 595 value = readl(ioaddr + XGMAC_CONTROL); 596 value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX); 597 writel(value, ioaddr + XGMAC_CONTROL); 598 } 599 600 static void xgmac_set_mac_addr(void __iomem *ioaddr, unsigned char *addr, 601 int num) 602 { 603 u32 data; 604 605 data = (addr[5] << 8) | addr[4] | (num ? XGMAC_ADDR_AE : 0); 606 writel(data, ioaddr + XGMAC_ADDR_HIGH(num)); 607 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 608 writel(data, ioaddr + XGMAC_ADDR_LOW(num)); 609 } 610 611 static void xgmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, 612 int num) 613 { 614 u32 hi_addr, lo_addr; 615 616 /* Read the MAC address from the hardware */ 617 hi_addr = readl(ioaddr + XGMAC_ADDR_HIGH(num)); 618 lo_addr = readl(ioaddr + XGMAC_ADDR_LOW(num)); 619 620 /* Extract the MAC address from the high and low words */ 621 addr[0] = lo_addr & 0xff; 622 addr[1] = (lo_addr >> 8) & 0xff; 623 addr[2] = (lo_addr >> 16) & 0xff; 624 addr[3] = (lo_addr >> 24) & 0xff; 625 addr[4] = hi_addr & 0xff; 626 addr[5] = (hi_addr >> 8) & 0xff; 627 } 628 629 static int xgmac_set_flow_ctrl(struct xgmac_priv *priv, int rx, int tx) 630 { 631 u32 reg; 632 unsigned int flow = 0; 633 634 priv->rx_pause = rx; 635 priv->tx_pause = tx; 636 637 if (rx || tx) { 638 if (rx) 639 flow |= XGMAC_FLOW_CTRL_RFE; 640 if (tx) 641 flow |= XGMAC_FLOW_CTRL_TFE; 642 643 flow |= XGMAC_FLOW_CTRL_PLT | XGMAC_FLOW_CTRL_UP; 644 flow |= (PAUSE_TIME << XGMAC_FLOW_CTRL_PT_SHIFT); 645 646 writel(flow, priv->base + XGMAC_FLOW_CTRL); 647 648 reg = readl(priv->base + XGMAC_OMR); 649 reg |= XGMAC_OMR_EFC; 650 writel(reg, priv->base + XGMAC_OMR); 651 } else { 652 writel(0, priv->base + XGMAC_FLOW_CTRL); 653 654 reg = readl(priv->base + XGMAC_OMR); 655 reg &= ~XGMAC_OMR_EFC; 656 writel(reg, priv->base + XGMAC_OMR); 657 } 658 659 return 0; 660 } 661 662 static void xgmac_rx_refill(struct xgmac_priv *priv) 663 { 664 struct xgmac_dma_desc *p; 665 dma_addr_t paddr; 666 667 while (dma_ring_space(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ) > 1) { 668 int entry = priv->rx_head; 669 struct sk_buff *skb; 670 671 p = priv->dma_rx + entry; 672 673 if (priv->rx_skbuff[entry] == NULL) { 674 skb = netdev_alloc_skb(priv->dev, priv->dma_buf_sz); 675 if (unlikely(skb == NULL)) 676 break; 677 678 priv->rx_skbuff[entry] = skb; 679 paddr = dma_map_single(priv->device, skb->data, 680 priv->dma_buf_sz, DMA_FROM_DEVICE); 681 desc_set_buf_addr(p, paddr, priv->dma_buf_sz); 682 } 683 684 netdev_dbg(priv->dev, "rx ring: head %d, tail %d\n", 685 priv->rx_head, priv->rx_tail); 686 687 priv->rx_head = dma_ring_incr(priv->rx_head, DMA_RX_RING_SZ); 688 desc_set_rx_owner(p); 689 } 690 } 691 692 /** 693 * init_xgmac_dma_desc_rings - init the RX/TX descriptor rings 694 * @dev: net device structure 695 * Description: this function initializes the DMA RX/TX descriptors 696 * and allocates the socket buffers. 697 */ 698 static int xgmac_dma_desc_rings_init(struct net_device *dev) 699 { 700 struct xgmac_priv *priv = netdev_priv(dev); 701 unsigned int bfsize; 702 703 /* Set the Buffer size according to the MTU; 704 * indeed, in case of jumbo we need to bump-up the buffer sizes. 705 */ 706 bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN + 64, 707 64); 708 709 netdev_dbg(priv->dev, "mtu [%d] bfsize [%d]\n", dev->mtu, bfsize); 710 711 priv->rx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_RX_RING_SZ, 712 GFP_KERNEL); 713 if (!priv->rx_skbuff) 714 return -ENOMEM; 715 716 priv->dma_rx = dma_alloc_coherent(priv->device, 717 DMA_RX_RING_SZ * 718 sizeof(struct xgmac_dma_desc), 719 &priv->dma_rx_phy, 720 GFP_KERNEL); 721 if (!priv->dma_rx) 722 goto err_dma_rx; 723 724 priv->tx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_TX_RING_SZ, 725 GFP_KERNEL); 726 if (!priv->tx_skbuff) 727 goto err_tx_skb; 728 729 priv->dma_tx = dma_alloc_coherent(priv->device, 730 DMA_TX_RING_SZ * 731 sizeof(struct xgmac_dma_desc), 732 &priv->dma_tx_phy, 733 GFP_KERNEL); 734 if (!priv->dma_tx) 735 goto err_dma_tx; 736 737 netdev_dbg(priv->dev, "DMA desc rings: virt addr (Rx %p, " 738 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", 739 priv->dma_rx, priv->dma_tx, 740 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); 741 742 priv->rx_tail = 0; 743 priv->rx_head = 0; 744 priv->dma_buf_sz = bfsize; 745 desc_init_rx_desc(priv->dma_rx, DMA_RX_RING_SZ, priv->dma_buf_sz); 746 xgmac_rx_refill(priv); 747 748 priv->tx_tail = 0; 749 priv->tx_head = 0; 750 desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ); 751 752 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); 753 writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR); 754 755 return 0; 756 757 err_dma_tx: 758 kfree(priv->tx_skbuff); 759 err_tx_skb: 760 dma_free_coherent(priv->device, 761 DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc), 762 priv->dma_rx, priv->dma_rx_phy); 763 err_dma_rx: 764 kfree(priv->rx_skbuff); 765 return -ENOMEM; 766 } 767 768 static void xgmac_free_rx_skbufs(struct xgmac_priv *priv) 769 { 770 int i; 771 struct xgmac_dma_desc *p; 772 773 if (!priv->rx_skbuff) 774 return; 775 776 for (i = 0; i < DMA_RX_RING_SZ; i++) { 777 if (priv->rx_skbuff[i] == NULL) 778 continue; 779 780 p = priv->dma_rx + i; 781 dma_unmap_single(priv->device, desc_get_buf_addr(p), 782 priv->dma_buf_sz, DMA_FROM_DEVICE); 783 dev_kfree_skb_any(priv->rx_skbuff[i]); 784 priv->rx_skbuff[i] = NULL; 785 } 786 } 787 788 static void xgmac_free_tx_skbufs(struct xgmac_priv *priv) 789 { 790 int i, f; 791 struct xgmac_dma_desc *p; 792 793 if (!priv->tx_skbuff) 794 return; 795 796 for (i = 0; i < DMA_TX_RING_SZ; i++) { 797 if (priv->tx_skbuff[i] == NULL) 798 continue; 799 800 p = priv->dma_tx + i; 801 dma_unmap_single(priv->device, desc_get_buf_addr(p), 802 desc_get_buf_len(p), DMA_TO_DEVICE); 803 804 for (f = 0; f < skb_shinfo(priv->tx_skbuff[i])->nr_frags; f++) { 805 p = priv->dma_tx + i++; 806 dma_unmap_page(priv->device, desc_get_buf_addr(p), 807 desc_get_buf_len(p), DMA_TO_DEVICE); 808 } 809 810 dev_kfree_skb_any(priv->tx_skbuff[i]); 811 priv->tx_skbuff[i] = NULL; 812 } 813 } 814 815 static void xgmac_free_dma_desc_rings(struct xgmac_priv *priv) 816 { 817 /* Release the DMA TX/RX socket buffers */ 818 xgmac_free_rx_skbufs(priv); 819 xgmac_free_tx_skbufs(priv); 820 821 /* Free the consistent memory allocated for descriptor rings */ 822 if (priv->dma_tx) { 823 dma_free_coherent(priv->device, 824 DMA_TX_RING_SZ * sizeof(struct xgmac_dma_desc), 825 priv->dma_tx, priv->dma_tx_phy); 826 priv->dma_tx = NULL; 827 } 828 if (priv->dma_rx) { 829 dma_free_coherent(priv->device, 830 DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc), 831 priv->dma_rx, priv->dma_rx_phy); 832 priv->dma_rx = NULL; 833 } 834 kfree(priv->rx_skbuff); 835 priv->rx_skbuff = NULL; 836 kfree(priv->tx_skbuff); 837 priv->tx_skbuff = NULL; 838 } 839 840 /** 841 * xgmac_tx: 842 * @priv: private driver structure 843 * Description: it reclaims resources after transmission completes. 844 */ 845 static void xgmac_tx_complete(struct xgmac_priv *priv) 846 { 847 int i; 848 void __iomem *ioaddr = priv->base; 849 850 writel(DMA_STATUS_TU | DMA_STATUS_NIS, ioaddr + XGMAC_DMA_STATUS); 851 852 while (dma_ring_cnt(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ)) { 853 unsigned int entry = priv->tx_tail; 854 struct sk_buff *skb = priv->tx_skbuff[entry]; 855 struct xgmac_dma_desc *p = priv->dma_tx + entry; 856 857 /* Check if the descriptor is owned by the DMA. */ 858 if (desc_get_owner(p)) 859 break; 860 861 /* Verify tx error by looking at the last segment */ 862 if (desc_get_tx_ls(p)) 863 desc_get_tx_status(priv, p); 864 865 netdev_dbg(priv->dev, "tx ring: curr %d, dirty %d\n", 866 priv->tx_head, priv->tx_tail); 867 868 dma_unmap_single(priv->device, desc_get_buf_addr(p), 869 desc_get_buf_len(p), DMA_TO_DEVICE); 870 871 priv->tx_skbuff[entry] = NULL; 872 priv->tx_tail = dma_ring_incr(entry, DMA_TX_RING_SZ); 873 874 if (!skb) { 875 continue; 876 } 877 878 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 879 entry = priv->tx_tail = dma_ring_incr(priv->tx_tail, 880 DMA_TX_RING_SZ); 881 p = priv->dma_tx + priv->tx_tail; 882 883 dma_unmap_page(priv->device, desc_get_buf_addr(p), 884 desc_get_buf_len(p), DMA_TO_DEVICE); 885 } 886 887 dev_kfree_skb(skb); 888 } 889 890 if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) > 891 TX_THRESH) 892 netif_wake_queue(priv->dev); 893 } 894 895 /** 896 * xgmac_tx_err: 897 * @priv: pointer to the private device structure 898 * Description: it cleans the descriptors and restarts the transmission 899 * in case of errors. 900 */ 901 static void xgmac_tx_err(struct xgmac_priv *priv) 902 { 903 u32 reg, value, inten; 904 905 netif_stop_queue(priv->dev); 906 907 inten = readl(priv->base + XGMAC_DMA_INTR_ENA); 908 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 909 910 reg = readl(priv->base + XGMAC_DMA_CONTROL); 911 writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); 912 do { 913 value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000; 914 } while (value && (value != 0x600000)); 915 916 xgmac_free_tx_skbufs(priv); 917 desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ); 918 priv->tx_tail = 0; 919 priv->tx_head = 0; 920 writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR); 921 writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); 922 923 writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS, 924 priv->base + XGMAC_DMA_STATUS); 925 writel(inten, priv->base + XGMAC_DMA_INTR_ENA); 926 927 netif_wake_queue(priv->dev); 928 } 929 930 static int xgmac_hw_init(struct net_device *dev) 931 { 932 u32 value, ctrl; 933 int limit; 934 struct xgmac_priv *priv = netdev_priv(dev); 935 void __iomem *ioaddr = priv->base; 936 937 /* Save the ctrl register value */ 938 ctrl = readl(ioaddr + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK; 939 940 /* SW reset */ 941 value = DMA_BUS_MODE_SFT_RESET; 942 writel(value, ioaddr + XGMAC_DMA_BUS_MODE); 943 limit = 15000; 944 while (limit-- && 945 (readl(ioaddr + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 946 cpu_relax(); 947 if (limit < 0) 948 return -EBUSY; 949 950 value = (0x10 << DMA_BUS_MODE_PBL_SHIFT) | 951 (0x10 << DMA_BUS_MODE_RPBL_SHIFT) | 952 DMA_BUS_MODE_FB | DMA_BUS_MODE_ATDS | DMA_BUS_MODE_AAL; 953 writel(value, ioaddr + XGMAC_DMA_BUS_MODE); 954 955 /* Enable interrupts */ 956 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS); 957 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); 958 959 /* XGMAC requires AXI bus init. This is a 'magic number' for now */ 960 writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS); 961 962 ctrl |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_JE | XGMAC_CONTROL_ACS | 963 XGMAC_CONTROL_CAR; 964 if (dev->features & NETIF_F_RXCSUM) 965 ctrl |= XGMAC_CONTROL_IPC; 966 writel(ctrl, ioaddr + XGMAC_CONTROL); 967 968 value = DMA_CONTROL_DFF; 969 writel(value, ioaddr + XGMAC_DMA_CONTROL); 970 971 /* Set the HW DMA mode and the COE */ 972 writel(XGMAC_OMR_TSF | XGMAC_OMR_RFD | XGMAC_OMR_RFA | 973 XGMAC_OMR_RTC_256, 974 ioaddr + XGMAC_OMR); 975 976 /* Reset the MMC counters */ 977 writel(1, ioaddr + XGMAC_MMC_CTRL); 978 return 0; 979 } 980 981 /** 982 * xgmac_open - open entry point of the driver 983 * @dev : pointer to the device structure. 984 * Description: 985 * This function is the open entry point of the driver. 986 * Return value: 987 * 0 on success and an appropriate (-)ve integer as defined in errno.h 988 * file on failure. 989 */ 990 static int xgmac_open(struct net_device *dev) 991 { 992 int ret; 993 struct xgmac_priv *priv = netdev_priv(dev); 994 void __iomem *ioaddr = priv->base; 995 996 /* Check that the MAC address is valid. If its not, refuse 997 * to bring the device up. The user must specify an 998 * address using the following linux command: 999 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */ 1000 if (!is_valid_ether_addr(dev->dev_addr)) { 1001 eth_hw_addr_random(dev); 1002 netdev_dbg(priv->dev, "generated random MAC address %pM\n", 1003 dev->dev_addr); 1004 } 1005 1006 memset(&priv->xstats, 0, sizeof(struct xgmac_extra_stats)); 1007 1008 /* Initialize the XGMAC and descriptors */ 1009 xgmac_hw_init(dev); 1010 xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0); 1011 xgmac_set_flow_ctrl(priv, priv->rx_pause, priv->tx_pause); 1012 1013 ret = xgmac_dma_desc_rings_init(dev); 1014 if (ret < 0) 1015 return ret; 1016 1017 /* Enable the MAC Rx/Tx */ 1018 xgmac_mac_enable(ioaddr); 1019 1020 napi_enable(&priv->napi); 1021 netif_start_queue(dev); 1022 1023 return 0; 1024 } 1025 1026 /** 1027 * xgmac_release - close entry point of the driver 1028 * @dev : device pointer. 1029 * Description: 1030 * This is the stop entry point of the driver. 1031 */ 1032 static int xgmac_stop(struct net_device *dev) 1033 { 1034 struct xgmac_priv *priv = netdev_priv(dev); 1035 1036 netif_stop_queue(dev); 1037 1038 if (readl(priv->base + XGMAC_DMA_INTR_ENA)) 1039 napi_disable(&priv->napi); 1040 1041 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 1042 1043 /* Disable the MAC core */ 1044 xgmac_mac_disable(priv->base); 1045 1046 /* Release and free the Rx/Tx resources */ 1047 xgmac_free_dma_desc_rings(priv); 1048 1049 return 0; 1050 } 1051 1052 /** 1053 * xgmac_xmit: 1054 * @skb : the socket buffer 1055 * @dev : device pointer 1056 * Description : Tx entry point of the driver. 1057 */ 1058 static netdev_tx_t xgmac_xmit(struct sk_buff *skb, struct net_device *dev) 1059 { 1060 struct xgmac_priv *priv = netdev_priv(dev); 1061 unsigned int entry; 1062 int i; 1063 int nfrags = skb_shinfo(skb)->nr_frags; 1064 struct xgmac_dma_desc *desc, *first; 1065 unsigned int desc_flags; 1066 unsigned int len; 1067 dma_addr_t paddr; 1068 1069 if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) < 1070 (nfrags + 1)) { 1071 writel(DMA_INTR_DEFAULT_MASK | DMA_INTR_ENA_TIE, 1072 priv->base + XGMAC_DMA_INTR_ENA); 1073 netif_stop_queue(dev); 1074 return NETDEV_TX_BUSY; 1075 } 1076 1077 desc_flags = (skb->ip_summed == CHECKSUM_PARTIAL) ? 1078 TXDESC_CSUM_ALL : 0; 1079 entry = priv->tx_head; 1080 desc = priv->dma_tx + entry; 1081 first = desc; 1082 1083 len = skb_headlen(skb); 1084 paddr = dma_map_single(priv->device, skb->data, len, DMA_TO_DEVICE); 1085 if (dma_mapping_error(priv->device, paddr)) { 1086 dev_kfree_skb(skb); 1087 return -EIO; 1088 } 1089 priv->tx_skbuff[entry] = skb; 1090 desc_set_buf_addr_and_size(desc, paddr, len); 1091 1092 for (i = 0; i < nfrags; i++) { 1093 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1094 1095 len = frag->size; 1096 1097 paddr = skb_frag_dma_map(priv->device, frag, 0, len, 1098 DMA_TO_DEVICE); 1099 if (dma_mapping_error(priv->device, paddr)) { 1100 dev_kfree_skb(skb); 1101 return -EIO; 1102 } 1103 1104 entry = dma_ring_incr(entry, DMA_TX_RING_SZ); 1105 desc = priv->dma_tx + entry; 1106 priv->tx_skbuff[entry] = NULL; 1107 1108 desc_set_buf_addr_and_size(desc, paddr, len); 1109 if (i < (nfrags - 1)) 1110 desc_set_tx_owner(desc, desc_flags); 1111 } 1112 1113 /* Interrupt on completition only for the latest segment */ 1114 if (desc != first) 1115 desc_set_tx_owner(desc, desc_flags | 1116 TXDESC_LAST_SEG | TXDESC_INTERRUPT); 1117 else 1118 desc_flags |= TXDESC_LAST_SEG | TXDESC_INTERRUPT; 1119 1120 /* Set owner on first desc last to avoid race condition */ 1121 wmb(); 1122 desc_set_tx_owner(first, desc_flags | TXDESC_FIRST_SEG); 1123 1124 priv->tx_head = dma_ring_incr(entry, DMA_TX_RING_SZ); 1125 1126 writel(1, priv->base + XGMAC_DMA_TX_POLL); 1127 1128 return NETDEV_TX_OK; 1129 } 1130 1131 static int xgmac_rx(struct xgmac_priv *priv, int limit) 1132 { 1133 unsigned int entry; 1134 unsigned int count = 0; 1135 struct xgmac_dma_desc *p; 1136 1137 while (count < limit) { 1138 int ip_checksum; 1139 struct sk_buff *skb; 1140 int frame_len; 1141 1142 writel(DMA_STATUS_RI | DMA_STATUS_NIS, 1143 priv->base + XGMAC_DMA_STATUS); 1144 1145 entry = priv->rx_tail; 1146 p = priv->dma_rx + entry; 1147 if (desc_get_owner(p)) 1148 break; 1149 1150 count++; 1151 priv->rx_tail = dma_ring_incr(priv->rx_tail, DMA_RX_RING_SZ); 1152 1153 /* read the status of the incoming frame */ 1154 ip_checksum = desc_get_rx_status(priv, p); 1155 if (ip_checksum < 0) 1156 continue; 1157 1158 skb = priv->rx_skbuff[entry]; 1159 if (unlikely(!skb)) { 1160 netdev_err(priv->dev, "Inconsistent Rx descriptor chain\n"); 1161 break; 1162 } 1163 priv->rx_skbuff[entry] = NULL; 1164 1165 frame_len = desc_get_rx_frame_len(p); 1166 netdev_dbg(priv->dev, "RX frame size %d, COE status: %d\n", 1167 frame_len, ip_checksum); 1168 1169 skb_put(skb, frame_len); 1170 dma_unmap_single(priv->device, desc_get_buf_addr(p), 1171 frame_len, DMA_FROM_DEVICE); 1172 1173 skb->protocol = eth_type_trans(skb, priv->dev); 1174 skb->ip_summed = ip_checksum; 1175 if (ip_checksum == CHECKSUM_NONE) 1176 netif_receive_skb(skb); 1177 else 1178 napi_gro_receive(&priv->napi, skb); 1179 } 1180 1181 xgmac_rx_refill(priv); 1182 1183 writel(1, priv->base + XGMAC_DMA_RX_POLL); 1184 1185 return count; 1186 } 1187 1188 /** 1189 * xgmac_poll - xgmac poll method (NAPI) 1190 * @napi : pointer to the napi structure. 1191 * @budget : maximum number of packets that the current CPU can receive from 1192 * all interfaces. 1193 * Description : 1194 * This function implements the the reception process. 1195 * Also it runs the TX completion thread 1196 */ 1197 static int xgmac_poll(struct napi_struct *napi, int budget) 1198 { 1199 struct xgmac_priv *priv = container_of(napi, 1200 struct xgmac_priv, napi); 1201 int work_done = 0; 1202 1203 xgmac_tx_complete(priv); 1204 work_done = xgmac_rx(priv, budget); 1205 1206 if (work_done < budget) { 1207 napi_complete(napi); 1208 writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA); 1209 } 1210 return work_done; 1211 } 1212 1213 /** 1214 * xgmac_tx_timeout 1215 * @dev : Pointer to net device structure 1216 * Description: this function is called when a packet transmission fails to 1217 * complete within a reasonable tmrate. The driver will mark the error in the 1218 * netdev structure and arrange for the device to be reset to a sane state 1219 * in order to transmit a new packet. 1220 */ 1221 static void xgmac_tx_timeout(struct net_device *dev) 1222 { 1223 struct xgmac_priv *priv = netdev_priv(dev); 1224 1225 /* Clear Tx resources and restart transmitting again */ 1226 xgmac_tx_err(priv); 1227 } 1228 1229 /** 1230 * xgmac_set_rx_mode - entry point for multicast addressing 1231 * @dev : pointer to the device structure 1232 * Description: 1233 * This function is a driver entry point which gets called by the kernel 1234 * whenever multicast addresses must be enabled/disabled. 1235 * Return value: 1236 * void. 1237 */ 1238 static void xgmac_set_rx_mode(struct net_device *dev) 1239 { 1240 int i; 1241 struct xgmac_priv *priv = netdev_priv(dev); 1242 void __iomem *ioaddr = priv->base; 1243 unsigned int value = 0; 1244 u32 hash_filter[XGMAC_NUM_HASH]; 1245 int reg = 1; 1246 struct netdev_hw_addr *ha; 1247 bool use_hash = false; 1248 1249 netdev_dbg(priv->dev, "# mcasts %d, # unicast %d\n", 1250 netdev_mc_count(dev), netdev_uc_count(dev)); 1251 1252 if (dev->flags & IFF_PROMISC) { 1253 writel(XGMAC_FRAME_FILTER_PR, ioaddr + XGMAC_FRAME_FILTER); 1254 return; 1255 } 1256 1257 memset(hash_filter, 0, sizeof(hash_filter)); 1258 1259 if (netdev_uc_count(dev) > XGMAC_MAX_FILTER_ADDR) { 1260 use_hash = true; 1261 value |= XGMAC_FRAME_FILTER_HUC | XGMAC_FRAME_FILTER_HPF; 1262 } 1263 netdev_for_each_uc_addr(ha, dev) { 1264 if (use_hash) { 1265 u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23; 1266 1267 /* The most significant 4 bits determine the register to 1268 * use (H/L) while the other 5 bits determine the bit 1269 * within the register. */ 1270 hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1271 } else { 1272 xgmac_set_mac_addr(ioaddr, ha->addr, reg); 1273 reg++; 1274 } 1275 } 1276 1277 if (dev->flags & IFF_ALLMULTI) { 1278 value |= XGMAC_FRAME_FILTER_PM; 1279 goto out; 1280 } 1281 1282 if ((netdev_mc_count(dev) + reg - 1) > XGMAC_MAX_FILTER_ADDR) { 1283 use_hash = true; 1284 value |= XGMAC_FRAME_FILTER_HMC | XGMAC_FRAME_FILTER_HPF; 1285 } 1286 netdev_for_each_mc_addr(ha, dev) { 1287 if (use_hash) { 1288 u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23; 1289 1290 /* The most significant 4 bits determine the register to 1291 * use (H/L) while the other 5 bits determine the bit 1292 * within the register. */ 1293 hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 1294 } else { 1295 xgmac_set_mac_addr(ioaddr, ha->addr, reg); 1296 reg++; 1297 } 1298 } 1299 1300 out: 1301 for (i = 0; i < XGMAC_NUM_HASH; i++) 1302 writel(hash_filter[i], ioaddr + XGMAC_HASH(i)); 1303 1304 writel(value, ioaddr + XGMAC_FRAME_FILTER); 1305 } 1306 1307 /** 1308 * xgmac_change_mtu - entry point to change MTU size for the device. 1309 * @dev : device pointer. 1310 * @new_mtu : the new MTU size for the device. 1311 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 1312 * to drive packet transmission. Ethernet has an MTU of 1500 octets 1313 * (ETH_DATA_LEN). This value can be changed with ifconfig. 1314 * Return value: 1315 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1316 * file on failure. 1317 */ 1318 static int xgmac_change_mtu(struct net_device *dev, int new_mtu) 1319 { 1320 struct xgmac_priv *priv = netdev_priv(dev); 1321 int old_mtu; 1322 1323 if ((new_mtu < 46) || (new_mtu > MAX_MTU)) { 1324 netdev_err(priv->dev, "invalid MTU, max MTU is: %d\n", MAX_MTU); 1325 return -EINVAL; 1326 } 1327 1328 old_mtu = dev->mtu; 1329 dev->mtu = new_mtu; 1330 1331 /* return early if the buffer sizes will not change */ 1332 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) 1333 return 0; 1334 if (old_mtu == new_mtu) 1335 return 0; 1336 1337 /* Stop everything, get ready to change the MTU */ 1338 if (!netif_running(dev)) 1339 return 0; 1340 1341 /* Bring the interface down and then back up */ 1342 xgmac_stop(dev); 1343 return xgmac_open(dev); 1344 } 1345 1346 static irqreturn_t xgmac_pmt_interrupt(int irq, void *dev_id) 1347 { 1348 u32 intr_status; 1349 struct net_device *dev = (struct net_device *)dev_id; 1350 struct xgmac_priv *priv = netdev_priv(dev); 1351 void __iomem *ioaddr = priv->base; 1352 1353 intr_status = readl(ioaddr + XGMAC_INT_STAT); 1354 if (intr_status & XGMAC_INT_STAT_PMT) { 1355 netdev_dbg(priv->dev, "received Magic frame\n"); 1356 /* clear the PMT bits 5 and 6 by reading the PMT */ 1357 readl(ioaddr + XGMAC_PMT); 1358 } 1359 return IRQ_HANDLED; 1360 } 1361 1362 static irqreturn_t xgmac_interrupt(int irq, void *dev_id) 1363 { 1364 u32 intr_status; 1365 bool tx_err = false; 1366 struct net_device *dev = (struct net_device *)dev_id; 1367 struct xgmac_priv *priv = netdev_priv(dev); 1368 struct xgmac_extra_stats *x = &priv->xstats; 1369 1370 /* read the status register (CSR5) */ 1371 intr_status = readl(priv->base + XGMAC_DMA_STATUS); 1372 intr_status &= readl(priv->base + XGMAC_DMA_INTR_ENA); 1373 writel(intr_status, priv->base + XGMAC_DMA_STATUS); 1374 1375 /* It displays the DMA process states (CSR5 register) */ 1376 /* ABNORMAL interrupts */ 1377 if (unlikely(intr_status & DMA_STATUS_AIS)) { 1378 if (intr_status & DMA_STATUS_TJT) { 1379 netdev_err(priv->dev, "transmit jabber\n"); 1380 x->tx_jabber++; 1381 } 1382 if (intr_status & DMA_STATUS_RU) 1383 x->rx_buf_unav++; 1384 if (intr_status & DMA_STATUS_RPS) { 1385 netdev_err(priv->dev, "receive process stopped\n"); 1386 x->rx_process_stopped++; 1387 } 1388 if (intr_status & DMA_STATUS_ETI) { 1389 netdev_err(priv->dev, "transmit early interrupt\n"); 1390 x->tx_early++; 1391 } 1392 if (intr_status & DMA_STATUS_TPS) { 1393 netdev_err(priv->dev, "transmit process stopped\n"); 1394 x->tx_process_stopped++; 1395 tx_err = true; 1396 } 1397 if (intr_status & DMA_STATUS_FBI) { 1398 netdev_err(priv->dev, "fatal bus error\n"); 1399 x->fatal_bus_error++; 1400 tx_err = true; 1401 } 1402 1403 if (tx_err) 1404 xgmac_tx_err(priv); 1405 } 1406 1407 /* TX/RX NORMAL interrupts */ 1408 if (intr_status & (DMA_STATUS_RI | DMA_STATUS_TU)) { 1409 writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA); 1410 napi_schedule(&priv->napi); 1411 } 1412 1413 return IRQ_HANDLED; 1414 } 1415 1416 #ifdef CONFIG_NET_POLL_CONTROLLER 1417 /* Polling receive - used by NETCONSOLE and other diagnostic tools 1418 * to allow network I/O with interrupts disabled. */ 1419 static void xgmac_poll_controller(struct net_device *dev) 1420 { 1421 disable_irq(dev->irq); 1422 xgmac_interrupt(dev->irq, dev); 1423 enable_irq(dev->irq); 1424 } 1425 #endif 1426 1427 static struct rtnl_link_stats64 * 1428 xgmac_get_stats64(struct net_device *dev, 1429 struct rtnl_link_stats64 *storage) 1430 { 1431 struct xgmac_priv *priv = netdev_priv(dev); 1432 void __iomem *base = priv->base; 1433 u32 count; 1434 1435 spin_lock_bh(&priv->stats_lock); 1436 writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL); 1437 1438 storage->rx_bytes = readl(base + XGMAC_MMC_RXOCTET_G_LO); 1439 storage->rx_bytes |= (u64)(readl(base + XGMAC_MMC_RXOCTET_G_HI)) << 32; 1440 1441 storage->rx_packets = readl(base + XGMAC_MMC_RXFRAME_GB_LO); 1442 storage->multicast = readl(base + XGMAC_MMC_RXMCFRAME_G); 1443 storage->rx_crc_errors = readl(base + XGMAC_MMC_RXCRCERR); 1444 storage->rx_length_errors = readl(base + XGMAC_MMC_RXLENGTHERR); 1445 storage->rx_missed_errors = readl(base + XGMAC_MMC_RXOVERFLOW); 1446 1447 storage->tx_bytes = readl(base + XGMAC_MMC_TXOCTET_G_LO); 1448 storage->tx_bytes |= (u64)(readl(base + XGMAC_MMC_TXOCTET_G_HI)) << 32; 1449 1450 count = readl(base + XGMAC_MMC_TXFRAME_GB_LO); 1451 storage->tx_errors = count - readl(base + XGMAC_MMC_TXFRAME_G_LO); 1452 storage->tx_packets = count; 1453 storage->tx_fifo_errors = readl(base + XGMAC_MMC_TXUNDERFLOW); 1454 1455 writel(0, base + XGMAC_MMC_CTRL); 1456 spin_unlock_bh(&priv->stats_lock); 1457 return storage; 1458 } 1459 1460 static int xgmac_set_mac_address(struct net_device *dev, void *p) 1461 { 1462 struct xgmac_priv *priv = netdev_priv(dev); 1463 void __iomem *ioaddr = priv->base; 1464 struct sockaddr *addr = p; 1465 1466 if (!is_valid_ether_addr(addr->sa_data)) 1467 return -EADDRNOTAVAIL; 1468 1469 dev->addr_assign_type &= ~NET_ADDR_RANDOM; 1470 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1471 1472 xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0); 1473 1474 return 0; 1475 } 1476 1477 static int xgmac_set_features(struct net_device *dev, netdev_features_t features) 1478 { 1479 u32 ctrl; 1480 struct xgmac_priv *priv = netdev_priv(dev); 1481 void __iomem *ioaddr = priv->base; 1482 u32 changed = dev->features ^ features; 1483 1484 if (!(changed & NETIF_F_RXCSUM)) 1485 return 0; 1486 1487 ctrl = readl(ioaddr + XGMAC_CONTROL); 1488 if (features & NETIF_F_RXCSUM) 1489 ctrl |= XGMAC_CONTROL_IPC; 1490 else 1491 ctrl &= ~XGMAC_CONTROL_IPC; 1492 writel(ctrl, ioaddr + XGMAC_CONTROL); 1493 1494 return 0; 1495 } 1496 1497 static const struct net_device_ops xgmac_netdev_ops = { 1498 .ndo_open = xgmac_open, 1499 .ndo_start_xmit = xgmac_xmit, 1500 .ndo_stop = xgmac_stop, 1501 .ndo_change_mtu = xgmac_change_mtu, 1502 .ndo_set_rx_mode = xgmac_set_rx_mode, 1503 .ndo_tx_timeout = xgmac_tx_timeout, 1504 .ndo_get_stats64 = xgmac_get_stats64, 1505 #ifdef CONFIG_NET_POLL_CONTROLLER 1506 .ndo_poll_controller = xgmac_poll_controller, 1507 #endif 1508 .ndo_set_mac_address = xgmac_set_mac_address, 1509 .ndo_set_features = xgmac_set_features, 1510 }; 1511 1512 static int xgmac_ethtool_getsettings(struct net_device *dev, 1513 struct ethtool_cmd *cmd) 1514 { 1515 cmd->autoneg = 0; 1516 cmd->duplex = DUPLEX_FULL; 1517 ethtool_cmd_speed_set(cmd, 10000); 1518 cmd->supported = 0; 1519 cmd->advertising = 0; 1520 cmd->transceiver = XCVR_INTERNAL; 1521 return 0; 1522 } 1523 1524 static void xgmac_get_pauseparam(struct net_device *netdev, 1525 struct ethtool_pauseparam *pause) 1526 { 1527 struct xgmac_priv *priv = netdev_priv(netdev); 1528 1529 pause->rx_pause = priv->rx_pause; 1530 pause->tx_pause = priv->tx_pause; 1531 } 1532 1533 static int xgmac_set_pauseparam(struct net_device *netdev, 1534 struct ethtool_pauseparam *pause) 1535 { 1536 struct xgmac_priv *priv = netdev_priv(netdev); 1537 1538 if (pause->autoneg) 1539 return -EINVAL; 1540 1541 return xgmac_set_flow_ctrl(priv, pause->rx_pause, pause->tx_pause); 1542 } 1543 1544 struct xgmac_stats { 1545 char stat_string[ETH_GSTRING_LEN]; 1546 int stat_offset; 1547 bool is_reg; 1548 }; 1549 1550 #define XGMAC_STAT(m) \ 1551 { #m, offsetof(struct xgmac_priv, xstats.m), false } 1552 #define XGMAC_HW_STAT(m, reg_offset) \ 1553 { #m, reg_offset, true } 1554 1555 static const struct xgmac_stats xgmac_gstrings_stats[] = { 1556 XGMAC_STAT(tx_frame_flushed), 1557 XGMAC_STAT(tx_payload_error), 1558 XGMAC_STAT(tx_ip_header_error), 1559 XGMAC_STAT(tx_local_fault), 1560 XGMAC_STAT(tx_remote_fault), 1561 XGMAC_STAT(tx_early), 1562 XGMAC_STAT(tx_process_stopped), 1563 XGMAC_STAT(tx_jabber), 1564 XGMAC_STAT(rx_buf_unav), 1565 XGMAC_STAT(rx_process_stopped), 1566 XGMAC_STAT(rx_payload_error), 1567 XGMAC_STAT(rx_ip_header_error), 1568 XGMAC_STAT(rx_da_filter_fail), 1569 XGMAC_STAT(rx_sa_filter_fail), 1570 XGMAC_STAT(fatal_bus_error), 1571 XGMAC_HW_STAT(rx_watchdog, XGMAC_MMC_RXWATCHDOG), 1572 XGMAC_HW_STAT(tx_vlan, XGMAC_MMC_TXVLANFRAME), 1573 XGMAC_HW_STAT(rx_vlan, XGMAC_MMC_RXVLANFRAME), 1574 XGMAC_HW_STAT(tx_pause, XGMAC_MMC_TXPAUSEFRAME), 1575 XGMAC_HW_STAT(rx_pause, XGMAC_MMC_RXPAUSEFRAME), 1576 }; 1577 #define XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats) 1578 1579 static void xgmac_get_ethtool_stats(struct net_device *dev, 1580 struct ethtool_stats *dummy, 1581 u64 *data) 1582 { 1583 struct xgmac_priv *priv = netdev_priv(dev); 1584 void *p = priv; 1585 int i; 1586 1587 for (i = 0; i < XGMAC_STATS_LEN; i++) { 1588 if (xgmac_gstrings_stats[i].is_reg) 1589 *data++ = readl(priv->base + 1590 xgmac_gstrings_stats[i].stat_offset); 1591 else 1592 *data++ = *(u32 *)(p + 1593 xgmac_gstrings_stats[i].stat_offset); 1594 } 1595 } 1596 1597 static int xgmac_get_sset_count(struct net_device *netdev, int sset) 1598 { 1599 switch (sset) { 1600 case ETH_SS_STATS: 1601 return XGMAC_STATS_LEN; 1602 default: 1603 return -EINVAL; 1604 } 1605 } 1606 1607 static void xgmac_get_strings(struct net_device *dev, u32 stringset, 1608 u8 *data) 1609 { 1610 int i; 1611 u8 *p = data; 1612 1613 switch (stringset) { 1614 case ETH_SS_STATS: 1615 for (i = 0; i < XGMAC_STATS_LEN; i++) { 1616 memcpy(p, xgmac_gstrings_stats[i].stat_string, 1617 ETH_GSTRING_LEN); 1618 p += ETH_GSTRING_LEN; 1619 } 1620 break; 1621 default: 1622 WARN_ON(1); 1623 break; 1624 } 1625 } 1626 1627 static void xgmac_get_wol(struct net_device *dev, 1628 struct ethtool_wolinfo *wol) 1629 { 1630 struct xgmac_priv *priv = netdev_priv(dev); 1631 1632 if (device_can_wakeup(priv->device)) { 1633 wol->supported = WAKE_MAGIC | WAKE_UCAST; 1634 wol->wolopts = priv->wolopts; 1635 } 1636 } 1637 1638 static int xgmac_set_wol(struct net_device *dev, 1639 struct ethtool_wolinfo *wol) 1640 { 1641 struct xgmac_priv *priv = netdev_priv(dev); 1642 u32 support = WAKE_MAGIC | WAKE_UCAST; 1643 1644 if (!device_can_wakeup(priv->device)) 1645 return -ENOTSUPP; 1646 1647 if (wol->wolopts & ~support) 1648 return -EINVAL; 1649 1650 priv->wolopts = wol->wolopts; 1651 1652 if (wol->wolopts) { 1653 device_set_wakeup_enable(priv->device, 1); 1654 enable_irq_wake(dev->irq); 1655 } else { 1656 device_set_wakeup_enable(priv->device, 0); 1657 disable_irq_wake(dev->irq); 1658 } 1659 1660 return 0; 1661 } 1662 1663 static const struct ethtool_ops xgmac_ethtool_ops = { 1664 .get_settings = xgmac_ethtool_getsettings, 1665 .get_link = ethtool_op_get_link, 1666 .get_pauseparam = xgmac_get_pauseparam, 1667 .set_pauseparam = xgmac_set_pauseparam, 1668 .get_ethtool_stats = xgmac_get_ethtool_stats, 1669 .get_strings = xgmac_get_strings, 1670 .get_wol = xgmac_get_wol, 1671 .set_wol = xgmac_set_wol, 1672 .get_sset_count = xgmac_get_sset_count, 1673 }; 1674 1675 /** 1676 * xgmac_probe 1677 * @pdev: platform device pointer 1678 * Description: the driver is initialized through platform_device. 1679 */ 1680 static int xgmac_probe(struct platform_device *pdev) 1681 { 1682 int ret = 0; 1683 struct resource *res; 1684 struct net_device *ndev = NULL; 1685 struct xgmac_priv *priv = NULL; 1686 u32 uid; 1687 1688 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1689 if (!res) 1690 return -ENODEV; 1691 1692 if (!request_mem_region(res->start, resource_size(res), pdev->name)) 1693 return -EBUSY; 1694 1695 ndev = alloc_etherdev(sizeof(struct xgmac_priv)); 1696 if (!ndev) { 1697 ret = -ENOMEM; 1698 goto err_alloc; 1699 } 1700 1701 SET_NETDEV_DEV(ndev, &pdev->dev); 1702 priv = netdev_priv(ndev); 1703 platform_set_drvdata(pdev, ndev); 1704 ether_setup(ndev); 1705 ndev->netdev_ops = &xgmac_netdev_ops; 1706 SET_ETHTOOL_OPS(ndev, &xgmac_ethtool_ops); 1707 spin_lock_init(&priv->stats_lock); 1708 1709 priv->device = &pdev->dev; 1710 priv->dev = ndev; 1711 priv->rx_pause = 1; 1712 priv->tx_pause = 1; 1713 1714 priv->base = ioremap(res->start, resource_size(res)); 1715 if (!priv->base) { 1716 netdev_err(ndev, "ioremap failed\n"); 1717 ret = -ENOMEM; 1718 goto err_io; 1719 } 1720 1721 uid = readl(priv->base + XGMAC_VERSION); 1722 netdev_info(ndev, "h/w version is 0x%x\n", uid); 1723 1724 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 1725 ndev->irq = platform_get_irq(pdev, 0); 1726 if (ndev->irq == -ENXIO) { 1727 netdev_err(ndev, "No irq resource\n"); 1728 ret = ndev->irq; 1729 goto err_irq; 1730 } 1731 1732 ret = request_irq(ndev->irq, xgmac_interrupt, 0, 1733 dev_name(&pdev->dev), ndev); 1734 if (ret < 0) { 1735 netdev_err(ndev, "Could not request irq %d - ret %d)\n", 1736 ndev->irq, ret); 1737 goto err_irq; 1738 } 1739 1740 priv->pmt_irq = platform_get_irq(pdev, 1); 1741 if (priv->pmt_irq == -ENXIO) { 1742 netdev_err(ndev, "No pmt irq resource\n"); 1743 ret = priv->pmt_irq; 1744 goto err_pmt_irq; 1745 } 1746 1747 ret = request_irq(priv->pmt_irq, xgmac_pmt_interrupt, 0, 1748 dev_name(&pdev->dev), ndev); 1749 if (ret < 0) { 1750 netdev_err(ndev, "Could not request irq %d - ret %d)\n", 1751 priv->pmt_irq, ret); 1752 goto err_pmt_irq; 1753 } 1754 1755 device_set_wakeup_capable(&pdev->dev, 1); 1756 if (device_can_wakeup(priv->device)) 1757 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */ 1758 1759 ndev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA; 1760 if (readl(priv->base + XGMAC_DMA_HW_FEATURE) & DMA_HW_FEAT_TXCOESEL) 1761 ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1762 NETIF_F_RXCSUM; 1763 ndev->features |= ndev->hw_features; 1764 ndev->priv_flags |= IFF_UNICAST_FLT; 1765 1766 /* Get the MAC address */ 1767 xgmac_get_mac_addr(priv->base, ndev->dev_addr, 0); 1768 if (!is_valid_ether_addr(ndev->dev_addr)) 1769 netdev_warn(ndev, "MAC address %pM not valid", 1770 ndev->dev_addr); 1771 1772 netif_napi_add(ndev, &priv->napi, xgmac_poll, 64); 1773 ret = register_netdev(ndev); 1774 if (ret) 1775 goto err_reg; 1776 1777 return 0; 1778 1779 err_reg: 1780 netif_napi_del(&priv->napi); 1781 free_irq(priv->pmt_irq, ndev); 1782 err_pmt_irq: 1783 free_irq(ndev->irq, ndev); 1784 err_irq: 1785 iounmap(priv->base); 1786 err_io: 1787 free_netdev(ndev); 1788 err_alloc: 1789 release_mem_region(res->start, resource_size(res)); 1790 platform_set_drvdata(pdev, NULL); 1791 return ret; 1792 } 1793 1794 /** 1795 * xgmac_dvr_remove 1796 * @pdev: platform device pointer 1797 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 1798 * changes the link status, releases the DMA descriptor rings, 1799 * unregisters the MDIO bus and unmaps the allocated memory. 1800 */ 1801 static int xgmac_remove(struct platform_device *pdev) 1802 { 1803 struct net_device *ndev = platform_get_drvdata(pdev); 1804 struct xgmac_priv *priv = netdev_priv(ndev); 1805 struct resource *res; 1806 1807 xgmac_mac_disable(priv->base); 1808 1809 /* Free the IRQ lines */ 1810 free_irq(ndev->irq, ndev); 1811 free_irq(priv->pmt_irq, ndev); 1812 1813 platform_set_drvdata(pdev, NULL); 1814 unregister_netdev(ndev); 1815 netif_napi_del(&priv->napi); 1816 1817 iounmap(priv->base); 1818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1819 release_mem_region(res->start, resource_size(res)); 1820 1821 free_netdev(ndev); 1822 1823 return 0; 1824 } 1825 1826 #ifdef CONFIG_PM_SLEEP 1827 static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode) 1828 { 1829 unsigned int pmt = 0; 1830 1831 if (mode & WAKE_MAGIC) 1832 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT; 1833 if (mode & WAKE_UCAST) 1834 pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST; 1835 1836 writel(pmt, ioaddr + XGMAC_PMT); 1837 } 1838 1839 static int xgmac_suspend(struct device *dev) 1840 { 1841 struct net_device *ndev = platform_get_drvdata(to_platform_device(dev)); 1842 struct xgmac_priv *priv = netdev_priv(ndev); 1843 u32 value; 1844 1845 if (!ndev || !netif_running(ndev)) 1846 return 0; 1847 1848 netif_device_detach(ndev); 1849 napi_disable(&priv->napi); 1850 writel(0, priv->base + XGMAC_DMA_INTR_ENA); 1851 1852 if (device_may_wakeup(priv->device)) { 1853 /* Stop TX/RX DMA Only */ 1854 value = readl(priv->base + XGMAC_DMA_CONTROL); 1855 value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR); 1856 writel(value, priv->base + XGMAC_DMA_CONTROL); 1857 1858 xgmac_pmt(priv->base, priv->wolopts); 1859 } else 1860 xgmac_mac_disable(priv->base); 1861 1862 return 0; 1863 } 1864 1865 static int xgmac_resume(struct device *dev) 1866 { 1867 struct net_device *ndev = platform_get_drvdata(to_platform_device(dev)); 1868 struct xgmac_priv *priv = netdev_priv(ndev); 1869 void __iomem *ioaddr = priv->base; 1870 1871 if (!netif_running(ndev)) 1872 return 0; 1873 1874 xgmac_pmt(ioaddr, 0); 1875 1876 /* Enable the MAC and DMA */ 1877 xgmac_mac_enable(ioaddr); 1878 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS); 1879 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); 1880 1881 netif_device_attach(ndev); 1882 napi_enable(&priv->napi); 1883 1884 return 0; 1885 } 1886 1887 static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume); 1888 #define XGMAC_PM_OPS (&xgmac_pm_ops) 1889 #else 1890 #define XGMAC_PM_OPS NULL 1891 #endif /* CONFIG_PM_SLEEP */ 1892 1893 static const struct of_device_id xgmac_of_match[] = { 1894 { .compatible = "calxeda,hb-xgmac", }, 1895 {}, 1896 }; 1897 MODULE_DEVICE_TABLE(of, xgmac_of_match); 1898 1899 static struct platform_driver xgmac_driver = { 1900 .driver = { 1901 .name = "calxedaxgmac", 1902 .of_match_table = xgmac_of_match, 1903 }, 1904 .probe = xgmac_probe, 1905 .remove = xgmac_remove, 1906 .driver.pm = XGMAC_PM_OPS, 1907 }; 1908 1909 module_platform_driver(xgmac_driver); 1910 1911 MODULE_AUTHOR("Calxeda, Inc."); 1912 MODULE_DESCRIPTION("Calxeda 10G XGMAC driver"); 1913 MODULE_LICENSE("GPL v2"); 1914