1 /*
2  * Cadence MACB/GEM Ethernet Controller driver
3  *
4  * Copyright (C) 2004-2006 Atmel Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/etherdevice.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_data/macb.h>
28 #include <linux/platform_device.h>
29 #include <linux/phy.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
35 #include <linux/ip.h>
36 #include <linux/udp.h>
37 #include <linux/tcp.h>
38 #include "macb.h"
39 
40 #define MACB_RX_BUFFER_SIZE	128
41 #define RX_BUFFER_MULTIPLE	64  /* bytes */
42 
43 #define DEFAULT_RX_RING_SIZE	512 /* must be power of 2 */
44 #define MIN_RX_RING_SIZE	64
45 #define MAX_RX_RING_SIZE	8192
46 #define RX_RING_BYTES(bp)	(macb_dma_desc_get_size(bp)	\
47 				 * (bp)->rx_ring_size)
48 
49 #define DEFAULT_TX_RING_SIZE	512 /* must be power of 2 */
50 #define MIN_TX_RING_SIZE	64
51 #define MAX_TX_RING_SIZE	4096
52 #define TX_RING_BYTES(bp)	(macb_dma_desc_get_size(bp)	\
53 				 * (bp)->tx_ring_size)
54 
55 /* level of occupied TX descriptors under which we wake up TX process */
56 #define MACB_TX_WAKEUP_THRESH(bp)	(3 * (bp)->tx_ring_size / 4)
57 
58 #define MACB_RX_INT_FLAGS	(MACB_BIT(RCOMP) | MACB_BIT(RXUBR)	\
59 				 | MACB_BIT(ISR_ROVR))
60 #define MACB_TX_ERR_FLAGS	(MACB_BIT(ISR_TUND)			\
61 					| MACB_BIT(ISR_RLE)		\
62 					| MACB_BIT(TXERR))
63 #define MACB_TX_INT_FLAGS	(MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
64 
65 /* Max length of transmit frame must be a multiple of 8 bytes */
66 #define MACB_TX_LEN_ALIGN	8
67 #define MACB_MAX_TX_LEN		((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
68 #define GEM_MAX_TX_LEN		((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
69 
70 #define GEM_MTU_MIN_SIZE	ETH_MIN_MTU
71 #define MACB_NETIF_LSO		NETIF_F_TSO
72 
73 #define MACB_WOL_HAS_MAGIC_PACKET	(0x1 << 0)
74 #define MACB_WOL_ENABLED		(0x1 << 1)
75 
76 /* Graceful stop timeouts in us. We should allow up to
77  * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
78  */
79 #define MACB_HALT_TIMEOUT	1230
80 
81 /* DMA buffer descriptor might be different size
82  * depends on hardware configuration:
83  *
84  * 1. dma address width 32 bits:
85  *    word 1: 32 bit address of Data Buffer
86  *    word 2: control
87  *
88  * 2. dma address width 64 bits:
89  *    word 1: 32 bit address of Data Buffer
90  *    word 2: control
91  *    word 3: upper 32 bit address of Data Buffer
92  *    word 4: unused
93  *
94  * 3. dma address width 32 bits with hardware timestamping:
95  *    word 1: 32 bit address of Data Buffer
96  *    word 2: control
97  *    word 3: timestamp word 1
98  *    word 4: timestamp word 2
99  *
100  * 4. dma address width 64 bits with hardware timestamping:
101  *    word 1: 32 bit address of Data Buffer
102  *    word 2: control
103  *    word 3: upper 32 bit address of Data Buffer
104  *    word 4: unused
105  *    word 5: timestamp word 1
106  *    word 6: timestamp word 2
107  */
108 static unsigned int macb_dma_desc_get_size(struct macb *bp)
109 {
110 #ifdef MACB_EXT_DESC
111 	unsigned int desc_size;
112 
113 	switch (bp->hw_dma_cap) {
114 	case HW_DMA_CAP_64B:
115 		desc_size = sizeof(struct macb_dma_desc)
116 			+ sizeof(struct macb_dma_desc_64);
117 		break;
118 	case HW_DMA_CAP_PTP:
119 		desc_size = sizeof(struct macb_dma_desc)
120 			+ sizeof(struct macb_dma_desc_ptp);
121 		break;
122 	case HW_DMA_CAP_64B_PTP:
123 		desc_size = sizeof(struct macb_dma_desc)
124 			+ sizeof(struct macb_dma_desc_64)
125 			+ sizeof(struct macb_dma_desc_ptp);
126 		break;
127 	default:
128 		desc_size = sizeof(struct macb_dma_desc);
129 	}
130 	return desc_size;
131 #endif
132 	return sizeof(struct macb_dma_desc);
133 }
134 
135 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
136 {
137 #ifdef MACB_EXT_DESC
138 	switch (bp->hw_dma_cap) {
139 	case HW_DMA_CAP_64B:
140 	case HW_DMA_CAP_PTP:
141 		desc_idx <<= 1;
142 		break;
143 	case HW_DMA_CAP_64B_PTP:
144 		desc_idx *= 3;
145 		break;
146 	default:
147 		break;
148 	}
149 #endif
150 	return desc_idx;
151 }
152 
153 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
154 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
155 {
156 	if (bp->hw_dma_cap & HW_DMA_CAP_64B)
157 		return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc));
158 	return NULL;
159 }
160 #endif
161 
162 /* Ring buffer accessors */
163 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
164 {
165 	return index & (bp->tx_ring_size - 1);
166 }
167 
168 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
169 					  unsigned int index)
170 {
171 	index = macb_tx_ring_wrap(queue->bp, index);
172 	index = macb_adj_dma_desc_idx(queue->bp, index);
173 	return &queue->tx_ring[index];
174 }
175 
176 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
177 				       unsigned int index)
178 {
179 	return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
180 }
181 
182 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
183 {
184 	dma_addr_t offset;
185 
186 	offset = macb_tx_ring_wrap(queue->bp, index) *
187 			macb_dma_desc_get_size(queue->bp);
188 
189 	return queue->tx_ring_dma + offset;
190 }
191 
192 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
193 {
194 	return index & (bp->rx_ring_size - 1);
195 }
196 
197 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
198 {
199 	index = macb_rx_ring_wrap(bp, index);
200 	index = macb_adj_dma_desc_idx(bp, index);
201 	return &bp->rx_ring[index];
202 }
203 
204 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
205 {
206 	return bp->rx_buffers + bp->rx_buffer_size *
207 	       macb_rx_ring_wrap(bp, index);
208 }
209 
210 /* I/O accessors */
211 static u32 hw_readl_native(struct macb *bp, int offset)
212 {
213 	return __raw_readl(bp->regs + offset);
214 }
215 
216 static void hw_writel_native(struct macb *bp, int offset, u32 value)
217 {
218 	__raw_writel(value, bp->regs + offset);
219 }
220 
221 static u32 hw_readl(struct macb *bp, int offset)
222 {
223 	return readl_relaxed(bp->regs + offset);
224 }
225 
226 static void hw_writel(struct macb *bp, int offset, u32 value)
227 {
228 	writel_relaxed(value, bp->regs + offset);
229 }
230 
231 /* Find the CPU endianness by using the loopback bit of NCR register. When the
232  * CPU is in big endian we need to program swapped mode for management
233  * descriptor access.
234  */
235 static bool hw_is_native_io(void __iomem *addr)
236 {
237 	u32 value = MACB_BIT(LLB);
238 
239 	__raw_writel(value, addr + MACB_NCR);
240 	value = __raw_readl(addr + MACB_NCR);
241 
242 	/* Write 0 back to disable everything */
243 	__raw_writel(0, addr + MACB_NCR);
244 
245 	return value == MACB_BIT(LLB);
246 }
247 
248 static bool hw_is_gem(void __iomem *addr, bool native_io)
249 {
250 	u32 id;
251 
252 	if (native_io)
253 		id = __raw_readl(addr + MACB_MID);
254 	else
255 		id = readl_relaxed(addr + MACB_MID);
256 
257 	return MACB_BFEXT(IDNUM, id) >= 0x2;
258 }
259 
260 static void macb_set_hwaddr(struct macb *bp)
261 {
262 	u32 bottom;
263 	u16 top;
264 
265 	bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
266 	macb_or_gem_writel(bp, SA1B, bottom);
267 	top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
268 	macb_or_gem_writel(bp, SA1T, top);
269 
270 	/* Clear unused address register sets */
271 	macb_or_gem_writel(bp, SA2B, 0);
272 	macb_or_gem_writel(bp, SA2T, 0);
273 	macb_or_gem_writel(bp, SA3B, 0);
274 	macb_or_gem_writel(bp, SA3T, 0);
275 	macb_or_gem_writel(bp, SA4B, 0);
276 	macb_or_gem_writel(bp, SA4T, 0);
277 }
278 
279 static void macb_get_hwaddr(struct macb *bp)
280 {
281 	struct macb_platform_data *pdata;
282 	u32 bottom;
283 	u16 top;
284 	u8 addr[6];
285 	int i;
286 
287 	pdata = dev_get_platdata(&bp->pdev->dev);
288 
289 	/* Check all 4 address register for valid address */
290 	for (i = 0; i < 4; i++) {
291 		bottom = macb_or_gem_readl(bp, SA1B + i * 8);
292 		top = macb_or_gem_readl(bp, SA1T + i * 8);
293 
294 		if (pdata && pdata->rev_eth_addr) {
295 			addr[5] = bottom & 0xff;
296 			addr[4] = (bottom >> 8) & 0xff;
297 			addr[3] = (bottom >> 16) & 0xff;
298 			addr[2] = (bottom >> 24) & 0xff;
299 			addr[1] = top & 0xff;
300 			addr[0] = (top & 0xff00) >> 8;
301 		} else {
302 			addr[0] = bottom & 0xff;
303 			addr[1] = (bottom >> 8) & 0xff;
304 			addr[2] = (bottom >> 16) & 0xff;
305 			addr[3] = (bottom >> 24) & 0xff;
306 			addr[4] = top & 0xff;
307 			addr[5] = (top >> 8) & 0xff;
308 		}
309 
310 		if (is_valid_ether_addr(addr)) {
311 			memcpy(bp->dev->dev_addr, addr, sizeof(addr));
312 			return;
313 		}
314 	}
315 
316 	dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
317 	eth_hw_addr_random(bp->dev);
318 }
319 
320 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
321 {
322 	struct macb *bp = bus->priv;
323 	int value;
324 
325 	macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
326 			      | MACB_BF(RW, MACB_MAN_READ)
327 			      | MACB_BF(PHYA, mii_id)
328 			      | MACB_BF(REGA, regnum)
329 			      | MACB_BF(CODE, MACB_MAN_CODE)));
330 
331 	/* wait for end of transfer */
332 	while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
333 		cpu_relax();
334 
335 	value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
336 
337 	return value;
338 }
339 
340 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
341 			   u16 value)
342 {
343 	struct macb *bp = bus->priv;
344 
345 	macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
346 			      | MACB_BF(RW, MACB_MAN_WRITE)
347 			      | MACB_BF(PHYA, mii_id)
348 			      | MACB_BF(REGA, regnum)
349 			      | MACB_BF(CODE, MACB_MAN_CODE)
350 			      | MACB_BF(DATA, value)));
351 
352 	/* wait for end of transfer */
353 	while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
354 		cpu_relax();
355 
356 	return 0;
357 }
358 
359 /**
360  * macb_set_tx_clk() - Set a clock to a new frequency
361  * @clk		Pointer to the clock to change
362  * @rate	New frequency in Hz
363  * @dev		Pointer to the struct net_device
364  */
365 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
366 {
367 	long ferr, rate, rate_rounded;
368 
369 	if (!clk)
370 		return;
371 
372 	switch (speed) {
373 	case SPEED_10:
374 		rate = 2500000;
375 		break;
376 	case SPEED_100:
377 		rate = 25000000;
378 		break;
379 	case SPEED_1000:
380 		rate = 125000000;
381 		break;
382 	default:
383 		return;
384 	}
385 
386 	rate_rounded = clk_round_rate(clk, rate);
387 	if (rate_rounded < 0)
388 		return;
389 
390 	/* RGMII allows 50 ppm frequency error. Test and warn if this limit
391 	 * is not satisfied.
392 	 */
393 	ferr = abs(rate_rounded - rate);
394 	ferr = DIV_ROUND_UP(ferr, rate / 100000);
395 	if (ferr > 5)
396 		netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
397 			    rate);
398 
399 	if (clk_set_rate(clk, rate_rounded))
400 		netdev_err(dev, "adjusting tx_clk failed.\n");
401 }
402 
403 static void macb_handle_link_change(struct net_device *dev)
404 {
405 	struct macb *bp = netdev_priv(dev);
406 	struct phy_device *phydev = dev->phydev;
407 	unsigned long flags;
408 	int status_change = 0;
409 
410 	spin_lock_irqsave(&bp->lock, flags);
411 
412 	if (phydev->link) {
413 		if ((bp->speed != phydev->speed) ||
414 		    (bp->duplex != phydev->duplex)) {
415 			u32 reg;
416 
417 			reg = macb_readl(bp, NCFGR);
418 			reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
419 			if (macb_is_gem(bp))
420 				reg &= ~GEM_BIT(GBE);
421 
422 			if (phydev->duplex)
423 				reg |= MACB_BIT(FD);
424 			if (phydev->speed == SPEED_100)
425 				reg |= MACB_BIT(SPD);
426 			if (phydev->speed == SPEED_1000 &&
427 			    bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
428 				reg |= GEM_BIT(GBE);
429 
430 			macb_or_gem_writel(bp, NCFGR, reg);
431 
432 			bp->speed = phydev->speed;
433 			bp->duplex = phydev->duplex;
434 			status_change = 1;
435 		}
436 	}
437 
438 	if (phydev->link != bp->link) {
439 		if (!phydev->link) {
440 			bp->speed = 0;
441 			bp->duplex = -1;
442 		}
443 		bp->link = phydev->link;
444 
445 		status_change = 1;
446 	}
447 
448 	spin_unlock_irqrestore(&bp->lock, flags);
449 
450 	if (status_change) {
451 		if (phydev->link) {
452 			/* Update the TX clock rate if and only if the link is
453 			 * up and there has been a link change.
454 			 */
455 			macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
456 
457 			netif_carrier_on(dev);
458 			netdev_info(dev, "link up (%d/%s)\n",
459 				    phydev->speed,
460 				    phydev->duplex == DUPLEX_FULL ?
461 				    "Full" : "Half");
462 		} else {
463 			netif_carrier_off(dev);
464 			netdev_info(dev, "link down\n");
465 		}
466 	}
467 }
468 
469 /* based on au1000_eth. c*/
470 static int macb_mii_probe(struct net_device *dev)
471 {
472 	struct macb *bp = netdev_priv(dev);
473 	struct macb_platform_data *pdata;
474 	struct phy_device *phydev;
475 	int phy_irq;
476 	int ret;
477 
478 	if (bp->phy_node) {
479 		phydev = of_phy_connect(dev, bp->phy_node,
480 					&macb_handle_link_change, 0,
481 					bp->phy_interface);
482 		if (!phydev)
483 			return -ENODEV;
484 	} else {
485 		phydev = phy_find_first(bp->mii_bus);
486 		if (!phydev) {
487 			netdev_err(dev, "no PHY found\n");
488 			return -ENXIO;
489 		}
490 
491 		pdata = dev_get_platdata(&bp->pdev->dev);
492 		if (pdata) {
493 			if (gpio_is_valid(pdata->phy_irq_pin)) {
494 				ret = devm_gpio_request(&bp->pdev->dev,
495 							pdata->phy_irq_pin, "phy int");
496 				if (!ret) {
497 					phy_irq = gpio_to_irq(pdata->phy_irq_pin);
498 					phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
499 				}
500 			} else {
501 				phydev->irq = PHY_POLL;
502 			}
503 		}
504 
505 		/* attach the mac to the phy */
506 		ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
507 					 bp->phy_interface);
508 		if (ret) {
509 			netdev_err(dev, "Could not attach to PHY\n");
510 			return ret;
511 		}
512 	}
513 
514 	/* mask with MAC supported features */
515 	if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
516 		phydev->supported &= PHY_GBIT_FEATURES;
517 	else
518 		phydev->supported &= PHY_BASIC_FEATURES;
519 
520 	if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
521 		phydev->supported &= ~SUPPORTED_1000baseT_Half;
522 
523 	phydev->advertising = phydev->supported;
524 
525 	bp->link = 0;
526 	bp->speed = 0;
527 	bp->duplex = -1;
528 
529 	return 0;
530 }
531 
532 static int macb_mii_init(struct macb *bp)
533 {
534 	struct macb_platform_data *pdata;
535 	struct device_node *np;
536 	int err = -ENXIO, i;
537 
538 	/* Enable management port */
539 	macb_writel(bp, NCR, MACB_BIT(MPE));
540 
541 	bp->mii_bus = mdiobus_alloc();
542 	if (!bp->mii_bus) {
543 		err = -ENOMEM;
544 		goto err_out;
545 	}
546 
547 	bp->mii_bus->name = "MACB_mii_bus";
548 	bp->mii_bus->read = &macb_mdio_read;
549 	bp->mii_bus->write = &macb_mdio_write;
550 	snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
551 		 bp->pdev->name, bp->pdev->id);
552 	bp->mii_bus->priv = bp;
553 	bp->mii_bus->parent = &bp->pdev->dev;
554 	pdata = dev_get_platdata(&bp->pdev->dev);
555 
556 	dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
557 
558 	np = bp->pdev->dev.of_node;
559 	if (np) {
560 		if (of_phy_is_fixed_link(np)) {
561 			if (of_phy_register_fixed_link(np) < 0) {
562 				dev_err(&bp->pdev->dev,
563 					"broken fixed-link specification\n");
564 				goto err_out_unregister_bus;
565 			}
566 			bp->phy_node = of_node_get(np);
567 
568 			err = mdiobus_register(bp->mii_bus);
569 		} else {
570 			/* try dt phy registration */
571 			err = of_mdiobus_register(bp->mii_bus, np);
572 
573 			/* fallback to standard phy registration if no phy were
574 			 * found during dt phy registration
575 			 */
576 			if (!err && !phy_find_first(bp->mii_bus)) {
577 				for (i = 0; i < PHY_MAX_ADDR; i++) {
578 					struct phy_device *phydev;
579 
580 					phydev = mdiobus_scan(bp->mii_bus, i);
581 					if (IS_ERR(phydev) &&
582 					    PTR_ERR(phydev) != -ENODEV) {
583 						err = PTR_ERR(phydev);
584 						break;
585 					}
586 				}
587 
588 				if (err)
589 					goto err_out_unregister_bus;
590 			}
591 		}
592 	} else {
593 		for (i = 0; i < PHY_MAX_ADDR; i++)
594 			bp->mii_bus->irq[i] = PHY_POLL;
595 
596 		if (pdata)
597 			bp->mii_bus->phy_mask = pdata->phy_mask;
598 
599 		err = mdiobus_register(bp->mii_bus);
600 	}
601 
602 	if (err)
603 		goto err_out_free_mdiobus;
604 
605 	err = macb_mii_probe(bp->dev);
606 	if (err)
607 		goto err_out_unregister_bus;
608 
609 	return 0;
610 
611 err_out_unregister_bus:
612 	mdiobus_unregister(bp->mii_bus);
613 err_out_free_mdiobus:
614 	mdiobus_free(bp->mii_bus);
615 err_out:
616 	return err;
617 }
618 
619 static void macb_update_stats(struct macb *bp)
620 {
621 	u32 *p = &bp->hw_stats.macb.rx_pause_frames;
622 	u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
623 	int offset = MACB_PFR;
624 
625 	WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
626 
627 	for (; p < end; p++, offset += 4)
628 		*p += bp->macb_reg_readl(bp, offset);
629 }
630 
631 static int macb_halt_tx(struct macb *bp)
632 {
633 	unsigned long	halt_time, timeout;
634 	u32		status;
635 
636 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
637 
638 	timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
639 	do {
640 		halt_time = jiffies;
641 		status = macb_readl(bp, TSR);
642 		if (!(status & MACB_BIT(TGO)))
643 			return 0;
644 
645 		usleep_range(10, 250);
646 	} while (time_before(halt_time, timeout));
647 
648 	return -ETIMEDOUT;
649 }
650 
651 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
652 {
653 	if (tx_skb->mapping) {
654 		if (tx_skb->mapped_as_page)
655 			dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
656 				       tx_skb->size, DMA_TO_DEVICE);
657 		else
658 			dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
659 					 tx_skb->size, DMA_TO_DEVICE);
660 		tx_skb->mapping = 0;
661 	}
662 
663 	if (tx_skb->skb) {
664 		dev_kfree_skb_any(tx_skb->skb);
665 		tx_skb->skb = NULL;
666 	}
667 }
668 
669 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
670 {
671 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
672 	struct macb_dma_desc_64 *desc_64;
673 
674 	if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
675 		desc_64 = macb_64b_desc(bp, desc);
676 		desc_64->addrh = upper_32_bits(addr);
677 	}
678 #endif
679 	desc->addr = lower_32_bits(addr);
680 }
681 
682 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
683 {
684 	dma_addr_t addr = 0;
685 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
686 	struct macb_dma_desc_64 *desc_64;
687 
688 	if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
689 		desc_64 = macb_64b_desc(bp, desc);
690 		addr = ((u64)(desc_64->addrh) << 32);
691 	}
692 #endif
693 	addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
694 	return addr;
695 }
696 
697 static void macb_tx_error_task(struct work_struct *work)
698 {
699 	struct macb_queue	*queue = container_of(work, struct macb_queue,
700 						      tx_error_task);
701 	struct macb		*bp = queue->bp;
702 	struct macb_tx_skb	*tx_skb;
703 	struct macb_dma_desc	*desc;
704 	struct sk_buff		*skb;
705 	unsigned int		tail;
706 	unsigned long		flags;
707 
708 	netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
709 		    (unsigned int)(queue - bp->queues),
710 		    queue->tx_tail, queue->tx_head);
711 
712 	/* Prevent the queue IRQ handlers from running: each of them may call
713 	 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
714 	 * As explained below, we have to halt the transmission before updating
715 	 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
716 	 * network engine about the macb/gem being halted.
717 	 */
718 	spin_lock_irqsave(&bp->lock, flags);
719 
720 	/* Make sure nobody is trying to queue up new packets */
721 	netif_tx_stop_all_queues(bp->dev);
722 
723 	/* Stop transmission now
724 	 * (in case we have just queued new packets)
725 	 * macb/gem must be halted to write TBQP register
726 	 */
727 	if (macb_halt_tx(bp))
728 		/* Just complain for now, reinitializing TX path can be good */
729 		netdev_err(bp->dev, "BUG: halt tx timed out\n");
730 
731 	/* Treat frames in TX queue including the ones that caused the error.
732 	 * Free transmit buffers in upper layer.
733 	 */
734 	for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
735 		u32	ctrl;
736 
737 		desc = macb_tx_desc(queue, tail);
738 		ctrl = desc->ctrl;
739 		tx_skb = macb_tx_skb(queue, tail);
740 		skb = tx_skb->skb;
741 
742 		if (ctrl & MACB_BIT(TX_USED)) {
743 			/* skb is set for the last buffer of the frame */
744 			while (!skb) {
745 				macb_tx_unmap(bp, tx_skb);
746 				tail++;
747 				tx_skb = macb_tx_skb(queue, tail);
748 				skb = tx_skb->skb;
749 			}
750 
751 			/* ctrl still refers to the first buffer descriptor
752 			 * since it's the only one written back by the hardware
753 			 */
754 			if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
755 				netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
756 					    macb_tx_ring_wrap(bp, tail),
757 					    skb->data);
758 				bp->dev->stats.tx_packets++;
759 				bp->dev->stats.tx_bytes += skb->len;
760 			}
761 		} else {
762 			/* "Buffers exhausted mid-frame" errors may only happen
763 			 * if the driver is buggy, so complain loudly about
764 			 * those. Statistics are updated by hardware.
765 			 */
766 			if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
767 				netdev_err(bp->dev,
768 					   "BUG: TX buffers exhausted mid-frame\n");
769 
770 			desc->ctrl = ctrl | MACB_BIT(TX_USED);
771 		}
772 
773 		macb_tx_unmap(bp, tx_skb);
774 	}
775 
776 	/* Set end of TX queue */
777 	desc = macb_tx_desc(queue, 0);
778 	macb_set_addr(bp, desc, 0);
779 	desc->ctrl = MACB_BIT(TX_USED);
780 
781 	/* Make descriptor updates visible to hardware */
782 	wmb();
783 
784 	/* Reinitialize the TX desc queue */
785 	queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
786 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
787 	if (bp->hw_dma_cap & HW_DMA_CAP_64B)
788 		queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
789 #endif
790 	/* Make TX ring reflect state of hardware */
791 	queue->tx_head = 0;
792 	queue->tx_tail = 0;
793 
794 	/* Housework before enabling TX IRQ */
795 	macb_writel(bp, TSR, macb_readl(bp, TSR));
796 	queue_writel(queue, IER, MACB_TX_INT_FLAGS);
797 
798 	/* Now we are ready to start transmission again */
799 	netif_tx_start_all_queues(bp->dev);
800 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
801 
802 	spin_unlock_irqrestore(&bp->lock, flags);
803 }
804 
805 static void macb_tx_interrupt(struct macb_queue *queue)
806 {
807 	unsigned int tail;
808 	unsigned int head;
809 	u32 status;
810 	struct macb *bp = queue->bp;
811 	u16 queue_index = queue - bp->queues;
812 
813 	status = macb_readl(bp, TSR);
814 	macb_writel(bp, TSR, status);
815 
816 	if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
817 		queue_writel(queue, ISR, MACB_BIT(TCOMP));
818 
819 	netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
820 		    (unsigned long)status);
821 
822 	head = queue->tx_head;
823 	for (tail = queue->tx_tail; tail != head; tail++) {
824 		struct macb_tx_skb	*tx_skb;
825 		struct sk_buff		*skb;
826 		struct macb_dma_desc	*desc;
827 		u32			ctrl;
828 
829 		desc = macb_tx_desc(queue, tail);
830 
831 		/* Make hw descriptor updates visible to CPU */
832 		rmb();
833 
834 		ctrl = desc->ctrl;
835 
836 		/* TX_USED bit is only set by hardware on the very first buffer
837 		 * descriptor of the transmitted frame.
838 		 */
839 		if (!(ctrl & MACB_BIT(TX_USED)))
840 			break;
841 
842 		/* Process all buffers of the current transmitted frame */
843 		for (;; tail++) {
844 			tx_skb = macb_tx_skb(queue, tail);
845 			skb = tx_skb->skb;
846 
847 			/* First, update TX stats if needed */
848 			if (skb) {
849 				if (gem_ptp_do_txstamp(queue, skb, desc) == 0) {
850 					/* skb now belongs to timestamp buffer
851 					 * and will be removed later
852 					 */
853 					tx_skb->skb = NULL;
854 				}
855 				netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
856 					    macb_tx_ring_wrap(bp, tail),
857 					    skb->data);
858 				bp->dev->stats.tx_packets++;
859 				bp->dev->stats.tx_bytes += skb->len;
860 			}
861 
862 			/* Now we can safely release resources */
863 			macb_tx_unmap(bp, tx_skb);
864 
865 			/* skb is set only for the last buffer of the frame.
866 			 * WARNING: at this point skb has been freed by
867 			 * macb_tx_unmap().
868 			 */
869 			if (skb)
870 				break;
871 		}
872 	}
873 
874 	queue->tx_tail = tail;
875 	if (__netif_subqueue_stopped(bp->dev, queue_index) &&
876 	    CIRC_CNT(queue->tx_head, queue->tx_tail,
877 		     bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
878 		netif_wake_subqueue(bp->dev, queue_index);
879 }
880 
881 static void gem_rx_refill(struct macb *bp)
882 {
883 	unsigned int		entry;
884 	struct sk_buff		*skb;
885 	dma_addr_t		paddr;
886 	struct macb_dma_desc *desc;
887 
888 	while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,
889 			  bp->rx_ring_size) > 0) {
890 		entry = macb_rx_ring_wrap(bp, bp->rx_prepared_head);
891 
892 		/* Make hw descriptor updates visible to CPU */
893 		rmb();
894 
895 		bp->rx_prepared_head++;
896 		desc = macb_rx_desc(bp, entry);
897 
898 		if (!bp->rx_skbuff[entry]) {
899 			/* allocate sk_buff for this free entry in ring */
900 			skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
901 			if (unlikely(!skb)) {
902 				netdev_err(bp->dev,
903 					   "Unable to allocate sk_buff\n");
904 				break;
905 			}
906 
907 			/* now fill corresponding descriptor entry */
908 			paddr = dma_map_single(&bp->pdev->dev, skb->data,
909 					       bp->rx_buffer_size,
910 					       DMA_FROM_DEVICE);
911 			if (dma_mapping_error(&bp->pdev->dev, paddr)) {
912 				dev_kfree_skb(skb);
913 				break;
914 			}
915 
916 			bp->rx_skbuff[entry] = skb;
917 
918 			if (entry == bp->rx_ring_size - 1)
919 				paddr |= MACB_BIT(RX_WRAP);
920 			macb_set_addr(bp, desc, paddr);
921 			desc->ctrl = 0;
922 
923 			/* properly align Ethernet header */
924 			skb_reserve(skb, NET_IP_ALIGN);
925 		} else {
926 			desc->addr &= ~MACB_BIT(RX_USED);
927 			desc->ctrl = 0;
928 		}
929 	}
930 
931 	/* Make descriptor updates visible to hardware */
932 	wmb();
933 
934 	netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
935 		    bp->rx_prepared_head, bp->rx_tail);
936 }
937 
938 /* Mark DMA descriptors from begin up to and not including end as unused */
939 static void discard_partial_frame(struct macb *bp, unsigned int begin,
940 				  unsigned int end)
941 {
942 	unsigned int frag;
943 
944 	for (frag = begin; frag != end; frag++) {
945 		struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
946 
947 		desc->addr &= ~MACB_BIT(RX_USED);
948 	}
949 
950 	/* Make descriptor updates visible to hardware */
951 	wmb();
952 
953 	/* When this happens, the hardware stats registers for
954 	 * whatever caused this is updated, so we don't have to record
955 	 * anything.
956 	 */
957 }
958 
959 static int gem_rx(struct macb *bp, int budget)
960 {
961 	unsigned int		len;
962 	unsigned int		entry;
963 	struct sk_buff		*skb;
964 	struct macb_dma_desc	*desc;
965 	int			count = 0;
966 
967 	while (count < budget) {
968 		u32 ctrl;
969 		dma_addr_t addr;
970 		bool rxused;
971 
972 		entry = macb_rx_ring_wrap(bp, bp->rx_tail);
973 		desc = macb_rx_desc(bp, entry);
974 
975 		/* Make hw descriptor updates visible to CPU */
976 		rmb();
977 
978 		rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
979 		addr = macb_get_addr(bp, desc);
980 		ctrl = desc->ctrl;
981 
982 		if (!rxused)
983 			break;
984 
985 		bp->rx_tail++;
986 		count++;
987 
988 		if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
989 			netdev_err(bp->dev,
990 				   "not whole frame pointed by descriptor\n");
991 			bp->dev->stats.rx_dropped++;
992 			break;
993 		}
994 		skb = bp->rx_skbuff[entry];
995 		if (unlikely(!skb)) {
996 			netdev_err(bp->dev,
997 				   "inconsistent Rx descriptor chain\n");
998 			bp->dev->stats.rx_dropped++;
999 			break;
1000 		}
1001 		/* now everything is ready for receiving packet */
1002 		bp->rx_skbuff[entry] = NULL;
1003 		len = ctrl & bp->rx_frm_len_mask;
1004 
1005 		netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1006 
1007 		skb_put(skb, len);
1008 		dma_unmap_single(&bp->pdev->dev, addr,
1009 				 bp->rx_buffer_size, DMA_FROM_DEVICE);
1010 
1011 		skb->protocol = eth_type_trans(skb, bp->dev);
1012 		skb_checksum_none_assert(skb);
1013 		if (bp->dev->features & NETIF_F_RXCSUM &&
1014 		    !(bp->dev->flags & IFF_PROMISC) &&
1015 		    GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1016 			skb->ip_summed = CHECKSUM_UNNECESSARY;
1017 
1018 		bp->dev->stats.rx_packets++;
1019 		bp->dev->stats.rx_bytes += skb->len;
1020 
1021 		gem_ptp_do_rxstamp(bp, skb, desc);
1022 
1023 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1024 		netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1025 			    skb->len, skb->csum);
1026 		print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1027 			       skb_mac_header(skb), 16, true);
1028 		print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1029 			       skb->data, 32, true);
1030 #endif
1031 
1032 		netif_receive_skb(skb);
1033 	}
1034 
1035 	gem_rx_refill(bp);
1036 
1037 	return count;
1038 }
1039 
1040 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
1041 			 unsigned int last_frag)
1042 {
1043 	unsigned int len;
1044 	unsigned int frag;
1045 	unsigned int offset;
1046 	struct sk_buff *skb;
1047 	struct macb_dma_desc *desc;
1048 
1049 	desc = macb_rx_desc(bp, last_frag);
1050 	len = desc->ctrl & bp->rx_frm_len_mask;
1051 
1052 	netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1053 		macb_rx_ring_wrap(bp, first_frag),
1054 		macb_rx_ring_wrap(bp, last_frag), len);
1055 
1056 	/* The ethernet header starts NET_IP_ALIGN bytes into the
1057 	 * first buffer. Since the header is 14 bytes, this makes the
1058 	 * payload word-aligned.
1059 	 *
1060 	 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1061 	 * the two padding bytes into the skb so that we avoid hitting
1062 	 * the slowpath in memcpy(), and pull them off afterwards.
1063 	 */
1064 	skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1065 	if (!skb) {
1066 		bp->dev->stats.rx_dropped++;
1067 		for (frag = first_frag; ; frag++) {
1068 			desc = macb_rx_desc(bp, frag);
1069 			desc->addr &= ~MACB_BIT(RX_USED);
1070 			if (frag == last_frag)
1071 				break;
1072 		}
1073 
1074 		/* Make descriptor updates visible to hardware */
1075 		wmb();
1076 
1077 		return 1;
1078 	}
1079 
1080 	offset = 0;
1081 	len += NET_IP_ALIGN;
1082 	skb_checksum_none_assert(skb);
1083 	skb_put(skb, len);
1084 
1085 	for (frag = first_frag; ; frag++) {
1086 		unsigned int frag_len = bp->rx_buffer_size;
1087 
1088 		if (offset + frag_len > len) {
1089 			if (unlikely(frag != last_frag)) {
1090 				dev_kfree_skb_any(skb);
1091 				return -1;
1092 			}
1093 			frag_len = len - offset;
1094 		}
1095 		skb_copy_to_linear_data_offset(skb, offset,
1096 					       macb_rx_buffer(bp, frag),
1097 					       frag_len);
1098 		offset += bp->rx_buffer_size;
1099 		desc = macb_rx_desc(bp, frag);
1100 		desc->addr &= ~MACB_BIT(RX_USED);
1101 
1102 		if (frag == last_frag)
1103 			break;
1104 	}
1105 
1106 	/* Make descriptor updates visible to hardware */
1107 	wmb();
1108 
1109 	__skb_pull(skb, NET_IP_ALIGN);
1110 	skb->protocol = eth_type_trans(skb, bp->dev);
1111 
1112 	bp->dev->stats.rx_packets++;
1113 	bp->dev->stats.rx_bytes += skb->len;
1114 	netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1115 		    skb->len, skb->csum);
1116 	netif_receive_skb(skb);
1117 
1118 	return 0;
1119 }
1120 
1121 static inline void macb_init_rx_ring(struct macb *bp)
1122 {
1123 	dma_addr_t addr;
1124 	struct macb_dma_desc *desc = NULL;
1125 	int i;
1126 
1127 	addr = bp->rx_buffers_dma;
1128 	for (i = 0; i < bp->rx_ring_size; i++) {
1129 		desc = macb_rx_desc(bp, i);
1130 		macb_set_addr(bp, desc, addr);
1131 		desc->ctrl = 0;
1132 		addr += bp->rx_buffer_size;
1133 	}
1134 	desc->addr |= MACB_BIT(RX_WRAP);
1135 	bp->rx_tail = 0;
1136 }
1137 
1138 static int macb_rx(struct macb *bp, int budget)
1139 {
1140 	bool reset_rx_queue = false;
1141 	int received = 0;
1142 	unsigned int tail;
1143 	int first_frag = -1;
1144 
1145 	for (tail = bp->rx_tail; budget > 0; tail++) {
1146 		struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
1147 		u32 ctrl;
1148 
1149 		/* Make hw descriptor updates visible to CPU */
1150 		rmb();
1151 
1152 		ctrl = desc->ctrl;
1153 
1154 		if (!(desc->addr & MACB_BIT(RX_USED)))
1155 			break;
1156 
1157 		if (ctrl & MACB_BIT(RX_SOF)) {
1158 			if (first_frag != -1)
1159 				discard_partial_frame(bp, first_frag, tail);
1160 			first_frag = tail;
1161 		}
1162 
1163 		if (ctrl & MACB_BIT(RX_EOF)) {
1164 			int dropped;
1165 
1166 			if (unlikely(first_frag == -1)) {
1167 				reset_rx_queue = true;
1168 				continue;
1169 			}
1170 
1171 			dropped = macb_rx_frame(bp, first_frag, tail);
1172 			first_frag = -1;
1173 			if (unlikely(dropped < 0)) {
1174 				reset_rx_queue = true;
1175 				continue;
1176 			}
1177 			if (!dropped) {
1178 				received++;
1179 				budget--;
1180 			}
1181 		}
1182 	}
1183 
1184 	if (unlikely(reset_rx_queue)) {
1185 		unsigned long flags;
1186 		u32 ctrl;
1187 
1188 		netdev_err(bp->dev, "RX queue corruption: reset it\n");
1189 
1190 		spin_lock_irqsave(&bp->lock, flags);
1191 
1192 		ctrl = macb_readl(bp, NCR);
1193 		macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1194 
1195 		macb_init_rx_ring(bp);
1196 		macb_writel(bp, RBQP, bp->rx_ring_dma);
1197 
1198 		macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1199 
1200 		spin_unlock_irqrestore(&bp->lock, flags);
1201 		return received;
1202 	}
1203 
1204 	if (first_frag != -1)
1205 		bp->rx_tail = first_frag;
1206 	else
1207 		bp->rx_tail = tail;
1208 
1209 	return received;
1210 }
1211 
1212 static int macb_poll(struct napi_struct *napi, int budget)
1213 {
1214 	struct macb *bp = container_of(napi, struct macb, napi);
1215 	int work_done;
1216 	u32 status;
1217 
1218 	status = macb_readl(bp, RSR);
1219 	macb_writel(bp, RSR, status);
1220 
1221 	work_done = 0;
1222 
1223 	netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1224 		    (unsigned long)status, budget);
1225 
1226 	work_done = bp->macbgem_ops.mog_rx(bp, budget);
1227 	if (work_done < budget) {
1228 		napi_complete_done(napi, work_done);
1229 
1230 		/* Packets received while interrupts were disabled */
1231 		status = macb_readl(bp, RSR);
1232 		if (status) {
1233 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1234 				macb_writel(bp, ISR, MACB_BIT(RCOMP));
1235 			napi_reschedule(napi);
1236 		} else {
1237 			macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1238 		}
1239 	}
1240 
1241 	/* TODO: Handle errors */
1242 
1243 	return work_done;
1244 }
1245 
1246 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1247 {
1248 	struct macb_queue *queue = dev_id;
1249 	struct macb *bp = queue->bp;
1250 	struct net_device *dev = bp->dev;
1251 	u32 status, ctrl;
1252 
1253 	status = queue_readl(queue, ISR);
1254 
1255 	if (unlikely(!status))
1256 		return IRQ_NONE;
1257 
1258 	spin_lock(&bp->lock);
1259 
1260 	while (status) {
1261 		/* close possible race with dev_close */
1262 		if (unlikely(!netif_running(dev))) {
1263 			queue_writel(queue, IDR, -1);
1264 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1265 				queue_writel(queue, ISR, -1);
1266 			break;
1267 		}
1268 
1269 		netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1270 			    (unsigned int)(queue - bp->queues),
1271 			    (unsigned long)status);
1272 
1273 		if (status & MACB_RX_INT_FLAGS) {
1274 			/* There's no point taking any more interrupts
1275 			 * until we have processed the buffers. The
1276 			 * scheduling call may fail if the poll routine
1277 			 * is already scheduled, so disable interrupts
1278 			 * now.
1279 			 */
1280 			queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1281 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1282 				queue_writel(queue, ISR, MACB_BIT(RCOMP));
1283 
1284 			if (napi_schedule_prep(&bp->napi)) {
1285 				netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1286 				__napi_schedule(&bp->napi);
1287 			}
1288 		}
1289 
1290 		if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1291 			queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1292 			schedule_work(&queue->tx_error_task);
1293 
1294 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1295 				queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1296 
1297 			break;
1298 		}
1299 
1300 		if (status & MACB_BIT(TCOMP))
1301 			macb_tx_interrupt(queue);
1302 
1303 		/* Link change detection isn't possible with RMII, so we'll
1304 		 * add that if/when we get our hands on a full-blown MII PHY.
1305 		 */
1306 
1307 		/* There is a hardware issue under heavy load where DMA can
1308 		 * stop, this causes endless "used buffer descriptor read"
1309 		 * interrupts but it can be cleared by re-enabling RX. See
1310 		 * the at91 manual, section 41.3.1 or the Zynq manual
1311 		 * section 16.7.4 for details.
1312 		 */
1313 		if (status & MACB_BIT(RXUBR)) {
1314 			ctrl = macb_readl(bp, NCR);
1315 			macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1316 			wmb();
1317 			macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1318 
1319 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1320 				queue_writel(queue, ISR, MACB_BIT(RXUBR));
1321 		}
1322 
1323 		if (status & MACB_BIT(ISR_ROVR)) {
1324 			/* We missed at least one packet */
1325 			if (macb_is_gem(bp))
1326 				bp->hw_stats.gem.rx_overruns++;
1327 			else
1328 				bp->hw_stats.macb.rx_overruns++;
1329 
1330 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1331 				queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1332 		}
1333 
1334 		if (status & MACB_BIT(HRESP)) {
1335 			/* TODO: Reset the hardware, and maybe move the
1336 			 * netdev_err to a lower-priority context as well
1337 			 * (work queue?)
1338 			 */
1339 			netdev_err(dev, "DMA bus error: HRESP not OK\n");
1340 
1341 			if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1342 				queue_writel(queue, ISR, MACB_BIT(HRESP));
1343 		}
1344 		status = queue_readl(queue, ISR);
1345 	}
1346 
1347 	spin_unlock(&bp->lock);
1348 
1349 	return IRQ_HANDLED;
1350 }
1351 
1352 #ifdef CONFIG_NET_POLL_CONTROLLER
1353 /* Polling receive - used by netconsole and other diagnostic tools
1354  * to allow network i/o with interrupts disabled.
1355  */
1356 static void macb_poll_controller(struct net_device *dev)
1357 {
1358 	struct macb *bp = netdev_priv(dev);
1359 	struct macb_queue *queue;
1360 	unsigned long flags;
1361 	unsigned int q;
1362 
1363 	local_irq_save(flags);
1364 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1365 		macb_interrupt(dev->irq, queue);
1366 	local_irq_restore(flags);
1367 }
1368 #endif
1369 
1370 static unsigned int macb_tx_map(struct macb *bp,
1371 				struct macb_queue *queue,
1372 				struct sk_buff *skb,
1373 				unsigned int hdrlen)
1374 {
1375 	dma_addr_t mapping;
1376 	unsigned int len, entry, i, tx_head = queue->tx_head;
1377 	struct macb_tx_skb *tx_skb = NULL;
1378 	struct macb_dma_desc *desc;
1379 	unsigned int offset, size, count = 0;
1380 	unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1381 	unsigned int eof = 1, mss_mfs = 0;
1382 	u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1383 
1384 	/* LSO */
1385 	if (skb_shinfo(skb)->gso_size != 0) {
1386 		if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1387 			/* UDP - UFO */
1388 			lso_ctrl = MACB_LSO_UFO_ENABLE;
1389 		else
1390 			/* TCP - TSO */
1391 			lso_ctrl = MACB_LSO_TSO_ENABLE;
1392 	}
1393 
1394 	/* First, map non-paged data */
1395 	len = skb_headlen(skb);
1396 
1397 	/* first buffer length */
1398 	size = hdrlen;
1399 
1400 	offset = 0;
1401 	while (len) {
1402 		entry = macb_tx_ring_wrap(bp, tx_head);
1403 		tx_skb = &queue->tx_skb[entry];
1404 
1405 		mapping = dma_map_single(&bp->pdev->dev,
1406 					 skb->data + offset,
1407 					 size, DMA_TO_DEVICE);
1408 		if (dma_mapping_error(&bp->pdev->dev, mapping))
1409 			goto dma_error;
1410 
1411 		/* Save info to properly release resources */
1412 		tx_skb->skb = NULL;
1413 		tx_skb->mapping = mapping;
1414 		tx_skb->size = size;
1415 		tx_skb->mapped_as_page = false;
1416 
1417 		len -= size;
1418 		offset += size;
1419 		count++;
1420 		tx_head++;
1421 
1422 		size = min(len, bp->max_tx_length);
1423 	}
1424 
1425 	/* Then, map paged data from fragments */
1426 	for (f = 0; f < nr_frags; f++) {
1427 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1428 
1429 		len = skb_frag_size(frag);
1430 		offset = 0;
1431 		while (len) {
1432 			size = min(len, bp->max_tx_length);
1433 			entry = macb_tx_ring_wrap(bp, tx_head);
1434 			tx_skb = &queue->tx_skb[entry];
1435 
1436 			mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1437 						   offset, size, DMA_TO_DEVICE);
1438 			if (dma_mapping_error(&bp->pdev->dev, mapping))
1439 				goto dma_error;
1440 
1441 			/* Save info to properly release resources */
1442 			tx_skb->skb = NULL;
1443 			tx_skb->mapping = mapping;
1444 			tx_skb->size = size;
1445 			tx_skb->mapped_as_page = true;
1446 
1447 			len -= size;
1448 			offset += size;
1449 			count++;
1450 			tx_head++;
1451 		}
1452 	}
1453 
1454 	/* Should never happen */
1455 	if (unlikely(!tx_skb)) {
1456 		netdev_err(bp->dev, "BUG! empty skb!\n");
1457 		return 0;
1458 	}
1459 
1460 	/* This is the last buffer of the frame: save socket buffer */
1461 	tx_skb->skb = skb;
1462 
1463 	/* Update TX ring: update buffer descriptors in reverse order
1464 	 * to avoid race condition
1465 	 */
1466 
1467 	/* Set 'TX_USED' bit in buffer descriptor at tx_head position
1468 	 * to set the end of TX queue
1469 	 */
1470 	i = tx_head;
1471 	entry = macb_tx_ring_wrap(bp, i);
1472 	ctrl = MACB_BIT(TX_USED);
1473 	desc = macb_tx_desc(queue, entry);
1474 	desc->ctrl = ctrl;
1475 
1476 	if (lso_ctrl) {
1477 		if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1478 			/* include header and FCS in value given to h/w */
1479 			mss_mfs = skb_shinfo(skb)->gso_size +
1480 					skb_transport_offset(skb) +
1481 					ETH_FCS_LEN;
1482 		else /* TSO */ {
1483 			mss_mfs = skb_shinfo(skb)->gso_size;
1484 			/* TCP Sequence Number Source Select
1485 			 * can be set only for TSO
1486 			 */
1487 			seq_ctrl = 0;
1488 		}
1489 	}
1490 
1491 	do {
1492 		i--;
1493 		entry = macb_tx_ring_wrap(bp, i);
1494 		tx_skb = &queue->tx_skb[entry];
1495 		desc = macb_tx_desc(queue, entry);
1496 
1497 		ctrl = (u32)tx_skb->size;
1498 		if (eof) {
1499 			ctrl |= MACB_BIT(TX_LAST);
1500 			eof = 0;
1501 		}
1502 		if (unlikely(entry == (bp->tx_ring_size - 1)))
1503 			ctrl |= MACB_BIT(TX_WRAP);
1504 
1505 		/* First descriptor is header descriptor */
1506 		if (i == queue->tx_head) {
1507 			ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1508 			ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1509 		} else
1510 			/* Only set MSS/MFS on payload descriptors
1511 			 * (second or later descriptor)
1512 			 */
1513 			ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1514 
1515 		/* Set TX buffer descriptor */
1516 		macb_set_addr(bp, desc, tx_skb->mapping);
1517 		/* desc->addr must be visible to hardware before clearing
1518 		 * 'TX_USED' bit in desc->ctrl.
1519 		 */
1520 		wmb();
1521 		desc->ctrl = ctrl;
1522 	} while (i != queue->tx_head);
1523 
1524 	queue->tx_head = tx_head;
1525 
1526 	return count;
1527 
1528 dma_error:
1529 	netdev_err(bp->dev, "TX DMA map failed\n");
1530 
1531 	for (i = queue->tx_head; i != tx_head; i++) {
1532 		tx_skb = macb_tx_skb(queue, i);
1533 
1534 		macb_tx_unmap(bp, tx_skb);
1535 	}
1536 
1537 	return 0;
1538 }
1539 
1540 static netdev_features_t macb_features_check(struct sk_buff *skb,
1541 					     struct net_device *dev,
1542 					     netdev_features_t features)
1543 {
1544 	unsigned int nr_frags, f;
1545 	unsigned int hdrlen;
1546 
1547 	/* Validate LSO compatibility */
1548 
1549 	/* there is only one buffer */
1550 	if (!skb_is_nonlinear(skb))
1551 		return features;
1552 
1553 	/* length of header */
1554 	hdrlen = skb_transport_offset(skb);
1555 	if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1556 		hdrlen += tcp_hdrlen(skb);
1557 
1558 	/* For LSO:
1559 	 * When software supplies two or more payload buffers all payload buffers
1560 	 * apart from the last must be a multiple of 8 bytes in size.
1561 	 */
1562 	if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1563 		return features & ~MACB_NETIF_LSO;
1564 
1565 	nr_frags = skb_shinfo(skb)->nr_frags;
1566 	/* No need to check last fragment */
1567 	nr_frags--;
1568 	for (f = 0; f < nr_frags; f++) {
1569 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1570 
1571 		if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1572 			return features & ~MACB_NETIF_LSO;
1573 	}
1574 	return features;
1575 }
1576 
1577 static inline int macb_clear_csum(struct sk_buff *skb)
1578 {
1579 	/* no change for packets without checksum offloading */
1580 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1581 		return 0;
1582 
1583 	/* make sure we can modify the header */
1584 	if (unlikely(skb_cow_head(skb, 0)))
1585 		return -1;
1586 
1587 	/* initialize checksum field
1588 	 * This is required - at least for Zynq, which otherwise calculates
1589 	 * wrong UDP header checksums for UDP packets with UDP data len <=2
1590 	 */
1591 	*(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1592 	return 0;
1593 }
1594 
1595 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1596 {
1597 	u16 queue_index = skb_get_queue_mapping(skb);
1598 	struct macb *bp = netdev_priv(dev);
1599 	struct macb_queue *queue = &bp->queues[queue_index];
1600 	unsigned long flags;
1601 	unsigned int desc_cnt, nr_frags, frag_size, f;
1602 	unsigned int hdrlen;
1603 	bool is_lso, is_udp = 0;
1604 
1605 	is_lso = (skb_shinfo(skb)->gso_size != 0);
1606 
1607 	if (is_lso) {
1608 		is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1609 
1610 		/* length of headers */
1611 		if (is_udp)
1612 			/* only queue eth + ip headers separately for UDP */
1613 			hdrlen = skb_transport_offset(skb);
1614 		else
1615 			hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1616 		if (skb_headlen(skb) < hdrlen) {
1617 			netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1618 			/* if this is required, would need to copy to single buffer */
1619 			return NETDEV_TX_BUSY;
1620 		}
1621 	} else
1622 		hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1623 
1624 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1625 	netdev_vdbg(bp->dev,
1626 		    "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1627 		    queue_index, skb->len, skb->head, skb->data,
1628 		    skb_tail_pointer(skb), skb_end_pointer(skb));
1629 	print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1630 		       skb->data, 16, true);
1631 #endif
1632 
1633 	/* Count how many TX buffer descriptors are needed to send this
1634 	 * socket buffer: skb fragments of jumbo frames may need to be
1635 	 * split into many buffer descriptors.
1636 	 */
1637 	if (is_lso && (skb_headlen(skb) > hdrlen))
1638 		/* extra header descriptor if also payload in first buffer */
1639 		desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1640 	else
1641 		desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1642 	nr_frags = skb_shinfo(skb)->nr_frags;
1643 	for (f = 0; f < nr_frags; f++) {
1644 		frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1645 		desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1646 	}
1647 
1648 	spin_lock_irqsave(&bp->lock, flags);
1649 
1650 	/* This is a hard error, log it. */
1651 	if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1652 		       bp->tx_ring_size) < desc_cnt) {
1653 		netif_stop_subqueue(dev, queue_index);
1654 		spin_unlock_irqrestore(&bp->lock, flags);
1655 		netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1656 			   queue->tx_head, queue->tx_tail);
1657 		return NETDEV_TX_BUSY;
1658 	}
1659 
1660 	if (macb_clear_csum(skb)) {
1661 		dev_kfree_skb_any(skb);
1662 		goto unlock;
1663 	}
1664 
1665 	/* Map socket buffer for DMA transfer */
1666 	if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1667 		dev_kfree_skb_any(skb);
1668 		goto unlock;
1669 	}
1670 
1671 	/* Make newly initialized descriptor visible to hardware */
1672 	wmb();
1673 	skb_tx_timestamp(skb);
1674 
1675 	macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1676 
1677 	if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1678 		netif_stop_subqueue(dev, queue_index);
1679 
1680 unlock:
1681 	spin_unlock_irqrestore(&bp->lock, flags);
1682 
1683 	return NETDEV_TX_OK;
1684 }
1685 
1686 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1687 {
1688 	if (!macb_is_gem(bp)) {
1689 		bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1690 	} else {
1691 		bp->rx_buffer_size = size;
1692 
1693 		if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1694 			netdev_dbg(bp->dev,
1695 				   "RX buffer must be multiple of %d bytes, expanding\n",
1696 				   RX_BUFFER_MULTIPLE);
1697 			bp->rx_buffer_size =
1698 				roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1699 		}
1700 	}
1701 
1702 	netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1703 		   bp->dev->mtu, bp->rx_buffer_size);
1704 }
1705 
1706 static void gem_free_rx_buffers(struct macb *bp)
1707 {
1708 	struct sk_buff		*skb;
1709 	struct macb_dma_desc	*desc;
1710 	dma_addr_t		addr;
1711 	int i;
1712 
1713 	if (!bp->rx_skbuff)
1714 		return;
1715 
1716 	for (i = 0; i < bp->rx_ring_size; i++) {
1717 		skb = bp->rx_skbuff[i];
1718 
1719 		if (!skb)
1720 			continue;
1721 
1722 		desc = macb_rx_desc(bp, i);
1723 		addr = macb_get_addr(bp, desc);
1724 
1725 		dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1726 				 DMA_FROM_DEVICE);
1727 		dev_kfree_skb_any(skb);
1728 		skb = NULL;
1729 	}
1730 
1731 	kfree(bp->rx_skbuff);
1732 	bp->rx_skbuff = NULL;
1733 }
1734 
1735 static void macb_free_rx_buffers(struct macb *bp)
1736 {
1737 	if (bp->rx_buffers) {
1738 		dma_free_coherent(&bp->pdev->dev,
1739 				  bp->rx_ring_size * bp->rx_buffer_size,
1740 				  bp->rx_buffers, bp->rx_buffers_dma);
1741 		bp->rx_buffers = NULL;
1742 	}
1743 }
1744 
1745 static void macb_free_consistent(struct macb *bp)
1746 {
1747 	struct macb_queue *queue;
1748 	unsigned int q;
1749 
1750 	bp->macbgem_ops.mog_free_rx_buffers(bp);
1751 	if (bp->rx_ring) {
1752 		dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES(bp),
1753 				  bp->rx_ring, bp->rx_ring_dma);
1754 		bp->rx_ring = NULL;
1755 	}
1756 
1757 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1758 		kfree(queue->tx_skb);
1759 		queue->tx_skb = NULL;
1760 		if (queue->tx_ring) {
1761 			dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES(bp),
1762 					  queue->tx_ring, queue->tx_ring_dma);
1763 			queue->tx_ring = NULL;
1764 		}
1765 	}
1766 }
1767 
1768 static int gem_alloc_rx_buffers(struct macb *bp)
1769 {
1770 	int size;
1771 
1772 	size = bp->rx_ring_size * sizeof(struct sk_buff *);
1773 	bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1774 	if (!bp->rx_skbuff)
1775 		return -ENOMEM;
1776 	else
1777 		netdev_dbg(bp->dev,
1778 			   "Allocated %d RX struct sk_buff entries at %p\n",
1779 			   bp->rx_ring_size, bp->rx_skbuff);
1780 	return 0;
1781 }
1782 
1783 static int macb_alloc_rx_buffers(struct macb *bp)
1784 {
1785 	int size;
1786 
1787 	size = bp->rx_ring_size * bp->rx_buffer_size;
1788 	bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1789 					    &bp->rx_buffers_dma, GFP_KERNEL);
1790 	if (!bp->rx_buffers)
1791 		return -ENOMEM;
1792 
1793 	netdev_dbg(bp->dev,
1794 		   "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1795 		   size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1796 	return 0;
1797 }
1798 
1799 static int macb_alloc_consistent(struct macb *bp)
1800 {
1801 	struct macb_queue *queue;
1802 	unsigned int q;
1803 	int size;
1804 
1805 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1806 		size = TX_RING_BYTES(bp);
1807 		queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1808 						    &queue->tx_ring_dma,
1809 						    GFP_KERNEL);
1810 		if (!queue->tx_ring)
1811 			goto out_err;
1812 		netdev_dbg(bp->dev,
1813 			   "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1814 			   q, size, (unsigned long)queue->tx_ring_dma,
1815 			   queue->tx_ring);
1816 
1817 		size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
1818 		queue->tx_skb = kmalloc(size, GFP_KERNEL);
1819 		if (!queue->tx_skb)
1820 			goto out_err;
1821 	}
1822 
1823 	size = RX_RING_BYTES(bp);
1824 	bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1825 					 &bp->rx_ring_dma, GFP_KERNEL);
1826 	if (!bp->rx_ring)
1827 		goto out_err;
1828 	netdev_dbg(bp->dev,
1829 		   "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1830 		   size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1831 
1832 	if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1833 		goto out_err;
1834 
1835 	return 0;
1836 
1837 out_err:
1838 	macb_free_consistent(bp);
1839 	return -ENOMEM;
1840 }
1841 
1842 static void gem_init_rings(struct macb *bp)
1843 {
1844 	struct macb_queue *queue;
1845 	struct macb_dma_desc *desc = NULL;
1846 	unsigned int q;
1847 	int i;
1848 
1849 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1850 		for (i = 0; i < bp->tx_ring_size; i++) {
1851 			desc = macb_tx_desc(queue, i);
1852 			macb_set_addr(bp, desc, 0);
1853 			desc->ctrl = MACB_BIT(TX_USED);
1854 		}
1855 		desc->ctrl |= MACB_BIT(TX_WRAP);
1856 		queue->tx_head = 0;
1857 		queue->tx_tail = 0;
1858 	}
1859 
1860 	bp->rx_tail = 0;
1861 	bp->rx_prepared_head = 0;
1862 
1863 	gem_rx_refill(bp);
1864 }
1865 
1866 static void macb_init_rings(struct macb *bp)
1867 {
1868 	int i;
1869 	struct macb_dma_desc *desc = NULL;
1870 
1871 	macb_init_rx_ring(bp);
1872 
1873 	for (i = 0; i < bp->tx_ring_size; i++) {
1874 		desc = macb_tx_desc(&bp->queues[0], i);
1875 		macb_set_addr(bp, desc, 0);
1876 		desc->ctrl = MACB_BIT(TX_USED);
1877 	}
1878 	bp->queues[0].tx_head = 0;
1879 	bp->queues[0].tx_tail = 0;
1880 	desc->ctrl |= MACB_BIT(TX_WRAP);
1881 }
1882 
1883 static void macb_reset_hw(struct macb *bp)
1884 {
1885 	struct macb_queue *queue;
1886 	unsigned int q;
1887 
1888 	/* Disable RX and TX (XXX: Should we halt the transmission
1889 	 * more gracefully?)
1890 	 */
1891 	macb_writel(bp, NCR, 0);
1892 
1893 	/* Clear the stats registers (XXX: Update stats first?) */
1894 	macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1895 
1896 	/* Clear all status flags */
1897 	macb_writel(bp, TSR, -1);
1898 	macb_writel(bp, RSR, -1);
1899 
1900 	/* Disable all interrupts */
1901 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1902 		queue_writel(queue, IDR, -1);
1903 		queue_readl(queue, ISR);
1904 		if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1905 			queue_writel(queue, ISR, -1);
1906 	}
1907 }
1908 
1909 static u32 gem_mdc_clk_div(struct macb *bp)
1910 {
1911 	u32 config;
1912 	unsigned long pclk_hz = clk_get_rate(bp->pclk);
1913 
1914 	if (pclk_hz <= 20000000)
1915 		config = GEM_BF(CLK, GEM_CLK_DIV8);
1916 	else if (pclk_hz <= 40000000)
1917 		config = GEM_BF(CLK, GEM_CLK_DIV16);
1918 	else if (pclk_hz <= 80000000)
1919 		config = GEM_BF(CLK, GEM_CLK_DIV32);
1920 	else if (pclk_hz <= 120000000)
1921 		config = GEM_BF(CLK, GEM_CLK_DIV48);
1922 	else if (pclk_hz <= 160000000)
1923 		config = GEM_BF(CLK, GEM_CLK_DIV64);
1924 	else
1925 		config = GEM_BF(CLK, GEM_CLK_DIV96);
1926 
1927 	return config;
1928 }
1929 
1930 static u32 macb_mdc_clk_div(struct macb *bp)
1931 {
1932 	u32 config;
1933 	unsigned long pclk_hz;
1934 
1935 	if (macb_is_gem(bp))
1936 		return gem_mdc_clk_div(bp);
1937 
1938 	pclk_hz = clk_get_rate(bp->pclk);
1939 	if (pclk_hz <= 20000000)
1940 		config = MACB_BF(CLK, MACB_CLK_DIV8);
1941 	else if (pclk_hz <= 40000000)
1942 		config = MACB_BF(CLK, MACB_CLK_DIV16);
1943 	else if (pclk_hz <= 80000000)
1944 		config = MACB_BF(CLK, MACB_CLK_DIV32);
1945 	else
1946 		config = MACB_BF(CLK, MACB_CLK_DIV64);
1947 
1948 	return config;
1949 }
1950 
1951 /* Get the DMA bus width field of the network configuration register that we
1952  * should program.  We find the width from decoding the design configuration
1953  * register to find the maximum supported data bus width.
1954  */
1955 static u32 macb_dbw(struct macb *bp)
1956 {
1957 	if (!macb_is_gem(bp))
1958 		return 0;
1959 
1960 	switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1961 	case 4:
1962 		return GEM_BF(DBW, GEM_DBW128);
1963 	case 2:
1964 		return GEM_BF(DBW, GEM_DBW64);
1965 	case 1:
1966 	default:
1967 		return GEM_BF(DBW, GEM_DBW32);
1968 	}
1969 }
1970 
1971 /* Configure the receive DMA engine
1972  * - use the correct receive buffer size
1973  * - set best burst length for DMA operations
1974  *   (if not supported by FIFO, it will fallback to default)
1975  * - set both rx/tx packet buffers to full memory size
1976  * These are configurable parameters for GEM.
1977  */
1978 static void macb_configure_dma(struct macb *bp)
1979 {
1980 	u32 dmacfg;
1981 
1982 	if (macb_is_gem(bp)) {
1983 		dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1984 		dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1985 		if (bp->dma_burst_length)
1986 			dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1987 		dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1988 		dmacfg &= ~GEM_BIT(ENDIA_PKT);
1989 
1990 		if (bp->native_io)
1991 			dmacfg &= ~GEM_BIT(ENDIA_DESC);
1992 		else
1993 			dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1994 
1995 		if (bp->dev->features & NETIF_F_HW_CSUM)
1996 			dmacfg |= GEM_BIT(TXCOEN);
1997 		else
1998 			dmacfg &= ~GEM_BIT(TXCOEN);
1999 
2000 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2001 		if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2002 			dmacfg |= GEM_BIT(ADDR64);
2003 #endif
2004 #ifdef CONFIG_MACB_USE_HWSTAMP
2005 		if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2006 			dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2007 #endif
2008 		netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2009 			   dmacfg);
2010 		gem_writel(bp, DMACFG, dmacfg);
2011 	}
2012 }
2013 
2014 static void macb_init_hw(struct macb *bp)
2015 {
2016 	struct macb_queue *queue;
2017 	unsigned int q;
2018 
2019 	u32 config;
2020 
2021 	macb_reset_hw(bp);
2022 	macb_set_hwaddr(bp);
2023 
2024 	config = macb_mdc_clk_div(bp);
2025 	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2026 		config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2027 	config |= MACB_BF(RBOF, NET_IP_ALIGN);	/* Make eth data aligned */
2028 	config |= MACB_BIT(PAE);		/* PAuse Enable */
2029 	config |= MACB_BIT(DRFCS);		/* Discard Rx FCS */
2030 	if (bp->caps & MACB_CAPS_JUMBO)
2031 		config |= MACB_BIT(JFRAME);	/* Enable jumbo frames */
2032 	else
2033 		config |= MACB_BIT(BIG);	/* Receive oversized frames */
2034 	if (bp->dev->flags & IFF_PROMISC)
2035 		config |= MACB_BIT(CAF);	/* Copy All Frames */
2036 	else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2037 		config |= GEM_BIT(RXCOEN);
2038 	if (!(bp->dev->flags & IFF_BROADCAST))
2039 		config |= MACB_BIT(NBC);	/* No BroadCast */
2040 	config |= macb_dbw(bp);
2041 	macb_writel(bp, NCFGR, config);
2042 	if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2043 		gem_writel(bp, JML, bp->jumbo_max_len);
2044 	bp->speed = SPEED_10;
2045 	bp->duplex = DUPLEX_HALF;
2046 	bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2047 	if (bp->caps & MACB_CAPS_JUMBO)
2048 		bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2049 
2050 	macb_configure_dma(bp);
2051 
2052 	/* Initialize TX and RX buffers */
2053 	macb_writel(bp, RBQP, lower_32_bits(bp->rx_ring_dma));
2054 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2055 	if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2056 		macb_writel(bp, RBQPH, upper_32_bits(bp->rx_ring_dma));
2057 #endif
2058 	for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2059 		queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
2060 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2061 		if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2062 			queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
2063 #endif
2064 
2065 		/* Enable interrupts */
2066 		queue_writel(queue, IER,
2067 			     MACB_RX_INT_FLAGS |
2068 			     MACB_TX_INT_FLAGS |
2069 			     MACB_BIT(HRESP));
2070 	}
2071 
2072 	/* Enable TX and RX */
2073 	macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
2074 }
2075 
2076 /* The hash address register is 64 bits long and takes up two
2077  * locations in the memory map.  The least significant bits are stored
2078  * in EMAC_HSL and the most significant bits in EMAC_HSH.
2079  *
2080  * The unicast hash enable and the multicast hash enable bits in the
2081  * network configuration register enable the reception of hash matched
2082  * frames. The destination address is reduced to a 6 bit index into
2083  * the 64 bit hash register using the following hash function.  The
2084  * hash function is an exclusive or of every sixth bit of the
2085  * destination address.
2086  *
2087  * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2088  * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2089  * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2090  * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2091  * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2092  * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2093  *
2094  * da[0] represents the least significant bit of the first byte
2095  * received, that is, the multicast/unicast indicator, and da[47]
2096  * represents the most significant bit of the last byte received.  If
2097  * the hash index, hi[n], points to a bit that is set in the hash
2098  * register then the frame will be matched according to whether the
2099  * frame is multicast or unicast.  A multicast match will be signalled
2100  * if the multicast hash enable bit is set, da[0] is 1 and the hash
2101  * index points to a bit set in the hash register.  A unicast match
2102  * will be signalled if the unicast hash enable bit is set, da[0] is 0
2103  * and the hash index points to a bit set in the hash register.  To
2104  * receive all multicast frames, the hash register should be set with
2105  * all ones and the multicast hash enable bit should be set in the
2106  * network configuration register.
2107  */
2108 
2109 static inline int hash_bit_value(int bitnr, __u8 *addr)
2110 {
2111 	if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2112 		return 1;
2113 	return 0;
2114 }
2115 
2116 /* Return the hash index value for the specified address. */
2117 static int hash_get_index(__u8 *addr)
2118 {
2119 	int i, j, bitval;
2120 	int hash_index = 0;
2121 
2122 	for (j = 0; j < 6; j++) {
2123 		for (i = 0, bitval = 0; i < 8; i++)
2124 			bitval ^= hash_bit_value(i * 6 + j, addr);
2125 
2126 		hash_index |= (bitval << j);
2127 	}
2128 
2129 	return hash_index;
2130 }
2131 
2132 /* Add multicast addresses to the internal multicast-hash table. */
2133 static void macb_sethashtable(struct net_device *dev)
2134 {
2135 	struct netdev_hw_addr *ha;
2136 	unsigned long mc_filter[2];
2137 	unsigned int bitnr;
2138 	struct macb *bp = netdev_priv(dev);
2139 
2140 	mc_filter[0] = 0;
2141 	mc_filter[1] = 0;
2142 
2143 	netdev_for_each_mc_addr(ha, dev) {
2144 		bitnr = hash_get_index(ha->addr);
2145 		mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2146 	}
2147 
2148 	macb_or_gem_writel(bp, HRB, mc_filter[0]);
2149 	macb_or_gem_writel(bp, HRT, mc_filter[1]);
2150 }
2151 
2152 /* Enable/Disable promiscuous and multicast modes. */
2153 static void macb_set_rx_mode(struct net_device *dev)
2154 {
2155 	unsigned long cfg;
2156 	struct macb *bp = netdev_priv(dev);
2157 
2158 	cfg = macb_readl(bp, NCFGR);
2159 
2160 	if (dev->flags & IFF_PROMISC) {
2161 		/* Enable promiscuous mode */
2162 		cfg |= MACB_BIT(CAF);
2163 
2164 		/* Disable RX checksum offload */
2165 		if (macb_is_gem(bp))
2166 			cfg &= ~GEM_BIT(RXCOEN);
2167 	} else {
2168 		/* Disable promiscuous mode */
2169 		cfg &= ~MACB_BIT(CAF);
2170 
2171 		/* Enable RX checksum offload only if requested */
2172 		if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2173 			cfg |= GEM_BIT(RXCOEN);
2174 	}
2175 
2176 	if (dev->flags & IFF_ALLMULTI) {
2177 		/* Enable all multicast mode */
2178 		macb_or_gem_writel(bp, HRB, -1);
2179 		macb_or_gem_writel(bp, HRT, -1);
2180 		cfg |= MACB_BIT(NCFGR_MTI);
2181 	} else if (!netdev_mc_empty(dev)) {
2182 		/* Enable specific multicasts */
2183 		macb_sethashtable(dev);
2184 		cfg |= MACB_BIT(NCFGR_MTI);
2185 	} else if (dev->flags & (~IFF_ALLMULTI)) {
2186 		/* Disable all multicast mode */
2187 		macb_or_gem_writel(bp, HRB, 0);
2188 		macb_or_gem_writel(bp, HRT, 0);
2189 		cfg &= ~MACB_BIT(NCFGR_MTI);
2190 	}
2191 
2192 	macb_writel(bp, NCFGR, cfg);
2193 }
2194 
2195 static int macb_open(struct net_device *dev)
2196 {
2197 	struct macb *bp = netdev_priv(dev);
2198 	size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2199 	int err;
2200 
2201 	netdev_dbg(bp->dev, "open\n");
2202 
2203 	/* carrier starts down */
2204 	netif_carrier_off(dev);
2205 
2206 	/* if the phy is not yet register, retry later*/
2207 	if (!dev->phydev)
2208 		return -EAGAIN;
2209 
2210 	/* RX buffers initialization */
2211 	macb_init_rx_buffer_size(bp, bufsz);
2212 
2213 	err = macb_alloc_consistent(bp);
2214 	if (err) {
2215 		netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2216 			   err);
2217 		return err;
2218 	}
2219 
2220 	napi_enable(&bp->napi);
2221 
2222 	bp->macbgem_ops.mog_init_rings(bp);
2223 	macb_init_hw(bp);
2224 
2225 	/* schedule a link state check */
2226 	phy_start(dev->phydev);
2227 
2228 	netif_tx_start_all_queues(dev);
2229 
2230 	if (bp->ptp_info)
2231 		bp->ptp_info->ptp_init(dev);
2232 
2233 	return 0;
2234 }
2235 
2236 static int macb_close(struct net_device *dev)
2237 {
2238 	struct macb *bp = netdev_priv(dev);
2239 	unsigned long flags;
2240 
2241 	netif_tx_stop_all_queues(dev);
2242 	napi_disable(&bp->napi);
2243 
2244 	if (dev->phydev)
2245 		phy_stop(dev->phydev);
2246 
2247 	spin_lock_irqsave(&bp->lock, flags);
2248 	macb_reset_hw(bp);
2249 	netif_carrier_off(dev);
2250 	spin_unlock_irqrestore(&bp->lock, flags);
2251 
2252 	macb_free_consistent(bp);
2253 
2254 	if (bp->ptp_info)
2255 		bp->ptp_info->ptp_remove(dev);
2256 
2257 	return 0;
2258 }
2259 
2260 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2261 {
2262 	if (netif_running(dev))
2263 		return -EBUSY;
2264 
2265 	dev->mtu = new_mtu;
2266 
2267 	return 0;
2268 }
2269 
2270 static void gem_update_stats(struct macb *bp)
2271 {
2272 	unsigned int i;
2273 	u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2274 
2275 	for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2276 		u32 offset = gem_statistics[i].offset;
2277 		u64 val = bp->macb_reg_readl(bp, offset);
2278 
2279 		bp->ethtool_stats[i] += val;
2280 		*p += val;
2281 
2282 		if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2283 			/* Add GEM_OCTTXH, GEM_OCTRXH */
2284 			val = bp->macb_reg_readl(bp, offset + 4);
2285 			bp->ethtool_stats[i] += ((u64)val) << 32;
2286 			*(++p) += val;
2287 		}
2288 	}
2289 }
2290 
2291 static struct net_device_stats *gem_get_stats(struct macb *bp)
2292 {
2293 	struct gem_stats *hwstat = &bp->hw_stats.gem;
2294 	struct net_device_stats *nstat = &bp->dev->stats;
2295 
2296 	gem_update_stats(bp);
2297 
2298 	nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2299 			    hwstat->rx_alignment_errors +
2300 			    hwstat->rx_resource_errors +
2301 			    hwstat->rx_overruns +
2302 			    hwstat->rx_oversize_frames +
2303 			    hwstat->rx_jabbers +
2304 			    hwstat->rx_undersized_frames +
2305 			    hwstat->rx_length_field_frame_errors);
2306 	nstat->tx_errors = (hwstat->tx_late_collisions +
2307 			    hwstat->tx_excessive_collisions +
2308 			    hwstat->tx_underrun +
2309 			    hwstat->tx_carrier_sense_errors);
2310 	nstat->multicast = hwstat->rx_multicast_frames;
2311 	nstat->collisions = (hwstat->tx_single_collision_frames +
2312 			     hwstat->tx_multiple_collision_frames +
2313 			     hwstat->tx_excessive_collisions);
2314 	nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2315 				   hwstat->rx_jabbers +
2316 				   hwstat->rx_undersized_frames +
2317 				   hwstat->rx_length_field_frame_errors);
2318 	nstat->rx_over_errors = hwstat->rx_resource_errors;
2319 	nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2320 	nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2321 	nstat->rx_fifo_errors = hwstat->rx_overruns;
2322 	nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2323 	nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2324 	nstat->tx_fifo_errors = hwstat->tx_underrun;
2325 
2326 	return nstat;
2327 }
2328 
2329 static void gem_get_ethtool_stats(struct net_device *dev,
2330 				  struct ethtool_stats *stats, u64 *data)
2331 {
2332 	struct macb *bp;
2333 
2334 	bp = netdev_priv(dev);
2335 	gem_update_stats(bp);
2336 	memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
2337 }
2338 
2339 static int gem_get_sset_count(struct net_device *dev, int sset)
2340 {
2341 	switch (sset) {
2342 	case ETH_SS_STATS:
2343 		return GEM_STATS_LEN;
2344 	default:
2345 		return -EOPNOTSUPP;
2346 	}
2347 }
2348 
2349 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2350 {
2351 	unsigned int i;
2352 
2353 	switch (sset) {
2354 	case ETH_SS_STATS:
2355 		for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2356 			memcpy(p, gem_statistics[i].stat_string,
2357 			       ETH_GSTRING_LEN);
2358 		break;
2359 	}
2360 }
2361 
2362 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2363 {
2364 	struct macb *bp = netdev_priv(dev);
2365 	struct net_device_stats *nstat = &bp->dev->stats;
2366 	struct macb_stats *hwstat = &bp->hw_stats.macb;
2367 
2368 	if (macb_is_gem(bp))
2369 		return gem_get_stats(bp);
2370 
2371 	/* read stats from hardware */
2372 	macb_update_stats(bp);
2373 
2374 	/* Convert HW stats into netdevice stats */
2375 	nstat->rx_errors = (hwstat->rx_fcs_errors +
2376 			    hwstat->rx_align_errors +
2377 			    hwstat->rx_resource_errors +
2378 			    hwstat->rx_overruns +
2379 			    hwstat->rx_oversize_pkts +
2380 			    hwstat->rx_jabbers +
2381 			    hwstat->rx_undersize_pkts +
2382 			    hwstat->rx_length_mismatch);
2383 	nstat->tx_errors = (hwstat->tx_late_cols +
2384 			    hwstat->tx_excessive_cols +
2385 			    hwstat->tx_underruns +
2386 			    hwstat->tx_carrier_errors +
2387 			    hwstat->sqe_test_errors);
2388 	nstat->collisions = (hwstat->tx_single_cols +
2389 			     hwstat->tx_multiple_cols +
2390 			     hwstat->tx_excessive_cols);
2391 	nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2392 				   hwstat->rx_jabbers +
2393 				   hwstat->rx_undersize_pkts +
2394 				   hwstat->rx_length_mismatch);
2395 	nstat->rx_over_errors = hwstat->rx_resource_errors +
2396 				   hwstat->rx_overruns;
2397 	nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2398 	nstat->rx_frame_errors = hwstat->rx_align_errors;
2399 	nstat->rx_fifo_errors = hwstat->rx_overruns;
2400 	/* XXX: What does "missed" mean? */
2401 	nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2402 	nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2403 	nstat->tx_fifo_errors = hwstat->tx_underruns;
2404 	/* Don't know about heartbeat or window errors... */
2405 
2406 	return nstat;
2407 }
2408 
2409 static int macb_get_regs_len(struct net_device *netdev)
2410 {
2411 	return MACB_GREGS_NBR * sizeof(u32);
2412 }
2413 
2414 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2415 			  void *p)
2416 {
2417 	struct macb *bp = netdev_priv(dev);
2418 	unsigned int tail, head;
2419 	u32 *regs_buff = p;
2420 
2421 	regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2422 			| MACB_GREGS_VERSION;
2423 
2424 	tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2425 	head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2426 
2427 	regs_buff[0]  = macb_readl(bp, NCR);
2428 	regs_buff[1]  = macb_or_gem_readl(bp, NCFGR);
2429 	regs_buff[2]  = macb_readl(bp, NSR);
2430 	regs_buff[3]  = macb_readl(bp, TSR);
2431 	regs_buff[4]  = macb_readl(bp, RBQP);
2432 	regs_buff[5]  = macb_readl(bp, TBQP);
2433 	regs_buff[6]  = macb_readl(bp, RSR);
2434 	regs_buff[7]  = macb_readl(bp, IMR);
2435 
2436 	regs_buff[8]  = tail;
2437 	regs_buff[9]  = head;
2438 	regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2439 	regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2440 
2441 	if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2442 		regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2443 	if (macb_is_gem(bp))
2444 		regs_buff[13] = gem_readl(bp, DMACFG);
2445 }
2446 
2447 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2448 {
2449 	struct macb *bp = netdev_priv(netdev);
2450 
2451 	wol->supported = 0;
2452 	wol->wolopts = 0;
2453 
2454 	if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
2455 		wol->supported = WAKE_MAGIC;
2456 
2457 		if (bp->wol & MACB_WOL_ENABLED)
2458 			wol->wolopts |= WAKE_MAGIC;
2459 	}
2460 }
2461 
2462 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2463 {
2464 	struct macb *bp = netdev_priv(netdev);
2465 
2466 	if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2467 	    (wol->wolopts & ~WAKE_MAGIC))
2468 		return -EOPNOTSUPP;
2469 
2470 	if (wol->wolopts & WAKE_MAGIC)
2471 		bp->wol |= MACB_WOL_ENABLED;
2472 	else
2473 		bp->wol &= ~MACB_WOL_ENABLED;
2474 
2475 	device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2476 
2477 	return 0;
2478 }
2479 
2480 static void macb_get_ringparam(struct net_device *netdev,
2481 			       struct ethtool_ringparam *ring)
2482 {
2483 	struct macb *bp = netdev_priv(netdev);
2484 
2485 	ring->rx_max_pending = MAX_RX_RING_SIZE;
2486 	ring->tx_max_pending = MAX_TX_RING_SIZE;
2487 
2488 	ring->rx_pending = bp->rx_ring_size;
2489 	ring->tx_pending = bp->tx_ring_size;
2490 }
2491 
2492 static int macb_set_ringparam(struct net_device *netdev,
2493 			      struct ethtool_ringparam *ring)
2494 {
2495 	struct macb *bp = netdev_priv(netdev);
2496 	u32 new_rx_size, new_tx_size;
2497 	unsigned int reset = 0;
2498 
2499 	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2500 		return -EINVAL;
2501 
2502 	new_rx_size = clamp_t(u32, ring->rx_pending,
2503 			      MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2504 	new_rx_size = roundup_pow_of_two(new_rx_size);
2505 
2506 	new_tx_size = clamp_t(u32, ring->tx_pending,
2507 			      MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2508 	new_tx_size = roundup_pow_of_two(new_tx_size);
2509 
2510 	if ((new_tx_size == bp->tx_ring_size) &&
2511 	    (new_rx_size == bp->rx_ring_size)) {
2512 		/* nothing to do */
2513 		return 0;
2514 	}
2515 
2516 	if (netif_running(bp->dev)) {
2517 		reset = 1;
2518 		macb_close(bp->dev);
2519 	}
2520 
2521 	bp->rx_ring_size = new_rx_size;
2522 	bp->tx_ring_size = new_tx_size;
2523 
2524 	if (reset)
2525 		macb_open(bp->dev);
2526 
2527 	return 0;
2528 }
2529 
2530 #ifdef CONFIG_MACB_USE_HWSTAMP
2531 static unsigned int gem_get_tsu_rate(struct macb *bp)
2532 {
2533 	struct clk *tsu_clk;
2534 	unsigned int tsu_rate;
2535 
2536 	tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2537 	if (!IS_ERR(tsu_clk))
2538 		tsu_rate = clk_get_rate(tsu_clk);
2539 	/* try pclk instead */
2540 	else if (!IS_ERR(bp->pclk)) {
2541 		tsu_clk = bp->pclk;
2542 		tsu_rate = clk_get_rate(tsu_clk);
2543 	} else
2544 		return -ENOTSUPP;
2545 	return tsu_rate;
2546 }
2547 
2548 static s32 gem_get_ptp_max_adj(void)
2549 {
2550 	return 64000000;
2551 }
2552 
2553 static int gem_get_ts_info(struct net_device *dev,
2554 			   struct ethtool_ts_info *info)
2555 {
2556 	struct macb *bp = netdev_priv(dev);
2557 
2558 	if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2559 		ethtool_op_get_ts_info(dev, info);
2560 		return 0;
2561 	}
2562 
2563 	info->so_timestamping =
2564 		SOF_TIMESTAMPING_TX_SOFTWARE |
2565 		SOF_TIMESTAMPING_RX_SOFTWARE |
2566 		SOF_TIMESTAMPING_SOFTWARE |
2567 		SOF_TIMESTAMPING_TX_HARDWARE |
2568 		SOF_TIMESTAMPING_RX_HARDWARE |
2569 		SOF_TIMESTAMPING_RAW_HARDWARE;
2570 	info->tx_types =
2571 		(1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2572 		(1 << HWTSTAMP_TX_OFF) |
2573 		(1 << HWTSTAMP_TX_ON);
2574 	info->rx_filters =
2575 		(1 << HWTSTAMP_FILTER_NONE) |
2576 		(1 << HWTSTAMP_FILTER_ALL);
2577 
2578 	info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2579 
2580 	return 0;
2581 }
2582 
2583 static struct macb_ptp_info gem_ptp_info = {
2584 	.ptp_init	 = gem_ptp_init,
2585 	.ptp_remove	 = gem_ptp_remove,
2586 	.get_ptp_max_adj = gem_get_ptp_max_adj,
2587 	.get_tsu_rate	 = gem_get_tsu_rate,
2588 	.get_ts_info	 = gem_get_ts_info,
2589 	.get_hwtst	 = gem_get_hwtst,
2590 	.set_hwtst	 = gem_set_hwtst,
2591 };
2592 #endif
2593 
2594 static int macb_get_ts_info(struct net_device *netdev,
2595 			    struct ethtool_ts_info *info)
2596 {
2597 	struct macb *bp = netdev_priv(netdev);
2598 
2599 	if (bp->ptp_info)
2600 		return bp->ptp_info->get_ts_info(netdev, info);
2601 
2602 	return ethtool_op_get_ts_info(netdev, info);
2603 }
2604 
2605 static const struct ethtool_ops macb_ethtool_ops = {
2606 	.get_regs_len		= macb_get_regs_len,
2607 	.get_regs		= macb_get_regs,
2608 	.get_link		= ethtool_op_get_link,
2609 	.get_ts_info		= ethtool_op_get_ts_info,
2610 	.get_wol		= macb_get_wol,
2611 	.set_wol		= macb_set_wol,
2612 	.get_link_ksettings     = phy_ethtool_get_link_ksettings,
2613 	.set_link_ksettings     = phy_ethtool_set_link_ksettings,
2614 	.get_ringparam		= macb_get_ringparam,
2615 	.set_ringparam		= macb_set_ringparam,
2616 };
2617 
2618 static const struct ethtool_ops gem_ethtool_ops = {
2619 	.get_regs_len		= macb_get_regs_len,
2620 	.get_regs		= macb_get_regs,
2621 	.get_link		= ethtool_op_get_link,
2622 	.get_ts_info		= macb_get_ts_info,
2623 	.get_ethtool_stats	= gem_get_ethtool_stats,
2624 	.get_strings		= gem_get_ethtool_strings,
2625 	.get_sset_count		= gem_get_sset_count,
2626 	.get_link_ksettings     = phy_ethtool_get_link_ksettings,
2627 	.set_link_ksettings     = phy_ethtool_set_link_ksettings,
2628 	.get_ringparam		= macb_get_ringparam,
2629 	.set_ringparam		= macb_set_ringparam,
2630 };
2631 
2632 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2633 {
2634 	struct phy_device *phydev = dev->phydev;
2635 	struct macb *bp = netdev_priv(dev);
2636 
2637 	if (!netif_running(dev))
2638 		return -EINVAL;
2639 
2640 	if (!phydev)
2641 		return -ENODEV;
2642 
2643 	if (!bp->ptp_info)
2644 		return phy_mii_ioctl(phydev, rq, cmd);
2645 
2646 	switch (cmd) {
2647 	case SIOCSHWTSTAMP:
2648 		return bp->ptp_info->set_hwtst(dev, rq, cmd);
2649 	case SIOCGHWTSTAMP:
2650 		return bp->ptp_info->get_hwtst(dev, rq);
2651 	default:
2652 		return phy_mii_ioctl(phydev, rq, cmd);
2653 	}
2654 }
2655 
2656 static int macb_set_features(struct net_device *netdev,
2657 			     netdev_features_t features)
2658 {
2659 	struct macb *bp = netdev_priv(netdev);
2660 	netdev_features_t changed = features ^ netdev->features;
2661 
2662 	/* TX checksum offload */
2663 	if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2664 		u32 dmacfg;
2665 
2666 		dmacfg = gem_readl(bp, DMACFG);
2667 		if (features & NETIF_F_HW_CSUM)
2668 			dmacfg |= GEM_BIT(TXCOEN);
2669 		else
2670 			dmacfg &= ~GEM_BIT(TXCOEN);
2671 		gem_writel(bp, DMACFG, dmacfg);
2672 	}
2673 
2674 	/* RX checksum offload */
2675 	if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2676 		u32 netcfg;
2677 
2678 		netcfg = gem_readl(bp, NCFGR);
2679 		if (features & NETIF_F_RXCSUM &&
2680 		    !(netdev->flags & IFF_PROMISC))
2681 			netcfg |= GEM_BIT(RXCOEN);
2682 		else
2683 			netcfg &= ~GEM_BIT(RXCOEN);
2684 		gem_writel(bp, NCFGR, netcfg);
2685 	}
2686 
2687 	return 0;
2688 }
2689 
2690 static const struct net_device_ops macb_netdev_ops = {
2691 	.ndo_open		= macb_open,
2692 	.ndo_stop		= macb_close,
2693 	.ndo_start_xmit		= macb_start_xmit,
2694 	.ndo_set_rx_mode	= macb_set_rx_mode,
2695 	.ndo_get_stats		= macb_get_stats,
2696 	.ndo_do_ioctl		= macb_ioctl,
2697 	.ndo_validate_addr	= eth_validate_addr,
2698 	.ndo_change_mtu		= macb_change_mtu,
2699 	.ndo_set_mac_address	= eth_mac_addr,
2700 #ifdef CONFIG_NET_POLL_CONTROLLER
2701 	.ndo_poll_controller	= macb_poll_controller,
2702 #endif
2703 	.ndo_set_features	= macb_set_features,
2704 	.ndo_features_check	= macb_features_check,
2705 };
2706 
2707 /* Configure peripheral capabilities according to device tree
2708  * and integration options used
2709  */
2710 static void macb_configure_caps(struct macb *bp,
2711 				const struct macb_config *dt_conf)
2712 {
2713 	u32 dcfg;
2714 
2715 	if (dt_conf)
2716 		bp->caps = dt_conf->caps;
2717 
2718 	if (hw_is_gem(bp->regs, bp->native_io)) {
2719 		bp->caps |= MACB_CAPS_MACB_IS_GEM;
2720 
2721 		dcfg = gem_readl(bp, DCFG1);
2722 		if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2723 			bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2724 		dcfg = gem_readl(bp, DCFG2);
2725 		if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2726 			bp->caps |= MACB_CAPS_FIFO_MODE;
2727 #ifdef CONFIG_MACB_USE_HWSTAMP
2728 		if (gem_has_ptp(bp)) {
2729 			if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
2730 				pr_err("GEM doesn't support hardware ptp.\n");
2731 			else {
2732 				bp->hw_dma_cap |= HW_DMA_CAP_PTP;
2733 				bp->ptp_info = &gem_ptp_info;
2734 			}
2735 		}
2736 #endif
2737 	}
2738 
2739 	dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
2740 }
2741 
2742 static void macb_probe_queues(void __iomem *mem,
2743 			      bool native_io,
2744 			      unsigned int *queue_mask,
2745 			      unsigned int *num_queues)
2746 {
2747 	unsigned int hw_q;
2748 
2749 	*queue_mask = 0x1;
2750 	*num_queues = 1;
2751 
2752 	/* is it macb or gem ?
2753 	 *
2754 	 * We need to read directly from the hardware here because
2755 	 * we are early in the probe process and don't have the
2756 	 * MACB_CAPS_MACB_IS_GEM flag positioned
2757 	 */
2758 	if (!hw_is_gem(mem, native_io))
2759 		return;
2760 
2761 	/* bit 0 is never set but queue 0 always exists */
2762 	*queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2763 
2764 	*queue_mask |= 0x1;
2765 
2766 	for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2767 		if (*queue_mask & (1 << hw_q))
2768 			(*num_queues)++;
2769 }
2770 
2771 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2772 			 struct clk **hclk, struct clk **tx_clk,
2773 			 struct clk **rx_clk)
2774 {
2775 	struct macb_platform_data *pdata;
2776 	int err;
2777 
2778 	pdata = dev_get_platdata(&pdev->dev);
2779 	if (pdata) {
2780 		*pclk = pdata->pclk;
2781 		*hclk = pdata->hclk;
2782 	} else {
2783 		*pclk = devm_clk_get(&pdev->dev, "pclk");
2784 		*hclk = devm_clk_get(&pdev->dev, "hclk");
2785 	}
2786 
2787 	if (IS_ERR(*pclk)) {
2788 		err = PTR_ERR(*pclk);
2789 		dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2790 		return err;
2791 	}
2792 
2793 	if (IS_ERR(*hclk)) {
2794 		err = PTR_ERR(*hclk);
2795 		dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2796 		return err;
2797 	}
2798 
2799 	*tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2800 	if (IS_ERR(*tx_clk))
2801 		*tx_clk = NULL;
2802 
2803 	*rx_clk = devm_clk_get(&pdev->dev, "rx_clk");
2804 	if (IS_ERR(*rx_clk))
2805 		*rx_clk = NULL;
2806 
2807 	err = clk_prepare_enable(*pclk);
2808 	if (err) {
2809 		dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2810 		return err;
2811 	}
2812 
2813 	err = clk_prepare_enable(*hclk);
2814 	if (err) {
2815 		dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2816 		goto err_disable_pclk;
2817 	}
2818 
2819 	err = clk_prepare_enable(*tx_clk);
2820 	if (err) {
2821 		dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2822 		goto err_disable_hclk;
2823 	}
2824 
2825 	err = clk_prepare_enable(*rx_clk);
2826 	if (err) {
2827 		dev_err(&pdev->dev, "failed to enable rx_clk (%u)\n", err);
2828 		goto err_disable_txclk;
2829 	}
2830 
2831 	return 0;
2832 
2833 err_disable_txclk:
2834 	clk_disable_unprepare(*tx_clk);
2835 
2836 err_disable_hclk:
2837 	clk_disable_unprepare(*hclk);
2838 
2839 err_disable_pclk:
2840 	clk_disable_unprepare(*pclk);
2841 
2842 	return err;
2843 }
2844 
2845 static int macb_init(struct platform_device *pdev)
2846 {
2847 	struct net_device *dev = platform_get_drvdata(pdev);
2848 	unsigned int hw_q, q;
2849 	struct macb *bp = netdev_priv(dev);
2850 	struct macb_queue *queue;
2851 	int err;
2852 	u32 val;
2853 
2854 	bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
2855 	bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
2856 
2857 	/* set the queue register mapping once for all: queue0 has a special
2858 	 * register mapping but we don't want to test the queue index then
2859 	 * compute the corresponding register offset at run time.
2860 	 */
2861 	for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2862 		if (!(bp->queue_mask & (1 << hw_q)))
2863 			continue;
2864 
2865 		queue = &bp->queues[q];
2866 		queue->bp = bp;
2867 		if (hw_q) {
2868 			queue->ISR  = GEM_ISR(hw_q - 1);
2869 			queue->IER  = GEM_IER(hw_q - 1);
2870 			queue->IDR  = GEM_IDR(hw_q - 1);
2871 			queue->IMR  = GEM_IMR(hw_q - 1);
2872 			queue->TBQP = GEM_TBQP(hw_q - 1);
2873 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2874 			if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2875 				queue->TBQPH = GEM_TBQPH(hw_q - 1);
2876 #endif
2877 		} else {
2878 			/* queue0 uses legacy registers */
2879 			queue->ISR  = MACB_ISR;
2880 			queue->IER  = MACB_IER;
2881 			queue->IDR  = MACB_IDR;
2882 			queue->IMR  = MACB_IMR;
2883 			queue->TBQP = MACB_TBQP;
2884 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2885 			if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2886 				queue->TBQPH = MACB_TBQPH;
2887 #endif
2888 		}
2889 
2890 		/* get irq: here we use the linux queue index, not the hardware
2891 		 * queue index. the queue irq definitions in the device tree
2892 		 * must remove the optional gaps that could exist in the
2893 		 * hardware queue mask.
2894 		 */
2895 		queue->irq = platform_get_irq(pdev, q);
2896 		err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2897 				       IRQF_SHARED, dev->name, queue);
2898 		if (err) {
2899 			dev_err(&pdev->dev,
2900 				"Unable to request IRQ %d (error %d)\n",
2901 				queue->irq, err);
2902 			return err;
2903 		}
2904 
2905 		INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2906 		q++;
2907 	}
2908 
2909 	dev->netdev_ops = &macb_netdev_ops;
2910 	netif_napi_add(dev, &bp->napi, macb_poll, 64);
2911 
2912 	/* setup appropriated routines according to adapter type */
2913 	if (macb_is_gem(bp)) {
2914 		bp->max_tx_length = GEM_MAX_TX_LEN;
2915 		bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2916 		bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2917 		bp->macbgem_ops.mog_init_rings = gem_init_rings;
2918 		bp->macbgem_ops.mog_rx = gem_rx;
2919 		dev->ethtool_ops = &gem_ethtool_ops;
2920 	} else {
2921 		bp->max_tx_length = MACB_MAX_TX_LEN;
2922 		bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2923 		bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2924 		bp->macbgem_ops.mog_init_rings = macb_init_rings;
2925 		bp->macbgem_ops.mog_rx = macb_rx;
2926 		dev->ethtool_ops = &macb_ethtool_ops;
2927 	}
2928 
2929 	/* Set features */
2930 	dev->hw_features = NETIF_F_SG;
2931 
2932 	/* Check LSO capability */
2933 	if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
2934 		dev->hw_features |= MACB_NETIF_LSO;
2935 
2936 	/* Checksum offload is only available on gem with packet buffer */
2937 	if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2938 		dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2939 	if (bp->caps & MACB_CAPS_SG_DISABLED)
2940 		dev->hw_features &= ~NETIF_F_SG;
2941 	dev->features = dev->hw_features;
2942 
2943 	if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
2944 		val = 0;
2945 		if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2946 			val = GEM_BIT(RGMII);
2947 		else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2948 			 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2949 			val = MACB_BIT(RMII);
2950 		else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
2951 			val = MACB_BIT(MII);
2952 
2953 		if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2954 			val |= MACB_BIT(CLKEN);
2955 
2956 		macb_or_gem_writel(bp, USRIO, val);
2957 	}
2958 
2959 	/* Set MII management clock divider */
2960 	val = macb_mdc_clk_div(bp);
2961 	val |= macb_dbw(bp);
2962 	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
2963 		val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
2964 	macb_writel(bp, NCFGR, val);
2965 
2966 	return 0;
2967 }
2968 
2969 #if defined(CONFIG_OF)
2970 /* 1518 rounded up */
2971 #define AT91ETHER_MAX_RBUFF_SZ	0x600
2972 /* max number of receive buffers */
2973 #define AT91ETHER_MAX_RX_DESCR	9
2974 
2975 /* Initialize and start the Receiver and Transmit subsystems */
2976 static int at91ether_start(struct net_device *dev)
2977 {
2978 	struct macb *lp = netdev_priv(dev);
2979 	struct macb_dma_desc *desc;
2980 	dma_addr_t addr;
2981 	u32 ctl;
2982 	int i;
2983 
2984 	lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2985 					 (AT91ETHER_MAX_RX_DESCR *
2986 					  macb_dma_desc_get_size(lp)),
2987 					 &lp->rx_ring_dma, GFP_KERNEL);
2988 	if (!lp->rx_ring)
2989 		return -ENOMEM;
2990 
2991 	lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2992 					    AT91ETHER_MAX_RX_DESCR *
2993 					    AT91ETHER_MAX_RBUFF_SZ,
2994 					    &lp->rx_buffers_dma, GFP_KERNEL);
2995 	if (!lp->rx_buffers) {
2996 		dma_free_coherent(&lp->pdev->dev,
2997 				  AT91ETHER_MAX_RX_DESCR *
2998 				  macb_dma_desc_get_size(lp),
2999 				  lp->rx_ring, lp->rx_ring_dma);
3000 		lp->rx_ring = NULL;
3001 		return -ENOMEM;
3002 	}
3003 
3004 	addr = lp->rx_buffers_dma;
3005 	for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3006 		desc = macb_rx_desc(lp, i);
3007 		macb_set_addr(lp, desc, addr);
3008 		desc->ctrl = 0;
3009 		addr += AT91ETHER_MAX_RBUFF_SZ;
3010 	}
3011 
3012 	/* Set the Wrap bit on the last descriptor */
3013 	desc->addr |= MACB_BIT(RX_WRAP);
3014 
3015 	/* Reset buffer index */
3016 	lp->rx_tail = 0;
3017 
3018 	/* Program address of descriptor list in Rx Buffer Queue register */
3019 	macb_writel(lp, RBQP, lp->rx_ring_dma);
3020 
3021 	/* Enable Receive and Transmit */
3022 	ctl = macb_readl(lp, NCR);
3023 	macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3024 
3025 	return 0;
3026 }
3027 
3028 /* Open the ethernet interface */
3029 static int at91ether_open(struct net_device *dev)
3030 {
3031 	struct macb *lp = netdev_priv(dev);
3032 	u32 ctl;
3033 	int ret;
3034 
3035 	/* Clear internal statistics */
3036 	ctl = macb_readl(lp, NCR);
3037 	macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3038 
3039 	macb_set_hwaddr(lp);
3040 
3041 	ret = at91ether_start(dev);
3042 	if (ret)
3043 		return ret;
3044 
3045 	/* Enable MAC interrupts */
3046 	macb_writel(lp, IER, MACB_BIT(RCOMP)	|
3047 			     MACB_BIT(RXUBR)	|
3048 			     MACB_BIT(ISR_TUND)	|
3049 			     MACB_BIT(ISR_RLE)	|
3050 			     MACB_BIT(TCOMP)	|
3051 			     MACB_BIT(ISR_ROVR)	|
3052 			     MACB_BIT(HRESP));
3053 
3054 	/* schedule a link state check */
3055 	phy_start(dev->phydev);
3056 
3057 	netif_start_queue(dev);
3058 
3059 	return 0;
3060 }
3061 
3062 /* Close the interface */
3063 static int at91ether_close(struct net_device *dev)
3064 {
3065 	struct macb *lp = netdev_priv(dev);
3066 	u32 ctl;
3067 
3068 	/* Disable Receiver and Transmitter */
3069 	ctl = macb_readl(lp, NCR);
3070 	macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3071 
3072 	/* Disable MAC interrupts */
3073 	macb_writel(lp, IDR, MACB_BIT(RCOMP)	|
3074 			     MACB_BIT(RXUBR)	|
3075 			     MACB_BIT(ISR_TUND)	|
3076 			     MACB_BIT(ISR_RLE)	|
3077 			     MACB_BIT(TCOMP)	|
3078 			     MACB_BIT(ISR_ROVR) |
3079 			     MACB_BIT(HRESP));
3080 
3081 	netif_stop_queue(dev);
3082 
3083 	dma_free_coherent(&lp->pdev->dev,
3084 			  AT91ETHER_MAX_RX_DESCR *
3085 			  macb_dma_desc_get_size(lp),
3086 			  lp->rx_ring, lp->rx_ring_dma);
3087 	lp->rx_ring = NULL;
3088 
3089 	dma_free_coherent(&lp->pdev->dev,
3090 			  AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3091 			  lp->rx_buffers, lp->rx_buffers_dma);
3092 	lp->rx_buffers = NULL;
3093 
3094 	return 0;
3095 }
3096 
3097 /* Transmit packet */
3098 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
3099 {
3100 	struct macb *lp = netdev_priv(dev);
3101 
3102 	if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3103 		netif_stop_queue(dev);
3104 
3105 		/* Store packet information (to free when Tx completed) */
3106 		lp->skb = skb;
3107 		lp->skb_length = skb->len;
3108 		lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
3109 							DMA_TO_DEVICE);
3110 		if (dma_mapping_error(NULL, lp->skb_physaddr)) {
3111 			dev_kfree_skb_any(skb);
3112 			dev->stats.tx_dropped++;
3113 			netdev_err(dev, "%s: DMA mapping error\n", __func__);
3114 			return NETDEV_TX_OK;
3115 		}
3116 
3117 		/* Set address of the data in the Transmit Address register */
3118 		macb_writel(lp, TAR, lp->skb_physaddr);
3119 		/* Set length of the packet in the Transmit Control register */
3120 		macb_writel(lp, TCR, skb->len);
3121 
3122 	} else {
3123 		netdev_err(dev, "%s called, but device is busy!\n", __func__);
3124 		return NETDEV_TX_BUSY;
3125 	}
3126 
3127 	return NETDEV_TX_OK;
3128 }
3129 
3130 /* Extract received frame from buffer descriptors and sent to upper layers.
3131  * (Called from interrupt context)
3132  */
3133 static void at91ether_rx(struct net_device *dev)
3134 {
3135 	struct macb *lp = netdev_priv(dev);
3136 	struct macb_dma_desc *desc;
3137 	unsigned char *p_recv;
3138 	struct sk_buff *skb;
3139 	unsigned int pktlen;
3140 
3141 	desc = macb_rx_desc(lp, lp->rx_tail);
3142 	while (desc->addr & MACB_BIT(RX_USED)) {
3143 		p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3144 		pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3145 		skb = netdev_alloc_skb(dev, pktlen + 2);
3146 		if (skb) {
3147 			skb_reserve(skb, 2);
3148 			skb_put_data(skb, p_recv, pktlen);
3149 
3150 			skb->protocol = eth_type_trans(skb, dev);
3151 			dev->stats.rx_packets++;
3152 			dev->stats.rx_bytes += pktlen;
3153 			netif_rx(skb);
3154 		} else {
3155 			dev->stats.rx_dropped++;
3156 		}
3157 
3158 		if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3159 			dev->stats.multicast++;
3160 
3161 		/* reset ownership bit */
3162 		desc->addr &= ~MACB_BIT(RX_USED);
3163 
3164 		/* wrap after last buffer */
3165 		if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3166 			lp->rx_tail = 0;
3167 		else
3168 			lp->rx_tail++;
3169 
3170 		desc = macb_rx_desc(lp, lp->rx_tail);
3171 	}
3172 }
3173 
3174 /* MAC interrupt handler */
3175 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3176 {
3177 	struct net_device *dev = dev_id;
3178 	struct macb *lp = netdev_priv(dev);
3179 	u32 intstatus, ctl;
3180 
3181 	/* MAC Interrupt Status register indicates what interrupts are pending.
3182 	 * It is automatically cleared once read.
3183 	 */
3184 	intstatus = macb_readl(lp, ISR);
3185 
3186 	/* Receive complete */
3187 	if (intstatus & MACB_BIT(RCOMP))
3188 		at91ether_rx(dev);
3189 
3190 	/* Transmit complete */
3191 	if (intstatus & MACB_BIT(TCOMP)) {
3192 		/* The TCOM bit is set even if the transmission failed */
3193 		if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3194 			dev->stats.tx_errors++;
3195 
3196 		if (lp->skb) {
3197 			dev_kfree_skb_irq(lp->skb);
3198 			lp->skb = NULL;
3199 			dma_unmap_single(NULL, lp->skb_physaddr,
3200 					 lp->skb_length, DMA_TO_DEVICE);
3201 			dev->stats.tx_packets++;
3202 			dev->stats.tx_bytes += lp->skb_length;
3203 		}
3204 		netif_wake_queue(dev);
3205 	}
3206 
3207 	/* Work-around for EMAC Errata section 41.3.1 */
3208 	if (intstatus & MACB_BIT(RXUBR)) {
3209 		ctl = macb_readl(lp, NCR);
3210 		macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3211 		wmb();
3212 		macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3213 	}
3214 
3215 	if (intstatus & MACB_BIT(ISR_ROVR))
3216 		netdev_err(dev, "ROVR error\n");
3217 
3218 	return IRQ_HANDLED;
3219 }
3220 
3221 #ifdef CONFIG_NET_POLL_CONTROLLER
3222 static void at91ether_poll_controller(struct net_device *dev)
3223 {
3224 	unsigned long flags;
3225 
3226 	local_irq_save(flags);
3227 	at91ether_interrupt(dev->irq, dev);
3228 	local_irq_restore(flags);
3229 }
3230 #endif
3231 
3232 static const struct net_device_ops at91ether_netdev_ops = {
3233 	.ndo_open		= at91ether_open,
3234 	.ndo_stop		= at91ether_close,
3235 	.ndo_start_xmit		= at91ether_start_xmit,
3236 	.ndo_get_stats		= macb_get_stats,
3237 	.ndo_set_rx_mode	= macb_set_rx_mode,
3238 	.ndo_set_mac_address	= eth_mac_addr,
3239 	.ndo_do_ioctl		= macb_ioctl,
3240 	.ndo_validate_addr	= eth_validate_addr,
3241 #ifdef CONFIG_NET_POLL_CONTROLLER
3242 	.ndo_poll_controller	= at91ether_poll_controller,
3243 #endif
3244 };
3245 
3246 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3247 			      struct clk **hclk, struct clk **tx_clk,
3248 			      struct clk **rx_clk)
3249 {
3250 	int err;
3251 
3252 	*hclk = NULL;
3253 	*tx_clk = NULL;
3254 	*rx_clk = NULL;
3255 
3256 	*pclk = devm_clk_get(&pdev->dev, "ether_clk");
3257 	if (IS_ERR(*pclk))
3258 		return PTR_ERR(*pclk);
3259 
3260 	err = clk_prepare_enable(*pclk);
3261 	if (err) {
3262 		dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
3263 		return err;
3264 	}
3265 
3266 	return 0;
3267 }
3268 
3269 static int at91ether_init(struct platform_device *pdev)
3270 {
3271 	struct net_device *dev = platform_get_drvdata(pdev);
3272 	struct macb *bp = netdev_priv(dev);
3273 	int err;
3274 	u32 reg;
3275 
3276 	dev->netdev_ops = &at91ether_netdev_ops;
3277 	dev->ethtool_ops = &macb_ethtool_ops;
3278 
3279 	err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
3280 			       0, dev->name, dev);
3281 	if (err)
3282 		return err;
3283 
3284 	macb_writel(bp, NCR, 0);
3285 
3286 	reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
3287 	if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
3288 		reg |= MACB_BIT(RM9200_RMII);
3289 
3290 	macb_writel(bp, NCFGR, reg);
3291 
3292 	return 0;
3293 }
3294 
3295 static const struct macb_config at91sam9260_config = {
3296 	.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3297 	.clk_init = macb_clk_init,
3298 	.init = macb_init,
3299 };
3300 
3301 static const struct macb_config pc302gem_config = {
3302 	.caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
3303 	.dma_burst_length = 16,
3304 	.clk_init = macb_clk_init,
3305 	.init = macb_init,
3306 };
3307 
3308 static const struct macb_config sama5d2_config = {
3309 	.caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3310 	.dma_burst_length = 16,
3311 	.clk_init = macb_clk_init,
3312 	.init = macb_init,
3313 };
3314 
3315 static const struct macb_config sama5d3_config = {
3316 	.caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
3317 	      | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
3318 	.dma_burst_length = 16,
3319 	.clk_init = macb_clk_init,
3320 	.init = macb_init,
3321 	.jumbo_max_len = 10240,
3322 };
3323 
3324 static const struct macb_config sama5d4_config = {
3325 	.caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
3326 	.dma_burst_length = 4,
3327 	.clk_init = macb_clk_init,
3328 	.init = macb_init,
3329 };
3330 
3331 static const struct macb_config emac_config = {
3332 	.clk_init = at91ether_clk_init,
3333 	.init = at91ether_init,
3334 };
3335 
3336 static const struct macb_config np4_config = {
3337 	.caps = MACB_CAPS_USRIO_DISABLED,
3338 	.clk_init = macb_clk_init,
3339 	.init = macb_init,
3340 };
3341 
3342 static const struct macb_config zynqmp_config = {
3343 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3344 			MACB_CAPS_JUMBO |
3345 			MACB_CAPS_GEM_HAS_PTP,
3346 	.dma_burst_length = 16,
3347 	.clk_init = macb_clk_init,
3348 	.init = macb_init,
3349 	.jumbo_max_len = 10240,
3350 };
3351 
3352 static const struct macb_config zynq_config = {
3353 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF,
3354 	.dma_burst_length = 16,
3355 	.clk_init = macb_clk_init,
3356 	.init = macb_init,
3357 };
3358 
3359 static const struct of_device_id macb_dt_ids[] = {
3360 	{ .compatible = "cdns,at32ap7000-macb" },
3361 	{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
3362 	{ .compatible = "cdns,macb" },
3363 	{ .compatible = "cdns,np4-macb", .data = &np4_config },
3364 	{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
3365 	{ .compatible = "cdns,gem", .data = &pc302gem_config },
3366 	{ .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
3367 	{ .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
3368 	{ .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
3369 	{ .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
3370 	{ .compatible = "cdns,emac", .data = &emac_config },
3371 	{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
3372 	{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
3373 	{ /* sentinel */ }
3374 };
3375 MODULE_DEVICE_TABLE(of, macb_dt_ids);
3376 #endif /* CONFIG_OF */
3377 
3378 static const struct macb_config default_gem_config = {
3379 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
3380 			MACB_CAPS_JUMBO |
3381 			MACB_CAPS_GEM_HAS_PTP,
3382 	.dma_burst_length = 16,
3383 	.clk_init = macb_clk_init,
3384 	.init = macb_init,
3385 	.jumbo_max_len = 10240,
3386 };
3387 
3388 static int macb_probe(struct platform_device *pdev)
3389 {
3390 	const struct macb_config *macb_config = &default_gem_config;
3391 	int (*clk_init)(struct platform_device *, struct clk **,
3392 			struct clk **, struct clk **,  struct clk **)
3393 					      = macb_config->clk_init;
3394 	int (*init)(struct platform_device *) = macb_config->init;
3395 	struct device_node *np = pdev->dev.of_node;
3396 	struct device_node *phy_node;
3397 	struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
3398 	unsigned int queue_mask, num_queues;
3399 	struct macb_platform_data *pdata;
3400 	bool native_io;
3401 	struct phy_device *phydev;
3402 	struct net_device *dev;
3403 	struct resource *regs;
3404 	void __iomem *mem;
3405 	const char *mac;
3406 	struct macb *bp;
3407 	int err;
3408 
3409 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3410 	mem = devm_ioremap_resource(&pdev->dev, regs);
3411 	if (IS_ERR(mem))
3412 		return PTR_ERR(mem);
3413 
3414 	if (np) {
3415 		const struct of_device_id *match;
3416 
3417 		match = of_match_node(macb_dt_ids, np);
3418 		if (match && match->data) {
3419 			macb_config = match->data;
3420 			clk_init = macb_config->clk_init;
3421 			init = macb_config->init;
3422 		}
3423 	}
3424 
3425 	err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk);
3426 	if (err)
3427 		return err;
3428 
3429 	native_io = hw_is_native_io(mem);
3430 
3431 	macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
3432 	dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
3433 	if (!dev) {
3434 		err = -ENOMEM;
3435 		goto err_disable_clocks;
3436 	}
3437 
3438 	dev->base_addr = regs->start;
3439 
3440 	SET_NETDEV_DEV(dev, &pdev->dev);
3441 
3442 	bp = netdev_priv(dev);
3443 	bp->pdev = pdev;
3444 	bp->dev = dev;
3445 	bp->regs = mem;
3446 	bp->native_io = native_io;
3447 	if (native_io) {
3448 		bp->macb_reg_readl = hw_readl_native;
3449 		bp->macb_reg_writel = hw_writel_native;
3450 	} else {
3451 		bp->macb_reg_readl = hw_readl;
3452 		bp->macb_reg_writel = hw_writel;
3453 	}
3454 	bp->num_queues = num_queues;
3455 	bp->queue_mask = queue_mask;
3456 	if (macb_config)
3457 		bp->dma_burst_length = macb_config->dma_burst_length;
3458 	bp->pclk = pclk;
3459 	bp->hclk = hclk;
3460 	bp->tx_clk = tx_clk;
3461 	bp->rx_clk = rx_clk;
3462 	if (macb_config)
3463 		bp->jumbo_max_len = macb_config->jumbo_max_len;
3464 
3465 	bp->wol = 0;
3466 	if (of_get_property(np, "magic-packet", NULL))
3467 		bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
3468 	device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
3469 
3470 	spin_lock_init(&bp->lock);
3471 
3472 	/* setup capabilities */
3473 	macb_configure_caps(bp, macb_config);
3474 
3475 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3476 	if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
3477 		dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
3478 		bp->hw_dma_cap |= HW_DMA_CAP_64B;
3479 	}
3480 #endif
3481 	platform_set_drvdata(pdev, dev);
3482 
3483 	dev->irq = platform_get_irq(pdev, 0);
3484 	if (dev->irq < 0) {
3485 		err = dev->irq;
3486 		goto err_out_free_netdev;
3487 	}
3488 
3489 	/* MTU range: 68 - 1500 or 10240 */
3490 	dev->min_mtu = GEM_MTU_MIN_SIZE;
3491 	if (bp->caps & MACB_CAPS_JUMBO)
3492 		dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
3493 	else
3494 		dev->max_mtu = ETH_DATA_LEN;
3495 
3496 	mac = of_get_mac_address(np);
3497 	if (mac)
3498 		ether_addr_copy(bp->dev->dev_addr, mac);
3499 	else
3500 		macb_get_hwaddr(bp);
3501 
3502 	/* Power up the PHY if there is a GPIO reset */
3503 	phy_node =  of_get_next_available_child(np, NULL);
3504 	if (phy_node) {
3505 		int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);
3506 
3507 		if (gpio_is_valid(gpio)) {
3508 			bp->reset_gpio = gpio_to_desc(gpio);
3509 			gpiod_direction_output(bp->reset_gpio, 1);
3510 		}
3511 	}
3512 	of_node_put(phy_node);
3513 
3514 	err = of_get_phy_mode(np);
3515 	if (err < 0) {
3516 		pdata = dev_get_platdata(&pdev->dev);
3517 		if (pdata && pdata->is_rmii)
3518 			bp->phy_interface = PHY_INTERFACE_MODE_RMII;
3519 		else
3520 			bp->phy_interface = PHY_INTERFACE_MODE_MII;
3521 	} else {
3522 		bp->phy_interface = err;
3523 	}
3524 
3525 	/* IP specific init */
3526 	err = init(pdev);
3527 	if (err)
3528 		goto err_out_free_netdev;
3529 
3530 	err = macb_mii_init(bp);
3531 	if (err)
3532 		goto err_out_free_netdev;
3533 
3534 	phydev = dev->phydev;
3535 
3536 	netif_carrier_off(dev);
3537 
3538 	err = register_netdev(dev);
3539 	if (err) {
3540 		dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
3541 		goto err_out_unregister_mdio;
3542 	}
3543 
3544 	phy_attached_info(phydev);
3545 
3546 	netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
3547 		    macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
3548 		    dev->base_addr, dev->irq, dev->dev_addr);
3549 
3550 	return 0;
3551 
3552 err_out_unregister_mdio:
3553 	phy_disconnect(dev->phydev);
3554 	mdiobus_unregister(bp->mii_bus);
3555 	mdiobus_free(bp->mii_bus);
3556 
3557 	/* Shutdown the PHY if there is a GPIO reset */
3558 	if (bp->reset_gpio)
3559 		gpiod_set_value(bp->reset_gpio, 0);
3560 
3561 err_out_free_netdev:
3562 	free_netdev(dev);
3563 
3564 err_disable_clocks:
3565 	clk_disable_unprepare(tx_clk);
3566 	clk_disable_unprepare(hclk);
3567 	clk_disable_unprepare(pclk);
3568 	clk_disable_unprepare(rx_clk);
3569 
3570 	return err;
3571 }
3572 
3573 static int macb_remove(struct platform_device *pdev)
3574 {
3575 	struct net_device *dev;
3576 	struct macb *bp;
3577 
3578 	dev = platform_get_drvdata(pdev);
3579 
3580 	if (dev) {
3581 		bp = netdev_priv(dev);
3582 		if (dev->phydev)
3583 			phy_disconnect(dev->phydev);
3584 		mdiobus_unregister(bp->mii_bus);
3585 		dev->phydev = NULL;
3586 		mdiobus_free(bp->mii_bus);
3587 
3588 		/* Shutdown the PHY if there is a GPIO reset */
3589 		if (bp->reset_gpio)
3590 			gpiod_set_value(bp->reset_gpio, 0);
3591 
3592 		unregister_netdev(dev);
3593 		clk_disable_unprepare(bp->tx_clk);
3594 		clk_disable_unprepare(bp->hclk);
3595 		clk_disable_unprepare(bp->pclk);
3596 		clk_disable_unprepare(bp->rx_clk);
3597 		of_node_put(bp->phy_node);
3598 		free_netdev(dev);
3599 	}
3600 
3601 	return 0;
3602 }
3603 
3604 static int __maybe_unused macb_suspend(struct device *dev)
3605 {
3606 	struct platform_device *pdev = to_platform_device(dev);
3607 	struct net_device *netdev = platform_get_drvdata(pdev);
3608 	struct macb *bp = netdev_priv(netdev);
3609 
3610 	netif_carrier_off(netdev);
3611 	netif_device_detach(netdev);
3612 
3613 	if (bp->wol & MACB_WOL_ENABLED) {
3614 		macb_writel(bp, IER, MACB_BIT(WOL));
3615 		macb_writel(bp, WOL, MACB_BIT(MAG));
3616 		enable_irq_wake(bp->queues[0].irq);
3617 	} else {
3618 		clk_disable_unprepare(bp->tx_clk);
3619 		clk_disable_unprepare(bp->hclk);
3620 		clk_disable_unprepare(bp->pclk);
3621 		clk_disable_unprepare(bp->rx_clk);
3622 	}
3623 
3624 	return 0;
3625 }
3626 
3627 static int __maybe_unused macb_resume(struct device *dev)
3628 {
3629 	struct platform_device *pdev = to_platform_device(dev);
3630 	struct net_device *netdev = platform_get_drvdata(pdev);
3631 	struct macb *bp = netdev_priv(netdev);
3632 
3633 	if (bp->wol & MACB_WOL_ENABLED) {
3634 		macb_writel(bp, IDR, MACB_BIT(WOL));
3635 		macb_writel(bp, WOL, 0);
3636 		disable_irq_wake(bp->queues[0].irq);
3637 	} else {
3638 		clk_prepare_enable(bp->pclk);
3639 		clk_prepare_enable(bp->hclk);
3640 		clk_prepare_enable(bp->tx_clk);
3641 		clk_prepare_enable(bp->rx_clk);
3642 	}
3643 
3644 	netif_device_attach(netdev);
3645 
3646 	return 0;
3647 }
3648 
3649 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3650 
3651 static struct platform_driver macb_driver = {
3652 	.probe		= macb_probe,
3653 	.remove		= macb_remove,
3654 	.driver		= {
3655 		.name		= "macb",
3656 		.of_match_table	= of_match_ptr(macb_dt_ids),
3657 		.pm	= &macb_pm_ops,
3658 	},
3659 };
3660 
3661 module_platform_driver(macb_driver);
3662 
3663 MODULE_LICENSE("GPL");
3664 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
3665 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
3666 MODULE_ALIAS("platform:macb");
3667