1 /* 2 * Atmel MACB Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _MACB_H 11 #define _MACB_H 12 13 #define MACB_GREGS_NBR 16 14 #define MACB_GREGS_VERSION 1 15 #define MACB_MAX_QUEUES 8 16 17 /* MACB register offsets */ 18 #define MACB_NCR 0x0000 19 #define MACB_NCFGR 0x0004 20 #define MACB_NSR 0x0008 21 #define MACB_TAR 0x000c /* AT91RM9200 only */ 22 #define MACB_TCR 0x0010 /* AT91RM9200 only */ 23 #define MACB_TSR 0x0014 24 #define MACB_RBQP 0x0018 25 #define MACB_TBQP 0x001c 26 #define MACB_RSR 0x0020 27 #define MACB_ISR 0x0024 28 #define MACB_IER 0x0028 29 #define MACB_IDR 0x002c 30 #define MACB_IMR 0x0030 31 #define MACB_MAN 0x0034 32 #define MACB_PTR 0x0038 33 #define MACB_PFR 0x003c 34 #define MACB_FTO 0x0040 35 #define MACB_SCF 0x0044 36 #define MACB_MCF 0x0048 37 #define MACB_FRO 0x004c 38 #define MACB_FCSE 0x0050 39 #define MACB_ALE 0x0054 40 #define MACB_DTF 0x0058 41 #define MACB_LCOL 0x005c 42 #define MACB_EXCOL 0x0060 43 #define MACB_TUND 0x0064 44 #define MACB_CSE 0x0068 45 #define MACB_RRE 0x006c 46 #define MACB_ROVR 0x0070 47 #define MACB_RSE 0x0074 48 #define MACB_ELE 0x0078 49 #define MACB_RJA 0x007c 50 #define MACB_USF 0x0080 51 #define MACB_STE 0x0084 52 #define MACB_RLE 0x0088 53 #define MACB_TPF 0x008c 54 #define MACB_HRB 0x0090 55 #define MACB_HRT 0x0094 56 #define MACB_SA1B 0x0098 57 #define MACB_SA1T 0x009c 58 #define MACB_SA2B 0x00a0 59 #define MACB_SA2T 0x00a4 60 #define MACB_SA3B 0x00a8 61 #define MACB_SA3T 0x00ac 62 #define MACB_SA4B 0x00b0 63 #define MACB_SA4T 0x00b4 64 #define MACB_TID 0x00b8 65 #define MACB_TPQ 0x00bc 66 #define MACB_USRIO 0x00c0 67 #define MACB_WOL 0x00c4 68 #define MACB_MID 0x00fc 69 70 /* GEM register offsets. */ 71 #define GEM_NCFGR 0x0004 72 #define GEM_USRIO 0x000c 73 #define GEM_DMACFG 0x0010 74 #define GEM_HRB 0x0080 75 #define GEM_HRT 0x0084 76 #define GEM_SA1B 0x0088 77 #define GEM_SA1T 0x008C 78 #define GEM_SA2B 0x0090 79 #define GEM_SA2T 0x0094 80 #define GEM_SA3B 0x0098 81 #define GEM_SA3T 0x009C 82 #define GEM_SA4B 0x00A0 83 #define GEM_SA4T 0x00A4 84 #define GEM_OTX 0x0100 85 #define GEM_DCFG1 0x0280 86 #define GEM_DCFG2 0x0284 87 #define GEM_DCFG3 0x0288 88 #define GEM_DCFG4 0x028c 89 #define GEM_DCFG5 0x0290 90 #define GEM_DCFG6 0x0294 91 #define GEM_DCFG7 0x0298 92 93 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 94 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 95 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 96 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 97 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 98 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 99 100 /* Bitfields in NCR */ 101 #define MACB_LB_OFFSET 0 102 #define MACB_LB_SIZE 1 103 #define MACB_LLB_OFFSET 1 104 #define MACB_LLB_SIZE 1 105 #define MACB_RE_OFFSET 2 106 #define MACB_RE_SIZE 1 107 #define MACB_TE_OFFSET 3 108 #define MACB_TE_SIZE 1 109 #define MACB_MPE_OFFSET 4 110 #define MACB_MPE_SIZE 1 111 #define MACB_CLRSTAT_OFFSET 5 112 #define MACB_CLRSTAT_SIZE 1 113 #define MACB_INCSTAT_OFFSET 6 114 #define MACB_INCSTAT_SIZE 1 115 #define MACB_WESTAT_OFFSET 7 116 #define MACB_WESTAT_SIZE 1 117 #define MACB_BP_OFFSET 8 118 #define MACB_BP_SIZE 1 119 #define MACB_TSTART_OFFSET 9 120 #define MACB_TSTART_SIZE 1 121 #define MACB_THALT_OFFSET 10 122 #define MACB_THALT_SIZE 1 123 #define MACB_NCR_TPF_OFFSET 11 124 #define MACB_NCR_TPF_SIZE 1 125 #define MACB_TZQ_OFFSET 12 126 #define MACB_TZQ_SIZE 1 127 128 /* Bitfields in NCFGR */ 129 #define MACB_SPD_OFFSET 0 130 #define MACB_SPD_SIZE 1 131 #define MACB_FD_OFFSET 1 132 #define MACB_FD_SIZE 1 133 #define MACB_BIT_RATE_OFFSET 2 134 #define MACB_BIT_RATE_SIZE 1 135 #define MACB_JFRAME_OFFSET 3 136 #define MACB_JFRAME_SIZE 1 137 #define MACB_CAF_OFFSET 4 138 #define MACB_CAF_SIZE 1 139 #define MACB_NBC_OFFSET 5 140 #define MACB_NBC_SIZE 1 141 #define MACB_NCFGR_MTI_OFFSET 6 142 #define MACB_NCFGR_MTI_SIZE 1 143 #define MACB_UNI_OFFSET 7 144 #define MACB_UNI_SIZE 1 145 #define MACB_BIG_OFFSET 8 146 #define MACB_BIG_SIZE 1 147 #define MACB_EAE_OFFSET 9 148 #define MACB_EAE_SIZE 1 149 #define MACB_CLK_OFFSET 10 150 #define MACB_CLK_SIZE 2 151 #define MACB_RTY_OFFSET 12 152 #define MACB_RTY_SIZE 1 153 #define MACB_PAE_OFFSET 13 154 #define MACB_PAE_SIZE 1 155 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 156 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 157 #define MACB_RBOF_OFFSET 14 158 #define MACB_RBOF_SIZE 2 159 #define MACB_RLCE_OFFSET 16 160 #define MACB_RLCE_SIZE 1 161 #define MACB_DRFCS_OFFSET 17 162 #define MACB_DRFCS_SIZE 1 163 #define MACB_EFRHD_OFFSET 18 164 #define MACB_EFRHD_SIZE 1 165 #define MACB_IRXFCS_OFFSET 19 166 #define MACB_IRXFCS_SIZE 1 167 168 /* GEM specific NCFGR bitfields. */ 169 #define GEM_GBE_OFFSET 10 170 #define GEM_GBE_SIZE 1 171 #define GEM_CLK_OFFSET 18 172 #define GEM_CLK_SIZE 3 173 #define GEM_DBW_OFFSET 21 174 #define GEM_DBW_SIZE 2 175 #define GEM_RXCOEN_OFFSET 24 176 #define GEM_RXCOEN_SIZE 1 177 178 /* Constants for data bus width. */ 179 #define GEM_DBW32 0 180 #define GEM_DBW64 1 181 #define GEM_DBW128 2 182 183 /* Bitfields in DMACFG. */ 184 #define GEM_FBLDO_OFFSET 0 185 #define GEM_FBLDO_SIZE 5 186 #define GEM_ENDIA_OFFSET 7 187 #define GEM_ENDIA_SIZE 1 188 #define GEM_RXBMS_OFFSET 8 189 #define GEM_RXBMS_SIZE 2 190 #define GEM_TXPBMS_OFFSET 10 191 #define GEM_TXPBMS_SIZE 1 192 #define GEM_TXCOEN_OFFSET 11 193 #define GEM_TXCOEN_SIZE 1 194 #define GEM_RXBS_OFFSET 16 195 #define GEM_RXBS_SIZE 8 196 #define GEM_DDRP_OFFSET 24 197 #define GEM_DDRP_SIZE 1 198 199 200 /* Bitfields in NSR */ 201 #define MACB_NSR_LINK_OFFSET 0 202 #define MACB_NSR_LINK_SIZE 1 203 #define MACB_MDIO_OFFSET 1 204 #define MACB_MDIO_SIZE 1 205 #define MACB_IDLE_OFFSET 2 206 #define MACB_IDLE_SIZE 1 207 208 /* Bitfields in TSR */ 209 #define MACB_UBR_OFFSET 0 210 #define MACB_UBR_SIZE 1 211 #define MACB_COL_OFFSET 1 212 #define MACB_COL_SIZE 1 213 #define MACB_TSR_RLE_OFFSET 2 214 #define MACB_TSR_RLE_SIZE 1 215 #define MACB_TGO_OFFSET 3 216 #define MACB_TGO_SIZE 1 217 #define MACB_BEX_OFFSET 4 218 #define MACB_BEX_SIZE 1 219 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 220 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 221 #define MACB_COMP_OFFSET 5 222 #define MACB_COMP_SIZE 1 223 #define MACB_UND_OFFSET 6 224 #define MACB_UND_SIZE 1 225 226 /* Bitfields in RSR */ 227 #define MACB_BNA_OFFSET 0 228 #define MACB_BNA_SIZE 1 229 #define MACB_REC_OFFSET 1 230 #define MACB_REC_SIZE 1 231 #define MACB_OVR_OFFSET 2 232 #define MACB_OVR_SIZE 1 233 234 /* Bitfields in ISR/IER/IDR/IMR */ 235 #define MACB_MFD_OFFSET 0 236 #define MACB_MFD_SIZE 1 237 #define MACB_RCOMP_OFFSET 1 238 #define MACB_RCOMP_SIZE 1 239 #define MACB_RXUBR_OFFSET 2 240 #define MACB_RXUBR_SIZE 1 241 #define MACB_TXUBR_OFFSET 3 242 #define MACB_TXUBR_SIZE 1 243 #define MACB_ISR_TUND_OFFSET 4 244 #define MACB_ISR_TUND_SIZE 1 245 #define MACB_ISR_RLE_OFFSET 5 246 #define MACB_ISR_RLE_SIZE 1 247 #define MACB_TXERR_OFFSET 6 248 #define MACB_TXERR_SIZE 1 249 #define MACB_TCOMP_OFFSET 7 250 #define MACB_TCOMP_SIZE 1 251 #define MACB_ISR_LINK_OFFSET 9 252 #define MACB_ISR_LINK_SIZE 1 253 #define MACB_ISR_ROVR_OFFSET 10 254 #define MACB_ISR_ROVR_SIZE 1 255 #define MACB_HRESP_OFFSET 11 256 #define MACB_HRESP_SIZE 1 257 #define MACB_PFR_OFFSET 12 258 #define MACB_PFR_SIZE 1 259 #define MACB_PTZ_OFFSET 13 260 #define MACB_PTZ_SIZE 1 261 262 /* Bitfields in MAN */ 263 #define MACB_DATA_OFFSET 0 264 #define MACB_DATA_SIZE 16 265 #define MACB_CODE_OFFSET 16 266 #define MACB_CODE_SIZE 2 267 #define MACB_REGA_OFFSET 18 268 #define MACB_REGA_SIZE 5 269 #define MACB_PHYA_OFFSET 23 270 #define MACB_PHYA_SIZE 5 271 #define MACB_RW_OFFSET 28 272 #define MACB_RW_SIZE 2 273 #define MACB_SOF_OFFSET 30 274 #define MACB_SOF_SIZE 2 275 276 /* Bitfields in USRIO (AVR32) */ 277 #define MACB_MII_OFFSET 0 278 #define MACB_MII_SIZE 1 279 #define MACB_EAM_OFFSET 1 280 #define MACB_EAM_SIZE 1 281 #define MACB_TX_PAUSE_OFFSET 2 282 #define MACB_TX_PAUSE_SIZE 1 283 #define MACB_TX_PAUSE_ZERO_OFFSET 3 284 #define MACB_TX_PAUSE_ZERO_SIZE 1 285 286 /* Bitfields in USRIO (AT91) */ 287 #define MACB_RMII_OFFSET 0 288 #define MACB_RMII_SIZE 1 289 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 290 #define GEM_RGMII_SIZE 1 291 #define MACB_CLKEN_OFFSET 1 292 #define MACB_CLKEN_SIZE 1 293 294 /* Bitfields in WOL */ 295 #define MACB_IP_OFFSET 0 296 #define MACB_IP_SIZE 16 297 #define MACB_MAG_OFFSET 16 298 #define MACB_MAG_SIZE 1 299 #define MACB_ARP_OFFSET 17 300 #define MACB_ARP_SIZE 1 301 #define MACB_SA1_OFFSET 18 302 #define MACB_SA1_SIZE 1 303 #define MACB_WOL_MTI_OFFSET 19 304 #define MACB_WOL_MTI_SIZE 1 305 306 /* Bitfields in MID */ 307 #define MACB_IDNUM_OFFSET 16 308 #define MACB_IDNUM_SIZE 16 309 #define MACB_REV_OFFSET 0 310 #define MACB_REV_SIZE 16 311 312 /* Bitfields in DCFG1. */ 313 #define GEM_IRQCOR_OFFSET 23 314 #define GEM_IRQCOR_SIZE 1 315 #define GEM_DBWDEF_OFFSET 25 316 #define GEM_DBWDEF_SIZE 3 317 318 /* Bitfields in DCFG2. */ 319 #define GEM_RX_PKT_BUFF_OFFSET 20 320 #define GEM_RX_PKT_BUFF_SIZE 1 321 #define GEM_TX_PKT_BUFF_OFFSET 21 322 #define GEM_TX_PKT_BUFF_SIZE 1 323 324 /* Constants for CLK */ 325 #define MACB_CLK_DIV8 0 326 #define MACB_CLK_DIV16 1 327 #define MACB_CLK_DIV32 2 328 #define MACB_CLK_DIV64 3 329 330 /* GEM specific constants for CLK. */ 331 #define GEM_CLK_DIV8 0 332 #define GEM_CLK_DIV16 1 333 #define GEM_CLK_DIV32 2 334 #define GEM_CLK_DIV48 3 335 #define GEM_CLK_DIV64 4 336 #define GEM_CLK_DIV96 5 337 338 /* Constants for MAN register */ 339 #define MACB_MAN_SOF 1 340 #define MACB_MAN_WRITE 1 341 #define MACB_MAN_READ 2 342 #define MACB_MAN_CODE 2 343 344 /* Capability mask bits */ 345 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 346 #define MACB_CAPS_FIFO_MODE 0x10000000 347 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 348 #define MACB_CAPS_SG_DISABLED 0x40000000 349 #define MACB_CAPS_MACB_IS_GEM 0x80000000 350 351 /* Bit manipulation macros */ 352 #define MACB_BIT(name) \ 353 (1 << MACB_##name##_OFFSET) 354 #define MACB_BF(name,value) \ 355 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 356 << MACB_##name##_OFFSET) 357 #define MACB_BFEXT(name,value)\ 358 (((value) >> MACB_##name##_OFFSET) \ 359 & ((1 << MACB_##name##_SIZE) - 1)) 360 #define MACB_BFINS(name,value,old) \ 361 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 362 << MACB_##name##_OFFSET)) \ 363 | MACB_BF(name,value)) 364 365 #define GEM_BIT(name) \ 366 (1 << GEM_##name##_OFFSET) 367 #define GEM_BF(name, value) \ 368 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 369 << GEM_##name##_OFFSET) 370 #define GEM_BFEXT(name, value)\ 371 (((value) >> GEM_##name##_OFFSET) \ 372 & ((1 << GEM_##name##_SIZE) - 1)) 373 #define GEM_BFINS(name, value, old) \ 374 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 375 << GEM_##name##_OFFSET)) \ 376 | GEM_BF(name, value)) 377 378 /* Register access macros */ 379 #define macb_readl(port,reg) \ 380 __raw_readl((port)->regs + MACB_##reg) 381 #define macb_writel(port,reg,value) \ 382 __raw_writel((value), (port)->regs + MACB_##reg) 383 #define gem_readl(port, reg) \ 384 __raw_readl((port)->regs + GEM_##reg) 385 #define gem_writel(port, reg, value) \ 386 __raw_writel((value), (port)->regs + GEM_##reg) 387 #define queue_readl(queue, reg) \ 388 __raw_readl((queue)->bp->regs + (queue)->reg) 389 #define queue_writel(queue, reg, value) \ 390 __raw_writel((value), (queue)->bp->regs + (queue)->reg) 391 392 /* 393 * Conditional GEM/MACB macros. These perform the operation to the correct 394 * register dependent on whether the device is a GEM or a MACB. For registers 395 * and bitfields that are common across both devices, use macb_{read,write}l 396 * to avoid the cost of the conditional. 397 */ 398 #define macb_or_gem_writel(__bp, __reg, __value) \ 399 ({ \ 400 if (macb_is_gem((__bp))) \ 401 gem_writel((__bp), __reg, __value); \ 402 else \ 403 macb_writel((__bp), __reg, __value); \ 404 }) 405 406 #define macb_or_gem_readl(__bp, __reg) \ 407 ({ \ 408 u32 __v; \ 409 if (macb_is_gem((__bp))) \ 410 __v = gem_readl((__bp), __reg); \ 411 else \ 412 __v = macb_readl((__bp), __reg); \ 413 __v; \ 414 }) 415 416 /** 417 * struct macb_dma_desc - Hardware DMA descriptor 418 * @addr: DMA address of data buffer 419 * @ctrl: Control and status bits 420 */ 421 struct macb_dma_desc { 422 u32 addr; 423 u32 ctrl; 424 }; 425 426 /* DMA descriptor bitfields */ 427 #define MACB_RX_USED_OFFSET 0 428 #define MACB_RX_USED_SIZE 1 429 #define MACB_RX_WRAP_OFFSET 1 430 #define MACB_RX_WRAP_SIZE 1 431 #define MACB_RX_WADDR_OFFSET 2 432 #define MACB_RX_WADDR_SIZE 30 433 434 #define MACB_RX_FRMLEN_OFFSET 0 435 #define MACB_RX_FRMLEN_SIZE 12 436 #define MACB_RX_OFFSET_OFFSET 12 437 #define MACB_RX_OFFSET_SIZE 2 438 #define MACB_RX_SOF_OFFSET 14 439 #define MACB_RX_SOF_SIZE 1 440 #define MACB_RX_EOF_OFFSET 15 441 #define MACB_RX_EOF_SIZE 1 442 #define MACB_RX_CFI_OFFSET 16 443 #define MACB_RX_CFI_SIZE 1 444 #define MACB_RX_VLAN_PRI_OFFSET 17 445 #define MACB_RX_VLAN_PRI_SIZE 3 446 #define MACB_RX_PRI_TAG_OFFSET 20 447 #define MACB_RX_PRI_TAG_SIZE 1 448 #define MACB_RX_VLAN_TAG_OFFSET 21 449 #define MACB_RX_VLAN_TAG_SIZE 1 450 #define MACB_RX_TYPEID_MATCH_OFFSET 22 451 #define MACB_RX_TYPEID_MATCH_SIZE 1 452 #define MACB_RX_SA4_MATCH_OFFSET 23 453 #define MACB_RX_SA4_MATCH_SIZE 1 454 #define MACB_RX_SA3_MATCH_OFFSET 24 455 #define MACB_RX_SA3_MATCH_SIZE 1 456 #define MACB_RX_SA2_MATCH_OFFSET 25 457 #define MACB_RX_SA2_MATCH_SIZE 1 458 #define MACB_RX_SA1_MATCH_OFFSET 26 459 #define MACB_RX_SA1_MATCH_SIZE 1 460 #define MACB_RX_EXT_MATCH_OFFSET 28 461 #define MACB_RX_EXT_MATCH_SIZE 1 462 #define MACB_RX_UHASH_MATCH_OFFSET 29 463 #define MACB_RX_UHASH_MATCH_SIZE 1 464 #define MACB_RX_MHASH_MATCH_OFFSET 30 465 #define MACB_RX_MHASH_MATCH_SIZE 1 466 #define MACB_RX_BROADCAST_OFFSET 31 467 #define MACB_RX_BROADCAST_SIZE 1 468 469 /* RX checksum offload disabled: bit 24 clear in NCFGR */ 470 #define GEM_RX_TYPEID_MATCH_OFFSET 22 471 #define GEM_RX_TYPEID_MATCH_SIZE 2 472 473 /* RX checksum offload enabled: bit 24 set in NCFGR */ 474 #define GEM_RX_CSUM_OFFSET 22 475 #define GEM_RX_CSUM_SIZE 2 476 477 #define MACB_TX_FRMLEN_OFFSET 0 478 #define MACB_TX_FRMLEN_SIZE 11 479 #define MACB_TX_LAST_OFFSET 15 480 #define MACB_TX_LAST_SIZE 1 481 #define MACB_TX_NOCRC_OFFSET 16 482 #define MACB_TX_NOCRC_SIZE 1 483 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 484 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 485 #define MACB_TX_UNDERRUN_OFFSET 28 486 #define MACB_TX_UNDERRUN_SIZE 1 487 #define MACB_TX_ERROR_OFFSET 29 488 #define MACB_TX_ERROR_SIZE 1 489 #define MACB_TX_WRAP_OFFSET 30 490 #define MACB_TX_WRAP_SIZE 1 491 #define MACB_TX_USED_OFFSET 31 492 #define MACB_TX_USED_SIZE 1 493 494 #define GEM_TX_FRMLEN_OFFSET 0 495 #define GEM_TX_FRMLEN_SIZE 14 496 497 /* Buffer descriptor constants */ 498 #define GEM_RX_CSUM_NONE 0 499 #define GEM_RX_CSUM_IP_ONLY 1 500 #define GEM_RX_CSUM_IP_TCP 2 501 #define GEM_RX_CSUM_IP_UDP 3 502 503 /* limit RX checksum offload to TCP and UDP packets */ 504 #define GEM_RX_CSUM_CHECKED_MASK 2 505 506 /** 507 * struct macb_tx_skb - data about an skb which is being transmitted 508 * @skb: skb currently being transmitted, only set for the last buffer 509 * of the frame 510 * @mapping: DMA address of the skb's fragment buffer 511 * @size: size of the DMA mapped buffer 512 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 513 * false when buffer was mapped with dma_map_single() 514 */ 515 struct macb_tx_skb { 516 struct sk_buff *skb; 517 dma_addr_t mapping; 518 size_t size; 519 bool mapped_as_page; 520 }; 521 522 /* 523 * Hardware-collected statistics. Used when updating the network 524 * device stats by a periodic timer. 525 */ 526 struct macb_stats { 527 u32 rx_pause_frames; 528 u32 tx_ok; 529 u32 tx_single_cols; 530 u32 tx_multiple_cols; 531 u32 rx_ok; 532 u32 rx_fcs_errors; 533 u32 rx_align_errors; 534 u32 tx_deferred; 535 u32 tx_late_cols; 536 u32 tx_excessive_cols; 537 u32 tx_underruns; 538 u32 tx_carrier_errors; 539 u32 rx_resource_errors; 540 u32 rx_overruns; 541 u32 rx_symbol_errors; 542 u32 rx_oversize_pkts; 543 u32 rx_jabbers; 544 u32 rx_undersize_pkts; 545 u32 sqe_test_errors; 546 u32 rx_length_mismatch; 547 u32 tx_pause_frames; 548 }; 549 550 struct gem_stats { 551 u32 tx_octets_31_0; 552 u32 tx_octets_47_32; 553 u32 tx_frames; 554 u32 tx_broadcast_frames; 555 u32 tx_multicast_frames; 556 u32 tx_pause_frames; 557 u32 tx_64_byte_frames; 558 u32 tx_65_127_byte_frames; 559 u32 tx_128_255_byte_frames; 560 u32 tx_256_511_byte_frames; 561 u32 tx_512_1023_byte_frames; 562 u32 tx_1024_1518_byte_frames; 563 u32 tx_greater_than_1518_byte_frames; 564 u32 tx_underrun; 565 u32 tx_single_collision_frames; 566 u32 tx_multiple_collision_frames; 567 u32 tx_excessive_collisions; 568 u32 tx_late_collisions; 569 u32 tx_deferred_frames; 570 u32 tx_carrier_sense_errors; 571 u32 rx_octets_31_0; 572 u32 rx_octets_47_32; 573 u32 rx_frames; 574 u32 rx_broadcast_frames; 575 u32 rx_multicast_frames; 576 u32 rx_pause_frames; 577 u32 rx_64_byte_frames; 578 u32 rx_65_127_byte_frames; 579 u32 rx_128_255_byte_frames; 580 u32 rx_256_511_byte_frames; 581 u32 rx_512_1023_byte_frames; 582 u32 rx_1024_1518_byte_frames; 583 u32 rx_greater_than_1518_byte_frames; 584 u32 rx_undersized_frames; 585 u32 rx_oversize_frames; 586 u32 rx_jabbers; 587 u32 rx_frame_check_sequence_errors; 588 u32 rx_length_field_frame_errors; 589 u32 rx_symbol_errors; 590 u32 rx_alignment_errors; 591 u32 rx_resource_errors; 592 u32 rx_overruns; 593 u32 rx_ip_header_checksum_errors; 594 u32 rx_tcp_checksum_errors; 595 u32 rx_udp_checksum_errors; 596 }; 597 598 struct macb; 599 600 struct macb_or_gem_ops { 601 int (*mog_alloc_rx_buffers)(struct macb *bp); 602 void (*mog_free_rx_buffers)(struct macb *bp); 603 void (*mog_init_rings)(struct macb *bp); 604 int (*mog_rx)(struct macb *bp, int budget); 605 }; 606 607 struct macb_config { 608 u32 caps; 609 unsigned int dma_burst_length; 610 }; 611 612 struct macb_queue { 613 struct macb *bp; 614 int irq; 615 616 unsigned int ISR; 617 unsigned int IER; 618 unsigned int IDR; 619 unsigned int IMR; 620 unsigned int TBQP; 621 622 unsigned int tx_head, tx_tail; 623 struct macb_dma_desc *tx_ring; 624 struct macb_tx_skb *tx_skb; 625 dma_addr_t tx_ring_dma; 626 struct work_struct tx_error_task; 627 }; 628 629 struct macb { 630 void __iomem *regs; 631 632 unsigned int rx_tail; 633 unsigned int rx_prepared_head; 634 struct macb_dma_desc *rx_ring; 635 struct sk_buff **rx_skbuff; 636 void *rx_buffers; 637 size_t rx_buffer_size; 638 639 unsigned int num_queues; 640 struct macb_queue queues[MACB_MAX_QUEUES]; 641 642 spinlock_t lock; 643 struct platform_device *pdev; 644 struct clk *pclk; 645 struct clk *hclk; 646 struct clk *tx_clk; 647 struct net_device *dev; 648 struct napi_struct napi; 649 struct net_device_stats stats; 650 union { 651 struct macb_stats macb; 652 struct gem_stats gem; 653 } hw_stats; 654 655 dma_addr_t rx_ring_dma; 656 dma_addr_t rx_buffers_dma; 657 658 struct macb_or_gem_ops macbgem_ops; 659 660 struct mii_bus *mii_bus; 661 struct phy_device *phy_dev; 662 unsigned int link; 663 unsigned int speed; 664 unsigned int duplex; 665 666 u32 caps; 667 unsigned int dma_burst_length; 668 669 phy_interface_t phy_interface; 670 671 /* AT91RM9200 transmit */ 672 struct sk_buff *skb; /* holds skb until xmit interrupt completes */ 673 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ 674 int skb_length; /* saved skb length for pci_unmap_single */ 675 unsigned int max_tx_length; 676 }; 677 678 extern const struct ethtool_ops macb_ethtool_ops; 679 680 int macb_mii_init(struct macb *bp); 681 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 682 struct net_device_stats *macb_get_stats(struct net_device *dev); 683 void macb_set_rx_mode(struct net_device *dev); 684 void macb_set_hwaddr(struct macb *bp); 685 void macb_get_hwaddr(struct macb *bp); 686 687 static inline bool macb_is_gem(struct macb *bp) 688 { 689 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 690 } 691 692 #endif /* _MACB_H */ 693