1 /* 2 * Atmel MACB Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _MACB_H 11 #define _MACB_H 12 13 #include <linux/phy.h> 14 15 #define MACB_GREGS_NBR 16 16 #define MACB_GREGS_VERSION 2 17 #define MACB_MAX_QUEUES 8 18 19 /* MACB register offsets */ 20 #define MACB_NCR 0x0000 /* Network Control */ 21 #define MACB_NCFGR 0x0004 /* Network Config */ 22 #define MACB_NSR 0x0008 /* Network Status */ 23 #define MACB_TAR 0x000c /* AT91RM9200 only */ 24 #define MACB_TCR 0x0010 /* AT91RM9200 only */ 25 #define MACB_TSR 0x0014 /* Transmit Status */ 26 #define MACB_RBQP 0x0018 /* RX Q Base Address */ 27 #define MACB_TBQP 0x001c /* TX Q Base Address */ 28 #define MACB_RSR 0x0020 /* Receive Status */ 29 #define MACB_ISR 0x0024 /* Interrupt Status */ 30 #define MACB_IER 0x0028 /* Interrupt Enable */ 31 #define MACB_IDR 0x002c /* Interrupt Disable */ 32 #define MACB_IMR 0x0030 /* Interrupt Mask */ 33 #define MACB_MAN 0x0034 /* PHY Maintenance */ 34 #define MACB_PTR 0x0038 35 #define MACB_PFR 0x003c 36 #define MACB_FTO 0x0040 37 #define MACB_SCF 0x0044 38 #define MACB_MCF 0x0048 39 #define MACB_FRO 0x004c 40 #define MACB_FCSE 0x0050 41 #define MACB_ALE 0x0054 42 #define MACB_DTF 0x0058 43 #define MACB_LCOL 0x005c 44 #define MACB_EXCOL 0x0060 45 #define MACB_TUND 0x0064 46 #define MACB_CSE 0x0068 47 #define MACB_RRE 0x006c 48 #define MACB_ROVR 0x0070 49 #define MACB_RSE 0x0074 50 #define MACB_ELE 0x0078 51 #define MACB_RJA 0x007c 52 #define MACB_USF 0x0080 53 #define MACB_STE 0x0084 54 #define MACB_RLE 0x0088 55 #define MACB_TPF 0x008c 56 #define MACB_HRB 0x0090 57 #define MACB_HRT 0x0094 58 #define MACB_SA1B 0x0098 59 #define MACB_SA1T 0x009c 60 #define MACB_SA2B 0x00a0 61 #define MACB_SA2T 0x00a4 62 #define MACB_SA3B 0x00a8 63 #define MACB_SA3T 0x00ac 64 #define MACB_SA4B 0x00b0 65 #define MACB_SA4T 0x00b4 66 #define MACB_TID 0x00b8 67 #define MACB_TPQ 0x00bc 68 #define MACB_USRIO 0x00c0 69 #define MACB_WOL 0x00c4 70 #define MACB_MID 0x00fc 71 #define MACB_TBQPH 0x04C8 72 #define MACB_RBQPH 0x04D4 73 74 /* GEM register offsets. */ 75 #define GEM_NCFGR 0x0004 /* Network Config */ 76 #define GEM_USRIO 0x000c /* User IO */ 77 #define GEM_DMACFG 0x0010 /* DMA Configuration */ 78 #define GEM_JML 0x0048 /* Jumbo Max Length */ 79 #define GEM_HRB 0x0080 /* Hash Bottom */ 80 #define GEM_HRT 0x0084 /* Hash Top */ 81 #define GEM_SA1B 0x0088 /* Specific1 Bottom */ 82 #define GEM_SA1T 0x008C /* Specific1 Top */ 83 #define GEM_SA2B 0x0090 /* Specific2 Bottom */ 84 #define GEM_SA2T 0x0094 /* Specific2 Top */ 85 #define GEM_SA3B 0x0098 /* Specific3 Bottom */ 86 #define GEM_SA3T 0x009C /* Specific3 Top */ 87 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ 88 #define GEM_SA4T 0x00A4 /* Specific4 Top */ 89 #define GEM_OTX 0x0100 /* Octets transmitted */ 90 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ 91 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ 92 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ 93 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ 94 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ 95 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ 96 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ 97 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ 98 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ 99 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ 100 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ 101 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ 102 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ 103 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ 104 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ 105 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ 106 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ 107 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ 108 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ 109 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ 110 #define GEM_ORX 0x0150 /* Octets received */ 111 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ 112 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ 113 #define GEM_RXCNT 0x0158 /* Frames Received Counter */ 114 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ 115 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ 116 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ 117 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ 118 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ 119 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ 120 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ 121 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ 122 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ 123 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ 124 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ 125 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ 126 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ 127 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ 128 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ 129 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ 130 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ 131 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ 132 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ 133 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ 134 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ 135 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ 136 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */ 137 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */ 138 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */ 139 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */ 140 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */ 141 #define GEM_TI 0x01dc /* 1588 Timer Increment */ 142 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */ 143 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */ 144 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */ 145 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */ 146 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */ 147 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ 148 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ 149 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ 150 #define GEM_DCFG1 0x0280 /* Design Config 1 */ 151 #define GEM_DCFG2 0x0284 /* Design Config 2 */ 152 #define GEM_DCFG3 0x0288 /* Design Config 3 */ 153 #define GEM_DCFG4 0x028c /* Design Config 4 */ 154 #define GEM_DCFG5 0x0290 /* Design Config 5 */ 155 #define GEM_DCFG6 0x0294 /* Design Config 6 */ 156 #define GEM_DCFG7 0x0298 /* Design Config 7 */ 157 158 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 159 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 160 #define GEM_TBQPH(hw_q) (0x04C8) 161 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 162 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 163 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 164 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 165 166 /* Bitfields in NCR */ 167 #define MACB_LB_OFFSET 0 /* reserved */ 168 #define MACB_LB_SIZE 1 169 #define MACB_LLB_OFFSET 1 /* Loop back local */ 170 #define MACB_LLB_SIZE 1 171 #define MACB_RE_OFFSET 2 /* Receive enable */ 172 #define MACB_RE_SIZE 1 173 #define MACB_TE_OFFSET 3 /* Transmit enable */ 174 #define MACB_TE_SIZE 1 175 #define MACB_MPE_OFFSET 4 /* Management port enable */ 176 #define MACB_MPE_SIZE 1 177 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ 178 #define MACB_CLRSTAT_SIZE 1 179 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ 180 #define MACB_INCSTAT_SIZE 1 181 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ 182 #define MACB_WESTAT_SIZE 1 183 #define MACB_BP_OFFSET 8 /* Back pressure */ 184 #define MACB_BP_SIZE 1 185 #define MACB_TSTART_OFFSET 9 /* Start transmission */ 186 #define MACB_TSTART_SIZE 1 187 #define MACB_THALT_OFFSET 10 /* Transmit halt */ 188 #define MACB_THALT_SIZE 1 189 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ 190 #define MACB_NCR_TPF_SIZE 1 191 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ 192 #define MACB_TZQ_SIZE 1 193 #define MACB_SRTSM_OFFSET 15 194 195 /* Bitfields in NCFGR */ 196 #define MACB_SPD_OFFSET 0 /* Speed */ 197 #define MACB_SPD_SIZE 1 198 #define MACB_FD_OFFSET 1 /* Full duplex */ 199 #define MACB_FD_SIZE 1 200 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ 201 #define MACB_BIT_RATE_SIZE 1 202 #define MACB_JFRAME_OFFSET 3 /* reserved */ 203 #define MACB_JFRAME_SIZE 1 204 #define MACB_CAF_OFFSET 4 /* Copy all frames */ 205 #define MACB_CAF_SIZE 1 206 #define MACB_NBC_OFFSET 5 /* No broadcast */ 207 #define MACB_NBC_SIZE 1 208 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ 209 #define MACB_NCFGR_MTI_SIZE 1 210 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ 211 #define MACB_UNI_SIZE 1 212 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ 213 #define MACB_BIG_SIZE 1 214 #define MACB_EAE_OFFSET 9 /* External address match enable */ 215 #define MACB_EAE_SIZE 1 216 #define MACB_CLK_OFFSET 10 217 #define MACB_CLK_SIZE 2 218 #define MACB_RTY_OFFSET 12 /* Retry test */ 219 #define MACB_RTY_SIZE 1 220 #define MACB_PAE_OFFSET 13 /* Pause enable */ 221 #define MACB_PAE_SIZE 1 222 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 223 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 224 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ 225 #define MACB_RBOF_SIZE 2 226 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ 227 #define MACB_RLCE_SIZE 1 228 #define MACB_DRFCS_OFFSET 17 /* FCS remove */ 229 #define MACB_DRFCS_SIZE 1 230 #define MACB_EFRHD_OFFSET 18 231 #define MACB_EFRHD_SIZE 1 232 #define MACB_IRXFCS_OFFSET 19 233 #define MACB_IRXFCS_SIZE 1 234 235 /* GEM specific NCFGR bitfields. */ 236 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ 237 #define GEM_GBE_SIZE 1 238 #define GEM_PCSSEL_OFFSET 11 239 #define GEM_PCSSEL_SIZE 1 240 #define GEM_CLK_OFFSET 18 /* MDC clock division */ 241 #define GEM_CLK_SIZE 3 242 #define GEM_DBW_OFFSET 21 /* Data bus width */ 243 #define GEM_DBW_SIZE 2 244 #define GEM_RXCOEN_OFFSET 24 245 #define GEM_RXCOEN_SIZE 1 246 #define GEM_SGMIIEN_OFFSET 27 247 #define GEM_SGMIIEN_SIZE 1 248 249 250 /* Constants for data bus width. */ 251 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 252 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 253 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 254 255 /* Bitfields in DMACFG. */ 256 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 257 #define GEM_FBLDO_SIZE 5 258 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 259 #define GEM_ENDIA_DESC_SIZE 1 260 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ 261 #define GEM_ENDIA_PKT_SIZE 1 262 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 263 #define GEM_RXBMS_SIZE 2 264 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 265 #define GEM_TXPBMS_SIZE 1 266 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 267 #define GEM_TXCOEN_SIZE 1 268 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ 269 #define GEM_RXBS_SIZE 8 270 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ 271 #define GEM_DDRP_SIZE 1 272 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ 273 #define GEM_ADDR64_SIZE 1 274 275 276 /* Bitfields in NSR */ 277 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ 278 #define MACB_NSR_LINK_SIZE 1 279 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ 280 #define MACB_MDIO_SIZE 1 281 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ 282 #define MACB_IDLE_SIZE 1 283 284 /* Bitfields in TSR */ 285 #define MACB_UBR_OFFSET 0 /* Used bit read */ 286 #define MACB_UBR_SIZE 1 287 #define MACB_COL_OFFSET 1 /* Collision occurred */ 288 #define MACB_COL_SIZE 1 289 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ 290 #define MACB_TSR_RLE_SIZE 1 291 #define MACB_TGO_OFFSET 3 /* Transmit go */ 292 #define MACB_TGO_SIZE 1 293 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ 294 #define MACB_BEX_SIZE 1 295 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 296 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 297 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ 298 #define MACB_COMP_SIZE 1 299 #define MACB_UND_OFFSET 6 /* Trnasmit under run */ 300 #define MACB_UND_SIZE 1 301 302 /* Bitfields in RSR */ 303 #define MACB_BNA_OFFSET 0 /* Buffer not available */ 304 #define MACB_BNA_SIZE 1 305 #define MACB_REC_OFFSET 1 /* Frame received */ 306 #define MACB_REC_SIZE 1 307 #define MACB_OVR_OFFSET 2 /* Receive overrun */ 308 #define MACB_OVR_SIZE 1 309 310 /* Bitfields in ISR/IER/IDR/IMR */ 311 #define MACB_MFD_OFFSET 0 /* Management frame sent */ 312 #define MACB_MFD_SIZE 1 313 #define MACB_RCOMP_OFFSET 1 /* Receive complete */ 314 #define MACB_RCOMP_SIZE 1 315 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ 316 #define MACB_RXUBR_SIZE 1 317 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ 318 #define MACB_TXUBR_SIZE 1 319 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ 320 #define MACB_ISR_TUND_SIZE 1 321 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ 322 #define MACB_ISR_RLE_SIZE 1 323 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ 324 #define MACB_TXERR_SIZE 1 325 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ 326 #define MACB_TCOMP_SIZE 1 327 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ 328 #define MACB_ISR_LINK_SIZE 1 329 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ 330 #define MACB_ISR_ROVR_SIZE 1 331 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ 332 #define MACB_HRESP_SIZE 1 333 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ 334 #define MACB_PFR_SIZE 1 335 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ 336 #define MACB_PTZ_SIZE 1 337 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */ 338 #define MACB_WOL_SIZE 1 339 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */ 340 #define MACB_DRQFR_SIZE 1 341 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */ 342 #define MACB_SFR_SIZE 1 343 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */ 344 #define MACB_DRQFT_SIZE 1 345 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */ 346 #define MACB_SFT_SIZE 1 347 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */ 348 #define MACB_PDRQFR_SIZE 1 349 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */ 350 #define MACB_PDRSFR_SIZE 1 351 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */ 352 #define MACB_PDRQFT_SIZE 1 353 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */ 354 #define MACB_PDRSFT_SIZE 1 355 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */ 356 #define MACB_SRI_SIZE 1 357 358 /* Timer increment fields */ 359 #define MACB_TI_CNS_OFFSET 0 360 #define MACB_TI_CNS_SIZE 8 361 #define MACB_TI_ACNS_OFFSET 8 362 #define MACB_TI_ACNS_SIZE 8 363 #define MACB_TI_NIT_OFFSET 16 364 #define MACB_TI_NIT_SIZE 8 365 366 /* Bitfields in MAN */ 367 #define MACB_DATA_OFFSET 0 /* data */ 368 #define MACB_DATA_SIZE 16 369 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ 370 #define MACB_CODE_SIZE 2 371 #define MACB_REGA_OFFSET 18 /* Register address */ 372 #define MACB_REGA_SIZE 5 373 #define MACB_PHYA_OFFSET 23 /* PHY address */ 374 #define MACB_PHYA_SIZE 5 375 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ 376 #define MACB_RW_SIZE 2 377 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ 378 #define MACB_SOF_SIZE 2 379 380 /* Bitfields in USRIO (AVR32) */ 381 #define MACB_MII_OFFSET 0 382 #define MACB_MII_SIZE 1 383 #define MACB_EAM_OFFSET 1 384 #define MACB_EAM_SIZE 1 385 #define MACB_TX_PAUSE_OFFSET 2 386 #define MACB_TX_PAUSE_SIZE 1 387 #define MACB_TX_PAUSE_ZERO_OFFSET 3 388 #define MACB_TX_PAUSE_ZERO_SIZE 1 389 390 /* Bitfields in USRIO (AT91) */ 391 #define MACB_RMII_OFFSET 0 392 #define MACB_RMII_SIZE 1 393 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 394 #define GEM_RGMII_SIZE 1 395 #define MACB_CLKEN_OFFSET 1 396 #define MACB_CLKEN_SIZE 1 397 398 /* Bitfields in WOL */ 399 #define MACB_IP_OFFSET 0 400 #define MACB_IP_SIZE 16 401 #define MACB_MAG_OFFSET 16 402 #define MACB_MAG_SIZE 1 403 #define MACB_ARP_OFFSET 17 404 #define MACB_ARP_SIZE 1 405 #define MACB_SA1_OFFSET 18 406 #define MACB_SA1_SIZE 1 407 #define MACB_WOL_MTI_OFFSET 19 408 #define MACB_WOL_MTI_SIZE 1 409 410 /* Bitfields in MID */ 411 #define MACB_IDNUM_OFFSET 16 412 #define MACB_IDNUM_SIZE 12 413 #define MACB_REV_OFFSET 0 414 #define MACB_REV_SIZE 16 415 416 /* Bitfields in DCFG1. */ 417 #define GEM_IRQCOR_OFFSET 23 418 #define GEM_IRQCOR_SIZE 1 419 #define GEM_DBWDEF_OFFSET 25 420 #define GEM_DBWDEF_SIZE 3 421 422 /* Bitfields in DCFG2. */ 423 #define GEM_RX_PKT_BUFF_OFFSET 20 424 #define GEM_RX_PKT_BUFF_SIZE 1 425 #define GEM_TX_PKT_BUFF_OFFSET 21 426 #define GEM_TX_PKT_BUFF_SIZE 1 427 428 /* Bitfields in DCFG6. */ 429 #define GEM_PBUF_LSO_OFFSET 27 430 #define GEM_PBUF_LSO_SIZE 1 431 #define GEM_DAW64_OFFSET 23 432 #define GEM_DAW64_SIZE 1 433 434 /* Bitfields in TISUBN */ 435 #define GEM_SUBNSINCR_OFFSET 0 436 #define GEM_SUBNSINCR_SIZE 16 437 438 /* Bitfields in TI */ 439 #define GEM_NSINCR_OFFSET 0 440 #define GEM_NSINCR_SIZE 8 441 442 /* Bitfields in ADJ */ 443 #define GEM_ADDSUB_OFFSET 31 444 #define GEM_ADDSUB_SIZE 1 445 /* Constants for CLK */ 446 #define MACB_CLK_DIV8 0 447 #define MACB_CLK_DIV16 1 448 #define MACB_CLK_DIV32 2 449 #define MACB_CLK_DIV64 3 450 451 /* GEM specific constants for CLK. */ 452 #define GEM_CLK_DIV8 0 453 #define GEM_CLK_DIV16 1 454 #define GEM_CLK_DIV32 2 455 #define GEM_CLK_DIV48 3 456 #define GEM_CLK_DIV64 4 457 #define GEM_CLK_DIV96 5 458 459 /* Constants for MAN register */ 460 #define MACB_MAN_SOF 1 461 #define MACB_MAN_WRITE 1 462 #define MACB_MAN_READ 2 463 #define MACB_MAN_CODE 2 464 465 /* Capability mask bits */ 466 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 467 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 468 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 469 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 470 #define MACB_CAPS_USRIO_DISABLED 0x00000010 471 #define MACB_CAPS_JUMBO 0x00000020 472 #define MACB_CAPS_GEM_HAS_PTP 0x00000040 473 #define MACB_CAPS_FIFO_MODE 0x10000000 474 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 475 #define MACB_CAPS_SG_DISABLED 0x40000000 476 #define MACB_CAPS_MACB_IS_GEM 0x80000000 477 478 /* LSO settings */ 479 #define MACB_LSO_UFO_ENABLE 0x01 480 #define MACB_LSO_TSO_ENABLE 0x02 481 482 /* Bit manipulation macros */ 483 #define MACB_BIT(name) \ 484 (1 << MACB_##name##_OFFSET) 485 #define MACB_BF(name,value) \ 486 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 487 << MACB_##name##_OFFSET) 488 #define MACB_BFEXT(name,value)\ 489 (((value) >> MACB_##name##_OFFSET) \ 490 & ((1 << MACB_##name##_SIZE) - 1)) 491 #define MACB_BFINS(name,value,old) \ 492 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 493 << MACB_##name##_OFFSET)) \ 494 | MACB_BF(name,value)) 495 496 #define GEM_BIT(name) \ 497 (1 << GEM_##name##_OFFSET) 498 #define GEM_BF(name, value) \ 499 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 500 << GEM_##name##_OFFSET) 501 #define GEM_BFEXT(name, value)\ 502 (((value) >> GEM_##name##_OFFSET) \ 503 & ((1 << GEM_##name##_SIZE) - 1)) 504 #define GEM_BFINS(name, value, old) \ 505 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 506 << GEM_##name##_OFFSET)) \ 507 | GEM_BF(name, value)) 508 509 /* Register access macros */ 510 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg) 511 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value)) 512 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg) 513 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value)) 514 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg) 515 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value)) 516 517 /* Conditional GEM/MACB macros. These perform the operation to the correct 518 * register dependent on whether the device is a GEM or a MACB. For registers 519 * and bitfields that are common across both devices, use macb_{read,write}l 520 * to avoid the cost of the conditional. 521 */ 522 #define macb_or_gem_writel(__bp, __reg, __value) \ 523 ({ \ 524 if (macb_is_gem((__bp))) \ 525 gem_writel((__bp), __reg, __value); \ 526 else \ 527 macb_writel((__bp), __reg, __value); \ 528 }) 529 530 #define macb_or_gem_readl(__bp, __reg) \ 531 ({ \ 532 u32 __v; \ 533 if (macb_is_gem((__bp))) \ 534 __v = gem_readl((__bp), __reg); \ 535 else \ 536 __v = macb_readl((__bp), __reg); \ 537 __v; \ 538 }) 539 540 /* struct macb_dma_desc - Hardware DMA descriptor 541 * @addr: DMA address of data buffer 542 * @ctrl: Control and status bits 543 */ 544 struct macb_dma_desc { 545 u32 addr; 546 u32 ctrl; 547 }; 548 549 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 550 enum macb_hw_dma_cap { 551 HW_DMA_CAP_32B, 552 HW_DMA_CAP_64B, 553 }; 554 555 struct macb_dma_desc_64 { 556 u32 addrh; 557 u32 resvd; 558 }; 559 #endif 560 561 /* DMA descriptor bitfields */ 562 #define MACB_RX_USED_OFFSET 0 563 #define MACB_RX_USED_SIZE 1 564 #define MACB_RX_WRAP_OFFSET 1 565 #define MACB_RX_WRAP_SIZE 1 566 #define MACB_RX_WADDR_OFFSET 2 567 #define MACB_RX_WADDR_SIZE 30 568 569 #define MACB_RX_FRMLEN_OFFSET 0 570 #define MACB_RX_FRMLEN_SIZE 12 571 #define MACB_RX_OFFSET_OFFSET 12 572 #define MACB_RX_OFFSET_SIZE 2 573 #define MACB_RX_SOF_OFFSET 14 574 #define MACB_RX_SOF_SIZE 1 575 #define MACB_RX_EOF_OFFSET 15 576 #define MACB_RX_EOF_SIZE 1 577 #define MACB_RX_CFI_OFFSET 16 578 #define MACB_RX_CFI_SIZE 1 579 #define MACB_RX_VLAN_PRI_OFFSET 17 580 #define MACB_RX_VLAN_PRI_SIZE 3 581 #define MACB_RX_PRI_TAG_OFFSET 20 582 #define MACB_RX_PRI_TAG_SIZE 1 583 #define MACB_RX_VLAN_TAG_OFFSET 21 584 #define MACB_RX_VLAN_TAG_SIZE 1 585 #define MACB_RX_TYPEID_MATCH_OFFSET 22 586 #define MACB_RX_TYPEID_MATCH_SIZE 1 587 #define MACB_RX_SA4_MATCH_OFFSET 23 588 #define MACB_RX_SA4_MATCH_SIZE 1 589 #define MACB_RX_SA3_MATCH_OFFSET 24 590 #define MACB_RX_SA3_MATCH_SIZE 1 591 #define MACB_RX_SA2_MATCH_OFFSET 25 592 #define MACB_RX_SA2_MATCH_SIZE 1 593 #define MACB_RX_SA1_MATCH_OFFSET 26 594 #define MACB_RX_SA1_MATCH_SIZE 1 595 #define MACB_RX_EXT_MATCH_OFFSET 28 596 #define MACB_RX_EXT_MATCH_SIZE 1 597 #define MACB_RX_UHASH_MATCH_OFFSET 29 598 #define MACB_RX_UHASH_MATCH_SIZE 1 599 #define MACB_RX_MHASH_MATCH_OFFSET 30 600 #define MACB_RX_MHASH_MATCH_SIZE 1 601 #define MACB_RX_BROADCAST_OFFSET 31 602 #define MACB_RX_BROADCAST_SIZE 1 603 604 #define MACB_RX_FRMLEN_MASK 0xFFF 605 #define MACB_RX_JFRMLEN_MASK 0x3FFF 606 607 /* RX checksum offload disabled: bit 24 clear in NCFGR */ 608 #define GEM_RX_TYPEID_MATCH_OFFSET 22 609 #define GEM_RX_TYPEID_MATCH_SIZE 2 610 611 /* RX checksum offload enabled: bit 24 set in NCFGR */ 612 #define GEM_RX_CSUM_OFFSET 22 613 #define GEM_RX_CSUM_SIZE 2 614 615 #define MACB_TX_FRMLEN_OFFSET 0 616 #define MACB_TX_FRMLEN_SIZE 11 617 #define MACB_TX_LAST_OFFSET 15 618 #define MACB_TX_LAST_SIZE 1 619 #define MACB_TX_NOCRC_OFFSET 16 620 #define MACB_TX_NOCRC_SIZE 1 621 #define MACB_MSS_MFS_OFFSET 16 622 #define MACB_MSS_MFS_SIZE 14 623 #define MACB_TX_LSO_OFFSET 17 624 #define MACB_TX_LSO_SIZE 2 625 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19 626 #define MACB_TX_TCP_SEQ_SRC_SIZE 1 627 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 628 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 629 #define MACB_TX_UNDERRUN_OFFSET 28 630 #define MACB_TX_UNDERRUN_SIZE 1 631 #define MACB_TX_ERROR_OFFSET 29 632 #define MACB_TX_ERROR_SIZE 1 633 #define MACB_TX_WRAP_OFFSET 30 634 #define MACB_TX_WRAP_SIZE 1 635 #define MACB_TX_USED_OFFSET 31 636 #define MACB_TX_USED_SIZE 1 637 638 #define GEM_TX_FRMLEN_OFFSET 0 639 #define GEM_TX_FRMLEN_SIZE 14 640 641 /* Buffer descriptor constants */ 642 #define GEM_RX_CSUM_NONE 0 643 #define GEM_RX_CSUM_IP_ONLY 1 644 #define GEM_RX_CSUM_IP_TCP 2 645 #define GEM_RX_CSUM_IP_UDP 3 646 647 /* limit RX checksum offload to TCP and UDP packets */ 648 #define GEM_RX_CSUM_CHECKED_MASK 2 649 650 /* struct macb_tx_skb - data about an skb which is being transmitted 651 * @skb: skb currently being transmitted, only set for the last buffer 652 * of the frame 653 * @mapping: DMA address of the skb's fragment buffer 654 * @size: size of the DMA mapped buffer 655 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 656 * false when buffer was mapped with dma_map_single() 657 */ 658 struct macb_tx_skb { 659 struct sk_buff *skb; 660 dma_addr_t mapping; 661 size_t size; 662 bool mapped_as_page; 663 }; 664 665 /* Hardware-collected statistics. Used when updating the network 666 * device stats by a periodic timer. 667 */ 668 struct macb_stats { 669 u32 rx_pause_frames; 670 u32 tx_ok; 671 u32 tx_single_cols; 672 u32 tx_multiple_cols; 673 u32 rx_ok; 674 u32 rx_fcs_errors; 675 u32 rx_align_errors; 676 u32 tx_deferred; 677 u32 tx_late_cols; 678 u32 tx_excessive_cols; 679 u32 tx_underruns; 680 u32 tx_carrier_errors; 681 u32 rx_resource_errors; 682 u32 rx_overruns; 683 u32 rx_symbol_errors; 684 u32 rx_oversize_pkts; 685 u32 rx_jabbers; 686 u32 rx_undersize_pkts; 687 u32 sqe_test_errors; 688 u32 rx_length_mismatch; 689 u32 tx_pause_frames; 690 }; 691 692 struct gem_stats { 693 u32 tx_octets_31_0; 694 u32 tx_octets_47_32; 695 u32 tx_frames; 696 u32 tx_broadcast_frames; 697 u32 tx_multicast_frames; 698 u32 tx_pause_frames; 699 u32 tx_64_byte_frames; 700 u32 tx_65_127_byte_frames; 701 u32 tx_128_255_byte_frames; 702 u32 tx_256_511_byte_frames; 703 u32 tx_512_1023_byte_frames; 704 u32 tx_1024_1518_byte_frames; 705 u32 tx_greater_than_1518_byte_frames; 706 u32 tx_underrun; 707 u32 tx_single_collision_frames; 708 u32 tx_multiple_collision_frames; 709 u32 tx_excessive_collisions; 710 u32 tx_late_collisions; 711 u32 tx_deferred_frames; 712 u32 tx_carrier_sense_errors; 713 u32 rx_octets_31_0; 714 u32 rx_octets_47_32; 715 u32 rx_frames; 716 u32 rx_broadcast_frames; 717 u32 rx_multicast_frames; 718 u32 rx_pause_frames; 719 u32 rx_64_byte_frames; 720 u32 rx_65_127_byte_frames; 721 u32 rx_128_255_byte_frames; 722 u32 rx_256_511_byte_frames; 723 u32 rx_512_1023_byte_frames; 724 u32 rx_1024_1518_byte_frames; 725 u32 rx_greater_than_1518_byte_frames; 726 u32 rx_undersized_frames; 727 u32 rx_oversize_frames; 728 u32 rx_jabbers; 729 u32 rx_frame_check_sequence_errors; 730 u32 rx_length_field_frame_errors; 731 u32 rx_symbol_errors; 732 u32 rx_alignment_errors; 733 u32 rx_resource_errors; 734 u32 rx_overruns; 735 u32 rx_ip_header_checksum_errors; 736 u32 rx_tcp_checksum_errors; 737 u32 rx_udp_checksum_errors; 738 }; 739 740 /* Describes the name and offset of an individual statistic register, as 741 * returned by `ethtool -S`. Also describes which net_device_stats statistics 742 * this register should contribute to. 743 */ 744 struct gem_statistic { 745 char stat_string[ETH_GSTRING_LEN]; 746 int offset; 747 u32 stat_bits; 748 }; 749 750 /* Bitfield defs for net_device_stat statistics */ 751 #define GEM_NDS_RXERR_OFFSET 0 752 #define GEM_NDS_RXLENERR_OFFSET 1 753 #define GEM_NDS_RXOVERERR_OFFSET 2 754 #define GEM_NDS_RXCRCERR_OFFSET 3 755 #define GEM_NDS_RXFRAMEERR_OFFSET 4 756 #define GEM_NDS_RXFIFOERR_OFFSET 5 757 #define GEM_NDS_TXERR_OFFSET 6 758 #define GEM_NDS_TXABORTEDERR_OFFSET 7 759 #define GEM_NDS_TXCARRIERERR_OFFSET 8 760 #define GEM_NDS_TXFIFOERR_OFFSET 9 761 #define GEM_NDS_COLLISIONS_OFFSET 10 762 763 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) 764 #define GEM_STAT_TITLE_BITS(name, title, bits) { \ 765 .stat_string = title, \ 766 .offset = GEM_##name, \ 767 .stat_bits = bits \ 768 } 769 770 /* list of gem statistic registers. The names MUST match the 771 * corresponding GEM_* definitions. 772 */ 773 static const struct gem_statistic gem_statistics[] = { 774 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ 775 GEM_STAT_TITLE(TXCNT, "tx_frames"), 776 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), 777 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), 778 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), 779 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), 780 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), 781 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), 782 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), 783 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), 784 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), 785 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), 786 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", 787 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), 788 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", 789 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 790 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", 791 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 792 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", 793 GEM_BIT(NDS_TXERR)| 794 GEM_BIT(NDS_TXABORTEDERR)| 795 GEM_BIT(NDS_COLLISIONS)), 796 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", 797 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 798 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), 799 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", 800 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 801 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ 802 GEM_STAT_TITLE(RXCNT, "rx_frames"), 803 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), 804 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), 805 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), 806 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), 807 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), 808 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), 809 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), 810 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), 811 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), 812 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), 813 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", 814 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 815 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", 816 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 817 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", 818 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 819 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", 820 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), 821 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", 822 GEM_BIT(NDS_RXERR)), 823 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", 824 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), 825 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", 826 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 827 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", 828 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 829 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", 830 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), 831 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", 832 GEM_BIT(NDS_RXERR)), 833 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", 834 GEM_BIT(NDS_RXERR)), 835 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", 836 GEM_BIT(NDS_RXERR)), 837 }; 838 839 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) 840 841 struct macb; 842 843 struct macb_or_gem_ops { 844 int (*mog_alloc_rx_buffers)(struct macb *bp); 845 void (*mog_free_rx_buffers)(struct macb *bp); 846 void (*mog_init_rings)(struct macb *bp); 847 int (*mog_rx)(struct macb *bp, int budget); 848 }; 849 850 /* MACB-PTP interface: adapt to platform needs. */ 851 struct macb_ptp_info { 852 void (*ptp_init)(struct net_device *ndev); 853 void (*ptp_remove)(struct net_device *ndev); 854 s32 (*get_ptp_max_adj)(void); 855 unsigned int (*get_tsu_rate)(struct macb *bp); 856 int (*get_ts_info)(struct net_device *dev, 857 struct ethtool_ts_info *info); 858 int (*get_hwtst)(struct net_device *netdev, 859 struct ifreq *ifr); 860 int (*set_hwtst)(struct net_device *netdev, 861 struct ifreq *ifr, int cmd); 862 }; 863 864 struct macb_config { 865 u32 caps; 866 unsigned int dma_burst_length; 867 int (*clk_init)(struct platform_device *pdev, struct clk **pclk, 868 struct clk **hclk, struct clk **tx_clk, 869 struct clk **rx_clk); 870 int (*init)(struct platform_device *pdev); 871 int jumbo_max_len; 872 }; 873 874 struct macb_queue { 875 struct macb *bp; 876 int irq; 877 878 unsigned int ISR; 879 unsigned int IER; 880 unsigned int IDR; 881 unsigned int IMR; 882 unsigned int TBQP; 883 unsigned int TBQPH; 884 885 unsigned int tx_head, tx_tail; 886 struct macb_dma_desc *tx_ring; 887 struct macb_tx_skb *tx_skb; 888 dma_addr_t tx_ring_dma; 889 struct work_struct tx_error_task; 890 }; 891 892 struct macb { 893 void __iomem *regs; 894 bool native_io; 895 896 /* hardware IO accessors */ 897 u32 (*macb_reg_readl)(struct macb *bp, int offset); 898 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value); 899 900 unsigned int rx_tail; 901 unsigned int rx_prepared_head; 902 struct macb_dma_desc *rx_ring; 903 struct sk_buff **rx_skbuff; 904 void *rx_buffers; 905 size_t rx_buffer_size; 906 907 unsigned int rx_ring_size; 908 unsigned int tx_ring_size; 909 910 unsigned int num_queues; 911 unsigned int queue_mask; 912 struct macb_queue queues[MACB_MAX_QUEUES]; 913 914 spinlock_t lock; 915 struct platform_device *pdev; 916 struct clk *pclk; 917 struct clk *hclk; 918 struct clk *tx_clk; 919 struct clk *rx_clk; 920 struct net_device *dev; 921 struct napi_struct napi; 922 struct net_device_stats stats; 923 union { 924 struct macb_stats macb; 925 struct gem_stats gem; 926 } hw_stats; 927 928 dma_addr_t rx_ring_dma; 929 dma_addr_t rx_buffers_dma; 930 931 struct macb_or_gem_ops macbgem_ops; 932 933 struct mii_bus *mii_bus; 934 int link; 935 int speed; 936 int duplex; 937 938 u32 caps; 939 unsigned int dma_burst_length; 940 941 phy_interface_t phy_interface; 942 struct gpio_desc *reset_gpio; 943 944 /* AT91RM9200 transmit */ 945 struct sk_buff *skb; /* holds skb until xmit interrupt completes */ 946 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ 947 int skb_length; /* saved skb length for pci_unmap_single */ 948 unsigned int max_tx_length; 949 950 u64 ethtool_stats[GEM_STATS_LEN]; 951 952 unsigned int rx_frm_len_mask; 953 unsigned int jumbo_max_len; 954 955 u32 wol; 956 957 struct macb_ptp_info *ptp_info; /* macb-ptp interface */ 958 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 959 enum macb_hw_dma_cap hw_dma_cap; 960 #endif 961 }; 962 963 static inline bool macb_is_gem(struct macb *bp) 964 { 965 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 966 } 967 968 static inline bool gem_has_ptp(struct macb *bp) 969 { 970 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP); 971 } 972 973 #endif /* _MACB_H */ 974