1 /* 2 * Atmel MACB Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _MACB_H 11 #define _MACB_H 12 13 #include <linux/phy.h> 14 #include <linux/ptp_clock_kernel.h> 15 #include <linux/net_tstamp.h> 16 17 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP) 18 #define MACB_EXT_DESC 19 #endif 20 21 #define MACB_GREGS_NBR 16 22 #define MACB_GREGS_VERSION 2 23 #define MACB_MAX_QUEUES 8 24 25 /* MACB register offsets */ 26 #define MACB_NCR 0x0000 /* Network Control */ 27 #define MACB_NCFGR 0x0004 /* Network Config */ 28 #define MACB_NSR 0x0008 /* Network Status */ 29 #define MACB_TAR 0x000c /* AT91RM9200 only */ 30 #define MACB_TCR 0x0010 /* AT91RM9200 only */ 31 #define MACB_TSR 0x0014 /* Transmit Status */ 32 #define MACB_RBQP 0x0018 /* RX Q Base Address */ 33 #define MACB_TBQP 0x001c /* TX Q Base Address */ 34 #define MACB_RSR 0x0020 /* Receive Status */ 35 #define MACB_ISR 0x0024 /* Interrupt Status */ 36 #define MACB_IER 0x0028 /* Interrupt Enable */ 37 #define MACB_IDR 0x002c /* Interrupt Disable */ 38 #define MACB_IMR 0x0030 /* Interrupt Mask */ 39 #define MACB_MAN 0x0034 /* PHY Maintenance */ 40 #define MACB_PTR 0x0038 41 #define MACB_PFR 0x003c 42 #define MACB_FTO 0x0040 43 #define MACB_SCF 0x0044 44 #define MACB_MCF 0x0048 45 #define MACB_FRO 0x004c 46 #define MACB_FCSE 0x0050 47 #define MACB_ALE 0x0054 48 #define MACB_DTF 0x0058 49 #define MACB_LCOL 0x005c 50 #define MACB_EXCOL 0x0060 51 #define MACB_TUND 0x0064 52 #define MACB_CSE 0x0068 53 #define MACB_RRE 0x006c 54 #define MACB_ROVR 0x0070 55 #define MACB_RSE 0x0074 56 #define MACB_ELE 0x0078 57 #define MACB_RJA 0x007c 58 #define MACB_USF 0x0080 59 #define MACB_STE 0x0084 60 #define MACB_RLE 0x0088 61 #define MACB_TPF 0x008c 62 #define MACB_HRB 0x0090 63 #define MACB_HRT 0x0094 64 #define MACB_SA1B 0x0098 65 #define MACB_SA1T 0x009c 66 #define MACB_SA2B 0x00a0 67 #define MACB_SA2T 0x00a4 68 #define MACB_SA3B 0x00a8 69 #define MACB_SA3T 0x00ac 70 #define MACB_SA4B 0x00b0 71 #define MACB_SA4T 0x00b4 72 #define MACB_TID 0x00b8 73 #define MACB_TPQ 0x00bc 74 #define MACB_USRIO 0x00c0 75 #define MACB_WOL 0x00c4 76 #define MACB_MID 0x00fc 77 #define MACB_TBQPH 0x04C8 78 #define MACB_RBQPH 0x04D4 79 80 /* GEM register offsets. */ 81 #define GEM_NCFGR 0x0004 /* Network Config */ 82 #define GEM_USRIO 0x000c /* User IO */ 83 #define GEM_DMACFG 0x0010 /* DMA Configuration */ 84 #define GEM_JML 0x0048 /* Jumbo Max Length */ 85 #define GEM_HRB 0x0080 /* Hash Bottom */ 86 #define GEM_HRT 0x0084 /* Hash Top */ 87 #define GEM_SA1B 0x0088 /* Specific1 Bottom */ 88 #define GEM_SA1T 0x008C /* Specific1 Top */ 89 #define GEM_SA2B 0x0090 /* Specific2 Bottom */ 90 #define GEM_SA2T 0x0094 /* Specific2 Top */ 91 #define GEM_SA3B 0x0098 /* Specific3 Bottom */ 92 #define GEM_SA3T 0x009C /* Specific3 Top */ 93 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ 94 #define GEM_SA4T 0x00A4 /* Specific4 Top */ 95 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */ 96 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */ 97 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */ 98 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */ 99 #define GEM_OTX 0x0100 /* Octets transmitted */ 100 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ 101 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ 102 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ 103 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ 104 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ 105 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ 106 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ 107 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ 108 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ 109 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ 110 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ 111 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ 112 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ 113 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ 114 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ 115 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ 116 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ 117 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ 118 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ 119 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ 120 #define GEM_ORX 0x0150 /* Octets received */ 121 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ 122 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ 123 #define GEM_RXCNT 0x0158 /* Frames Received Counter */ 124 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ 125 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ 126 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ 127 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ 128 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ 129 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ 130 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ 131 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ 132 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ 133 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ 134 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ 135 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ 136 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ 137 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ 138 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ 139 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ 140 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ 141 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ 142 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ 143 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ 144 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ 145 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ 146 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */ 147 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */ 148 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */ 149 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */ 150 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */ 151 #define GEM_TI 0x01dc /* 1588 Timer Increment */ 152 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */ 153 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */ 154 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */ 155 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */ 156 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */ 157 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ 158 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ 159 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ 160 #define GEM_DCFG1 0x0280 /* Design Config 1 */ 161 #define GEM_DCFG2 0x0284 /* Design Config 2 */ 162 #define GEM_DCFG3 0x0288 /* Design Config 3 */ 163 #define GEM_DCFG4 0x028c /* Design Config 4 */ 164 #define GEM_DCFG5 0x0290 /* Design Config 5 */ 165 #define GEM_DCFG6 0x0294 /* Design Config 6 */ 166 #define GEM_DCFG7 0x0298 /* Design Config 7 */ 167 #define GEM_DCFG8 0x029C /* Design Config 8 */ 168 169 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ 170 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ 171 172 /* Screener Type 2 match registers */ 173 #define GEM_SCRT2 0x540 174 175 /* EtherType registers */ 176 #define GEM_ETHT 0x06E0 177 178 /* Type 2 compare registers */ 179 #define GEM_T2CMPW0 0x0700 180 #define GEM_T2CMPW1 0x0704 181 #define T2CMP_OFST(t2idx) (t2idx * 2) 182 183 /* type 2 compare registers 184 * each location requires 3 compare regs 185 */ 186 #define GEM_IP4SRC_CMP(idx) (idx * 3) 187 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1) 188 #define GEM_PORT_CMP(idx) (idx * 3 + 2) 189 190 /* Which screening type 2 EtherType register will be used (0 - 7) */ 191 #define SCRT2_ETHT 0 192 193 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 194 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 195 #define GEM_TBQPH(hw_q) (0x04C8) 196 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 197 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) 198 #define GEM_RBQPH(hw_q) (0x04D4) 199 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 200 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 201 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 202 203 /* Bitfields in NCR */ 204 #define MACB_LB_OFFSET 0 /* reserved */ 205 #define MACB_LB_SIZE 1 206 #define MACB_LLB_OFFSET 1 /* Loop back local */ 207 #define MACB_LLB_SIZE 1 208 #define MACB_RE_OFFSET 2 /* Receive enable */ 209 #define MACB_RE_SIZE 1 210 #define MACB_TE_OFFSET 3 /* Transmit enable */ 211 #define MACB_TE_SIZE 1 212 #define MACB_MPE_OFFSET 4 /* Management port enable */ 213 #define MACB_MPE_SIZE 1 214 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ 215 #define MACB_CLRSTAT_SIZE 1 216 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ 217 #define MACB_INCSTAT_SIZE 1 218 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ 219 #define MACB_WESTAT_SIZE 1 220 #define MACB_BP_OFFSET 8 /* Back pressure */ 221 #define MACB_BP_SIZE 1 222 #define MACB_TSTART_OFFSET 9 /* Start transmission */ 223 #define MACB_TSTART_SIZE 1 224 #define MACB_THALT_OFFSET 10 /* Transmit halt */ 225 #define MACB_THALT_SIZE 1 226 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ 227 #define MACB_NCR_TPF_SIZE 1 228 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ 229 #define MACB_TZQ_SIZE 1 230 #define MACB_SRTSM_OFFSET 15 231 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ 232 #define MACB_OSSMODE_SIZE 1 233 234 /* Bitfields in NCFGR */ 235 #define MACB_SPD_OFFSET 0 /* Speed */ 236 #define MACB_SPD_SIZE 1 237 #define MACB_FD_OFFSET 1 /* Full duplex */ 238 #define MACB_FD_SIZE 1 239 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ 240 #define MACB_BIT_RATE_SIZE 1 241 #define MACB_JFRAME_OFFSET 3 /* reserved */ 242 #define MACB_JFRAME_SIZE 1 243 #define MACB_CAF_OFFSET 4 /* Copy all frames */ 244 #define MACB_CAF_SIZE 1 245 #define MACB_NBC_OFFSET 5 /* No broadcast */ 246 #define MACB_NBC_SIZE 1 247 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ 248 #define MACB_NCFGR_MTI_SIZE 1 249 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ 250 #define MACB_UNI_SIZE 1 251 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ 252 #define MACB_BIG_SIZE 1 253 #define MACB_EAE_OFFSET 9 /* External address match enable */ 254 #define MACB_EAE_SIZE 1 255 #define MACB_CLK_OFFSET 10 256 #define MACB_CLK_SIZE 2 257 #define MACB_RTY_OFFSET 12 /* Retry test */ 258 #define MACB_RTY_SIZE 1 259 #define MACB_PAE_OFFSET 13 /* Pause enable */ 260 #define MACB_PAE_SIZE 1 261 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 262 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 263 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ 264 #define MACB_RBOF_SIZE 2 265 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ 266 #define MACB_RLCE_SIZE 1 267 #define MACB_DRFCS_OFFSET 17 /* FCS remove */ 268 #define MACB_DRFCS_SIZE 1 269 #define MACB_EFRHD_OFFSET 18 270 #define MACB_EFRHD_SIZE 1 271 #define MACB_IRXFCS_OFFSET 19 272 #define MACB_IRXFCS_SIZE 1 273 274 /* GEM specific NCFGR bitfields. */ 275 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ 276 #define GEM_GBE_SIZE 1 277 #define GEM_PCSSEL_OFFSET 11 278 #define GEM_PCSSEL_SIZE 1 279 #define GEM_CLK_OFFSET 18 /* MDC clock division */ 280 #define GEM_CLK_SIZE 3 281 #define GEM_DBW_OFFSET 21 /* Data bus width */ 282 #define GEM_DBW_SIZE 2 283 #define GEM_RXCOEN_OFFSET 24 284 #define GEM_RXCOEN_SIZE 1 285 #define GEM_SGMIIEN_OFFSET 27 286 #define GEM_SGMIIEN_SIZE 1 287 288 289 /* Constants for data bus width. */ 290 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 291 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 292 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 293 294 /* Bitfields in DMACFG. */ 295 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 296 #define GEM_FBLDO_SIZE 5 297 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 298 #define GEM_ENDIA_DESC_SIZE 1 299 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ 300 #define GEM_ENDIA_PKT_SIZE 1 301 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 302 #define GEM_RXBMS_SIZE 2 303 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 304 #define GEM_TXPBMS_SIZE 1 305 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 306 #define GEM_TXCOEN_SIZE 1 307 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ 308 #define GEM_RXBS_SIZE 8 309 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ 310 #define GEM_DDRP_SIZE 1 311 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */ 312 #define GEM_RXEXT_SIZE 1 313 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */ 314 #define GEM_TXEXT_SIZE 1 315 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ 316 #define GEM_ADDR64_SIZE 1 317 318 319 /* Bitfields in NSR */ 320 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ 321 #define MACB_NSR_LINK_SIZE 1 322 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ 323 #define MACB_MDIO_SIZE 1 324 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ 325 #define MACB_IDLE_SIZE 1 326 327 /* Bitfields in TSR */ 328 #define MACB_UBR_OFFSET 0 /* Used bit read */ 329 #define MACB_UBR_SIZE 1 330 #define MACB_COL_OFFSET 1 /* Collision occurred */ 331 #define MACB_COL_SIZE 1 332 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ 333 #define MACB_TSR_RLE_SIZE 1 334 #define MACB_TGO_OFFSET 3 /* Transmit go */ 335 #define MACB_TGO_SIZE 1 336 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ 337 #define MACB_BEX_SIZE 1 338 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 339 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 340 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ 341 #define MACB_COMP_SIZE 1 342 #define MACB_UND_OFFSET 6 /* Trnasmit under run */ 343 #define MACB_UND_SIZE 1 344 345 /* Bitfields in RSR */ 346 #define MACB_BNA_OFFSET 0 /* Buffer not available */ 347 #define MACB_BNA_SIZE 1 348 #define MACB_REC_OFFSET 1 /* Frame received */ 349 #define MACB_REC_SIZE 1 350 #define MACB_OVR_OFFSET 2 /* Receive overrun */ 351 #define MACB_OVR_SIZE 1 352 353 /* Bitfields in ISR/IER/IDR/IMR */ 354 #define MACB_MFD_OFFSET 0 /* Management frame sent */ 355 #define MACB_MFD_SIZE 1 356 #define MACB_RCOMP_OFFSET 1 /* Receive complete */ 357 #define MACB_RCOMP_SIZE 1 358 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ 359 #define MACB_RXUBR_SIZE 1 360 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ 361 #define MACB_TXUBR_SIZE 1 362 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ 363 #define MACB_ISR_TUND_SIZE 1 364 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ 365 #define MACB_ISR_RLE_SIZE 1 366 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ 367 #define MACB_TXERR_SIZE 1 368 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ 369 #define MACB_TCOMP_SIZE 1 370 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ 371 #define MACB_ISR_LINK_SIZE 1 372 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ 373 #define MACB_ISR_ROVR_SIZE 1 374 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ 375 #define MACB_HRESP_SIZE 1 376 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ 377 #define MACB_PFR_SIZE 1 378 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ 379 #define MACB_PTZ_SIZE 1 380 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */ 381 #define MACB_WOL_SIZE 1 382 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */ 383 #define MACB_DRQFR_SIZE 1 384 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */ 385 #define MACB_SFR_SIZE 1 386 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */ 387 #define MACB_DRQFT_SIZE 1 388 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */ 389 #define MACB_SFT_SIZE 1 390 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */ 391 #define MACB_PDRQFR_SIZE 1 392 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */ 393 #define MACB_PDRSFR_SIZE 1 394 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */ 395 #define MACB_PDRQFT_SIZE 1 396 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */ 397 #define MACB_PDRSFT_SIZE 1 398 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */ 399 #define MACB_SRI_SIZE 1 400 401 /* Timer increment fields */ 402 #define MACB_TI_CNS_OFFSET 0 403 #define MACB_TI_CNS_SIZE 8 404 #define MACB_TI_ACNS_OFFSET 8 405 #define MACB_TI_ACNS_SIZE 8 406 #define MACB_TI_NIT_OFFSET 16 407 #define MACB_TI_NIT_SIZE 8 408 409 /* Bitfields in MAN */ 410 #define MACB_DATA_OFFSET 0 /* data */ 411 #define MACB_DATA_SIZE 16 412 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ 413 #define MACB_CODE_SIZE 2 414 #define MACB_REGA_OFFSET 18 /* Register address */ 415 #define MACB_REGA_SIZE 5 416 #define MACB_PHYA_OFFSET 23 /* PHY address */ 417 #define MACB_PHYA_SIZE 5 418 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ 419 #define MACB_RW_SIZE 2 420 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ 421 #define MACB_SOF_SIZE 2 422 423 /* Bitfields in USRIO (AVR32) */ 424 #define MACB_MII_OFFSET 0 425 #define MACB_MII_SIZE 1 426 #define MACB_EAM_OFFSET 1 427 #define MACB_EAM_SIZE 1 428 #define MACB_TX_PAUSE_OFFSET 2 429 #define MACB_TX_PAUSE_SIZE 1 430 #define MACB_TX_PAUSE_ZERO_OFFSET 3 431 #define MACB_TX_PAUSE_ZERO_SIZE 1 432 433 /* Bitfields in USRIO (AT91) */ 434 #define MACB_RMII_OFFSET 0 435 #define MACB_RMII_SIZE 1 436 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 437 #define GEM_RGMII_SIZE 1 438 #define MACB_CLKEN_OFFSET 1 439 #define MACB_CLKEN_SIZE 1 440 441 /* Bitfields in WOL */ 442 #define MACB_IP_OFFSET 0 443 #define MACB_IP_SIZE 16 444 #define MACB_MAG_OFFSET 16 445 #define MACB_MAG_SIZE 1 446 #define MACB_ARP_OFFSET 17 447 #define MACB_ARP_SIZE 1 448 #define MACB_SA1_OFFSET 18 449 #define MACB_SA1_SIZE 1 450 #define MACB_WOL_MTI_OFFSET 19 451 #define MACB_WOL_MTI_SIZE 1 452 453 /* Bitfields in MID */ 454 #define MACB_IDNUM_OFFSET 16 455 #define MACB_IDNUM_SIZE 12 456 #define MACB_REV_OFFSET 0 457 #define MACB_REV_SIZE 16 458 459 /* Bitfields in DCFG1. */ 460 #define GEM_IRQCOR_OFFSET 23 461 #define GEM_IRQCOR_SIZE 1 462 #define GEM_DBWDEF_OFFSET 25 463 #define GEM_DBWDEF_SIZE 3 464 465 /* Bitfields in DCFG2. */ 466 #define GEM_RX_PKT_BUFF_OFFSET 20 467 #define GEM_RX_PKT_BUFF_SIZE 1 468 #define GEM_TX_PKT_BUFF_OFFSET 21 469 #define GEM_TX_PKT_BUFF_SIZE 1 470 471 472 /* Bitfields in DCFG5. */ 473 #define GEM_TSU_OFFSET 8 474 #define GEM_TSU_SIZE 1 475 476 /* Bitfields in DCFG6. */ 477 #define GEM_PBUF_LSO_OFFSET 27 478 #define GEM_PBUF_LSO_SIZE 1 479 #define GEM_DAW64_OFFSET 23 480 #define GEM_DAW64_SIZE 1 481 482 /* Bitfields in DCFG8. */ 483 #define GEM_T1SCR_OFFSET 24 484 #define GEM_T1SCR_SIZE 8 485 #define GEM_T2SCR_OFFSET 16 486 #define GEM_T2SCR_SIZE 8 487 #define GEM_SCR2ETH_OFFSET 8 488 #define GEM_SCR2ETH_SIZE 8 489 #define GEM_SCR2CMP_OFFSET 0 490 #define GEM_SCR2CMP_SIZE 8 491 492 /* Bitfields in TISUBN */ 493 #define GEM_SUBNSINCR_OFFSET 0 494 #define GEM_SUBNSINCR_SIZE 16 495 496 /* Bitfields in TI */ 497 #define GEM_NSINCR_OFFSET 0 498 #define GEM_NSINCR_SIZE 8 499 500 /* Bitfields in TSH */ 501 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */ 502 #define GEM_TSH_SIZE 16 503 504 /* Bitfields in TSL */ 505 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */ 506 #define GEM_TSL_SIZE 32 507 508 /* Bitfields in TN */ 509 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */ 510 #define GEM_TN_SIZE 30 511 512 /* Bitfields in TXBDCTRL */ 513 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */ 514 #define GEM_TXTSMODE_SIZE 2 515 516 /* Bitfields in RXBDCTRL */ 517 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */ 518 #define GEM_RXTSMODE_SIZE 2 519 520 /* Bitfields in SCRT2 */ 521 #define GEM_QUEUE_OFFSET 0 /* Queue Number */ 522 #define GEM_QUEUE_SIZE 4 523 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */ 524 #define GEM_VLANPR_SIZE 3 525 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */ 526 #define GEM_VLANEN_SIZE 1 527 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */ 528 #define GEM_ETHT2IDX_SIZE 3 529 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */ 530 #define GEM_ETHTEN_SIZE 1 531 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */ 532 #define GEM_CMPA_SIZE 5 533 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */ 534 #define GEM_CMPAEN_SIZE 1 535 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */ 536 #define GEM_CMPB_SIZE 5 537 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */ 538 #define GEM_CMPBEN_SIZE 1 539 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */ 540 #define GEM_CMPC_SIZE 5 541 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */ 542 #define GEM_CMPCEN_SIZE 1 543 544 /* Bitfields in ETHT */ 545 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */ 546 #define GEM_ETHTCMP_SIZE 16 547 548 /* Bitfields in T2CMPW0 */ 549 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */ 550 #define GEM_T2CMP_SIZE 16 551 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */ 552 #define GEM_T2MASK_SIZE 16 553 554 /* Bitfields in T2CMPW1 */ 555 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */ 556 #define GEM_T2DISMSK_SIZE 1 557 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */ 558 #define GEM_T2CMPOFST_SIZE 2 559 #define GEM_T2OFST_OFFSET 0 /* offset value */ 560 #define GEM_T2OFST_SIZE 7 561 562 /* Offset for screener type 2 compare values (T2CMPOFST). 563 * Note the offset is applied after the specified point, 564 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset 565 * of 12 bytes from this would be the source IP address in an IP header 566 */ 567 #define GEM_T2COMPOFST_SOF 0 568 #define GEM_T2COMPOFST_ETYPE 1 569 #define GEM_T2COMPOFST_IPHDR 2 570 #define GEM_T2COMPOFST_TCPUDP 3 571 572 /* offset from EtherType to IP address */ 573 #define ETYPE_SRCIP_OFFSET 12 574 #define ETYPE_DSTIP_OFFSET 16 575 576 /* offset from IP header to port */ 577 #define IPHDR_SRCPORT_OFFSET 0 578 #define IPHDR_DSTPORT_OFFSET 2 579 580 /* Transmit DMA buffer descriptor Word 1 */ 581 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */ 582 #define GEM_DMA_TXVALID_SIZE 1 583 584 /* Receive DMA buffer descriptor Word 0 */ 585 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */ 586 #define GEM_DMA_RXVALID_SIZE 1 587 588 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */ 589 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */ 590 #define GEM_DMA_SECL_SIZE 2 591 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */ 592 #define GEM_DMA_NSEC_SIZE 30 593 594 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */ 595 596 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor. 597 * Old hardware supports only 6 bit precision but it is enough for PTP. 598 * Less accuracy is used always instead of checking hardware version. 599 */ 600 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */ 601 #define GEM_DMA_SECH_SIZE 4 602 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE) 603 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH) 604 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1) 605 606 /* Bitfields in ADJ */ 607 #define GEM_ADDSUB_OFFSET 31 608 #define GEM_ADDSUB_SIZE 1 609 /* Constants for CLK */ 610 #define MACB_CLK_DIV8 0 611 #define MACB_CLK_DIV16 1 612 #define MACB_CLK_DIV32 2 613 #define MACB_CLK_DIV64 3 614 615 /* GEM specific constants for CLK. */ 616 #define GEM_CLK_DIV8 0 617 #define GEM_CLK_DIV16 1 618 #define GEM_CLK_DIV32 2 619 #define GEM_CLK_DIV48 3 620 #define GEM_CLK_DIV64 4 621 #define GEM_CLK_DIV96 5 622 623 /* Constants for MAN register */ 624 #define MACB_MAN_SOF 1 625 #define MACB_MAN_WRITE 1 626 #define MACB_MAN_READ 2 627 #define MACB_MAN_CODE 2 628 629 /* Capability mask bits */ 630 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 631 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 632 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 633 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 634 #define MACB_CAPS_USRIO_DISABLED 0x00000010 635 #define MACB_CAPS_JUMBO 0x00000020 636 #define MACB_CAPS_GEM_HAS_PTP 0x00000040 637 #define MACB_CAPS_FIFO_MODE 0x10000000 638 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 639 #define MACB_CAPS_SG_DISABLED 0x40000000 640 #define MACB_CAPS_MACB_IS_GEM 0x80000000 641 642 /* LSO settings */ 643 #define MACB_LSO_UFO_ENABLE 0x01 644 #define MACB_LSO_TSO_ENABLE 0x02 645 646 /* Bit manipulation macros */ 647 #define MACB_BIT(name) \ 648 (1 << MACB_##name##_OFFSET) 649 #define MACB_BF(name,value) \ 650 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 651 << MACB_##name##_OFFSET) 652 #define MACB_BFEXT(name,value)\ 653 (((value) >> MACB_##name##_OFFSET) \ 654 & ((1 << MACB_##name##_SIZE) - 1)) 655 #define MACB_BFINS(name,value,old) \ 656 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 657 << MACB_##name##_OFFSET)) \ 658 | MACB_BF(name,value)) 659 660 #define GEM_BIT(name) \ 661 (1 << GEM_##name##_OFFSET) 662 #define GEM_BF(name, value) \ 663 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 664 << GEM_##name##_OFFSET) 665 #define GEM_BFEXT(name, value)\ 666 (((value) >> GEM_##name##_OFFSET) \ 667 & ((1 << GEM_##name##_SIZE) - 1)) 668 #define GEM_BFINS(name, value, old) \ 669 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 670 << GEM_##name##_OFFSET)) \ 671 | GEM_BF(name, value)) 672 673 /* Register access macros */ 674 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg) 675 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value)) 676 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg) 677 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value)) 678 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg) 679 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value)) 680 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4) 681 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value)) 682 683 #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */ 684 685 /* Conditional GEM/MACB macros. These perform the operation to the correct 686 * register dependent on whether the device is a GEM or a MACB. For registers 687 * and bitfields that are common across both devices, use macb_{read,write}l 688 * to avoid the cost of the conditional. 689 */ 690 #define macb_or_gem_writel(__bp, __reg, __value) \ 691 ({ \ 692 if (macb_is_gem((__bp))) \ 693 gem_writel((__bp), __reg, __value); \ 694 else \ 695 macb_writel((__bp), __reg, __value); \ 696 }) 697 698 #define macb_or_gem_readl(__bp, __reg) \ 699 ({ \ 700 u32 __v; \ 701 if (macb_is_gem((__bp))) \ 702 __v = gem_readl((__bp), __reg); \ 703 else \ 704 __v = macb_readl((__bp), __reg); \ 705 __v; \ 706 }) 707 708 /* struct macb_dma_desc - Hardware DMA descriptor 709 * @addr: DMA address of data buffer 710 * @ctrl: Control and status bits 711 */ 712 struct macb_dma_desc { 713 u32 addr; 714 u32 ctrl; 715 }; 716 717 #ifdef MACB_EXT_DESC 718 #define HW_DMA_CAP_32B 0 719 #define HW_DMA_CAP_64B (1 << 0) 720 #define HW_DMA_CAP_PTP (1 << 1) 721 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP) 722 723 struct macb_dma_desc_64 { 724 u32 addrh; 725 u32 resvd; 726 }; 727 728 struct macb_dma_desc_ptp { 729 u32 ts_1; 730 u32 ts_2; 731 }; 732 733 struct gem_tx_ts { 734 struct sk_buff *skb; 735 struct macb_dma_desc_ptp desc_ptp; 736 }; 737 #endif 738 739 /* DMA descriptor bitfields */ 740 #define MACB_RX_USED_OFFSET 0 741 #define MACB_RX_USED_SIZE 1 742 #define MACB_RX_WRAP_OFFSET 1 743 #define MACB_RX_WRAP_SIZE 1 744 #define MACB_RX_WADDR_OFFSET 2 745 #define MACB_RX_WADDR_SIZE 30 746 747 #define MACB_RX_FRMLEN_OFFSET 0 748 #define MACB_RX_FRMLEN_SIZE 12 749 #define MACB_RX_OFFSET_OFFSET 12 750 #define MACB_RX_OFFSET_SIZE 2 751 #define MACB_RX_SOF_OFFSET 14 752 #define MACB_RX_SOF_SIZE 1 753 #define MACB_RX_EOF_OFFSET 15 754 #define MACB_RX_EOF_SIZE 1 755 #define MACB_RX_CFI_OFFSET 16 756 #define MACB_RX_CFI_SIZE 1 757 #define MACB_RX_VLAN_PRI_OFFSET 17 758 #define MACB_RX_VLAN_PRI_SIZE 3 759 #define MACB_RX_PRI_TAG_OFFSET 20 760 #define MACB_RX_PRI_TAG_SIZE 1 761 #define MACB_RX_VLAN_TAG_OFFSET 21 762 #define MACB_RX_VLAN_TAG_SIZE 1 763 #define MACB_RX_TYPEID_MATCH_OFFSET 22 764 #define MACB_RX_TYPEID_MATCH_SIZE 1 765 #define MACB_RX_SA4_MATCH_OFFSET 23 766 #define MACB_RX_SA4_MATCH_SIZE 1 767 #define MACB_RX_SA3_MATCH_OFFSET 24 768 #define MACB_RX_SA3_MATCH_SIZE 1 769 #define MACB_RX_SA2_MATCH_OFFSET 25 770 #define MACB_RX_SA2_MATCH_SIZE 1 771 #define MACB_RX_SA1_MATCH_OFFSET 26 772 #define MACB_RX_SA1_MATCH_SIZE 1 773 #define MACB_RX_EXT_MATCH_OFFSET 28 774 #define MACB_RX_EXT_MATCH_SIZE 1 775 #define MACB_RX_UHASH_MATCH_OFFSET 29 776 #define MACB_RX_UHASH_MATCH_SIZE 1 777 #define MACB_RX_MHASH_MATCH_OFFSET 30 778 #define MACB_RX_MHASH_MATCH_SIZE 1 779 #define MACB_RX_BROADCAST_OFFSET 31 780 #define MACB_RX_BROADCAST_SIZE 1 781 782 #define MACB_RX_FRMLEN_MASK 0xFFF 783 #define MACB_RX_JFRMLEN_MASK 0x3FFF 784 785 /* RX checksum offload disabled: bit 24 clear in NCFGR */ 786 #define GEM_RX_TYPEID_MATCH_OFFSET 22 787 #define GEM_RX_TYPEID_MATCH_SIZE 2 788 789 /* RX checksum offload enabled: bit 24 set in NCFGR */ 790 #define GEM_RX_CSUM_OFFSET 22 791 #define GEM_RX_CSUM_SIZE 2 792 793 #define MACB_TX_FRMLEN_OFFSET 0 794 #define MACB_TX_FRMLEN_SIZE 11 795 #define MACB_TX_LAST_OFFSET 15 796 #define MACB_TX_LAST_SIZE 1 797 #define MACB_TX_NOCRC_OFFSET 16 798 #define MACB_TX_NOCRC_SIZE 1 799 #define MACB_MSS_MFS_OFFSET 16 800 #define MACB_MSS_MFS_SIZE 14 801 #define MACB_TX_LSO_OFFSET 17 802 #define MACB_TX_LSO_SIZE 2 803 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19 804 #define MACB_TX_TCP_SEQ_SRC_SIZE 1 805 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 806 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 807 #define MACB_TX_UNDERRUN_OFFSET 28 808 #define MACB_TX_UNDERRUN_SIZE 1 809 #define MACB_TX_ERROR_OFFSET 29 810 #define MACB_TX_ERROR_SIZE 1 811 #define MACB_TX_WRAP_OFFSET 30 812 #define MACB_TX_WRAP_SIZE 1 813 #define MACB_TX_USED_OFFSET 31 814 #define MACB_TX_USED_SIZE 1 815 816 #define GEM_TX_FRMLEN_OFFSET 0 817 #define GEM_TX_FRMLEN_SIZE 14 818 819 /* Buffer descriptor constants */ 820 #define GEM_RX_CSUM_NONE 0 821 #define GEM_RX_CSUM_IP_ONLY 1 822 #define GEM_RX_CSUM_IP_TCP 2 823 #define GEM_RX_CSUM_IP_UDP 3 824 825 /* limit RX checksum offload to TCP and UDP packets */ 826 #define GEM_RX_CSUM_CHECKED_MASK 2 827 828 /* struct macb_tx_skb - data about an skb which is being transmitted 829 * @skb: skb currently being transmitted, only set for the last buffer 830 * of the frame 831 * @mapping: DMA address of the skb's fragment buffer 832 * @size: size of the DMA mapped buffer 833 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 834 * false when buffer was mapped with dma_map_single() 835 */ 836 struct macb_tx_skb { 837 struct sk_buff *skb; 838 dma_addr_t mapping; 839 size_t size; 840 bool mapped_as_page; 841 }; 842 843 /* Hardware-collected statistics. Used when updating the network 844 * device stats by a periodic timer. 845 */ 846 struct macb_stats { 847 u32 rx_pause_frames; 848 u32 tx_ok; 849 u32 tx_single_cols; 850 u32 tx_multiple_cols; 851 u32 rx_ok; 852 u32 rx_fcs_errors; 853 u32 rx_align_errors; 854 u32 tx_deferred; 855 u32 tx_late_cols; 856 u32 tx_excessive_cols; 857 u32 tx_underruns; 858 u32 tx_carrier_errors; 859 u32 rx_resource_errors; 860 u32 rx_overruns; 861 u32 rx_symbol_errors; 862 u32 rx_oversize_pkts; 863 u32 rx_jabbers; 864 u32 rx_undersize_pkts; 865 u32 sqe_test_errors; 866 u32 rx_length_mismatch; 867 u32 tx_pause_frames; 868 }; 869 870 struct gem_stats { 871 u32 tx_octets_31_0; 872 u32 tx_octets_47_32; 873 u32 tx_frames; 874 u32 tx_broadcast_frames; 875 u32 tx_multicast_frames; 876 u32 tx_pause_frames; 877 u32 tx_64_byte_frames; 878 u32 tx_65_127_byte_frames; 879 u32 tx_128_255_byte_frames; 880 u32 tx_256_511_byte_frames; 881 u32 tx_512_1023_byte_frames; 882 u32 tx_1024_1518_byte_frames; 883 u32 tx_greater_than_1518_byte_frames; 884 u32 tx_underrun; 885 u32 tx_single_collision_frames; 886 u32 tx_multiple_collision_frames; 887 u32 tx_excessive_collisions; 888 u32 tx_late_collisions; 889 u32 tx_deferred_frames; 890 u32 tx_carrier_sense_errors; 891 u32 rx_octets_31_0; 892 u32 rx_octets_47_32; 893 u32 rx_frames; 894 u32 rx_broadcast_frames; 895 u32 rx_multicast_frames; 896 u32 rx_pause_frames; 897 u32 rx_64_byte_frames; 898 u32 rx_65_127_byte_frames; 899 u32 rx_128_255_byte_frames; 900 u32 rx_256_511_byte_frames; 901 u32 rx_512_1023_byte_frames; 902 u32 rx_1024_1518_byte_frames; 903 u32 rx_greater_than_1518_byte_frames; 904 u32 rx_undersized_frames; 905 u32 rx_oversize_frames; 906 u32 rx_jabbers; 907 u32 rx_frame_check_sequence_errors; 908 u32 rx_length_field_frame_errors; 909 u32 rx_symbol_errors; 910 u32 rx_alignment_errors; 911 u32 rx_resource_errors; 912 u32 rx_overruns; 913 u32 rx_ip_header_checksum_errors; 914 u32 rx_tcp_checksum_errors; 915 u32 rx_udp_checksum_errors; 916 }; 917 918 /* Describes the name and offset of an individual statistic register, as 919 * returned by `ethtool -S`. Also describes which net_device_stats statistics 920 * this register should contribute to. 921 */ 922 struct gem_statistic { 923 char stat_string[ETH_GSTRING_LEN]; 924 int offset; 925 u32 stat_bits; 926 }; 927 928 /* Bitfield defs for net_device_stat statistics */ 929 #define GEM_NDS_RXERR_OFFSET 0 930 #define GEM_NDS_RXLENERR_OFFSET 1 931 #define GEM_NDS_RXOVERERR_OFFSET 2 932 #define GEM_NDS_RXCRCERR_OFFSET 3 933 #define GEM_NDS_RXFRAMEERR_OFFSET 4 934 #define GEM_NDS_RXFIFOERR_OFFSET 5 935 #define GEM_NDS_TXERR_OFFSET 6 936 #define GEM_NDS_TXABORTEDERR_OFFSET 7 937 #define GEM_NDS_TXCARRIERERR_OFFSET 8 938 #define GEM_NDS_TXFIFOERR_OFFSET 9 939 #define GEM_NDS_COLLISIONS_OFFSET 10 940 941 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) 942 #define GEM_STAT_TITLE_BITS(name, title, bits) { \ 943 .stat_string = title, \ 944 .offset = GEM_##name, \ 945 .stat_bits = bits \ 946 } 947 948 /* list of gem statistic registers. The names MUST match the 949 * corresponding GEM_* definitions. 950 */ 951 static const struct gem_statistic gem_statistics[] = { 952 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ 953 GEM_STAT_TITLE(TXCNT, "tx_frames"), 954 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), 955 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), 956 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), 957 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), 958 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), 959 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), 960 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), 961 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), 962 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), 963 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), 964 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", 965 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), 966 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", 967 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 968 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", 969 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 970 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", 971 GEM_BIT(NDS_TXERR)| 972 GEM_BIT(NDS_TXABORTEDERR)| 973 GEM_BIT(NDS_COLLISIONS)), 974 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", 975 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 976 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), 977 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", 978 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 979 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ 980 GEM_STAT_TITLE(RXCNT, "rx_frames"), 981 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), 982 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), 983 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), 984 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), 985 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), 986 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), 987 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), 988 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), 989 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), 990 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), 991 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", 992 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 993 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", 994 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 995 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", 996 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 997 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", 998 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), 999 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", 1000 GEM_BIT(NDS_RXERR)), 1001 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", 1002 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), 1003 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", 1004 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 1005 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", 1006 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 1007 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", 1008 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), 1009 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", 1010 GEM_BIT(NDS_RXERR)), 1011 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", 1012 GEM_BIT(NDS_RXERR)), 1013 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", 1014 GEM_BIT(NDS_RXERR)), 1015 }; 1016 1017 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) 1018 1019 #define QUEUE_STAT_TITLE(title) { \ 1020 .stat_string = title, \ 1021 } 1022 1023 /* per queue statistics, each should be unsigned long type */ 1024 struct queue_stats { 1025 union { 1026 unsigned long first; 1027 unsigned long rx_packets; 1028 }; 1029 unsigned long rx_bytes; 1030 unsigned long rx_dropped; 1031 unsigned long tx_packets; 1032 unsigned long tx_bytes; 1033 unsigned long tx_dropped; 1034 }; 1035 1036 static const struct gem_statistic queue_statistics[] = { 1037 QUEUE_STAT_TITLE("rx_packets"), 1038 QUEUE_STAT_TITLE("rx_bytes"), 1039 QUEUE_STAT_TITLE("rx_dropped"), 1040 QUEUE_STAT_TITLE("tx_packets"), 1041 QUEUE_STAT_TITLE("tx_bytes"), 1042 QUEUE_STAT_TITLE("tx_dropped"), 1043 }; 1044 1045 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics) 1046 1047 struct macb; 1048 struct macb_queue; 1049 1050 struct macb_or_gem_ops { 1051 int (*mog_alloc_rx_buffers)(struct macb *bp); 1052 void (*mog_free_rx_buffers)(struct macb *bp); 1053 void (*mog_init_rings)(struct macb *bp); 1054 int (*mog_rx)(struct macb_queue *queue, int budget); 1055 }; 1056 1057 /* MACB-PTP interface: adapt to platform needs. */ 1058 struct macb_ptp_info { 1059 void (*ptp_init)(struct net_device *ndev); 1060 void (*ptp_remove)(struct net_device *ndev); 1061 s32 (*get_ptp_max_adj)(void); 1062 unsigned int (*get_tsu_rate)(struct macb *bp); 1063 int (*get_ts_info)(struct net_device *dev, 1064 struct ethtool_ts_info *info); 1065 int (*get_hwtst)(struct net_device *netdev, 1066 struct ifreq *ifr); 1067 int (*set_hwtst)(struct net_device *netdev, 1068 struct ifreq *ifr, int cmd); 1069 }; 1070 1071 struct macb_config { 1072 u32 caps; 1073 unsigned int dma_burst_length; 1074 int (*clk_init)(struct platform_device *pdev, struct clk **pclk, 1075 struct clk **hclk, struct clk **tx_clk, 1076 struct clk **rx_clk); 1077 int (*init)(struct platform_device *pdev); 1078 int jumbo_max_len; 1079 }; 1080 1081 struct tsu_incr { 1082 u32 sub_ns; 1083 u32 ns; 1084 }; 1085 1086 struct macb_queue { 1087 struct macb *bp; 1088 int irq; 1089 1090 unsigned int ISR; 1091 unsigned int IER; 1092 unsigned int IDR; 1093 unsigned int IMR; 1094 unsigned int TBQP; 1095 unsigned int TBQPH; 1096 unsigned int RBQS; 1097 unsigned int RBQP; 1098 unsigned int RBQPH; 1099 1100 unsigned int tx_head, tx_tail; 1101 struct macb_dma_desc *tx_ring; 1102 struct macb_tx_skb *tx_skb; 1103 dma_addr_t tx_ring_dma; 1104 struct work_struct tx_error_task; 1105 1106 dma_addr_t rx_ring_dma; 1107 dma_addr_t rx_buffers_dma; 1108 unsigned int rx_tail; 1109 unsigned int rx_prepared_head; 1110 struct macb_dma_desc *rx_ring; 1111 struct sk_buff **rx_skbuff; 1112 void *rx_buffers; 1113 struct napi_struct napi; 1114 struct queue_stats stats; 1115 1116 #ifdef CONFIG_MACB_USE_HWSTAMP 1117 struct work_struct tx_ts_task; 1118 unsigned int tx_ts_head, tx_ts_tail; 1119 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE]; 1120 #endif 1121 }; 1122 1123 struct ethtool_rx_fs_item { 1124 struct ethtool_rx_flow_spec fs; 1125 struct list_head list; 1126 }; 1127 1128 struct ethtool_rx_fs_list { 1129 struct list_head list; 1130 unsigned int count; 1131 }; 1132 1133 struct macb { 1134 void __iomem *regs; 1135 bool native_io; 1136 1137 /* hardware IO accessors */ 1138 u32 (*macb_reg_readl)(struct macb *bp, int offset); 1139 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value); 1140 1141 size_t rx_buffer_size; 1142 1143 unsigned int rx_ring_size; 1144 unsigned int tx_ring_size; 1145 1146 unsigned int num_queues; 1147 unsigned int queue_mask; 1148 struct macb_queue queues[MACB_MAX_QUEUES]; 1149 1150 spinlock_t lock; 1151 struct platform_device *pdev; 1152 struct clk *pclk; 1153 struct clk *hclk; 1154 struct clk *tx_clk; 1155 struct clk *rx_clk; 1156 struct net_device *dev; 1157 union { 1158 struct macb_stats macb; 1159 struct gem_stats gem; 1160 } hw_stats; 1161 1162 struct macb_or_gem_ops macbgem_ops; 1163 1164 struct mii_bus *mii_bus; 1165 struct device_node *phy_node; 1166 int link; 1167 int speed; 1168 int duplex; 1169 1170 u32 caps; 1171 unsigned int dma_burst_length; 1172 1173 phy_interface_t phy_interface; 1174 1175 /* AT91RM9200 transmit */ 1176 struct sk_buff *skb; /* holds skb until xmit interrupt completes */ 1177 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ 1178 int skb_length; /* saved skb length for pci_unmap_single */ 1179 unsigned int max_tx_length; 1180 1181 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES]; 1182 1183 unsigned int rx_frm_len_mask; 1184 unsigned int jumbo_max_len; 1185 1186 u32 wol; 1187 1188 struct macb_ptp_info *ptp_info; /* macb-ptp interface */ 1189 #ifdef MACB_EXT_DESC 1190 uint8_t hw_dma_cap; 1191 #endif 1192 spinlock_t tsu_clk_lock; /* gem tsu clock locking */ 1193 unsigned int tsu_rate; 1194 struct ptp_clock *ptp_clock; 1195 struct ptp_clock_info ptp_clock_info; 1196 struct tsu_incr tsu_incr; 1197 struct hwtstamp_config tstamp_config; 1198 1199 /* RX queue filer rule set*/ 1200 struct ethtool_rx_fs_list rx_fs_list; 1201 spinlock_t rx_fs_lock; 1202 unsigned int max_tuples; 1203 }; 1204 1205 #ifdef CONFIG_MACB_USE_HWSTAMP 1206 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE) 1207 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1) 1208 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1) 1209 1210 enum macb_bd_control { 1211 TSTAMP_DISABLED, 1212 TSTAMP_FRAME_PTP_EVENT_ONLY, 1213 TSTAMP_ALL_PTP_FRAMES, 1214 TSTAMP_ALL_FRAMES, 1215 }; 1216 1217 void gem_ptp_init(struct net_device *ndev); 1218 void gem_ptp_remove(struct net_device *ndev); 1219 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des); 1220 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc); 1221 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) 1222 { 1223 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED) 1224 return -ENOTSUPP; 1225 1226 return gem_ptp_txstamp(queue, skb, desc); 1227 } 1228 1229 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) 1230 { 1231 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED) 1232 return; 1233 1234 gem_ptp_rxstamp(bp, skb, desc); 1235 } 1236 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq); 1237 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd); 1238 #else 1239 static inline void gem_ptp_init(struct net_device *ndev) { } 1240 static inline void gem_ptp_remove(struct net_device *ndev) { } 1241 1242 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) 1243 { 1244 return -1; 1245 } 1246 1247 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { } 1248 #endif 1249 1250 static inline bool macb_is_gem(struct macb *bp) 1251 { 1252 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 1253 } 1254 1255 static inline bool gem_has_ptp(struct macb *bp) 1256 { 1257 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP); 1258 } 1259 1260 #endif /* _MACB_H */ 1261