1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Atmel MACB Ethernet Controller driver 4 * 5 * Copyright (C) 2004-2006 Atmel Corporation 6 */ 7 #ifndef _MACB_H 8 #define _MACB_H 9 10 #include <linux/clk.h> 11 #include <linux/phylink.h> 12 #include <linux/ptp_clock_kernel.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/interrupt.h> 15 16 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP) 17 #define MACB_EXT_DESC 18 #endif 19 20 #define MACB_GREGS_NBR 16 21 #define MACB_GREGS_VERSION 2 22 #define MACB_MAX_QUEUES 8 23 24 /* MACB register offsets */ 25 #define MACB_NCR 0x0000 /* Network Control */ 26 #define MACB_NCFGR 0x0004 /* Network Config */ 27 #define MACB_NSR 0x0008 /* Network Status */ 28 #define MACB_TAR 0x000c /* AT91RM9200 only */ 29 #define MACB_TCR 0x0010 /* AT91RM9200 only */ 30 #define MACB_TSR 0x0014 /* Transmit Status */ 31 #define MACB_RBQP 0x0018 /* RX Q Base Address */ 32 #define MACB_TBQP 0x001c /* TX Q Base Address */ 33 #define MACB_RSR 0x0020 /* Receive Status */ 34 #define MACB_ISR 0x0024 /* Interrupt Status */ 35 #define MACB_IER 0x0028 /* Interrupt Enable */ 36 #define MACB_IDR 0x002c /* Interrupt Disable */ 37 #define MACB_IMR 0x0030 /* Interrupt Mask */ 38 #define MACB_MAN 0x0034 /* PHY Maintenance */ 39 #define MACB_PTR 0x0038 40 #define MACB_PFR 0x003c 41 #define MACB_FTO 0x0040 42 #define MACB_SCF 0x0044 43 #define MACB_MCF 0x0048 44 #define MACB_FRO 0x004c 45 #define MACB_FCSE 0x0050 46 #define MACB_ALE 0x0054 47 #define MACB_DTF 0x0058 48 #define MACB_LCOL 0x005c 49 #define MACB_EXCOL 0x0060 50 #define MACB_TUND 0x0064 51 #define MACB_CSE 0x0068 52 #define MACB_RRE 0x006c 53 #define MACB_ROVR 0x0070 54 #define MACB_RSE 0x0074 55 #define MACB_ELE 0x0078 56 #define MACB_RJA 0x007c 57 #define MACB_USF 0x0080 58 #define MACB_STE 0x0084 59 #define MACB_RLE 0x0088 60 #define MACB_TPF 0x008c 61 #define MACB_HRB 0x0090 62 #define MACB_HRT 0x0094 63 #define MACB_SA1B 0x0098 64 #define MACB_SA1T 0x009c 65 #define MACB_SA2B 0x00a0 66 #define MACB_SA2T 0x00a4 67 #define MACB_SA3B 0x00a8 68 #define MACB_SA3T 0x00ac 69 #define MACB_SA4B 0x00b0 70 #define MACB_SA4T 0x00b4 71 #define MACB_TID 0x00b8 72 #define MACB_TPQ 0x00bc 73 #define MACB_USRIO 0x00c0 74 #define MACB_WOL 0x00c4 75 #define MACB_MID 0x00fc 76 #define MACB_TBQPH 0x04C8 77 #define MACB_RBQPH 0x04D4 78 79 /* GEM register offsets. */ 80 #define GEM_NCR 0x0000 /* Network Control */ 81 #define GEM_NCFGR 0x0004 /* Network Config */ 82 #define GEM_USRIO 0x000c /* User IO */ 83 #define GEM_DMACFG 0x0010 /* DMA Configuration */ 84 #define GEM_JML 0x0048 /* Jumbo Max Length */ 85 #define GEM_HS_MAC_CONFIG 0x0050 /* GEM high speed config */ 86 #define GEM_HRB 0x0080 /* Hash Bottom */ 87 #define GEM_HRT 0x0084 /* Hash Top */ 88 #define GEM_SA1B 0x0088 /* Specific1 Bottom */ 89 #define GEM_SA1T 0x008C /* Specific1 Top */ 90 #define GEM_SA2B 0x0090 /* Specific2 Bottom */ 91 #define GEM_SA2T 0x0094 /* Specific2 Top */ 92 #define GEM_SA3B 0x0098 /* Specific3 Bottom */ 93 #define GEM_SA3T 0x009C /* Specific3 Top */ 94 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ 95 #define GEM_SA4T 0x00A4 /* Specific4 Top */ 96 #define GEM_WOL 0x00b8 /* Wake on LAN */ 97 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */ 98 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */ 99 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */ 100 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */ 101 #define GEM_OTX 0x0100 /* Octets transmitted */ 102 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ 103 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ 104 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ 105 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ 106 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ 107 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ 108 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ 109 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ 110 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ 111 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ 112 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ 113 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ 114 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ 115 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ 116 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ 117 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ 118 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ 119 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ 120 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ 121 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ 122 #define GEM_ORX 0x0150 /* Octets received */ 123 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ 124 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ 125 #define GEM_RXCNT 0x0158 /* Frames Received Counter */ 126 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ 127 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ 128 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ 129 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ 130 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ 131 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ 132 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ 133 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ 134 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ 135 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ 136 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ 137 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ 138 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ 139 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ 140 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ 141 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ 142 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ 143 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ 144 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ 145 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ 146 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ 147 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ 148 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */ 149 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */ 150 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */ 151 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */ 152 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */ 153 #define GEM_TI 0x01dc /* 1588 Timer Increment */ 154 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */ 155 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */ 156 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */ 157 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */ 158 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */ 159 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ 160 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ 161 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ 162 #define GEM_DCFG1 0x0280 /* Design Config 1 */ 163 #define GEM_DCFG2 0x0284 /* Design Config 2 */ 164 #define GEM_DCFG3 0x0288 /* Design Config 3 */ 165 #define GEM_DCFG4 0x028c /* Design Config 4 */ 166 #define GEM_DCFG5 0x0290 /* Design Config 5 */ 167 #define GEM_DCFG6 0x0294 /* Design Config 6 */ 168 #define GEM_DCFG7 0x0298 /* Design Config 7 */ 169 #define GEM_DCFG8 0x029C /* Design Config 8 */ 170 #define GEM_DCFG10 0x02A4 /* Design Config 10 */ 171 #define GEM_DCFG12 0x02AC /* Design Config 12 */ 172 #define GEM_USX_CONTROL 0x0A80 /* High speed PCS control register */ 173 #define GEM_USX_STATUS 0x0A88 /* High speed PCS status register */ 174 175 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ 176 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ 177 178 /* Screener Type 2 match registers */ 179 #define GEM_SCRT2 0x540 180 181 /* EtherType registers */ 182 #define GEM_ETHT 0x06E0 183 184 /* Type 2 compare registers */ 185 #define GEM_T2CMPW0 0x0700 186 #define GEM_T2CMPW1 0x0704 187 #define T2CMP_OFST(t2idx) (t2idx * 2) 188 189 /* type 2 compare registers 190 * each location requires 3 compare regs 191 */ 192 #define GEM_IP4SRC_CMP(idx) (idx * 3) 193 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1) 194 #define GEM_PORT_CMP(idx) (idx * 3 + 2) 195 196 /* Which screening type 2 EtherType register will be used (0 - 7) */ 197 #define SCRT2_ETHT 0 198 199 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 200 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 201 #define GEM_TBQPH(hw_q) (0x04C8) 202 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 203 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) 204 #define GEM_RBQPH(hw_q) (0x04D4) 205 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 206 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 207 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 208 209 /* Bitfields in NCR */ 210 #define MACB_LB_OFFSET 0 /* reserved */ 211 #define MACB_LB_SIZE 1 212 #define MACB_LLB_OFFSET 1 /* Loop back local */ 213 #define MACB_LLB_SIZE 1 214 #define MACB_RE_OFFSET 2 /* Receive enable */ 215 #define MACB_RE_SIZE 1 216 #define MACB_TE_OFFSET 3 /* Transmit enable */ 217 #define MACB_TE_SIZE 1 218 #define MACB_MPE_OFFSET 4 /* Management port enable */ 219 #define MACB_MPE_SIZE 1 220 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ 221 #define MACB_CLRSTAT_SIZE 1 222 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ 223 #define MACB_INCSTAT_SIZE 1 224 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ 225 #define MACB_WESTAT_SIZE 1 226 #define MACB_BP_OFFSET 8 /* Back pressure */ 227 #define MACB_BP_SIZE 1 228 #define MACB_TSTART_OFFSET 9 /* Start transmission */ 229 #define MACB_TSTART_SIZE 1 230 #define MACB_THALT_OFFSET 10 /* Transmit halt */ 231 #define MACB_THALT_SIZE 1 232 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ 233 #define MACB_NCR_TPF_SIZE 1 234 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ 235 #define MACB_TZQ_SIZE 1 236 #define MACB_SRTSM_OFFSET 15 237 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ 238 #define MACB_OSSMODE_SIZE 1 239 240 /* Bitfields in NCFGR */ 241 #define MACB_SPD_OFFSET 0 /* Speed */ 242 #define MACB_SPD_SIZE 1 243 #define MACB_FD_OFFSET 1 /* Full duplex */ 244 #define MACB_FD_SIZE 1 245 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ 246 #define MACB_BIT_RATE_SIZE 1 247 #define MACB_JFRAME_OFFSET 3 /* reserved */ 248 #define MACB_JFRAME_SIZE 1 249 #define MACB_CAF_OFFSET 4 /* Copy all frames */ 250 #define MACB_CAF_SIZE 1 251 #define MACB_NBC_OFFSET 5 /* No broadcast */ 252 #define MACB_NBC_SIZE 1 253 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ 254 #define MACB_NCFGR_MTI_SIZE 1 255 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ 256 #define MACB_UNI_SIZE 1 257 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ 258 #define MACB_BIG_SIZE 1 259 #define MACB_EAE_OFFSET 9 /* External address match enable */ 260 #define MACB_EAE_SIZE 1 261 #define MACB_CLK_OFFSET 10 262 #define MACB_CLK_SIZE 2 263 #define MACB_RTY_OFFSET 12 /* Retry test */ 264 #define MACB_RTY_SIZE 1 265 #define MACB_PAE_OFFSET 13 /* Pause enable */ 266 #define MACB_PAE_SIZE 1 267 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 268 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 269 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ 270 #define MACB_RBOF_SIZE 2 271 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ 272 #define MACB_RLCE_SIZE 1 273 #define MACB_DRFCS_OFFSET 17 /* FCS remove */ 274 #define MACB_DRFCS_SIZE 1 275 #define MACB_EFRHD_OFFSET 18 276 #define MACB_EFRHD_SIZE 1 277 #define MACB_IRXFCS_OFFSET 19 278 #define MACB_IRXFCS_SIZE 1 279 280 /* GEM specific NCR bitfields. */ 281 #define GEM_ENABLE_HS_MAC_OFFSET 31 282 #define GEM_ENABLE_HS_MAC_SIZE 1 283 284 /* GEM specific NCFGR bitfields. */ 285 #define GEM_FD_OFFSET 1 /* Full duplex */ 286 #define GEM_FD_SIZE 1 287 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ 288 #define GEM_GBE_SIZE 1 289 #define GEM_PCSSEL_OFFSET 11 290 #define GEM_PCSSEL_SIZE 1 291 #define GEM_PAE_OFFSET 13 /* Pause enable */ 292 #define GEM_PAE_SIZE 1 293 #define GEM_CLK_OFFSET 18 /* MDC clock division */ 294 #define GEM_CLK_SIZE 3 295 #define GEM_DBW_OFFSET 21 /* Data bus width */ 296 #define GEM_DBW_SIZE 2 297 #define GEM_RXCOEN_OFFSET 24 298 #define GEM_RXCOEN_SIZE 1 299 #define GEM_SGMIIEN_OFFSET 27 300 #define GEM_SGMIIEN_SIZE 1 301 302 303 /* Constants for data bus width. */ 304 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 305 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 306 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 307 308 /* Bitfields in DMACFG. */ 309 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 310 #define GEM_FBLDO_SIZE 5 311 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 312 #define GEM_ENDIA_DESC_SIZE 1 313 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ 314 #define GEM_ENDIA_PKT_SIZE 1 315 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 316 #define GEM_RXBMS_SIZE 2 317 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 318 #define GEM_TXPBMS_SIZE 1 319 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 320 #define GEM_TXCOEN_SIZE 1 321 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ 322 #define GEM_RXBS_SIZE 8 323 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ 324 #define GEM_DDRP_SIZE 1 325 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */ 326 #define GEM_RXEXT_SIZE 1 327 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */ 328 #define GEM_TXEXT_SIZE 1 329 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ 330 #define GEM_ADDR64_SIZE 1 331 332 333 /* Bitfields in NSR */ 334 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ 335 #define MACB_NSR_LINK_SIZE 1 336 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ 337 #define MACB_MDIO_SIZE 1 338 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ 339 #define MACB_IDLE_SIZE 1 340 341 /* Bitfields in TSR */ 342 #define MACB_UBR_OFFSET 0 /* Used bit read */ 343 #define MACB_UBR_SIZE 1 344 #define MACB_COL_OFFSET 1 /* Collision occurred */ 345 #define MACB_COL_SIZE 1 346 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ 347 #define MACB_TSR_RLE_SIZE 1 348 #define MACB_TGO_OFFSET 3 /* Transmit go */ 349 #define MACB_TGO_SIZE 1 350 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ 351 #define MACB_BEX_SIZE 1 352 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 353 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 354 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ 355 #define MACB_COMP_SIZE 1 356 #define MACB_UND_OFFSET 6 /* Trnasmit under run */ 357 #define MACB_UND_SIZE 1 358 359 /* Bitfields in RSR */ 360 #define MACB_BNA_OFFSET 0 /* Buffer not available */ 361 #define MACB_BNA_SIZE 1 362 #define MACB_REC_OFFSET 1 /* Frame received */ 363 #define MACB_REC_SIZE 1 364 #define MACB_OVR_OFFSET 2 /* Receive overrun */ 365 #define MACB_OVR_SIZE 1 366 367 /* Bitfields in ISR/IER/IDR/IMR */ 368 #define MACB_MFD_OFFSET 0 /* Management frame sent */ 369 #define MACB_MFD_SIZE 1 370 #define MACB_RCOMP_OFFSET 1 /* Receive complete */ 371 #define MACB_RCOMP_SIZE 1 372 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ 373 #define MACB_RXUBR_SIZE 1 374 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ 375 #define MACB_TXUBR_SIZE 1 376 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ 377 #define MACB_ISR_TUND_SIZE 1 378 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ 379 #define MACB_ISR_RLE_SIZE 1 380 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ 381 #define MACB_TXERR_SIZE 1 382 #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */ 383 #define MACB_RM9200_TBRE_SIZE 1 384 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ 385 #define MACB_TCOMP_SIZE 1 386 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ 387 #define MACB_ISR_LINK_SIZE 1 388 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ 389 #define MACB_ISR_ROVR_SIZE 1 390 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ 391 #define MACB_HRESP_SIZE 1 392 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ 393 #define MACB_PFR_SIZE 1 394 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ 395 #define MACB_PTZ_SIZE 1 396 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */ 397 #define MACB_WOL_SIZE 1 398 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */ 399 #define MACB_DRQFR_SIZE 1 400 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */ 401 #define MACB_SFR_SIZE 1 402 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */ 403 #define MACB_DRQFT_SIZE 1 404 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */ 405 #define MACB_SFT_SIZE 1 406 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */ 407 #define MACB_PDRQFR_SIZE 1 408 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */ 409 #define MACB_PDRSFR_SIZE 1 410 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */ 411 #define MACB_PDRQFT_SIZE 1 412 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */ 413 #define MACB_PDRSFT_SIZE 1 414 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */ 415 #define MACB_SRI_SIZE 1 416 #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */ 417 #define GEM_WOL_SIZE 1 418 419 /* Timer increment fields */ 420 #define MACB_TI_CNS_OFFSET 0 421 #define MACB_TI_CNS_SIZE 8 422 #define MACB_TI_ACNS_OFFSET 8 423 #define MACB_TI_ACNS_SIZE 8 424 #define MACB_TI_NIT_OFFSET 16 425 #define MACB_TI_NIT_SIZE 8 426 427 /* Bitfields in MAN */ 428 #define MACB_DATA_OFFSET 0 /* data */ 429 #define MACB_DATA_SIZE 16 430 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ 431 #define MACB_CODE_SIZE 2 432 #define MACB_REGA_OFFSET 18 /* Register address */ 433 #define MACB_REGA_SIZE 5 434 #define MACB_PHYA_OFFSET 23 /* PHY address */ 435 #define MACB_PHYA_SIZE 5 436 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ 437 #define MACB_RW_SIZE 2 438 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ 439 #define MACB_SOF_SIZE 2 440 441 /* Bitfields in USRIO (AVR32) */ 442 #define MACB_MII_OFFSET 0 443 #define MACB_MII_SIZE 1 444 #define MACB_EAM_OFFSET 1 445 #define MACB_EAM_SIZE 1 446 #define MACB_TX_PAUSE_OFFSET 2 447 #define MACB_TX_PAUSE_SIZE 1 448 #define MACB_TX_PAUSE_ZERO_OFFSET 3 449 #define MACB_TX_PAUSE_ZERO_SIZE 1 450 451 /* Bitfields in USRIO (AT91) */ 452 #define MACB_RMII_OFFSET 0 453 #define MACB_RMII_SIZE 1 454 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 455 #define GEM_RGMII_SIZE 1 456 #define MACB_CLKEN_OFFSET 1 457 #define MACB_CLKEN_SIZE 1 458 459 /* Bitfields in WOL */ 460 #define MACB_IP_OFFSET 0 461 #define MACB_IP_SIZE 16 462 #define MACB_MAG_OFFSET 16 463 #define MACB_MAG_SIZE 1 464 #define MACB_ARP_OFFSET 17 465 #define MACB_ARP_SIZE 1 466 #define MACB_SA1_OFFSET 18 467 #define MACB_SA1_SIZE 1 468 #define MACB_WOL_MTI_OFFSET 19 469 #define MACB_WOL_MTI_SIZE 1 470 471 /* Bitfields in MID */ 472 #define MACB_IDNUM_OFFSET 16 473 #define MACB_IDNUM_SIZE 12 474 #define MACB_REV_OFFSET 0 475 #define MACB_REV_SIZE 16 476 477 /* Bitfield in HS_MAC_CONFIG */ 478 #define GEM_HS_MAC_SPEED_OFFSET 0 479 #define GEM_HS_MAC_SPEED_SIZE 3 480 481 /* Bitfields in DCFG1. */ 482 #define GEM_IRQCOR_OFFSET 23 483 #define GEM_IRQCOR_SIZE 1 484 #define GEM_DBWDEF_OFFSET 25 485 #define GEM_DBWDEF_SIZE 3 486 #define GEM_NO_PCS_OFFSET 0 487 #define GEM_NO_PCS_SIZE 1 488 489 /* Bitfields in DCFG2. */ 490 #define GEM_RX_PKT_BUFF_OFFSET 20 491 #define GEM_RX_PKT_BUFF_SIZE 1 492 #define GEM_TX_PKT_BUFF_OFFSET 21 493 #define GEM_TX_PKT_BUFF_SIZE 1 494 495 496 /* Bitfields in DCFG5. */ 497 #define GEM_TSU_OFFSET 8 498 #define GEM_TSU_SIZE 1 499 500 /* Bitfields in DCFG6. */ 501 #define GEM_PBUF_LSO_OFFSET 27 502 #define GEM_PBUF_LSO_SIZE 1 503 #define GEM_DAW64_OFFSET 23 504 #define GEM_DAW64_SIZE 1 505 506 /* Bitfields in DCFG8. */ 507 #define GEM_T1SCR_OFFSET 24 508 #define GEM_T1SCR_SIZE 8 509 #define GEM_T2SCR_OFFSET 16 510 #define GEM_T2SCR_SIZE 8 511 #define GEM_SCR2ETH_OFFSET 8 512 #define GEM_SCR2ETH_SIZE 8 513 #define GEM_SCR2CMP_OFFSET 0 514 #define GEM_SCR2CMP_SIZE 8 515 516 /* Bitfields in DCFG10 */ 517 #define GEM_TXBD_RDBUFF_OFFSET 12 518 #define GEM_TXBD_RDBUFF_SIZE 4 519 #define GEM_RXBD_RDBUFF_OFFSET 8 520 #define GEM_RXBD_RDBUFF_SIZE 4 521 522 /* Bitfields in DCFG12. */ 523 #define GEM_HIGH_SPEED_OFFSET 26 524 #define GEM_HIGH_SPEED_SIZE 1 525 526 /* Bitfields in USX_CONTROL. */ 527 #define GEM_USX_CTRL_SPEED_OFFSET 14 528 #define GEM_USX_CTRL_SPEED_SIZE 3 529 #define GEM_SERDES_RATE_OFFSET 12 530 #define GEM_SERDES_RATE_SIZE 2 531 #define GEM_RX_SCR_BYPASS_OFFSET 9 532 #define GEM_RX_SCR_BYPASS_SIZE 1 533 #define GEM_TX_SCR_BYPASS_OFFSET 8 534 #define GEM_TX_SCR_BYPASS_SIZE 1 535 #define GEM_TX_EN_OFFSET 1 536 #define GEM_TX_EN_SIZE 1 537 #define GEM_SIGNAL_OK_OFFSET 0 538 #define GEM_SIGNAL_OK_SIZE 1 539 540 /* Bitfields in USX_STATUS. */ 541 #define GEM_USX_BLOCK_LOCK_OFFSET 0 542 #define GEM_USX_BLOCK_LOCK_SIZE 1 543 544 /* Bitfields in TISUBN */ 545 #define GEM_SUBNSINCR_OFFSET 0 546 #define GEM_SUBNSINCRL_OFFSET 24 547 #define GEM_SUBNSINCRL_SIZE 8 548 #define GEM_SUBNSINCRH_OFFSET 0 549 #define GEM_SUBNSINCRH_SIZE 16 550 #define GEM_SUBNSINCR_SIZE 24 551 552 /* Bitfields in TI */ 553 #define GEM_NSINCR_OFFSET 0 554 #define GEM_NSINCR_SIZE 8 555 556 /* Bitfields in TSH */ 557 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */ 558 #define GEM_TSH_SIZE 16 559 560 /* Bitfields in TSL */ 561 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */ 562 #define GEM_TSL_SIZE 32 563 564 /* Bitfields in TN */ 565 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */ 566 #define GEM_TN_SIZE 30 567 568 /* Bitfields in TXBDCTRL */ 569 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */ 570 #define GEM_TXTSMODE_SIZE 2 571 572 /* Bitfields in RXBDCTRL */ 573 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */ 574 #define GEM_RXTSMODE_SIZE 2 575 576 /* Bitfields in SCRT2 */ 577 #define GEM_QUEUE_OFFSET 0 /* Queue Number */ 578 #define GEM_QUEUE_SIZE 4 579 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */ 580 #define GEM_VLANPR_SIZE 3 581 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */ 582 #define GEM_VLANEN_SIZE 1 583 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */ 584 #define GEM_ETHT2IDX_SIZE 3 585 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */ 586 #define GEM_ETHTEN_SIZE 1 587 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */ 588 #define GEM_CMPA_SIZE 5 589 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */ 590 #define GEM_CMPAEN_SIZE 1 591 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */ 592 #define GEM_CMPB_SIZE 5 593 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */ 594 #define GEM_CMPBEN_SIZE 1 595 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */ 596 #define GEM_CMPC_SIZE 5 597 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */ 598 #define GEM_CMPCEN_SIZE 1 599 600 /* Bitfields in ETHT */ 601 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */ 602 #define GEM_ETHTCMP_SIZE 16 603 604 /* Bitfields in T2CMPW0 */ 605 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */ 606 #define GEM_T2CMP_SIZE 16 607 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */ 608 #define GEM_T2MASK_SIZE 16 609 610 /* Bitfields in T2CMPW1 */ 611 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */ 612 #define GEM_T2DISMSK_SIZE 1 613 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */ 614 #define GEM_T2CMPOFST_SIZE 2 615 #define GEM_T2OFST_OFFSET 0 /* offset value */ 616 #define GEM_T2OFST_SIZE 7 617 618 /* Offset for screener type 2 compare values (T2CMPOFST). 619 * Note the offset is applied after the specified point, 620 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset 621 * of 12 bytes from this would be the source IP address in an IP header 622 */ 623 #define GEM_T2COMPOFST_SOF 0 624 #define GEM_T2COMPOFST_ETYPE 1 625 #define GEM_T2COMPOFST_IPHDR 2 626 #define GEM_T2COMPOFST_TCPUDP 3 627 628 /* offset from EtherType to IP address */ 629 #define ETYPE_SRCIP_OFFSET 12 630 #define ETYPE_DSTIP_OFFSET 16 631 632 /* offset from IP header to port */ 633 #define IPHDR_SRCPORT_OFFSET 0 634 #define IPHDR_DSTPORT_OFFSET 2 635 636 /* Transmit DMA buffer descriptor Word 1 */ 637 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */ 638 #define GEM_DMA_TXVALID_SIZE 1 639 640 /* Receive DMA buffer descriptor Word 0 */ 641 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */ 642 #define GEM_DMA_RXVALID_SIZE 1 643 644 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */ 645 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */ 646 #define GEM_DMA_SECL_SIZE 2 647 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */ 648 #define GEM_DMA_NSEC_SIZE 30 649 650 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */ 651 652 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor. 653 * Old hardware supports only 6 bit precision but it is enough for PTP. 654 * Less accuracy is used always instead of checking hardware version. 655 */ 656 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */ 657 #define GEM_DMA_SECH_SIZE 4 658 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE) 659 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH) 660 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1) 661 662 /* Bitfields in ADJ */ 663 #define GEM_ADDSUB_OFFSET 31 664 #define GEM_ADDSUB_SIZE 1 665 /* Constants for CLK */ 666 #define MACB_CLK_DIV8 0 667 #define MACB_CLK_DIV16 1 668 #define MACB_CLK_DIV32 2 669 #define MACB_CLK_DIV64 3 670 671 /* GEM specific constants for CLK. */ 672 #define GEM_CLK_DIV8 0 673 #define GEM_CLK_DIV16 1 674 #define GEM_CLK_DIV32 2 675 #define GEM_CLK_DIV48 3 676 #define GEM_CLK_DIV64 4 677 #define GEM_CLK_DIV96 5 678 679 /* Constants for MAN register */ 680 #define MACB_MAN_C22_SOF 1 681 #define MACB_MAN_C22_WRITE 1 682 #define MACB_MAN_C22_READ 2 683 #define MACB_MAN_C22_CODE 2 684 685 #define MACB_MAN_C45_SOF 0 686 #define MACB_MAN_C45_ADDR 0 687 #define MACB_MAN_C45_WRITE 1 688 #define MACB_MAN_C45_POST_READ_INCR 2 689 #define MACB_MAN_C45_READ 3 690 #define MACB_MAN_C45_CODE 2 691 692 /* Capability mask bits */ 693 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 694 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 695 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 696 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 697 #define MACB_CAPS_USRIO_DISABLED 0x00000010 698 #define MACB_CAPS_JUMBO 0x00000020 699 #define MACB_CAPS_GEM_HAS_PTP 0x00000040 700 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 701 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 702 #define MACB_CAPS_CLK_HW_CHG 0x04000000 703 #define MACB_CAPS_MACB_IS_EMAC 0x08000000 704 #define MACB_CAPS_FIFO_MODE 0x10000000 705 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 706 #define MACB_CAPS_SG_DISABLED 0x40000000 707 #define MACB_CAPS_MACB_IS_GEM 0x80000000 708 #define MACB_CAPS_PCS 0x01000000 709 #define MACB_CAPS_HIGH_SPEED 0x02000000 710 711 /* LSO settings */ 712 #define MACB_LSO_UFO_ENABLE 0x01 713 #define MACB_LSO_TSO_ENABLE 0x02 714 715 /* Bit manipulation macros */ 716 #define MACB_BIT(name) \ 717 (1 << MACB_##name##_OFFSET) 718 #define MACB_BF(name,value) \ 719 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 720 << MACB_##name##_OFFSET) 721 #define MACB_BFEXT(name,value)\ 722 (((value) >> MACB_##name##_OFFSET) \ 723 & ((1 << MACB_##name##_SIZE) - 1)) 724 #define MACB_BFINS(name,value,old) \ 725 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 726 << MACB_##name##_OFFSET)) \ 727 | MACB_BF(name,value)) 728 729 #define GEM_BIT(name) \ 730 (1 << GEM_##name##_OFFSET) 731 #define GEM_BF(name, value) \ 732 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 733 << GEM_##name##_OFFSET) 734 #define GEM_BFEXT(name, value)\ 735 (((value) >> GEM_##name##_OFFSET) \ 736 & ((1 << GEM_##name##_SIZE) - 1)) 737 #define GEM_BFINS(name, value, old) \ 738 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 739 << GEM_##name##_OFFSET)) \ 740 | GEM_BF(name, value)) 741 742 /* Register access macros */ 743 #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg) 744 #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value)) 745 #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg) 746 #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value)) 747 #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg) 748 #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value)) 749 #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4) 750 #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value)) 751 752 #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */ 753 754 /* Conditional GEM/MACB macros. These perform the operation to the correct 755 * register dependent on whether the device is a GEM or a MACB. For registers 756 * and bitfields that are common across both devices, use macb_{read,write}l 757 * to avoid the cost of the conditional. 758 */ 759 #define macb_or_gem_writel(__bp, __reg, __value) \ 760 ({ \ 761 if (macb_is_gem((__bp))) \ 762 gem_writel((__bp), __reg, __value); \ 763 else \ 764 macb_writel((__bp), __reg, __value); \ 765 }) 766 767 #define macb_or_gem_readl(__bp, __reg) \ 768 ({ \ 769 u32 __v; \ 770 if (macb_is_gem((__bp))) \ 771 __v = gem_readl((__bp), __reg); \ 772 else \ 773 __v = macb_readl((__bp), __reg); \ 774 __v; \ 775 }) 776 777 #define MACB_READ_NSR(bp) macb_readl(bp, NSR) 778 779 /* struct macb_dma_desc - Hardware DMA descriptor 780 * @addr: DMA address of data buffer 781 * @ctrl: Control and status bits 782 */ 783 struct macb_dma_desc { 784 u32 addr; 785 u32 ctrl; 786 }; 787 788 #ifdef MACB_EXT_DESC 789 #define HW_DMA_CAP_32B 0 790 #define HW_DMA_CAP_64B (1 << 0) 791 #define HW_DMA_CAP_PTP (1 << 1) 792 #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP) 793 794 struct macb_dma_desc_64 { 795 u32 addrh; 796 u32 resvd; 797 }; 798 799 struct macb_dma_desc_ptp { 800 u32 ts_1; 801 u32 ts_2; 802 }; 803 804 struct gem_tx_ts { 805 struct sk_buff *skb; 806 struct macb_dma_desc_ptp desc_ptp; 807 }; 808 #endif 809 810 /* DMA descriptor bitfields */ 811 #define MACB_RX_USED_OFFSET 0 812 #define MACB_RX_USED_SIZE 1 813 #define MACB_RX_WRAP_OFFSET 1 814 #define MACB_RX_WRAP_SIZE 1 815 #define MACB_RX_WADDR_OFFSET 2 816 #define MACB_RX_WADDR_SIZE 30 817 818 #define MACB_RX_FRMLEN_OFFSET 0 819 #define MACB_RX_FRMLEN_SIZE 12 820 #define MACB_RX_OFFSET_OFFSET 12 821 #define MACB_RX_OFFSET_SIZE 2 822 #define MACB_RX_SOF_OFFSET 14 823 #define MACB_RX_SOF_SIZE 1 824 #define MACB_RX_EOF_OFFSET 15 825 #define MACB_RX_EOF_SIZE 1 826 #define MACB_RX_CFI_OFFSET 16 827 #define MACB_RX_CFI_SIZE 1 828 #define MACB_RX_VLAN_PRI_OFFSET 17 829 #define MACB_RX_VLAN_PRI_SIZE 3 830 #define MACB_RX_PRI_TAG_OFFSET 20 831 #define MACB_RX_PRI_TAG_SIZE 1 832 #define MACB_RX_VLAN_TAG_OFFSET 21 833 #define MACB_RX_VLAN_TAG_SIZE 1 834 #define MACB_RX_TYPEID_MATCH_OFFSET 22 835 #define MACB_RX_TYPEID_MATCH_SIZE 1 836 #define MACB_RX_SA4_MATCH_OFFSET 23 837 #define MACB_RX_SA4_MATCH_SIZE 1 838 #define MACB_RX_SA3_MATCH_OFFSET 24 839 #define MACB_RX_SA3_MATCH_SIZE 1 840 #define MACB_RX_SA2_MATCH_OFFSET 25 841 #define MACB_RX_SA2_MATCH_SIZE 1 842 #define MACB_RX_SA1_MATCH_OFFSET 26 843 #define MACB_RX_SA1_MATCH_SIZE 1 844 #define MACB_RX_EXT_MATCH_OFFSET 28 845 #define MACB_RX_EXT_MATCH_SIZE 1 846 #define MACB_RX_UHASH_MATCH_OFFSET 29 847 #define MACB_RX_UHASH_MATCH_SIZE 1 848 #define MACB_RX_MHASH_MATCH_OFFSET 30 849 #define MACB_RX_MHASH_MATCH_SIZE 1 850 #define MACB_RX_BROADCAST_OFFSET 31 851 #define MACB_RX_BROADCAST_SIZE 1 852 853 #define MACB_RX_FRMLEN_MASK 0xFFF 854 #define MACB_RX_JFRMLEN_MASK 0x3FFF 855 856 /* RX checksum offload disabled: bit 24 clear in NCFGR */ 857 #define GEM_RX_TYPEID_MATCH_OFFSET 22 858 #define GEM_RX_TYPEID_MATCH_SIZE 2 859 860 /* RX checksum offload enabled: bit 24 set in NCFGR */ 861 #define GEM_RX_CSUM_OFFSET 22 862 #define GEM_RX_CSUM_SIZE 2 863 864 #define MACB_TX_FRMLEN_OFFSET 0 865 #define MACB_TX_FRMLEN_SIZE 11 866 #define MACB_TX_LAST_OFFSET 15 867 #define MACB_TX_LAST_SIZE 1 868 #define MACB_TX_NOCRC_OFFSET 16 869 #define MACB_TX_NOCRC_SIZE 1 870 #define MACB_MSS_MFS_OFFSET 16 871 #define MACB_MSS_MFS_SIZE 14 872 #define MACB_TX_LSO_OFFSET 17 873 #define MACB_TX_LSO_SIZE 2 874 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19 875 #define MACB_TX_TCP_SEQ_SRC_SIZE 1 876 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 877 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 878 #define MACB_TX_UNDERRUN_OFFSET 28 879 #define MACB_TX_UNDERRUN_SIZE 1 880 #define MACB_TX_ERROR_OFFSET 29 881 #define MACB_TX_ERROR_SIZE 1 882 #define MACB_TX_WRAP_OFFSET 30 883 #define MACB_TX_WRAP_SIZE 1 884 #define MACB_TX_USED_OFFSET 31 885 #define MACB_TX_USED_SIZE 1 886 887 #define GEM_TX_FRMLEN_OFFSET 0 888 #define GEM_TX_FRMLEN_SIZE 14 889 890 /* Buffer descriptor constants */ 891 #define GEM_RX_CSUM_NONE 0 892 #define GEM_RX_CSUM_IP_ONLY 1 893 #define GEM_RX_CSUM_IP_TCP 2 894 #define GEM_RX_CSUM_IP_UDP 3 895 896 /* limit RX checksum offload to TCP and UDP packets */ 897 #define GEM_RX_CSUM_CHECKED_MASK 2 898 899 /* Scaled PPM fraction */ 900 #define PPM_FRACTION 16 901 902 /* struct macb_tx_skb - data about an skb which is being transmitted 903 * @skb: skb currently being transmitted, only set for the last buffer 904 * of the frame 905 * @mapping: DMA address of the skb's fragment buffer 906 * @size: size of the DMA mapped buffer 907 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 908 * false when buffer was mapped with dma_map_single() 909 */ 910 struct macb_tx_skb { 911 struct sk_buff *skb; 912 dma_addr_t mapping; 913 size_t size; 914 bool mapped_as_page; 915 }; 916 917 /* Hardware-collected statistics. Used when updating the network 918 * device stats by a periodic timer. 919 */ 920 struct macb_stats { 921 u32 rx_pause_frames; 922 u32 tx_ok; 923 u32 tx_single_cols; 924 u32 tx_multiple_cols; 925 u32 rx_ok; 926 u32 rx_fcs_errors; 927 u32 rx_align_errors; 928 u32 tx_deferred; 929 u32 tx_late_cols; 930 u32 tx_excessive_cols; 931 u32 tx_underruns; 932 u32 tx_carrier_errors; 933 u32 rx_resource_errors; 934 u32 rx_overruns; 935 u32 rx_symbol_errors; 936 u32 rx_oversize_pkts; 937 u32 rx_jabbers; 938 u32 rx_undersize_pkts; 939 u32 sqe_test_errors; 940 u32 rx_length_mismatch; 941 u32 tx_pause_frames; 942 }; 943 944 struct gem_stats { 945 u32 tx_octets_31_0; 946 u32 tx_octets_47_32; 947 u32 tx_frames; 948 u32 tx_broadcast_frames; 949 u32 tx_multicast_frames; 950 u32 tx_pause_frames; 951 u32 tx_64_byte_frames; 952 u32 tx_65_127_byte_frames; 953 u32 tx_128_255_byte_frames; 954 u32 tx_256_511_byte_frames; 955 u32 tx_512_1023_byte_frames; 956 u32 tx_1024_1518_byte_frames; 957 u32 tx_greater_than_1518_byte_frames; 958 u32 tx_underrun; 959 u32 tx_single_collision_frames; 960 u32 tx_multiple_collision_frames; 961 u32 tx_excessive_collisions; 962 u32 tx_late_collisions; 963 u32 tx_deferred_frames; 964 u32 tx_carrier_sense_errors; 965 u32 rx_octets_31_0; 966 u32 rx_octets_47_32; 967 u32 rx_frames; 968 u32 rx_broadcast_frames; 969 u32 rx_multicast_frames; 970 u32 rx_pause_frames; 971 u32 rx_64_byte_frames; 972 u32 rx_65_127_byte_frames; 973 u32 rx_128_255_byte_frames; 974 u32 rx_256_511_byte_frames; 975 u32 rx_512_1023_byte_frames; 976 u32 rx_1024_1518_byte_frames; 977 u32 rx_greater_than_1518_byte_frames; 978 u32 rx_undersized_frames; 979 u32 rx_oversize_frames; 980 u32 rx_jabbers; 981 u32 rx_frame_check_sequence_errors; 982 u32 rx_length_field_frame_errors; 983 u32 rx_symbol_errors; 984 u32 rx_alignment_errors; 985 u32 rx_resource_errors; 986 u32 rx_overruns; 987 u32 rx_ip_header_checksum_errors; 988 u32 rx_tcp_checksum_errors; 989 u32 rx_udp_checksum_errors; 990 }; 991 992 /* Describes the name and offset of an individual statistic register, as 993 * returned by `ethtool -S`. Also describes which net_device_stats statistics 994 * this register should contribute to. 995 */ 996 struct gem_statistic { 997 char stat_string[ETH_GSTRING_LEN]; 998 int offset; 999 u32 stat_bits; 1000 }; 1001 1002 /* Bitfield defs for net_device_stat statistics */ 1003 #define GEM_NDS_RXERR_OFFSET 0 1004 #define GEM_NDS_RXLENERR_OFFSET 1 1005 #define GEM_NDS_RXOVERERR_OFFSET 2 1006 #define GEM_NDS_RXCRCERR_OFFSET 3 1007 #define GEM_NDS_RXFRAMEERR_OFFSET 4 1008 #define GEM_NDS_RXFIFOERR_OFFSET 5 1009 #define GEM_NDS_TXERR_OFFSET 6 1010 #define GEM_NDS_TXABORTEDERR_OFFSET 7 1011 #define GEM_NDS_TXCARRIERERR_OFFSET 8 1012 #define GEM_NDS_TXFIFOERR_OFFSET 9 1013 #define GEM_NDS_COLLISIONS_OFFSET 10 1014 1015 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0) 1016 #define GEM_STAT_TITLE_BITS(name, title, bits) { \ 1017 .stat_string = title, \ 1018 .offset = GEM_##name, \ 1019 .stat_bits = bits \ 1020 } 1021 1022 /* list of gem statistic registers. The names MUST match the 1023 * corresponding GEM_* definitions. 1024 */ 1025 static const struct gem_statistic gem_statistics[] = { 1026 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */ 1027 GEM_STAT_TITLE(TXCNT, "tx_frames"), 1028 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"), 1029 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"), 1030 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"), 1031 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"), 1032 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"), 1033 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"), 1034 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"), 1035 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"), 1036 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"), 1037 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"), 1038 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun", 1039 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)), 1040 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames", 1041 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1042 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames", 1043 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1044 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions", 1045 GEM_BIT(NDS_TXERR)| 1046 GEM_BIT(NDS_TXABORTEDERR)| 1047 GEM_BIT(NDS_COLLISIONS)), 1048 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions", 1049 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1050 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"), 1051 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors", 1052 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)), 1053 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */ 1054 GEM_STAT_TITLE(RXCNT, "rx_frames"), 1055 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"), 1056 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"), 1057 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"), 1058 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"), 1059 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"), 1060 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"), 1061 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"), 1062 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"), 1063 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"), 1064 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"), 1065 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames", 1066 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 1067 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames", 1068 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 1069 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers", 1070 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)), 1071 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors", 1072 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)), 1073 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors", 1074 GEM_BIT(NDS_RXERR)), 1075 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors", 1076 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)), 1077 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors", 1078 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 1079 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors", 1080 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)), 1081 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns", 1082 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)), 1083 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors", 1084 GEM_BIT(NDS_RXERR)), 1085 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors", 1086 GEM_BIT(NDS_RXERR)), 1087 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors", 1088 GEM_BIT(NDS_RXERR)), 1089 }; 1090 1091 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics) 1092 1093 #define QUEUE_STAT_TITLE(title) { \ 1094 .stat_string = title, \ 1095 } 1096 1097 /* per queue statistics, each should be unsigned long type */ 1098 struct queue_stats { 1099 union { 1100 unsigned long first; 1101 unsigned long rx_packets; 1102 }; 1103 unsigned long rx_bytes; 1104 unsigned long rx_dropped; 1105 unsigned long tx_packets; 1106 unsigned long tx_bytes; 1107 unsigned long tx_dropped; 1108 }; 1109 1110 static const struct gem_statistic queue_statistics[] = { 1111 QUEUE_STAT_TITLE("rx_packets"), 1112 QUEUE_STAT_TITLE("rx_bytes"), 1113 QUEUE_STAT_TITLE("rx_dropped"), 1114 QUEUE_STAT_TITLE("tx_packets"), 1115 QUEUE_STAT_TITLE("tx_bytes"), 1116 QUEUE_STAT_TITLE("tx_dropped"), 1117 }; 1118 1119 #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics) 1120 1121 struct macb; 1122 struct macb_queue; 1123 1124 struct macb_or_gem_ops { 1125 int (*mog_alloc_rx_buffers)(struct macb *bp); 1126 void (*mog_free_rx_buffers)(struct macb *bp); 1127 void (*mog_init_rings)(struct macb *bp); 1128 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi, 1129 int budget); 1130 }; 1131 1132 /* MACB-PTP interface: adapt to platform needs. */ 1133 struct macb_ptp_info { 1134 void (*ptp_init)(struct net_device *ndev); 1135 void (*ptp_remove)(struct net_device *ndev); 1136 s32 (*get_ptp_max_adj)(void); 1137 unsigned int (*get_tsu_rate)(struct macb *bp); 1138 int (*get_ts_info)(struct net_device *dev, 1139 struct ethtool_ts_info *info); 1140 int (*get_hwtst)(struct net_device *netdev, 1141 struct ifreq *ifr); 1142 int (*set_hwtst)(struct net_device *netdev, 1143 struct ifreq *ifr, int cmd); 1144 }; 1145 1146 struct macb_pm_data { 1147 u32 scrt2; 1148 u32 usrio; 1149 }; 1150 1151 struct macb_usrio_config { 1152 u32 mii; 1153 u32 rmii; 1154 u32 rgmii; 1155 u32 refclk; 1156 u32 hdfctlen; 1157 }; 1158 1159 struct macb_config { 1160 u32 caps; 1161 unsigned int dma_burst_length; 1162 int (*clk_init)(struct platform_device *pdev, struct clk **pclk, 1163 struct clk **hclk, struct clk **tx_clk, 1164 struct clk **rx_clk, struct clk **tsu_clk); 1165 int (*init)(struct platform_device *pdev); 1166 int jumbo_max_len; 1167 const struct macb_usrio_config *usrio; 1168 }; 1169 1170 struct tsu_incr { 1171 u32 sub_ns; 1172 u32 ns; 1173 }; 1174 1175 struct macb_queue { 1176 struct macb *bp; 1177 int irq; 1178 1179 unsigned int ISR; 1180 unsigned int IER; 1181 unsigned int IDR; 1182 unsigned int IMR; 1183 unsigned int TBQP; 1184 unsigned int TBQPH; 1185 unsigned int RBQS; 1186 unsigned int RBQP; 1187 unsigned int RBQPH; 1188 1189 unsigned int tx_head, tx_tail; 1190 struct macb_dma_desc *tx_ring; 1191 struct macb_tx_skb *tx_skb; 1192 dma_addr_t tx_ring_dma; 1193 struct work_struct tx_error_task; 1194 1195 dma_addr_t rx_ring_dma; 1196 dma_addr_t rx_buffers_dma; 1197 unsigned int rx_tail; 1198 unsigned int rx_prepared_head; 1199 struct macb_dma_desc *rx_ring; 1200 struct sk_buff **rx_skbuff; 1201 void *rx_buffers; 1202 struct napi_struct napi; 1203 struct queue_stats stats; 1204 1205 #ifdef CONFIG_MACB_USE_HWSTAMP 1206 struct work_struct tx_ts_task; 1207 unsigned int tx_ts_head, tx_ts_tail; 1208 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE]; 1209 #endif 1210 }; 1211 1212 struct ethtool_rx_fs_item { 1213 struct ethtool_rx_flow_spec fs; 1214 struct list_head list; 1215 }; 1216 1217 struct ethtool_rx_fs_list { 1218 struct list_head list; 1219 unsigned int count; 1220 }; 1221 1222 struct macb { 1223 void __iomem *regs; 1224 bool native_io; 1225 1226 /* hardware IO accessors */ 1227 u32 (*macb_reg_readl)(struct macb *bp, int offset); 1228 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value); 1229 1230 size_t rx_buffer_size; 1231 1232 unsigned int rx_ring_size; 1233 unsigned int tx_ring_size; 1234 1235 unsigned int num_queues; 1236 unsigned int queue_mask; 1237 struct macb_queue queues[MACB_MAX_QUEUES]; 1238 1239 spinlock_t lock; 1240 struct platform_device *pdev; 1241 struct clk *pclk; 1242 struct clk *hclk; 1243 struct clk *tx_clk; 1244 struct clk *rx_clk; 1245 struct clk *tsu_clk; 1246 struct net_device *dev; 1247 union { 1248 struct macb_stats macb; 1249 struct gem_stats gem; 1250 } hw_stats; 1251 1252 struct macb_or_gem_ops macbgem_ops; 1253 1254 struct mii_bus *mii_bus; 1255 struct phylink *phylink; 1256 struct phylink_config phylink_config; 1257 struct phylink_pcs phylink_pcs; 1258 1259 u32 caps; 1260 unsigned int dma_burst_length; 1261 1262 phy_interface_t phy_interface; 1263 1264 /* AT91RM9200 transmit queue (1 on wire + 1 queued) */ 1265 struct macb_tx_skb rm9200_txq[2]; 1266 unsigned int max_tx_length; 1267 1268 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES]; 1269 1270 unsigned int rx_frm_len_mask; 1271 unsigned int jumbo_max_len; 1272 1273 u32 wol; 1274 1275 struct macb_ptp_info *ptp_info; /* macb-ptp interface */ 1276 #ifdef MACB_EXT_DESC 1277 uint8_t hw_dma_cap; 1278 #endif 1279 spinlock_t tsu_clk_lock; /* gem tsu clock locking */ 1280 unsigned int tsu_rate; 1281 struct ptp_clock *ptp_clock; 1282 struct ptp_clock_info ptp_clock_info; 1283 struct tsu_incr tsu_incr; 1284 struct hwtstamp_config tstamp_config; 1285 1286 /* RX queue filer rule set*/ 1287 struct ethtool_rx_fs_list rx_fs_list; 1288 spinlock_t rx_fs_lock; 1289 unsigned int max_tuples; 1290 1291 struct tasklet_struct hresp_err_tasklet; 1292 1293 int rx_bd_rd_prefetch; 1294 int tx_bd_rd_prefetch; 1295 1296 u32 rx_intr_mask; 1297 1298 struct macb_pm_data pm_data; 1299 const struct macb_usrio_config *usrio; 1300 }; 1301 1302 #ifdef CONFIG_MACB_USE_HWSTAMP 1303 #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE) 1304 #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1) 1305 #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1) 1306 1307 enum macb_bd_control { 1308 TSTAMP_DISABLED, 1309 TSTAMP_FRAME_PTP_EVENT_ONLY, 1310 TSTAMP_ALL_PTP_FRAMES, 1311 TSTAMP_ALL_FRAMES, 1312 }; 1313 1314 void gem_ptp_init(struct net_device *ndev); 1315 void gem_ptp_remove(struct net_device *ndev); 1316 int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des); 1317 void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc); 1318 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) 1319 { 1320 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED) 1321 return -ENOTSUPP; 1322 1323 return gem_ptp_txstamp(queue, skb, desc); 1324 } 1325 1326 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) 1327 { 1328 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED) 1329 return; 1330 1331 gem_ptp_rxstamp(bp, skb, desc); 1332 } 1333 int gem_get_hwtst(struct net_device *dev, struct ifreq *rq); 1334 int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd); 1335 #else 1336 static inline void gem_ptp_init(struct net_device *ndev) { } 1337 static inline void gem_ptp_remove(struct net_device *ndev) { } 1338 1339 static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc) 1340 { 1341 return -1; 1342 } 1343 1344 static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { } 1345 #endif 1346 1347 static inline bool macb_is_gem(struct macb *bp) 1348 { 1349 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 1350 } 1351 1352 static inline bool gem_has_ptp(struct macb *bp) 1353 { 1354 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP); 1355 } 1356 1357 /** 1358 * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration 1359 * @pclk: platform clock 1360 * @hclk: AHB clock 1361 */ 1362 struct macb_platform_data { 1363 struct clk *pclk; 1364 struct clk *hclk; 1365 }; 1366 1367 #endif /* _MACB_H */ 1368