1 /*
2  * Atmel MACB Ethernet Controller driver
3  *
4  * Copyright (C) 2004-2006 Atmel Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 #ifndef _MACB_H
11 #define _MACB_H
12 
13 #define MACB_GREGS_NBR 16
14 #define MACB_GREGS_VERSION 2
15 #define MACB_MAX_QUEUES 8
16 
17 /* MACB register offsets */
18 #define MACB_NCR		0x0000 /* Network Control */
19 #define MACB_NCFGR		0x0004 /* Network Config */
20 #define MACB_NSR		0x0008 /* Network Status */
21 #define MACB_TAR		0x000c /* AT91RM9200 only */
22 #define MACB_TCR		0x0010 /* AT91RM9200 only */
23 #define MACB_TSR		0x0014 /* Transmit Status */
24 #define MACB_RBQP		0x0018 /* RX Q Base Address */
25 #define MACB_TBQP		0x001c /* TX Q Base Address */
26 #define MACB_RSR		0x0020 /* Receive Status */
27 #define MACB_ISR		0x0024 /* Interrupt Status */
28 #define MACB_IER		0x0028 /* Interrupt Enable */
29 #define MACB_IDR		0x002c /* Interrupt Disable */
30 #define MACB_IMR		0x0030 /* Interrupt Mask */
31 #define MACB_MAN		0x0034 /* PHY Maintenance */
32 #define MACB_PTR		0x0038
33 #define MACB_PFR		0x003c
34 #define MACB_FTO		0x0040
35 #define MACB_SCF		0x0044
36 #define MACB_MCF		0x0048
37 #define MACB_FRO		0x004c
38 #define MACB_FCSE		0x0050
39 #define MACB_ALE		0x0054
40 #define MACB_DTF		0x0058
41 #define MACB_LCOL		0x005c
42 #define MACB_EXCOL		0x0060
43 #define MACB_TUND		0x0064
44 #define MACB_CSE		0x0068
45 #define MACB_RRE		0x006c
46 #define MACB_ROVR		0x0070
47 #define MACB_RSE		0x0074
48 #define MACB_ELE		0x0078
49 #define MACB_RJA		0x007c
50 #define MACB_USF		0x0080
51 #define MACB_STE		0x0084
52 #define MACB_RLE		0x0088
53 #define MACB_TPF		0x008c
54 #define MACB_HRB		0x0090
55 #define MACB_HRT		0x0094
56 #define MACB_SA1B		0x0098
57 #define MACB_SA1T		0x009c
58 #define MACB_SA2B		0x00a0
59 #define MACB_SA2T		0x00a4
60 #define MACB_SA3B		0x00a8
61 #define MACB_SA3T		0x00ac
62 #define MACB_SA4B		0x00b0
63 #define MACB_SA4T		0x00b4
64 #define MACB_TID		0x00b8
65 #define MACB_TPQ		0x00bc
66 #define MACB_USRIO		0x00c0
67 #define MACB_WOL		0x00c4
68 #define MACB_MID		0x00fc
69 #define MACB_TBQPH		0x04C8
70 #define MACB_RBQPH		0x04D4
71 
72 /* GEM register offsets. */
73 #define GEM_NCFGR		0x0004 /* Network Config */
74 #define GEM_USRIO		0x000c /* User IO */
75 #define GEM_DMACFG		0x0010 /* DMA Configuration */
76 #define GEM_JML			0x0048 /* Jumbo Max Length */
77 #define GEM_HRB			0x0080 /* Hash Bottom */
78 #define GEM_HRT			0x0084 /* Hash Top */
79 #define GEM_SA1B		0x0088 /* Specific1 Bottom */
80 #define GEM_SA1T		0x008C /* Specific1 Top */
81 #define GEM_SA2B		0x0090 /* Specific2 Bottom */
82 #define GEM_SA2T		0x0094 /* Specific2 Top */
83 #define GEM_SA3B		0x0098 /* Specific3 Bottom */
84 #define GEM_SA3T		0x009C /* Specific3 Top */
85 #define GEM_SA4B		0x00A0 /* Specific4 Bottom */
86 #define GEM_SA4T		0x00A4 /* Specific4 Top */
87 #define GEM_OTX			0x0100 /* Octets transmitted */
88 #define GEM_OCTTXL		0x0100 /* Octets transmitted [31:0] */
89 #define GEM_OCTTXH		0x0104 /* Octets transmitted [47:32] */
90 #define GEM_TXCNT		0x0108 /* Frames Transmitted counter */
91 #define GEM_TXBCCNT		0x010c /* Broadcast Frames counter */
92 #define GEM_TXMCCNT		0x0110 /* Multicast Frames counter */
93 #define GEM_TXPAUSECNT		0x0114 /* Pause Frames Transmitted Counter */
94 #define GEM_TX64CNT		0x0118 /* 64 byte Frames TX counter */
95 #define GEM_TX65CNT		0x011c /* 65-127 byte Frames TX counter */
96 #define GEM_TX128CNT		0x0120 /* 128-255 byte Frames TX counter */
97 #define GEM_TX256CNT		0x0124 /* 256-511 byte Frames TX counter */
98 #define GEM_TX512CNT		0x0128 /* 512-1023 byte Frames TX counter */
99 #define GEM_TX1024CNT		0x012c /* 1024-1518 byte Frames TX counter */
100 #define GEM_TX1519CNT		0x0130 /* 1519+ byte Frames TX counter */
101 #define GEM_TXURUNCNT		0x0134 /* TX under run error counter */
102 #define GEM_SNGLCOLLCNT		0x0138 /* Single Collision Frame Counter */
103 #define GEM_MULTICOLLCNT	0x013c /* Multiple Collision Frame Counter */
104 #define GEM_EXCESSCOLLCNT	0x0140 /* Excessive Collision Frame Counter */
105 #define GEM_LATECOLLCNT		0x0144 /* Late Collision Frame Counter */
106 #define GEM_TXDEFERCNT		0x0148 /* Deferred Transmission Frame Counter */
107 #define GEM_TXCSENSECNT		0x014c /* Carrier Sense Error Counter */
108 #define GEM_ORX			0x0150 /* Octets received */
109 #define GEM_OCTRXL		0x0150 /* Octets received [31:0] */
110 #define GEM_OCTRXH		0x0154 /* Octets received [47:32] */
111 #define GEM_RXCNT		0x0158 /* Frames Received Counter */
112 #define GEM_RXBROADCNT		0x015c /* Broadcast Frames Received Counter */
113 #define GEM_RXMULTICNT		0x0160 /* Multicast Frames Received Counter */
114 #define GEM_RXPAUSECNT		0x0164 /* Pause Frames Received Counter */
115 #define GEM_RX64CNT		0x0168 /* 64 byte Frames RX Counter */
116 #define GEM_RX65CNT		0x016c /* 65-127 byte Frames RX Counter */
117 #define GEM_RX128CNT		0x0170 /* 128-255 byte Frames RX Counter */
118 #define GEM_RX256CNT		0x0174 /* 256-511 byte Frames RX Counter */
119 #define GEM_RX512CNT		0x0178 /* 512-1023 byte Frames RX Counter */
120 #define GEM_RX1024CNT		0x017c /* 1024-1518 byte Frames RX Counter */
121 #define GEM_RX1519CNT		0x0180 /* 1519+ byte Frames RX Counter */
122 #define GEM_RXUNDRCNT		0x0184 /* Undersize Frames Received Counter */
123 #define GEM_RXOVRCNT		0x0188 /* Oversize Frames Received Counter */
124 #define GEM_RXJABCNT		0x018c /* Jabbers Received Counter */
125 #define GEM_RXFCSCNT		0x0190 /* Frame Check Sequence Error Counter */
126 #define GEM_RXLENGTHCNT		0x0194 /* Length Field Error Counter */
127 #define GEM_RXSYMBCNT		0x0198 /* Symbol Error Counter */
128 #define GEM_RXALIGNCNT		0x019c /* Alignment Error Counter */
129 #define GEM_RXRESERRCNT		0x01a0 /* Receive Resource Error Counter */
130 #define GEM_RXORCNT		0x01a4 /* Receive Overrun Counter */
131 #define GEM_RXIPCCNT		0x01a8 /* IP header Checksum Error Counter */
132 #define GEM_RXTCPCCNT		0x01ac /* TCP Checksum Error Counter */
133 #define GEM_RXUDPCCNT		0x01b0 /* UDP Checksum Error Counter */
134 #define GEM_DCFG1		0x0280 /* Design Config 1 */
135 #define GEM_DCFG2		0x0284 /* Design Config 2 */
136 #define GEM_DCFG3		0x0288 /* Design Config 3 */
137 #define GEM_DCFG4		0x028c /* Design Config 4 */
138 #define GEM_DCFG5		0x0290 /* Design Config 5 */
139 #define GEM_DCFG6		0x0294 /* Design Config 6 */
140 #define GEM_DCFG7		0x0298 /* Design Config 7 */
141 
142 #define GEM_ISR(hw_q)		(0x0400 + ((hw_q) << 2))
143 #define GEM_TBQP(hw_q)		(0x0440 + ((hw_q) << 2))
144 #define GEM_TBQPH(hw_q)		(0x04C8)
145 #define GEM_RBQP(hw_q)		(0x0480 + ((hw_q) << 2))
146 #define GEM_IER(hw_q)		(0x0600 + ((hw_q) << 2))
147 #define GEM_IDR(hw_q)		(0x0620 + ((hw_q) << 2))
148 #define GEM_IMR(hw_q)		(0x0640 + ((hw_q) << 2))
149 
150 /* Bitfields in NCR */
151 #define MACB_LB_OFFSET		0 /* reserved */
152 #define MACB_LB_SIZE		1
153 #define MACB_LLB_OFFSET		1 /* Loop back local */
154 #define MACB_LLB_SIZE		1
155 #define MACB_RE_OFFSET		2 /* Receive enable */
156 #define MACB_RE_SIZE		1
157 #define MACB_TE_OFFSET		3 /* Transmit enable */
158 #define MACB_TE_SIZE		1
159 #define MACB_MPE_OFFSET		4 /* Management port enable */
160 #define MACB_MPE_SIZE		1
161 #define MACB_CLRSTAT_OFFSET	5 /* Clear stats regs */
162 #define MACB_CLRSTAT_SIZE	1
163 #define MACB_INCSTAT_OFFSET	6 /* Incremental stats regs */
164 #define MACB_INCSTAT_SIZE	1
165 #define MACB_WESTAT_OFFSET	7 /* Write enable stats regs */
166 #define MACB_WESTAT_SIZE	1
167 #define MACB_BP_OFFSET		8 /* Back pressure */
168 #define MACB_BP_SIZE		1
169 #define MACB_TSTART_OFFSET	9 /* Start transmission */
170 #define MACB_TSTART_SIZE	1
171 #define MACB_THALT_OFFSET	10 /* Transmit halt */
172 #define MACB_THALT_SIZE		1
173 #define MACB_NCR_TPF_OFFSET	11 /* Transmit pause frame */
174 #define MACB_NCR_TPF_SIZE	1
175 #define MACB_TZQ_OFFSET		12 /* Transmit zero quantum pause frame */
176 #define MACB_TZQ_SIZE		1
177 
178 /* Bitfields in NCFGR */
179 #define MACB_SPD_OFFSET		0 /* Speed */
180 #define MACB_SPD_SIZE		1
181 #define MACB_FD_OFFSET		1 /* Full duplex */
182 #define MACB_FD_SIZE		1
183 #define MACB_BIT_RATE_OFFSET	2 /* Discard non-VLAN frames */
184 #define MACB_BIT_RATE_SIZE	1
185 #define MACB_JFRAME_OFFSET	3 /* reserved */
186 #define MACB_JFRAME_SIZE	1
187 #define MACB_CAF_OFFSET		4 /* Copy all frames */
188 #define MACB_CAF_SIZE		1
189 #define MACB_NBC_OFFSET		5 /* No broadcast */
190 #define MACB_NBC_SIZE		1
191 #define MACB_NCFGR_MTI_OFFSET	6 /* Multicast hash enable */
192 #define MACB_NCFGR_MTI_SIZE	1
193 #define MACB_UNI_OFFSET		7 /* Unicast hash enable */
194 #define MACB_UNI_SIZE		1
195 #define MACB_BIG_OFFSET		8 /* Receive 1536 byte frames */
196 #define MACB_BIG_SIZE		1
197 #define MACB_EAE_OFFSET		9 /* External address match enable */
198 #define MACB_EAE_SIZE		1
199 #define MACB_CLK_OFFSET		10
200 #define MACB_CLK_SIZE		2
201 #define MACB_RTY_OFFSET		12 /* Retry test */
202 #define MACB_RTY_SIZE		1
203 #define MACB_PAE_OFFSET		13 /* Pause enable */
204 #define MACB_PAE_SIZE		1
205 #define MACB_RM9200_RMII_OFFSET	13 /* AT91RM9200 only */
206 #define MACB_RM9200_RMII_SIZE	1  /* AT91RM9200 only */
207 #define MACB_RBOF_OFFSET	14 /* Receive buffer offset */
208 #define MACB_RBOF_SIZE		2
209 #define MACB_RLCE_OFFSET	16 /* Length field error frame discard */
210 #define MACB_RLCE_SIZE		1
211 #define MACB_DRFCS_OFFSET	17 /* FCS remove */
212 #define MACB_DRFCS_SIZE		1
213 #define MACB_EFRHD_OFFSET	18
214 #define MACB_EFRHD_SIZE		1
215 #define MACB_IRXFCS_OFFSET	19
216 #define MACB_IRXFCS_SIZE	1
217 
218 /* GEM specific NCFGR bitfields. */
219 #define GEM_GBE_OFFSET		10 /* Gigabit mode enable */
220 #define GEM_GBE_SIZE		1
221 #define GEM_PCSSEL_OFFSET	11
222 #define GEM_PCSSEL_SIZE		1
223 #define GEM_CLK_OFFSET		18 /* MDC clock division */
224 #define GEM_CLK_SIZE		3
225 #define GEM_DBW_OFFSET		21 /* Data bus width */
226 #define GEM_DBW_SIZE		2
227 #define GEM_RXCOEN_OFFSET	24
228 #define GEM_RXCOEN_SIZE		1
229 #define GEM_SGMIIEN_OFFSET	27
230 #define GEM_SGMIIEN_SIZE	1
231 
232 
233 /* Constants for data bus width. */
234 #define GEM_DBW32		0 /* 32 bit AMBA AHB data bus width */
235 #define GEM_DBW64		1 /* 64 bit AMBA AHB data bus width */
236 #define GEM_DBW128		2 /* 128 bit AMBA AHB data bus width */
237 
238 /* Bitfields in DMACFG. */
239 #define GEM_FBLDO_OFFSET	0 /* fixed burst length for DMA */
240 #define GEM_FBLDO_SIZE		5
241 #define GEM_ENDIA_DESC_OFFSET	6 /* endian swap mode for management descriptor access */
242 #define GEM_ENDIA_DESC_SIZE	1
243 #define GEM_ENDIA_PKT_OFFSET	7 /* endian swap mode for packet data access */
244 #define GEM_ENDIA_PKT_SIZE	1
245 #define GEM_RXBMS_OFFSET	8 /* RX packet buffer memory size select */
246 #define GEM_RXBMS_SIZE		2
247 #define GEM_TXPBMS_OFFSET	10 /* TX packet buffer memory size select */
248 #define GEM_TXPBMS_SIZE		1
249 #define GEM_TXCOEN_OFFSET	11 /* TX IP/TCP/UDP checksum gen offload */
250 #define GEM_TXCOEN_SIZE		1
251 #define GEM_RXBS_OFFSET		16 /* DMA receive buffer size */
252 #define GEM_RXBS_SIZE		8
253 #define GEM_DDRP_OFFSET		24 /* disc_when_no_ahb */
254 #define GEM_DDRP_SIZE		1
255 #define GEM_ADDR64_OFFSET	30 /* Address bus width - 64b or 32b */
256 #define GEM_ADDR64_SIZE		1
257 
258 
259 /* Bitfields in NSR */
260 #define MACB_NSR_LINK_OFFSET	0 /* pcs_link_state */
261 #define MACB_NSR_LINK_SIZE	1
262 #define MACB_MDIO_OFFSET	1 /* status of the mdio_in pin */
263 #define MACB_MDIO_SIZE		1
264 #define MACB_IDLE_OFFSET	2 /* The PHY management logic is idle */
265 #define MACB_IDLE_SIZE		1
266 
267 /* Bitfields in TSR */
268 #define MACB_UBR_OFFSET		0 /* Used bit read */
269 #define MACB_UBR_SIZE		1
270 #define MACB_COL_OFFSET		1 /* Collision occurred */
271 #define MACB_COL_SIZE		1
272 #define MACB_TSR_RLE_OFFSET	2 /* Retry limit exceeded */
273 #define MACB_TSR_RLE_SIZE	1
274 #define MACB_TGO_OFFSET		3 /* Transmit go */
275 #define MACB_TGO_SIZE		1
276 #define MACB_BEX_OFFSET		4 /* TX frame corruption due to AHB error */
277 #define MACB_BEX_SIZE		1
278 #define MACB_RM9200_BNQ_OFFSET	4 /* AT91RM9200 only */
279 #define MACB_RM9200_BNQ_SIZE	1 /* AT91RM9200 only */
280 #define MACB_COMP_OFFSET	5 /* Trnasmit complete */
281 #define MACB_COMP_SIZE		1
282 #define MACB_UND_OFFSET		6 /* Trnasmit under run */
283 #define MACB_UND_SIZE		1
284 
285 /* Bitfields in RSR */
286 #define MACB_BNA_OFFSET		0 /* Buffer not available */
287 #define MACB_BNA_SIZE		1
288 #define MACB_REC_OFFSET		1 /* Frame received */
289 #define MACB_REC_SIZE		1
290 #define MACB_OVR_OFFSET		2 /* Receive overrun */
291 #define MACB_OVR_SIZE		1
292 
293 /* Bitfields in ISR/IER/IDR/IMR */
294 #define MACB_MFD_OFFSET		0 /* Management frame sent */
295 #define MACB_MFD_SIZE		1
296 #define MACB_RCOMP_OFFSET	1 /* Receive complete */
297 #define MACB_RCOMP_SIZE		1
298 #define MACB_RXUBR_OFFSET	2 /* RX used bit read */
299 #define MACB_RXUBR_SIZE		1
300 #define MACB_TXUBR_OFFSET	3 /* TX used bit read */
301 #define MACB_TXUBR_SIZE		1
302 #define MACB_ISR_TUND_OFFSET	4 /* Enable TX buffer under run interrupt */
303 #define MACB_ISR_TUND_SIZE	1
304 #define MACB_ISR_RLE_OFFSET	5 /* EN retry exceeded/late coll interrupt */
305 #define MACB_ISR_RLE_SIZE	1
306 #define MACB_TXERR_OFFSET	6 /* EN TX frame corrupt from error interrupt */
307 #define MACB_TXERR_SIZE		1
308 #define MACB_TCOMP_OFFSET	7 /* Enable transmit complete interrupt */
309 #define MACB_TCOMP_SIZE		1
310 #define MACB_ISR_LINK_OFFSET	9 /* Enable link change interrupt */
311 #define MACB_ISR_LINK_SIZE	1
312 #define MACB_ISR_ROVR_OFFSET	10 /* Enable receive overrun interrupt */
313 #define MACB_ISR_ROVR_SIZE	1
314 #define MACB_HRESP_OFFSET	11 /* Enable hrsep not OK interrupt */
315 #define MACB_HRESP_SIZE		1
316 #define MACB_PFR_OFFSET		12 /* Enable pause frame w/ quantum interrupt */
317 #define MACB_PFR_SIZE		1
318 #define MACB_PTZ_OFFSET		13 /* Enable pause time zero interrupt */
319 #define MACB_PTZ_SIZE		1
320 #define MACB_WOL_OFFSET		14 /* Enable wake-on-lan interrupt */
321 #define MACB_WOL_SIZE		1
322 
323 /* Bitfields in MAN */
324 #define MACB_DATA_OFFSET	0 /* data */
325 #define MACB_DATA_SIZE		16
326 #define MACB_CODE_OFFSET	16 /* Must be written to 10 */
327 #define MACB_CODE_SIZE		2
328 #define MACB_REGA_OFFSET	18 /* Register address */
329 #define MACB_REGA_SIZE		5
330 #define MACB_PHYA_OFFSET	23 /* PHY address */
331 #define MACB_PHYA_SIZE		5
332 #define MACB_RW_OFFSET		28 /* Operation. 10 is read. 01 is write. */
333 #define MACB_RW_SIZE		2
334 #define MACB_SOF_OFFSET		30 /* Must be written to 1 for Clause 22 */
335 #define MACB_SOF_SIZE		2
336 
337 /* Bitfields in USRIO (AVR32) */
338 #define MACB_MII_OFFSET				0
339 #define MACB_MII_SIZE				1
340 #define MACB_EAM_OFFSET				1
341 #define MACB_EAM_SIZE				1
342 #define MACB_TX_PAUSE_OFFSET			2
343 #define MACB_TX_PAUSE_SIZE			1
344 #define MACB_TX_PAUSE_ZERO_OFFSET		3
345 #define MACB_TX_PAUSE_ZERO_SIZE			1
346 
347 /* Bitfields in USRIO (AT91) */
348 #define MACB_RMII_OFFSET			0
349 #define MACB_RMII_SIZE				1
350 #define GEM_RGMII_OFFSET			0 /* GEM gigabit mode */
351 #define GEM_RGMII_SIZE				1
352 #define MACB_CLKEN_OFFSET			1
353 #define MACB_CLKEN_SIZE				1
354 
355 /* Bitfields in WOL */
356 #define MACB_IP_OFFSET				0
357 #define MACB_IP_SIZE				16
358 #define MACB_MAG_OFFSET				16
359 #define MACB_MAG_SIZE				1
360 #define MACB_ARP_OFFSET				17
361 #define MACB_ARP_SIZE				1
362 #define MACB_SA1_OFFSET				18
363 #define MACB_SA1_SIZE				1
364 #define MACB_WOL_MTI_OFFSET			19
365 #define MACB_WOL_MTI_SIZE			1
366 
367 /* Bitfields in MID */
368 #define MACB_IDNUM_OFFSET			16
369 #define MACB_IDNUM_SIZE				12
370 #define MACB_REV_OFFSET				0
371 #define MACB_REV_SIZE				16
372 
373 /* Bitfields in DCFG1. */
374 #define GEM_IRQCOR_OFFSET			23
375 #define GEM_IRQCOR_SIZE				1
376 #define GEM_DBWDEF_OFFSET			25
377 #define GEM_DBWDEF_SIZE				3
378 
379 /* Bitfields in DCFG2. */
380 #define GEM_RX_PKT_BUFF_OFFSET			20
381 #define GEM_RX_PKT_BUFF_SIZE			1
382 #define GEM_TX_PKT_BUFF_OFFSET			21
383 #define GEM_TX_PKT_BUFF_SIZE			1
384 
385 /* Constants for CLK */
386 #define MACB_CLK_DIV8				0
387 #define MACB_CLK_DIV16				1
388 #define MACB_CLK_DIV32				2
389 #define MACB_CLK_DIV64				3
390 
391 /* GEM specific constants for CLK. */
392 #define GEM_CLK_DIV8				0
393 #define GEM_CLK_DIV16				1
394 #define GEM_CLK_DIV32				2
395 #define GEM_CLK_DIV48				3
396 #define GEM_CLK_DIV64				4
397 #define GEM_CLK_DIV96				5
398 
399 /* Constants for MAN register */
400 #define MACB_MAN_SOF				1
401 #define MACB_MAN_WRITE				1
402 #define MACB_MAN_READ				2
403 #define MACB_MAN_CODE				2
404 
405 /* Capability mask bits */
406 #define MACB_CAPS_ISR_CLEAR_ON_WRITE		0x00000001
407 #define MACB_CAPS_USRIO_HAS_CLKEN		0x00000002
408 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII	0x00000004
409 #define MACB_CAPS_NO_GIGABIT_HALF		0x00000008
410 #define MACB_CAPS_USRIO_DISABLED		0x00000010
411 #define MACB_CAPS_JUMBO				0x00000020
412 #define MACB_CAPS_FIFO_MODE			0x10000000
413 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE	0x20000000
414 #define MACB_CAPS_SG_DISABLED			0x40000000
415 #define MACB_CAPS_MACB_IS_GEM			0x80000000
416 
417 /* Bit manipulation macros */
418 #define MACB_BIT(name)					\
419 	(1 << MACB_##name##_OFFSET)
420 #define MACB_BF(name,value)				\
421 	(((value) & ((1 << MACB_##name##_SIZE) - 1))	\
422 	 << MACB_##name##_OFFSET)
423 #define MACB_BFEXT(name,value)\
424 	(((value) >> MACB_##name##_OFFSET)		\
425 	 & ((1 << MACB_##name##_SIZE) - 1))
426 #define MACB_BFINS(name,value,old)			\
427 	(((old) & ~(((1 << MACB_##name##_SIZE) - 1)	\
428 		    << MACB_##name##_OFFSET))		\
429 	 | MACB_BF(name,value))
430 
431 #define GEM_BIT(name)					\
432 	(1 << GEM_##name##_OFFSET)
433 #define GEM_BF(name, value)				\
434 	(((value) & ((1 << GEM_##name##_SIZE) - 1))	\
435 	 << GEM_##name##_OFFSET)
436 #define GEM_BFEXT(name, value)\
437 	(((value) >> GEM_##name##_OFFSET)		\
438 	 & ((1 << GEM_##name##_SIZE) - 1))
439 #define GEM_BFINS(name, value, old)			\
440 	(((old) & ~(((1 << GEM_##name##_SIZE) - 1)	\
441 		    << GEM_##name##_OFFSET))		\
442 	 | GEM_BF(name, value))
443 
444 /* Register access macros */
445 #define macb_readl(port, reg)		(port)->macb_reg_readl((port), MACB_##reg)
446 #define macb_writel(port, reg, value)	(port)->macb_reg_writel((port), MACB_##reg, (value))
447 #define gem_readl(port, reg)		(port)->macb_reg_readl((port), GEM_##reg)
448 #define gem_writel(port, reg, value)	(port)->macb_reg_writel((port), GEM_##reg, (value))
449 #define queue_readl(queue, reg)		(queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
450 #define queue_writel(queue, reg, value)	(queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
451 
452 /* Conditional GEM/MACB macros.  These perform the operation to the correct
453  * register dependent on whether the device is a GEM or a MACB.  For registers
454  * and bitfields that are common across both devices, use macb_{read,write}l
455  * to avoid the cost of the conditional.
456  */
457 #define macb_or_gem_writel(__bp, __reg, __value) \
458 	({ \
459 		if (macb_is_gem((__bp))) \
460 			gem_writel((__bp), __reg, __value); \
461 		else \
462 			macb_writel((__bp), __reg, __value); \
463 	})
464 
465 #define macb_or_gem_readl(__bp, __reg) \
466 	({ \
467 		u32 __v; \
468 		if (macb_is_gem((__bp))) \
469 			__v = gem_readl((__bp), __reg); \
470 		else \
471 			__v = macb_readl((__bp), __reg); \
472 		__v; \
473 	})
474 
475 /* struct macb_dma_desc - Hardware DMA descriptor
476  * @addr: DMA address of data buffer
477  * @ctrl: Control and status bits
478  */
479 struct macb_dma_desc {
480 	u32	addr;
481 	u32	ctrl;
482 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
483 	u32     addrh;
484 	u32     resvd;
485 #endif
486 };
487 
488 /* DMA descriptor bitfields */
489 #define MACB_RX_USED_OFFSET			0
490 #define MACB_RX_USED_SIZE			1
491 #define MACB_RX_WRAP_OFFSET			1
492 #define MACB_RX_WRAP_SIZE			1
493 #define MACB_RX_WADDR_OFFSET			2
494 #define MACB_RX_WADDR_SIZE			30
495 
496 #define MACB_RX_FRMLEN_OFFSET			0
497 #define MACB_RX_FRMLEN_SIZE			12
498 #define MACB_RX_OFFSET_OFFSET			12
499 #define MACB_RX_OFFSET_SIZE			2
500 #define MACB_RX_SOF_OFFSET			14
501 #define MACB_RX_SOF_SIZE			1
502 #define MACB_RX_EOF_OFFSET			15
503 #define MACB_RX_EOF_SIZE			1
504 #define MACB_RX_CFI_OFFSET			16
505 #define MACB_RX_CFI_SIZE			1
506 #define MACB_RX_VLAN_PRI_OFFSET			17
507 #define MACB_RX_VLAN_PRI_SIZE			3
508 #define MACB_RX_PRI_TAG_OFFSET			20
509 #define MACB_RX_PRI_TAG_SIZE			1
510 #define MACB_RX_VLAN_TAG_OFFSET			21
511 #define MACB_RX_VLAN_TAG_SIZE			1
512 #define MACB_RX_TYPEID_MATCH_OFFSET		22
513 #define MACB_RX_TYPEID_MATCH_SIZE		1
514 #define MACB_RX_SA4_MATCH_OFFSET		23
515 #define MACB_RX_SA4_MATCH_SIZE			1
516 #define MACB_RX_SA3_MATCH_OFFSET		24
517 #define MACB_RX_SA3_MATCH_SIZE			1
518 #define MACB_RX_SA2_MATCH_OFFSET		25
519 #define MACB_RX_SA2_MATCH_SIZE			1
520 #define MACB_RX_SA1_MATCH_OFFSET		26
521 #define MACB_RX_SA1_MATCH_SIZE			1
522 #define MACB_RX_EXT_MATCH_OFFSET		28
523 #define MACB_RX_EXT_MATCH_SIZE			1
524 #define MACB_RX_UHASH_MATCH_OFFSET		29
525 #define MACB_RX_UHASH_MATCH_SIZE		1
526 #define MACB_RX_MHASH_MATCH_OFFSET		30
527 #define MACB_RX_MHASH_MATCH_SIZE		1
528 #define MACB_RX_BROADCAST_OFFSET		31
529 #define MACB_RX_BROADCAST_SIZE			1
530 
531 #define MACB_RX_FRMLEN_MASK			0xFFF
532 #define MACB_RX_JFRMLEN_MASK			0x3FFF
533 
534 /* RX checksum offload disabled: bit 24 clear in NCFGR */
535 #define GEM_RX_TYPEID_MATCH_OFFSET		22
536 #define GEM_RX_TYPEID_MATCH_SIZE		2
537 
538 /* RX checksum offload enabled: bit 24 set in NCFGR */
539 #define GEM_RX_CSUM_OFFSET			22
540 #define GEM_RX_CSUM_SIZE			2
541 
542 #define MACB_TX_FRMLEN_OFFSET			0
543 #define MACB_TX_FRMLEN_SIZE			11
544 #define MACB_TX_LAST_OFFSET			15
545 #define MACB_TX_LAST_SIZE			1
546 #define MACB_TX_NOCRC_OFFSET			16
547 #define MACB_TX_NOCRC_SIZE			1
548 #define MACB_TX_BUF_EXHAUSTED_OFFSET		27
549 #define MACB_TX_BUF_EXHAUSTED_SIZE		1
550 #define MACB_TX_UNDERRUN_OFFSET			28
551 #define MACB_TX_UNDERRUN_SIZE			1
552 #define MACB_TX_ERROR_OFFSET			29
553 #define MACB_TX_ERROR_SIZE			1
554 #define MACB_TX_WRAP_OFFSET			30
555 #define MACB_TX_WRAP_SIZE			1
556 #define MACB_TX_USED_OFFSET			31
557 #define MACB_TX_USED_SIZE			1
558 
559 #define GEM_TX_FRMLEN_OFFSET			0
560 #define GEM_TX_FRMLEN_SIZE			14
561 
562 /* Buffer descriptor constants */
563 #define GEM_RX_CSUM_NONE			0
564 #define GEM_RX_CSUM_IP_ONLY			1
565 #define GEM_RX_CSUM_IP_TCP			2
566 #define GEM_RX_CSUM_IP_UDP			3
567 
568 /* limit RX checksum offload to TCP and UDP packets */
569 #define GEM_RX_CSUM_CHECKED_MASK		2
570 
571 /* struct macb_tx_skb - data about an skb which is being transmitted
572  * @skb: skb currently being transmitted, only set for the last buffer
573  *       of the frame
574  * @mapping: DMA address of the skb's fragment buffer
575  * @size: size of the DMA mapped buffer
576  * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
577  *                  false when buffer was mapped with dma_map_single()
578  */
579 struct macb_tx_skb {
580 	struct sk_buff		*skb;
581 	dma_addr_t		mapping;
582 	size_t			size;
583 	bool			mapped_as_page;
584 };
585 
586 /* Hardware-collected statistics. Used when updating the network
587  * device stats by a periodic timer.
588  */
589 struct macb_stats {
590 	u32	rx_pause_frames;
591 	u32	tx_ok;
592 	u32	tx_single_cols;
593 	u32	tx_multiple_cols;
594 	u32	rx_ok;
595 	u32	rx_fcs_errors;
596 	u32	rx_align_errors;
597 	u32	tx_deferred;
598 	u32	tx_late_cols;
599 	u32	tx_excessive_cols;
600 	u32	tx_underruns;
601 	u32	tx_carrier_errors;
602 	u32	rx_resource_errors;
603 	u32	rx_overruns;
604 	u32	rx_symbol_errors;
605 	u32	rx_oversize_pkts;
606 	u32	rx_jabbers;
607 	u32	rx_undersize_pkts;
608 	u32	sqe_test_errors;
609 	u32	rx_length_mismatch;
610 	u32	tx_pause_frames;
611 };
612 
613 struct gem_stats {
614 	u32	tx_octets_31_0;
615 	u32	tx_octets_47_32;
616 	u32	tx_frames;
617 	u32	tx_broadcast_frames;
618 	u32	tx_multicast_frames;
619 	u32	tx_pause_frames;
620 	u32	tx_64_byte_frames;
621 	u32	tx_65_127_byte_frames;
622 	u32	tx_128_255_byte_frames;
623 	u32	tx_256_511_byte_frames;
624 	u32	tx_512_1023_byte_frames;
625 	u32	tx_1024_1518_byte_frames;
626 	u32	tx_greater_than_1518_byte_frames;
627 	u32	tx_underrun;
628 	u32	tx_single_collision_frames;
629 	u32	tx_multiple_collision_frames;
630 	u32	tx_excessive_collisions;
631 	u32	tx_late_collisions;
632 	u32	tx_deferred_frames;
633 	u32	tx_carrier_sense_errors;
634 	u32	rx_octets_31_0;
635 	u32	rx_octets_47_32;
636 	u32	rx_frames;
637 	u32	rx_broadcast_frames;
638 	u32	rx_multicast_frames;
639 	u32	rx_pause_frames;
640 	u32	rx_64_byte_frames;
641 	u32	rx_65_127_byte_frames;
642 	u32	rx_128_255_byte_frames;
643 	u32	rx_256_511_byte_frames;
644 	u32	rx_512_1023_byte_frames;
645 	u32	rx_1024_1518_byte_frames;
646 	u32	rx_greater_than_1518_byte_frames;
647 	u32	rx_undersized_frames;
648 	u32	rx_oversize_frames;
649 	u32	rx_jabbers;
650 	u32	rx_frame_check_sequence_errors;
651 	u32	rx_length_field_frame_errors;
652 	u32	rx_symbol_errors;
653 	u32	rx_alignment_errors;
654 	u32	rx_resource_errors;
655 	u32	rx_overruns;
656 	u32	rx_ip_header_checksum_errors;
657 	u32	rx_tcp_checksum_errors;
658 	u32	rx_udp_checksum_errors;
659 };
660 
661 /* Describes the name and offset of an individual statistic register, as
662  * returned by `ethtool -S`. Also describes which net_device_stats statistics
663  * this register should contribute to.
664  */
665 struct gem_statistic {
666 	char stat_string[ETH_GSTRING_LEN];
667 	int offset;
668 	u32 stat_bits;
669 };
670 
671 /* Bitfield defs for net_device_stat statistics */
672 #define GEM_NDS_RXERR_OFFSET		0
673 #define GEM_NDS_RXLENERR_OFFSET		1
674 #define GEM_NDS_RXOVERERR_OFFSET	2
675 #define GEM_NDS_RXCRCERR_OFFSET		3
676 #define GEM_NDS_RXFRAMEERR_OFFSET	4
677 #define GEM_NDS_RXFIFOERR_OFFSET	5
678 #define GEM_NDS_TXERR_OFFSET		6
679 #define GEM_NDS_TXABORTEDERR_OFFSET	7
680 #define GEM_NDS_TXCARRIERERR_OFFSET	8
681 #define GEM_NDS_TXFIFOERR_OFFSET	9
682 #define GEM_NDS_COLLISIONS_OFFSET	10
683 
684 #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
685 #define GEM_STAT_TITLE_BITS(name, title, bits) {	\
686 	.stat_string = title,				\
687 	.offset = GEM_##name,				\
688 	.stat_bits = bits				\
689 }
690 
691 /* list of gem statistic registers. The names MUST match the
692  * corresponding GEM_* definitions.
693  */
694 static const struct gem_statistic gem_statistics[] = {
695 	GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
696 	GEM_STAT_TITLE(TXCNT, "tx_frames"),
697 	GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
698 	GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
699 	GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
700 	GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
701 	GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
702 	GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
703 	GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
704 	GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
705 	GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
706 	GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
707 	GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
708 			    GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
709 	GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
710 			    GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
711 	GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
712 			    GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
713 	GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
714 			    GEM_BIT(NDS_TXERR)|
715 			    GEM_BIT(NDS_TXABORTEDERR)|
716 			    GEM_BIT(NDS_COLLISIONS)),
717 	GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
718 			    GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
719 	GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
720 	GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
721 			    GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
722 	GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
723 	GEM_STAT_TITLE(RXCNT, "rx_frames"),
724 	GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
725 	GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
726 	GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
727 	GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
728 	GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
729 	GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
730 	GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
731 	GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
732 	GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
733 	GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
734 	GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
735 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
736 	GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
737 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
738 	GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
739 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
740 	GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
741 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
742 	GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
743 			    GEM_BIT(NDS_RXERR)),
744 	GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
745 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
746 	GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
747 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
748 	GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
749 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
750 	GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
751 			    GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
752 	GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
753 			    GEM_BIT(NDS_RXERR)),
754 	GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
755 			    GEM_BIT(NDS_RXERR)),
756 	GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
757 			    GEM_BIT(NDS_RXERR)),
758 };
759 
760 #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
761 
762 struct macb;
763 
764 struct macb_or_gem_ops {
765 	int	(*mog_alloc_rx_buffers)(struct macb *bp);
766 	void	(*mog_free_rx_buffers)(struct macb *bp);
767 	void	(*mog_init_rings)(struct macb *bp);
768 	int	(*mog_rx)(struct macb *bp, int budget);
769 };
770 
771 struct macb_config {
772 	u32			caps;
773 	unsigned int		dma_burst_length;
774 	int	(*clk_init)(struct platform_device *pdev, struct clk **pclk,
775 			    struct clk **hclk, struct clk **tx_clk,
776 			    struct clk **rx_clk);
777 	int	(*init)(struct platform_device *pdev);
778 	int	jumbo_max_len;
779 };
780 
781 struct macb_queue {
782 	struct macb		*bp;
783 	int			irq;
784 
785 	unsigned int		ISR;
786 	unsigned int		IER;
787 	unsigned int		IDR;
788 	unsigned int		IMR;
789 	unsigned int		TBQP;
790 	unsigned int		TBQPH;
791 
792 	unsigned int		tx_head, tx_tail;
793 	struct macb_dma_desc	*tx_ring;
794 	struct macb_tx_skb	*tx_skb;
795 	dma_addr_t		tx_ring_dma;
796 	struct work_struct	tx_error_task;
797 };
798 
799 struct macb {
800 	void __iomem		*regs;
801 	bool			native_io;
802 
803 	/* hardware IO accessors */
804 	u32	(*macb_reg_readl)(struct macb *bp, int offset);
805 	void	(*macb_reg_writel)(struct macb *bp, int offset, u32 value);
806 
807 	unsigned int		rx_tail;
808 	unsigned int		rx_prepared_head;
809 	struct macb_dma_desc	*rx_ring;
810 	struct sk_buff		**rx_skbuff;
811 	void			*rx_buffers;
812 	size_t			rx_buffer_size;
813 
814 	unsigned int		num_queues;
815 	unsigned int		queue_mask;
816 	struct macb_queue	queues[MACB_MAX_QUEUES];
817 
818 	spinlock_t		lock;
819 	struct platform_device	*pdev;
820 	struct clk		*pclk;
821 	struct clk		*hclk;
822 	struct clk		*tx_clk;
823 	struct clk		*rx_clk;
824 	struct net_device	*dev;
825 	struct napi_struct	napi;
826 	struct net_device_stats	stats;
827 	union {
828 		struct macb_stats	macb;
829 		struct gem_stats	gem;
830 	}			hw_stats;
831 
832 	dma_addr_t		rx_ring_dma;
833 	dma_addr_t		rx_buffers_dma;
834 
835 	struct macb_or_gem_ops	macbgem_ops;
836 
837 	struct mii_bus		*mii_bus;
838 	int 			link;
839 	int 			speed;
840 	int 			duplex;
841 
842 	u32			caps;
843 	unsigned int		dma_burst_length;
844 
845 	phy_interface_t		phy_interface;
846 	struct gpio_desc	*reset_gpio;
847 
848 	/* AT91RM9200 transmit */
849 	struct sk_buff *skb;			/* holds skb until xmit interrupt completes */
850 	dma_addr_t skb_physaddr;		/* phys addr from pci_map_single */
851 	int skb_length;				/* saved skb length for pci_unmap_single */
852 	unsigned int		max_tx_length;
853 
854 	u64			ethtool_stats[GEM_STATS_LEN];
855 
856 	unsigned int		rx_frm_len_mask;
857 	unsigned int		jumbo_max_len;
858 
859 	u32			wol;
860 };
861 
862 static inline bool macb_is_gem(struct macb *bp)
863 {
864 	return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
865 }
866 
867 #endif /* _MACB_H */
868