1 /* 2 * Atmel MACB Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _MACB_H 11 #define _MACB_H 12 13 /* MACB register offsets */ 14 #define MACB_NCR 0x0000 15 #define MACB_NCFGR 0x0004 16 #define MACB_NSR 0x0008 17 #define MACB_TSR 0x0014 18 #define MACB_RBQP 0x0018 19 #define MACB_TBQP 0x001c 20 #define MACB_RSR 0x0020 21 #define MACB_ISR 0x0024 22 #define MACB_IER 0x0028 23 #define MACB_IDR 0x002c 24 #define MACB_IMR 0x0030 25 #define MACB_MAN 0x0034 26 #define MACB_PTR 0x0038 27 #define MACB_PFR 0x003c 28 #define MACB_FTO 0x0040 29 #define MACB_SCF 0x0044 30 #define MACB_MCF 0x0048 31 #define MACB_FRO 0x004c 32 #define MACB_FCSE 0x0050 33 #define MACB_ALE 0x0054 34 #define MACB_DTF 0x0058 35 #define MACB_LCOL 0x005c 36 #define MACB_EXCOL 0x0060 37 #define MACB_TUND 0x0064 38 #define MACB_CSE 0x0068 39 #define MACB_RRE 0x006c 40 #define MACB_ROVR 0x0070 41 #define MACB_RSE 0x0074 42 #define MACB_ELE 0x0078 43 #define MACB_RJA 0x007c 44 #define MACB_USF 0x0080 45 #define MACB_STE 0x0084 46 #define MACB_RLE 0x0088 47 #define MACB_TPF 0x008c 48 #define MACB_HRB 0x0090 49 #define MACB_HRT 0x0094 50 #define MACB_SA1B 0x0098 51 #define MACB_SA1T 0x009c 52 #define MACB_SA2B 0x00a0 53 #define MACB_SA2T 0x00a4 54 #define MACB_SA3B 0x00a8 55 #define MACB_SA3T 0x00ac 56 #define MACB_SA4B 0x00b0 57 #define MACB_SA4T 0x00b4 58 #define MACB_TID 0x00b8 59 #define MACB_TPQ 0x00bc 60 #define MACB_USRIO 0x00c0 61 #define MACB_WOL 0x00c4 62 #define MACB_MID 0x00fc 63 64 /* GEM register offsets. */ 65 #define GEM_NCFGR 0x0004 66 #define GEM_USRIO 0x000c 67 #define GEM_DMACFG 0x0010 68 #define GEM_HRB 0x0080 69 #define GEM_HRT 0x0084 70 #define GEM_SA1B 0x0088 71 #define GEM_SA1T 0x008C 72 #define GEM_OTX 0x0100 73 #define GEM_DCFG1 0x0280 74 #define GEM_DCFG2 0x0284 75 #define GEM_DCFG3 0x0288 76 #define GEM_DCFG4 0x028c 77 #define GEM_DCFG5 0x0290 78 #define GEM_DCFG6 0x0294 79 #define GEM_DCFG7 0x0298 80 81 /* Bitfields in NCR */ 82 #define MACB_LB_OFFSET 0 83 #define MACB_LB_SIZE 1 84 #define MACB_LLB_OFFSET 1 85 #define MACB_LLB_SIZE 1 86 #define MACB_RE_OFFSET 2 87 #define MACB_RE_SIZE 1 88 #define MACB_TE_OFFSET 3 89 #define MACB_TE_SIZE 1 90 #define MACB_MPE_OFFSET 4 91 #define MACB_MPE_SIZE 1 92 #define MACB_CLRSTAT_OFFSET 5 93 #define MACB_CLRSTAT_SIZE 1 94 #define MACB_INCSTAT_OFFSET 6 95 #define MACB_INCSTAT_SIZE 1 96 #define MACB_WESTAT_OFFSET 7 97 #define MACB_WESTAT_SIZE 1 98 #define MACB_BP_OFFSET 8 99 #define MACB_BP_SIZE 1 100 #define MACB_TSTART_OFFSET 9 101 #define MACB_TSTART_SIZE 1 102 #define MACB_THALT_OFFSET 10 103 #define MACB_THALT_SIZE 1 104 #define MACB_NCR_TPF_OFFSET 11 105 #define MACB_NCR_TPF_SIZE 1 106 #define MACB_TZQ_OFFSET 12 107 #define MACB_TZQ_SIZE 1 108 109 /* Bitfields in NCFGR */ 110 #define MACB_SPD_OFFSET 0 111 #define MACB_SPD_SIZE 1 112 #define MACB_FD_OFFSET 1 113 #define MACB_FD_SIZE 1 114 #define MACB_BIT_RATE_OFFSET 2 115 #define MACB_BIT_RATE_SIZE 1 116 #define MACB_JFRAME_OFFSET 3 117 #define MACB_JFRAME_SIZE 1 118 #define MACB_CAF_OFFSET 4 119 #define MACB_CAF_SIZE 1 120 #define MACB_NBC_OFFSET 5 121 #define MACB_NBC_SIZE 1 122 #define MACB_NCFGR_MTI_OFFSET 6 123 #define MACB_NCFGR_MTI_SIZE 1 124 #define MACB_UNI_OFFSET 7 125 #define MACB_UNI_SIZE 1 126 #define MACB_BIG_OFFSET 8 127 #define MACB_BIG_SIZE 1 128 #define MACB_EAE_OFFSET 9 129 #define MACB_EAE_SIZE 1 130 #define MACB_CLK_OFFSET 10 131 #define MACB_CLK_SIZE 2 132 #define MACB_RTY_OFFSET 12 133 #define MACB_RTY_SIZE 1 134 #define MACB_PAE_OFFSET 13 135 #define MACB_PAE_SIZE 1 136 #define MACB_RBOF_OFFSET 14 137 #define MACB_RBOF_SIZE 2 138 #define MACB_RLCE_OFFSET 16 139 #define MACB_RLCE_SIZE 1 140 #define MACB_DRFCS_OFFSET 17 141 #define MACB_DRFCS_SIZE 1 142 #define MACB_EFRHD_OFFSET 18 143 #define MACB_EFRHD_SIZE 1 144 #define MACB_IRXFCS_OFFSET 19 145 #define MACB_IRXFCS_SIZE 1 146 147 /* GEM specific NCFGR bitfields. */ 148 #define GEM_CLK_OFFSET 18 149 #define GEM_CLK_SIZE 3 150 #define GEM_DBW_OFFSET 21 151 #define GEM_DBW_SIZE 2 152 153 /* Constants for data bus width. */ 154 #define GEM_DBW32 0 155 #define GEM_DBW64 1 156 #define GEM_DBW128 2 157 158 /* Bitfields in DMACFG. */ 159 #define GEM_RXBS_OFFSET 16 160 #define GEM_RXBS_SIZE 8 161 162 /* Bitfields in NSR */ 163 #define MACB_NSR_LINK_OFFSET 0 164 #define MACB_NSR_LINK_SIZE 1 165 #define MACB_MDIO_OFFSET 1 166 #define MACB_MDIO_SIZE 1 167 #define MACB_IDLE_OFFSET 2 168 #define MACB_IDLE_SIZE 1 169 170 /* Bitfields in TSR */ 171 #define MACB_UBR_OFFSET 0 172 #define MACB_UBR_SIZE 1 173 #define MACB_COL_OFFSET 1 174 #define MACB_COL_SIZE 1 175 #define MACB_TSR_RLE_OFFSET 2 176 #define MACB_TSR_RLE_SIZE 1 177 #define MACB_TGO_OFFSET 3 178 #define MACB_TGO_SIZE 1 179 #define MACB_BEX_OFFSET 4 180 #define MACB_BEX_SIZE 1 181 #define MACB_COMP_OFFSET 5 182 #define MACB_COMP_SIZE 1 183 #define MACB_UND_OFFSET 6 184 #define MACB_UND_SIZE 1 185 186 /* Bitfields in RSR */ 187 #define MACB_BNA_OFFSET 0 188 #define MACB_BNA_SIZE 1 189 #define MACB_REC_OFFSET 1 190 #define MACB_REC_SIZE 1 191 #define MACB_OVR_OFFSET 2 192 #define MACB_OVR_SIZE 1 193 194 /* Bitfields in ISR/IER/IDR/IMR */ 195 #define MACB_MFD_OFFSET 0 196 #define MACB_MFD_SIZE 1 197 #define MACB_RCOMP_OFFSET 1 198 #define MACB_RCOMP_SIZE 1 199 #define MACB_RXUBR_OFFSET 2 200 #define MACB_RXUBR_SIZE 1 201 #define MACB_TXUBR_OFFSET 3 202 #define MACB_TXUBR_SIZE 1 203 #define MACB_ISR_TUND_OFFSET 4 204 #define MACB_ISR_TUND_SIZE 1 205 #define MACB_ISR_RLE_OFFSET 5 206 #define MACB_ISR_RLE_SIZE 1 207 #define MACB_TXERR_OFFSET 6 208 #define MACB_TXERR_SIZE 1 209 #define MACB_TCOMP_OFFSET 7 210 #define MACB_TCOMP_SIZE 1 211 #define MACB_ISR_LINK_OFFSET 9 212 #define MACB_ISR_LINK_SIZE 1 213 #define MACB_ISR_ROVR_OFFSET 10 214 #define MACB_ISR_ROVR_SIZE 1 215 #define MACB_HRESP_OFFSET 11 216 #define MACB_HRESP_SIZE 1 217 #define MACB_PFR_OFFSET 12 218 #define MACB_PFR_SIZE 1 219 #define MACB_PTZ_OFFSET 13 220 #define MACB_PTZ_SIZE 1 221 222 /* Bitfields in MAN */ 223 #define MACB_DATA_OFFSET 0 224 #define MACB_DATA_SIZE 16 225 #define MACB_CODE_OFFSET 16 226 #define MACB_CODE_SIZE 2 227 #define MACB_REGA_OFFSET 18 228 #define MACB_REGA_SIZE 5 229 #define MACB_PHYA_OFFSET 23 230 #define MACB_PHYA_SIZE 5 231 #define MACB_RW_OFFSET 28 232 #define MACB_RW_SIZE 2 233 #define MACB_SOF_OFFSET 30 234 #define MACB_SOF_SIZE 2 235 236 /* Bitfields in USRIO (AVR32) */ 237 #define MACB_MII_OFFSET 0 238 #define MACB_MII_SIZE 1 239 #define MACB_EAM_OFFSET 1 240 #define MACB_EAM_SIZE 1 241 #define MACB_TX_PAUSE_OFFSET 2 242 #define MACB_TX_PAUSE_SIZE 1 243 #define MACB_TX_PAUSE_ZERO_OFFSET 3 244 #define MACB_TX_PAUSE_ZERO_SIZE 1 245 246 /* Bitfields in USRIO (AT91) */ 247 #define MACB_RMII_OFFSET 0 248 #define MACB_RMII_SIZE 1 249 #define MACB_CLKEN_OFFSET 1 250 #define MACB_CLKEN_SIZE 1 251 252 /* Bitfields in WOL */ 253 #define MACB_IP_OFFSET 0 254 #define MACB_IP_SIZE 16 255 #define MACB_MAG_OFFSET 16 256 #define MACB_MAG_SIZE 1 257 #define MACB_ARP_OFFSET 17 258 #define MACB_ARP_SIZE 1 259 #define MACB_SA1_OFFSET 18 260 #define MACB_SA1_SIZE 1 261 #define MACB_WOL_MTI_OFFSET 19 262 #define MACB_WOL_MTI_SIZE 1 263 264 /* Bitfields in MID */ 265 #define MACB_IDNUM_OFFSET 16 266 #define MACB_IDNUM_SIZE 16 267 #define MACB_REV_OFFSET 0 268 #define MACB_REV_SIZE 16 269 270 /* Bitfields in DCFG1. */ 271 #define GEM_DBWDEF_OFFSET 25 272 #define GEM_DBWDEF_SIZE 3 273 274 /* Constants for CLK */ 275 #define MACB_CLK_DIV8 0 276 #define MACB_CLK_DIV16 1 277 #define MACB_CLK_DIV32 2 278 #define MACB_CLK_DIV64 3 279 280 /* GEM specific constants for CLK. */ 281 #define GEM_CLK_DIV8 0 282 #define GEM_CLK_DIV16 1 283 #define GEM_CLK_DIV32 2 284 #define GEM_CLK_DIV48 3 285 #define GEM_CLK_DIV64 4 286 #define GEM_CLK_DIV96 5 287 288 /* Constants for MAN register */ 289 #define MACB_MAN_SOF 1 290 #define MACB_MAN_WRITE 1 291 #define MACB_MAN_READ 2 292 #define MACB_MAN_CODE 2 293 294 /* Bit manipulation macros */ 295 #define MACB_BIT(name) \ 296 (1 << MACB_##name##_OFFSET) 297 #define MACB_BF(name,value) \ 298 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 299 << MACB_##name##_OFFSET) 300 #define MACB_BFEXT(name,value)\ 301 (((value) >> MACB_##name##_OFFSET) \ 302 & ((1 << MACB_##name##_SIZE) - 1)) 303 #define MACB_BFINS(name,value,old) \ 304 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 305 << MACB_##name##_OFFSET)) \ 306 | MACB_BF(name,value)) 307 308 #define GEM_BIT(name) \ 309 (1 << GEM_##name##_OFFSET) 310 #define GEM_BF(name, value) \ 311 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 312 << GEM_##name##_OFFSET) 313 #define GEM_BFEXT(name, value)\ 314 (((value) >> GEM_##name##_OFFSET) \ 315 & ((1 << GEM_##name##_SIZE) - 1)) 316 #define GEM_BFINS(name, value, old) \ 317 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 318 << GEM_##name##_OFFSET)) \ 319 | GEM_BF(name, value)) 320 321 /* Register access macros */ 322 #define macb_readl(port,reg) \ 323 __raw_readl((port)->regs + MACB_##reg) 324 #define macb_writel(port,reg,value) \ 325 __raw_writel((value), (port)->regs + MACB_##reg) 326 #define gem_readl(port, reg) \ 327 __raw_readl((port)->regs + GEM_##reg) 328 #define gem_writel(port, reg, value) \ 329 __raw_writel((value), (port)->regs + GEM_##reg) 330 331 /* 332 * Conditional GEM/MACB macros. These perform the operation to the correct 333 * register dependent on whether the device is a GEM or a MACB. For registers 334 * and bitfields that are common across both devices, use macb_{read,write}l 335 * to avoid the cost of the conditional. 336 */ 337 #define macb_or_gem_writel(__bp, __reg, __value) \ 338 ({ \ 339 if (macb_is_gem((__bp))) \ 340 gem_writel((__bp), __reg, __value); \ 341 else \ 342 macb_writel((__bp), __reg, __value); \ 343 }) 344 345 #define macb_or_gem_readl(__bp, __reg) \ 346 ({ \ 347 u32 __v; \ 348 if (macb_is_gem((__bp))) \ 349 __v = gem_readl((__bp), __reg); \ 350 else \ 351 __v = macb_readl((__bp), __reg); \ 352 __v; \ 353 }) 354 355 struct dma_desc { 356 u32 addr; 357 u32 ctrl; 358 }; 359 360 /* DMA descriptor bitfields */ 361 #define MACB_RX_USED_OFFSET 0 362 #define MACB_RX_USED_SIZE 1 363 #define MACB_RX_WRAP_OFFSET 1 364 #define MACB_RX_WRAP_SIZE 1 365 #define MACB_RX_WADDR_OFFSET 2 366 #define MACB_RX_WADDR_SIZE 30 367 368 #define MACB_RX_FRMLEN_OFFSET 0 369 #define MACB_RX_FRMLEN_SIZE 12 370 #define MACB_RX_OFFSET_OFFSET 12 371 #define MACB_RX_OFFSET_SIZE 2 372 #define MACB_RX_SOF_OFFSET 14 373 #define MACB_RX_SOF_SIZE 1 374 #define MACB_RX_EOF_OFFSET 15 375 #define MACB_RX_EOF_SIZE 1 376 #define MACB_RX_CFI_OFFSET 16 377 #define MACB_RX_CFI_SIZE 1 378 #define MACB_RX_VLAN_PRI_OFFSET 17 379 #define MACB_RX_VLAN_PRI_SIZE 3 380 #define MACB_RX_PRI_TAG_OFFSET 20 381 #define MACB_RX_PRI_TAG_SIZE 1 382 #define MACB_RX_VLAN_TAG_OFFSET 21 383 #define MACB_RX_VLAN_TAG_SIZE 1 384 #define MACB_RX_TYPEID_MATCH_OFFSET 22 385 #define MACB_RX_TYPEID_MATCH_SIZE 1 386 #define MACB_RX_SA4_MATCH_OFFSET 23 387 #define MACB_RX_SA4_MATCH_SIZE 1 388 #define MACB_RX_SA3_MATCH_OFFSET 24 389 #define MACB_RX_SA3_MATCH_SIZE 1 390 #define MACB_RX_SA2_MATCH_OFFSET 25 391 #define MACB_RX_SA2_MATCH_SIZE 1 392 #define MACB_RX_SA1_MATCH_OFFSET 26 393 #define MACB_RX_SA1_MATCH_SIZE 1 394 #define MACB_RX_EXT_MATCH_OFFSET 28 395 #define MACB_RX_EXT_MATCH_SIZE 1 396 #define MACB_RX_UHASH_MATCH_OFFSET 29 397 #define MACB_RX_UHASH_MATCH_SIZE 1 398 #define MACB_RX_MHASH_MATCH_OFFSET 30 399 #define MACB_RX_MHASH_MATCH_SIZE 1 400 #define MACB_RX_BROADCAST_OFFSET 31 401 #define MACB_RX_BROADCAST_SIZE 1 402 403 #define MACB_TX_FRMLEN_OFFSET 0 404 #define MACB_TX_FRMLEN_SIZE 11 405 #define MACB_TX_LAST_OFFSET 15 406 #define MACB_TX_LAST_SIZE 1 407 #define MACB_TX_NOCRC_OFFSET 16 408 #define MACB_TX_NOCRC_SIZE 1 409 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 410 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 411 #define MACB_TX_UNDERRUN_OFFSET 28 412 #define MACB_TX_UNDERRUN_SIZE 1 413 #define MACB_TX_ERROR_OFFSET 29 414 #define MACB_TX_ERROR_SIZE 1 415 #define MACB_TX_WRAP_OFFSET 30 416 #define MACB_TX_WRAP_SIZE 1 417 #define MACB_TX_USED_OFFSET 31 418 #define MACB_TX_USED_SIZE 1 419 420 struct ring_info { 421 struct sk_buff *skb; 422 dma_addr_t mapping; 423 }; 424 425 /* 426 * Hardware-collected statistics. Used when updating the network 427 * device stats by a periodic timer. 428 */ 429 struct macb_stats { 430 u32 rx_pause_frames; 431 u32 tx_ok; 432 u32 tx_single_cols; 433 u32 tx_multiple_cols; 434 u32 rx_ok; 435 u32 rx_fcs_errors; 436 u32 rx_align_errors; 437 u32 tx_deferred; 438 u32 tx_late_cols; 439 u32 tx_excessive_cols; 440 u32 tx_underruns; 441 u32 tx_carrier_errors; 442 u32 rx_resource_errors; 443 u32 rx_overruns; 444 u32 rx_symbol_errors; 445 u32 rx_oversize_pkts; 446 u32 rx_jabbers; 447 u32 rx_undersize_pkts; 448 u32 sqe_test_errors; 449 u32 rx_length_mismatch; 450 u32 tx_pause_frames; 451 }; 452 453 struct gem_stats { 454 u32 tx_octets_31_0; 455 u32 tx_octets_47_32; 456 u32 tx_frames; 457 u32 tx_broadcast_frames; 458 u32 tx_multicast_frames; 459 u32 tx_pause_frames; 460 u32 tx_64_byte_frames; 461 u32 tx_65_127_byte_frames; 462 u32 tx_128_255_byte_frames; 463 u32 tx_256_511_byte_frames; 464 u32 tx_512_1023_byte_frames; 465 u32 tx_1024_1518_byte_frames; 466 u32 tx_greater_than_1518_byte_frames; 467 u32 tx_underrun; 468 u32 tx_single_collision_frames; 469 u32 tx_multiple_collision_frames; 470 u32 tx_excessive_collisions; 471 u32 tx_late_collisions; 472 u32 tx_deferred_frames; 473 u32 tx_carrier_sense_errors; 474 u32 rx_octets_31_0; 475 u32 rx_octets_47_32; 476 u32 rx_frames; 477 u32 rx_broadcast_frames; 478 u32 rx_multicast_frames; 479 u32 rx_pause_frames; 480 u32 rx_64_byte_frames; 481 u32 rx_65_127_byte_frames; 482 u32 rx_128_255_byte_frames; 483 u32 rx_256_511_byte_frames; 484 u32 rx_512_1023_byte_frames; 485 u32 rx_1024_1518_byte_frames; 486 u32 rx_greater_than_1518_byte_frames; 487 u32 rx_undersized_frames; 488 u32 rx_oversize_frames; 489 u32 rx_jabbers; 490 u32 rx_frame_check_sequence_errors; 491 u32 rx_length_field_frame_errors; 492 u32 rx_symbol_errors; 493 u32 rx_alignment_errors; 494 u32 rx_resource_errors; 495 u32 rx_overruns; 496 u32 rx_ip_header_checksum_errors; 497 u32 rx_tcp_checksum_errors; 498 u32 rx_udp_checksum_errors; 499 }; 500 501 struct macb { 502 void __iomem *regs; 503 504 unsigned int rx_tail; 505 struct dma_desc *rx_ring; 506 void *rx_buffers; 507 508 unsigned int tx_head, tx_tail; 509 struct dma_desc *tx_ring; 510 struct ring_info *tx_skb; 511 512 spinlock_t lock; 513 struct platform_device *pdev; 514 struct clk *pclk; 515 struct clk *hclk; 516 struct net_device *dev; 517 struct napi_struct napi; 518 struct net_device_stats stats; 519 union { 520 struct macb_stats macb; 521 struct gem_stats gem; 522 } hw_stats; 523 524 dma_addr_t rx_ring_dma; 525 dma_addr_t tx_ring_dma; 526 dma_addr_t rx_buffers_dma; 527 528 unsigned int rx_pending, tx_pending; 529 530 struct mii_bus *mii_bus; 531 struct phy_device *phy_dev; 532 unsigned int link; 533 unsigned int speed; 534 unsigned int duplex; 535 536 phy_interface_t phy_interface; 537 }; 538 539 static inline bool macb_is_gem(struct macb *bp) 540 { 541 return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2; 542 } 543 544 #endif /* _MACB_H */ 545