1 /* 2 * Atmel MACB Ethernet Controller driver 3 * 4 * Copyright (C) 2004-2006 Atmel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _MACB_H 11 #define _MACB_H 12 13 #define MACB_GREGS_NBR 16 14 #define MACB_GREGS_VERSION 1 15 16 /* MACB register offsets */ 17 #define MACB_NCR 0x0000 18 #define MACB_NCFGR 0x0004 19 #define MACB_NSR 0x0008 20 #define MACB_TAR 0x000c /* AT91RM9200 only */ 21 #define MACB_TCR 0x0010 /* AT91RM9200 only */ 22 #define MACB_TSR 0x0014 23 #define MACB_RBQP 0x0018 24 #define MACB_TBQP 0x001c 25 #define MACB_RSR 0x0020 26 #define MACB_ISR 0x0024 27 #define MACB_IER 0x0028 28 #define MACB_IDR 0x002c 29 #define MACB_IMR 0x0030 30 #define MACB_MAN 0x0034 31 #define MACB_PTR 0x0038 32 #define MACB_PFR 0x003c 33 #define MACB_FTO 0x0040 34 #define MACB_SCF 0x0044 35 #define MACB_MCF 0x0048 36 #define MACB_FRO 0x004c 37 #define MACB_FCSE 0x0050 38 #define MACB_ALE 0x0054 39 #define MACB_DTF 0x0058 40 #define MACB_LCOL 0x005c 41 #define MACB_EXCOL 0x0060 42 #define MACB_TUND 0x0064 43 #define MACB_CSE 0x0068 44 #define MACB_RRE 0x006c 45 #define MACB_ROVR 0x0070 46 #define MACB_RSE 0x0074 47 #define MACB_ELE 0x0078 48 #define MACB_RJA 0x007c 49 #define MACB_USF 0x0080 50 #define MACB_STE 0x0084 51 #define MACB_RLE 0x0088 52 #define MACB_TPF 0x008c 53 #define MACB_HRB 0x0090 54 #define MACB_HRT 0x0094 55 #define MACB_SA1B 0x0098 56 #define MACB_SA1T 0x009c 57 #define MACB_SA2B 0x00a0 58 #define MACB_SA2T 0x00a4 59 #define MACB_SA3B 0x00a8 60 #define MACB_SA3T 0x00ac 61 #define MACB_SA4B 0x00b0 62 #define MACB_SA4T 0x00b4 63 #define MACB_TID 0x00b8 64 #define MACB_TPQ 0x00bc 65 #define MACB_USRIO 0x00c0 66 #define MACB_WOL 0x00c4 67 #define MACB_MID 0x00fc 68 69 /* GEM register offsets. */ 70 #define GEM_NCFGR 0x0004 71 #define GEM_USRIO 0x000c 72 #define GEM_DMACFG 0x0010 73 #define GEM_HRB 0x0080 74 #define GEM_HRT 0x0084 75 #define GEM_SA1B 0x0088 76 #define GEM_SA1T 0x008C 77 #define GEM_SA2B 0x0090 78 #define GEM_SA2T 0x0094 79 #define GEM_SA3B 0x0098 80 #define GEM_SA3T 0x009C 81 #define GEM_SA4B 0x00A0 82 #define GEM_SA4T 0x00A4 83 #define GEM_OTX 0x0100 84 #define GEM_DCFG1 0x0280 85 #define GEM_DCFG2 0x0284 86 #define GEM_DCFG3 0x0288 87 #define GEM_DCFG4 0x028c 88 #define GEM_DCFG5 0x0290 89 #define GEM_DCFG6 0x0294 90 #define GEM_DCFG7 0x0298 91 92 /* Bitfields in NCR */ 93 #define MACB_LB_OFFSET 0 94 #define MACB_LB_SIZE 1 95 #define MACB_LLB_OFFSET 1 96 #define MACB_LLB_SIZE 1 97 #define MACB_RE_OFFSET 2 98 #define MACB_RE_SIZE 1 99 #define MACB_TE_OFFSET 3 100 #define MACB_TE_SIZE 1 101 #define MACB_MPE_OFFSET 4 102 #define MACB_MPE_SIZE 1 103 #define MACB_CLRSTAT_OFFSET 5 104 #define MACB_CLRSTAT_SIZE 1 105 #define MACB_INCSTAT_OFFSET 6 106 #define MACB_INCSTAT_SIZE 1 107 #define MACB_WESTAT_OFFSET 7 108 #define MACB_WESTAT_SIZE 1 109 #define MACB_BP_OFFSET 8 110 #define MACB_BP_SIZE 1 111 #define MACB_TSTART_OFFSET 9 112 #define MACB_TSTART_SIZE 1 113 #define MACB_THALT_OFFSET 10 114 #define MACB_THALT_SIZE 1 115 #define MACB_NCR_TPF_OFFSET 11 116 #define MACB_NCR_TPF_SIZE 1 117 #define MACB_TZQ_OFFSET 12 118 #define MACB_TZQ_SIZE 1 119 120 /* Bitfields in NCFGR */ 121 #define MACB_SPD_OFFSET 0 122 #define MACB_SPD_SIZE 1 123 #define MACB_FD_OFFSET 1 124 #define MACB_FD_SIZE 1 125 #define MACB_BIT_RATE_OFFSET 2 126 #define MACB_BIT_RATE_SIZE 1 127 #define MACB_JFRAME_OFFSET 3 128 #define MACB_JFRAME_SIZE 1 129 #define MACB_CAF_OFFSET 4 130 #define MACB_CAF_SIZE 1 131 #define MACB_NBC_OFFSET 5 132 #define MACB_NBC_SIZE 1 133 #define MACB_NCFGR_MTI_OFFSET 6 134 #define MACB_NCFGR_MTI_SIZE 1 135 #define MACB_UNI_OFFSET 7 136 #define MACB_UNI_SIZE 1 137 #define MACB_BIG_OFFSET 8 138 #define MACB_BIG_SIZE 1 139 #define MACB_EAE_OFFSET 9 140 #define MACB_EAE_SIZE 1 141 #define MACB_CLK_OFFSET 10 142 #define MACB_CLK_SIZE 2 143 #define MACB_RTY_OFFSET 12 144 #define MACB_RTY_SIZE 1 145 #define MACB_PAE_OFFSET 13 146 #define MACB_PAE_SIZE 1 147 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 148 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 149 #define MACB_RBOF_OFFSET 14 150 #define MACB_RBOF_SIZE 2 151 #define MACB_RLCE_OFFSET 16 152 #define MACB_RLCE_SIZE 1 153 #define MACB_DRFCS_OFFSET 17 154 #define MACB_DRFCS_SIZE 1 155 #define MACB_EFRHD_OFFSET 18 156 #define MACB_EFRHD_SIZE 1 157 #define MACB_IRXFCS_OFFSET 19 158 #define MACB_IRXFCS_SIZE 1 159 160 /* GEM specific NCFGR bitfields. */ 161 #define GEM_GBE_OFFSET 10 162 #define GEM_GBE_SIZE 1 163 #define GEM_CLK_OFFSET 18 164 #define GEM_CLK_SIZE 3 165 #define GEM_DBW_OFFSET 21 166 #define GEM_DBW_SIZE 2 167 #define GEM_RXCOEN_OFFSET 24 168 #define GEM_RXCOEN_SIZE 1 169 170 /* Constants for data bus width. */ 171 #define GEM_DBW32 0 172 #define GEM_DBW64 1 173 #define GEM_DBW128 2 174 175 /* Bitfields in DMACFG. */ 176 #define GEM_FBLDO_OFFSET 0 177 #define GEM_FBLDO_SIZE 5 178 #define GEM_ENDIA_OFFSET 7 179 #define GEM_ENDIA_SIZE 1 180 #define GEM_RXBMS_OFFSET 8 181 #define GEM_RXBMS_SIZE 2 182 #define GEM_TXPBMS_OFFSET 10 183 #define GEM_TXPBMS_SIZE 1 184 #define GEM_TXCOEN_OFFSET 11 185 #define GEM_TXCOEN_SIZE 1 186 #define GEM_RXBS_OFFSET 16 187 #define GEM_RXBS_SIZE 8 188 #define GEM_DDRP_OFFSET 24 189 #define GEM_DDRP_SIZE 1 190 191 192 /* Bitfields in NSR */ 193 #define MACB_NSR_LINK_OFFSET 0 194 #define MACB_NSR_LINK_SIZE 1 195 #define MACB_MDIO_OFFSET 1 196 #define MACB_MDIO_SIZE 1 197 #define MACB_IDLE_OFFSET 2 198 #define MACB_IDLE_SIZE 1 199 200 /* Bitfields in TSR */ 201 #define MACB_UBR_OFFSET 0 202 #define MACB_UBR_SIZE 1 203 #define MACB_COL_OFFSET 1 204 #define MACB_COL_SIZE 1 205 #define MACB_TSR_RLE_OFFSET 2 206 #define MACB_TSR_RLE_SIZE 1 207 #define MACB_TGO_OFFSET 3 208 #define MACB_TGO_SIZE 1 209 #define MACB_BEX_OFFSET 4 210 #define MACB_BEX_SIZE 1 211 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 212 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 213 #define MACB_COMP_OFFSET 5 214 #define MACB_COMP_SIZE 1 215 #define MACB_UND_OFFSET 6 216 #define MACB_UND_SIZE 1 217 218 /* Bitfields in RSR */ 219 #define MACB_BNA_OFFSET 0 220 #define MACB_BNA_SIZE 1 221 #define MACB_REC_OFFSET 1 222 #define MACB_REC_SIZE 1 223 #define MACB_OVR_OFFSET 2 224 #define MACB_OVR_SIZE 1 225 226 /* Bitfields in ISR/IER/IDR/IMR */ 227 #define MACB_MFD_OFFSET 0 228 #define MACB_MFD_SIZE 1 229 #define MACB_RCOMP_OFFSET 1 230 #define MACB_RCOMP_SIZE 1 231 #define MACB_RXUBR_OFFSET 2 232 #define MACB_RXUBR_SIZE 1 233 #define MACB_TXUBR_OFFSET 3 234 #define MACB_TXUBR_SIZE 1 235 #define MACB_ISR_TUND_OFFSET 4 236 #define MACB_ISR_TUND_SIZE 1 237 #define MACB_ISR_RLE_OFFSET 5 238 #define MACB_ISR_RLE_SIZE 1 239 #define MACB_TXERR_OFFSET 6 240 #define MACB_TXERR_SIZE 1 241 #define MACB_TCOMP_OFFSET 7 242 #define MACB_TCOMP_SIZE 1 243 #define MACB_ISR_LINK_OFFSET 9 244 #define MACB_ISR_LINK_SIZE 1 245 #define MACB_ISR_ROVR_OFFSET 10 246 #define MACB_ISR_ROVR_SIZE 1 247 #define MACB_HRESP_OFFSET 11 248 #define MACB_HRESP_SIZE 1 249 #define MACB_PFR_OFFSET 12 250 #define MACB_PFR_SIZE 1 251 #define MACB_PTZ_OFFSET 13 252 #define MACB_PTZ_SIZE 1 253 254 /* Bitfields in MAN */ 255 #define MACB_DATA_OFFSET 0 256 #define MACB_DATA_SIZE 16 257 #define MACB_CODE_OFFSET 16 258 #define MACB_CODE_SIZE 2 259 #define MACB_REGA_OFFSET 18 260 #define MACB_REGA_SIZE 5 261 #define MACB_PHYA_OFFSET 23 262 #define MACB_PHYA_SIZE 5 263 #define MACB_RW_OFFSET 28 264 #define MACB_RW_SIZE 2 265 #define MACB_SOF_OFFSET 30 266 #define MACB_SOF_SIZE 2 267 268 /* Bitfields in USRIO (AVR32) */ 269 #define MACB_MII_OFFSET 0 270 #define MACB_MII_SIZE 1 271 #define MACB_EAM_OFFSET 1 272 #define MACB_EAM_SIZE 1 273 #define MACB_TX_PAUSE_OFFSET 2 274 #define MACB_TX_PAUSE_SIZE 1 275 #define MACB_TX_PAUSE_ZERO_OFFSET 3 276 #define MACB_TX_PAUSE_ZERO_SIZE 1 277 278 /* Bitfields in USRIO (AT91) */ 279 #define MACB_RMII_OFFSET 0 280 #define MACB_RMII_SIZE 1 281 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 282 #define GEM_RGMII_SIZE 1 283 #define MACB_CLKEN_OFFSET 1 284 #define MACB_CLKEN_SIZE 1 285 286 /* Bitfields in WOL */ 287 #define MACB_IP_OFFSET 0 288 #define MACB_IP_SIZE 16 289 #define MACB_MAG_OFFSET 16 290 #define MACB_MAG_SIZE 1 291 #define MACB_ARP_OFFSET 17 292 #define MACB_ARP_SIZE 1 293 #define MACB_SA1_OFFSET 18 294 #define MACB_SA1_SIZE 1 295 #define MACB_WOL_MTI_OFFSET 19 296 #define MACB_WOL_MTI_SIZE 1 297 298 /* Bitfields in MID */ 299 #define MACB_IDNUM_OFFSET 16 300 #define MACB_IDNUM_SIZE 16 301 #define MACB_REV_OFFSET 0 302 #define MACB_REV_SIZE 16 303 304 /* Bitfields in DCFG1. */ 305 #define GEM_IRQCOR_OFFSET 23 306 #define GEM_IRQCOR_SIZE 1 307 #define GEM_DBWDEF_OFFSET 25 308 #define GEM_DBWDEF_SIZE 3 309 310 /* Bitfields in DCFG2. */ 311 #define GEM_RX_PKT_BUFF_OFFSET 20 312 #define GEM_RX_PKT_BUFF_SIZE 1 313 #define GEM_TX_PKT_BUFF_OFFSET 21 314 #define GEM_TX_PKT_BUFF_SIZE 1 315 316 /* Constants for CLK */ 317 #define MACB_CLK_DIV8 0 318 #define MACB_CLK_DIV16 1 319 #define MACB_CLK_DIV32 2 320 #define MACB_CLK_DIV64 3 321 322 /* GEM specific constants for CLK. */ 323 #define GEM_CLK_DIV8 0 324 #define GEM_CLK_DIV16 1 325 #define GEM_CLK_DIV32 2 326 #define GEM_CLK_DIV48 3 327 #define GEM_CLK_DIV64 4 328 #define GEM_CLK_DIV96 5 329 330 /* Constants for MAN register */ 331 #define MACB_MAN_SOF 1 332 #define MACB_MAN_WRITE 1 333 #define MACB_MAN_READ 2 334 #define MACB_MAN_CODE 2 335 336 /* Capability mask bits */ 337 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 338 #define MACB_CAPS_FIFO_MODE 0x10000000 339 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 340 #define MACB_CAPS_SG_DISABLED 0x40000000 341 #define MACB_CAPS_MACB_IS_GEM 0x80000000 342 343 /* Bit manipulation macros */ 344 #define MACB_BIT(name) \ 345 (1 << MACB_##name##_OFFSET) 346 #define MACB_BF(name,value) \ 347 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 348 << MACB_##name##_OFFSET) 349 #define MACB_BFEXT(name,value)\ 350 (((value) >> MACB_##name##_OFFSET) \ 351 & ((1 << MACB_##name##_SIZE) - 1)) 352 #define MACB_BFINS(name,value,old) \ 353 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 354 << MACB_##name##_OFFSET)) \ 355 | MACB_BF(name,value)) 356 357 #define GEM_BIT(name) \ 358 (1 << GEM_##name##_OFFSET) 359 #define GEM_BF(name, value) \ 360 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 361 << GEM_##name##_OFFSET) 362 #define GEM_BFEXT(name, value)\ 363 (((value) >> GEM_##name##_OFFSET) \ 364 & ((1 << GEM_##name##_SIZE) - 1)) 365 #define GEM_BFINS(name, value, old) \ 366 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 367 << GEM_##name##_OFFSET)) \ 368 | GEM_BF(name, value)) 369 370 /* Register access macros */ 371 #define macb_readl(port,reg) \ 372 __raw_readl((port)->regs + MACB_##reg) 373 #define macb_writel(port,reg,value) \ 374 __raw_writel((value), (port)->regs + MACB_##reg) 375 #define gem_readl(port, reg) \ 376 __raw_readl((port)->regs + GEM_##reg) 377 #define gem_writel(port, reg, value) \ 378 __raw_writel((value), (port)->regs + GEM_##reg) 379 380 /* 381 * Conditional GEM/MACB macros. These perform the operation to the correct 382 * register dependent on whether the device is a GEM or a MACB. For registers 383 * and bitfields that are common across both devices, use macb_{read,write}l 384 * to avoid the cost of the conditional. 385 */ 386 #define macb_or_gem_writel(__bp, __reg, __value) \ 387 ({ \ 388 if (macb_is_gem((__bp))) \ 389 gem_writel((__bp), __reg, __value); \ 390 else \ 391 macb_writel((__bp), __reg, __value); \ 392 }) 393 394 #define macb_or_gem_readl(__bp, __reg) \ 395 ({ \ 396 u32 __v; \ 397 if (macb_is_gem((__bp))) \ 398 __v = gem_readl((__bp), __reg); \ 399 else \ 400 __v = macb_readl((__bp), __reg); \ 401 __v; \ 402 }) 403 404 /** 405 * struct macb_dma_desc - Hardware DMA descriptor 406 * @addr: DMA address of data buffer 407 * @ctrl: Control and status bits 408 */ 409 struct macb_dma_desc { 410 u32 addr; 411 u32 ctrl; 412 }; 413 414 /* DMA descriptor bitfields */ 415 #define MACB_RX_USED_OFFSET 0 416 #define MACB_RX_USED_SIZE 1 417 #define MACB_RX_WRAP_OFFSET 1 418 #define MACB_RX_WRAP_SIZE 1 419 #define MACB_RX_WADDR_OFFSET 2 420 #define MACB_RX_WADDR_SIZE 30 421 422 #define MACB_RX_FRMLEN_OFFSET 0 423 #define MACB_RX_FRMLEN_SIZE 12 424 #define MACB_RX_OFFSET_OFFSET 12 425 #define MACB_RX_OFFSET_SIZE 2 426 #define MACB_RX_SOF_OFFSET 14 427 #define MACB_RX_SOF_SIZE 1 428 #define MACB_RX_EOF_OFFSET 15 429 #define MACB_RX_EOF_SIZE 1 430 #define MACB_RX_CFI_OFFSET 16 431 #define MACB_RX_CFI_SIZE 1 432 #define MACB_RX_VLAN_PRI_OFFSET 17 433 #define MACB_RX_VLAN_PRI_SIZE 3 434 #define MACB_RX_PRI_TAG_OFFSET 20 435 #define MACB_RX_PRI_TAG_SIZE 1 436 #define MACB_RX_VLAN_TAG_OFFSET 21 437 #define MACB_RX_VLAN_TAG_SIZE 1 438 #define MACB_RX_TYPEID_MATCH_OFFSET 22 439 #define MACB_RX_TYPEID_MATCH_SIZE 1 440 #define MACB_RX_SA4_MATCH_OFFSET 23 441 #define MACB_RX_SA4_MATCH_SIZE 1 442 #define MACB_RX_SA3_MATCH_OFFSET 24 443 #define MACB_RX_SA3_MATCH_SIZE 1 444 #define MACB_RX_SA2_MATCH_OFFSET 25 445 #define MACB_RX_SA2_MATCH_SIZE 1 446 #define MACB_RX_SA1_MATCH_OFFSET 26 447 #define MACB_RX_SA1_MATCH_SIZE 1 448 #define MACB_RX_EXT_MATCH_OFFSET 28 449 #define MACB_RX_EXT_MATCH_SIZE 1 450 #define MACB_RX_UHASH_MATCH_OFFSET 29 451 #define MACB_RX_UHASH_MATCH_SIZE 1 452 #define MACB_RX_MHASH_MATCH_OFFSET 30 453 #define MACB_RX_MHASH_MATCH_SIZE 1 454 #define MACB_RX_BROADCAST_OFFSET 31 455 #define MACB_RX_BROADCAST_SIZE 1 456 457 /* RX checksum offload disabled: bit 24 clear in NCFGR */ 458 #define GEM_RX_TYPEID_MATCH_OFFSET 22 459 #define GEM_RX_TYPEID_MATCH_SIZE 2 460 461 /* RX checksum offload enabled: bit 24 set in NCFGR */ 462 #define GEM_RX_CSUM_OFFSET 22 463 #define GEM_RX_CSUM_SIZE 2 464 465 #define MACB_TX_FRMLEN_OFFSET 0 466 #define MACB_TX_FRMLEN_SIZE 11 467 #define MACB_TX_LAST_OFFSET 15 468 #define MACB_TX_LAST_SIZE 1 469 #define MACB_TX_NOCRC_OFFSET 16 470 #define MACB_TX_NOCRC_SIZE 1 471 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 472 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 473 #define MACB_TX_UNDERRUN_OFFSET 28 474 #define MACB_TX_UNDERRUN_SIZE 1 475 #define MACB_TX_ERROR_OFFSET 29 476 #define MACB_TX_ERROR_SIZE 1 477 #define MACB_TX_WRAP_OFFSET 30 478 #define MACB_TX_WRAP_SIZE 1 479 #define MACB_TX_USED_OFFSET 31 480 #define MACB_TX_USED_SIZE 1 481 482 #define GEM_TX_FRMLEN_OFFSET 0 483 #define GEM_TX_FRMLEN_SIZE 14 484 485 /* Buffer descriptor constants */ 486 #define GEM_RX_CSUM_NONE 0 487 #define GEM_RX_CSUM_IP_ONLY 1 488 #define GEM_RX_CSUM_IP_TCP 2 489 #define GEM_RX_CSUM_IP_UDP 3 490 491 /* limit RX checksum offload to TCP and UDP packets */ 492 #define GEM_RX_CSUM_CHECKED_MASK 2 493 494 /** 495 * struct macb_tx_skb - data about an skb which is being transmitted 496 * @skb: skb currently being transmitted, only set for the last buffer 497 * of the frame 498 * @mapping: DMA address of the skb's fragment buffer 499 * @size: size of the DMA mapped buffer 500 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(), 501 * false when buffer was mapped with dma_map_single() 502 */ 503 struct macb_tx_skb { 504 struct sk_buff *skb; 505 dma_addr_t mapping; 506 size_t size; 507 bool mapped_as_page; 508 }; 509 510 /* 511 * Hardware-collected statistics. Used when updating the network 512 * device stats by a periodic timer. 513 */ 514 struct macb_stats { 515 u32 rx_pause_frames; 516 u32 tx_ok; 517 u32 tx_single_cols; 518 u32 tx_multiple_cols; 519 u32 rx_ok; 520 u32 rx_fcs_errors; 521 u32 rx_align_errors; 522 u32 tx_deferred; 523 u32 tx_late_cols; 524 u32 tx_excessive_cols; 525 u32 tx_underruns; 526 u32 tx_carrier_errors; 527 u32 rx_resource_errors; 528 u32 rx_overruns; 529 u32 rx_symbol_errors; 530 u32 rx_oversize_pkts; 531 u32 rx_jabbers; 532 u32 rx_undersize_pkts; 533 u32 sqe_test_errors; 534 u32 rx_length_mismatch; 535 u32 tx_pause_frames; 536 }; 537 538 struct gem_stats { 539 u32 tx_octets_31_0; 540 u32 tx_octets_47_32; 541 u32 tx_frames; 542 u32 tx_broadcast_frames; 543 u32 tx_multicast_frames; 544 u32 tx_pause_frames; 545 u32 tx_64_byte_frames; 546 u32 tx_65_127_byte_frames; 547 u32 tx_128_255_byte_frames; 548 u32 tx_256_511_byte_frames; 549 u32 tx_512_1023_byte_frames; 550 u32 tx_1024_1518_byte_frames; 551 u32 tx_greater_than_1518_byte_frames; 552 u32 tx_underrun; 553 u32 tx_single_collision_frames; 554 u32 tx_multiple_collision_frames; 555 u32 tx_excessive_collisions; 556 u32 tx_late_collisions; 557 u32 tx_deferred_frames; 558 u32 tx_carrier_sense_errors; 559 u32 rx_octets_31_0; 560 u32 rx_octets_47_32; 561 u32 rx_frames; 562 u32 rx_broadcast_frames; 563 u32 rx_multicast_frames; 564 u32 rx_pause_frames; 565 u32 rx_64_byte_frames; 566 u32 rx_65_127_byte_frames; 567 u32 rx_128_255_byte_frames; 568 u32 rx_256_511_byte_frames; 569 u32 rx_512_1023_byte_frames; 570 u32 rx_1024_1518_byte_frames; 571 u32 rx_greater_than_1518_byte_frames; 572 u32 rx_undersized_frames; 573 u32 rx_oversize_frames; 574 u32 rx_jabbers; 575 u32 rx_frame_check_sequence_errors; 576 u32 rx_length_field_frame_errors; 577 u32 rx_symbol_errors; 578 u32 rx_alignment_errors; 579 u32 rx_resource_errors; 580 u32 rx_overruns; 581 u32 rx_ip_header_checksum_errors; 582 u32 rx_tcp_checksum_errors; 583 u32 rx_udp_checksum_errors; 584 }; 585 586 struct macb; 587 588 struct macb_or_gem_ops { 589 int (*mog_alloc_rx_buffers)(struct macb *bp); 590 void (*mog_free_rx_buffers)(struct macb *bp); 591 void (*mog_init_rings)(struct macb *bp); 592 int (*mog_rx)(struct macb *bp, int budget); 593 }; 594 595 struct macb_config { 596 u32 caps; 597 unsigned int dma_burst_length; 598 }; 599 600 struct macb { 601 void __iomem *regs; 602 603 unsigned int rx_tail; 604 unsigned int rx_prepared_head; 605 struct macb_dma_desc *rx_ring; 606 struct sk_buff **rx_skbuff; 607 void *rx_buffers; 608 size_t rx_buffer_size; 609 610 unsigned int tx_head, tx_tail; 611 struct macb_dma_desc *tx_ring; 612 struct macb_tx_skb *tx_skb; 613 614 spinlock_t lock; 615 struct platform_device *pdev; 616 struct clk *pclk; 617 struct clk *hclk; 618 struct clk *tx_clk; 619 struct net_device *dev; 620 struct napi_struct napi; 621 struct work_struct tx_error_task; 622 struct net_device_stats stats; 623 union { 624 struct macb_stats macb; 625 struct gem_stats gem; 626 } hw_stats; 627 628 dma_addr_t rx_ring_dma; 629 dma_addr_t tx_ring_dma; 630 dma_addr_t rx_buffers_dma; 631 632 struct macb_or_gem_ops macbgem_ops; 633 634 struct mii_bus *mii_bus; 635 struct phy_device *phy_dev; 636 unsigned int link; 637 unsigned int speed; 638 unsigned int duplex; 639 640 u32 caps; 641 unsigned int dma_burst_length; 642 643 phy_interface_t phy_interface; 644 645 /* AT91RM9200 transmit */ 646 struct sk_buff *skb; /* holds skb until xmit interrupt completes */ 647 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ 648 int skb_length; /* saved skb length for pci_unmap_single */ 649 unsigned int max_tx_length; 650 }; 651 652 extern const struct ethtool_ops macb_ethtool_ops; 653 654 int macb_mii_init(struct macb *bp); 655 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 656 struct net_device_stats *macb_get_stats(struct net_device *dev); 657 void macb_set_rx_mode(struct net_device *dev); 658 void macb_set_hwaddr(struct macb *bp); 659 void macb_get_hwaddr(struct macb *bp); 660 661 static inline bool macb_is_gem(struct macb *bp) 662 { 663 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM); 664 } 665 666 #endif /* _MACB_H */ 667