1f844a0eaSJeff Kirsher /* 22732ba56SRasesh Mody * Linux network driver for QLogic BR-series Converged Network Adapter. 3f844a0eaSJeff Kirsher * 4f844a0eaSJeff Kirsher * This program is free software; you can redistribute it and/or modify it 5f844a0eaSJeff Kirsher * under the terms of the GNU General Public License (GPL) Version 2 as 6f844a0eaSJeff Kirsher * published by the Free Software Foundation 7f844a0eaSJeff Kirsher * 8f844a0eaSJeff Kirsher * This program is distributed in the hope that it will be useful, but 9f844a0eaSJeff Kirsher * WITHOUT ANY WARRANTY; without even the implied warranty of 10f844a0eaSJeff Kirsher * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11f844a0eaSJeff Kirsher * General Public License for more details. 12f844a0eaSJeff Kirsher */ 13f844a0eaSJeff Kirsher /* 142732ba56SRasesh Mody * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 152732ba56SRasesh Mody * Copyright (c) 2014-2015 QLogic Corporation 16f844a0eaSJeff Kirsher * All rights reserved 172732ba56SRasesh Mody * www.qlogic.com 18f844a0eaSJeff Kirsher */ 19f844a0eaSJeff Kirsher #ifndef __BNAD_H__ 20f844a0eaSJeff Kirsher #define __BNAD_H__ 21f844a0eaSJeff Kirsher 22f844a0eaSJeff Kirsher #include <linux/rtnetlink.h> 23f844a0eaSJeff Kirsher #include <linux/workqueue.h> 24f844a0eaSJeff Kirsher #include <linux/ipv6.h> 25f844a0eaSJeff Kirsher #include <linux/etherdevice.h> 26f844a0eaSJeff Kirsher #include <linux/mutex.h> 27f844a0eaSJeff Kirsher #include <linux/firmware.h> 28f844a0eaSJeff Kirsher #include <linux/if_vlan.h> 29f844a0eaSJeff Kirsher 30f844a0eaSJeff Kirsher /* Fix for IA64 */ 31f844a0eaSJeff Kirsher #include <asm/checksum.h> 32f844a0eaSJeff Kirsher #include <net/ip6_checksum.h> 33f844a0eaSJeff Kirsher 34f844a0eaSJeff Kirsher #include <net/ip.h> 35f844a0eaSJeff Kirsher #include <net/tcp.h> 36f844a0eaSJeff Kirsher 37f844a0eaSJeff Kirsher #include "bna.h" 38f844a0eaSJeff Kirsher 39f844a0eaSJeff Kirsher #define BNAD_TXQ_DEPTH 2048 40f844a0eaSJeff Kirsher #define BNAD_RXQ_DEPTH 2048 41f844a0eaSJeff Kirsher 42772b5235SRasesh Mody #define BNAD_MAX_TX 1 43f844a0eaSJeff Kirsher #define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */ 44f844a0eaSJeff Kirsher #define BNAD_TXQ_NUM 1 45f844a0eaSJeff Kirsher 46772b5235SRasesh Mody #define BNAD_MAX_RX 1 47772b5235SRasesh Mody #define BNAD_MAX_RXP_PER_RX 16 48078086f3SRasesh Mody #define BNAD_MAX_RXQ_PER_RXP 2 49f844a0eaSJeff Kirsher 50f844a0eaSJeff Kirsher /* 51f844a0eaSJeff Kirsher * Control structure pointed to ccb->ctrl, which 52f844a0eaSJeff Kirsher * determines the NAPI / LRO behavior CCB 53f844a0eaSJeff Kirsher * There is 1:1 corres. between ccb & ctrl 54f844a0eaSJeff Kirsher */ 55f844a0eaSJeff Kirsher struct bnad_rx_ctrl { 56f844a0eaSJeff Kirsher struct bna_ccb *ccb; 572be67144SRasesh Mody struct bnad *bnad; 58f844a0eaSJeff Kirsher unsigned long flags; 59f844a0eaSJeff Kirsher struct napi_struct napi; 60271e8b79SRasesh Mody u64 rx_intr_ctr; 61271e8b79SRasesh Mody u64 rx_poll_ctr; 62271e8b79SRasesh Mody u64 rx_schedule; 63271e8b79SRasesh Mody u64 rx_keep_poll; 64271e8b79SRasesh Mody u64 rx_complete; 65f844a0eaSJeff Kirsher }; 66f844a0eaSJeff Kirsher 67f844a0eaSJeff Kirsher #define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC 68f844a0eaSJeff Kirsher 69f844a0eaSJeff Kirsher /* 70f844a0eaSJeff Kirsher * GLOBAL #defines (CONSTANTS) 71f844a0eaSJeff Kirsher */ 72f844a0eaSJeff Kirsher #define BNAD_NAME "bna" 73f844a0eaSJeff Kirsher #define BNAD_NAME_LEN 64 74f844a0eaSJeff Kirsher 753f307c3dSRasesh Mody #define BNAD_VERSION "3.2.25.1" 76f844a0eaSJeff Kirsher 77f844a0eaSJeff Kirsher #define BNAD_MAILBOX_MSIX_INDEX 0 78f844a0eaSJeff Kirsher #define BNAD_MAILBOX_MSIX_VECTORS 1 79f844a0eaSJeff Kirsher #define BNAD_INTX_TX_IB_BITMASK 0x1 80f844a0eaSJeff Kirsher #define BNAD_INTX_RX_IB_BITMASK 0x2 81f844a0eaSJeff Kirsher 82f844a0eaSJeff Kirsher #define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */ 83f844a0eaSJeff Kirsher #define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */ 84f844a0eaSJeff Kirsher 85078086f3SRasesh Mody #define BNAD_IOCETH_TIMEOUT 10000 86078086f3SRasesh Mody 875216562aSRasesh Mody #define BNAD_MIN_Q_DEPTH 512 8866f9513aSRasesh Mody #define BNAD_MAX_RXQ_DEPTH 16384 895216562aSRasesh Mody #define BNAD_MAX_TXQ_DEPTH 2048 9041eb5ba4SRasesh Mody 91f844a0eaSJeff Kirsher #define BNAD_JUMBO_MTU 9000 92f844a0eaSJeff Kirsher 93f844a0eaSJeff Kirsher #define BNAD_NETIF_WAKE_THRESHOLD 8 94f844a0eaSJeff Kirsher 95f844a0eaSJeff Kirsher #define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3 96f844a0eaSJeff Kirsher 97f844a0eaSJeff Kirsher /* Bit positions for tcb->flags */ 98f844a0eaSJeff Kirsher #define BNAD_TXQ_FREE_SENT 0 99f844a0eaSJeff Kirsher #define BNAD_TXQ_TX_STARTED 1 100f844a0eaSJeff Kirsher 101f844a0eaSJeff Kirsher /* Bit positions for rcb->flags */ 1025216562aSRasesh Mody #define BNAD_RXQ_STARTED 0 1035216562aSRasesh Mody #define BNAD_RXQ_POST_OK 1 104f844a0eaSJeff Kirsher 105078086f3SRasesh Mody /* Resource limits */ 106078086f3SRasesh Mody #define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx) 107078086f3SRasesh Mody #define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx) 108078086f3SRasesh Mody 109e29aa339SRasesh Mody #define BNAD_FRAME_SIZE(_mtu) \ 110e29aa339SRasesh Mody (ETH_HLEN + VLAN_HLEN + (_mtu) + ETH_FCS_LEN) 111e29aa339SRasesh Mody 112f844a0eaSJeff Kirsher /* 113f844a0eaSJeff Kirsher * DATA STRUCTURES 114f844a0eaSJeff Kirsher */ 115f844a0eaSJeff Kirsher 116f844a0eaSJeff Kirsher /* enums */ 117f844a0eaSJeff Kirsher enum bnad_intr_source { 118f844a0eaSJeff Kirsher BNAD_INTR_TX = 1, 119f844a0eaSJeff Kirsher BNAD_INTR_RX = 2 120f844a0eaSJeff Kirsher }; 121f844a0eaSJeff Kirsher 122f844a0eaSJeff Kirsher enum bnad_link_state { 123f844a0eaSJeff Kirsher BNAD_LS_DOWN = 0, 124f844a0eaSJeff Kirsher BNAD_LS_UP = 1 125f844a0eaSJeff Kirsher }; 126f844a0eaSJeff Kirsher 12772a9730bSKrishna Gudipati struct bnad_iocmd_comp { 12872a9730bSKrishna Gudipati struct bnad *bnad; 12972a9730bSKrishna Gudipati struct completion comp; 13072a9730bSKrishna Gudipati int comp_status; 13172a9730bSKrishna Gudipati }; 13272a9730bSKrishna Gudipati 133f844a0eaSJeff Kirsher struct bnad_completion { 134f844a0eaSJeff Kirsher struct completion ioc_comp; 135f844a0eaSJeff Kirsher struct completion ucast_comp; 136f844a0eaSJeff Kirsher struct completion mcast_comp; 137f844a0eaSJeff Kirsher struct completion tx_comp; 138f844a0eaSJeff Kirsher struct completion rx_comp; 139f844a0eaSJeff Kirsher struct completion stats_comp; 140078086f3SRasesh Mody struct completion enet_comp; 141078086f3SRasesh Mody struct completion mtu_comp; 142f844a0eaSJeff Kirsher 143f844a0eaSJeff Kirsher u8 ioc_comp_status; 144f844a0eaSJeff Kirsher u8 ucast_comp_status; 145f844a0eaSJeff Kirsher u8 mcast_comp_status; 146f844a0eaSJeff Kirsher u8 tx_comp_status; 147f844a0eaSJeff Kirsher u8 rx_comp_status; 148f844a0eaSJeff Kirsher u8 stats_comp_status; 149f844a0eaSJeff Kirsher u8 port_comp_status; 150078086f3SRasesh Mody u8 mtu_comp_status; 151f844a0eaSJeff Kirsher }; 152f844a0eaSJeff Kirsher 153f844a0eaSJeff Kirsher /* Tx Rx Control Stats */ 154f844a0eaSJeff Kirsher struct bnad_drv_stats { 155f844a0eaSJeff Kirsher u64 netif_queue_stop; 156f844a0eaSJeff Kirsher u64 netif_queue_wakeup; 157f844a0eaSJeff Kirsher u64 netif_queue_stopped; 158f844a0eaSJeff Kirsher u64 tso4; 159f844a0eaSJeff Kirsher u64 tso6; 160f844a0eaSJeff Kirsher u64 tso_err; 161f844a0eaSJeff Kirsher u64 tcpcsum_offload; 162f844a0eaSJeff Kirsher u64 udpcsum_offload; 163f844a0eaSJeff Kirsher u64 csum_help; 164271e8b79SRasesh Mody u64 tx_skb_too_short; 165271e8b79SRasesh Mody u64 tx_skb_stopping; 166271e8b79SRasesh Mody u64 tx_skb_max_vectors; 167271e8b79SRasesh Mody u64 tx_skb_mss_too_long; 168271e8b79SRasesh Mody u64 tx_skb_tso_too_short; 169271e8b79SRasesh Mody u64 tx_skb_tso_prepare; 170271e8b79SRasesh Mody u64 tx_skb_non_tso_too_long; 171271e8b79SRasesh Mody u64 tx_skb_tcp_hdr; 172271e8b79SRasesh Mody u64 tx_skb_udp_hdr; 173271e8b79SRasesh Mody u64 tx_skb_csum_err; 174271e8b79SRasesh Mody u64 tx_skb_headlen_too_long; 175271e8b79SRasesh Mody u64 tx_skb_headlen_zero; 176271e8b79SRasesh Mody u64 tx_skb_frag_zero; 177271e8b79SRasesh Mody u64 tx_skb_len_mismatch; 178ba5ca784SIvan Vecera u64 tx_skb_map_failed; 179f844a0eaSJeff Kirsher 180f844a0eaSJeff Kirsher u64 hw_stats_updates; 181f844a0eaSJeff Kirsher u64 netif_rx_dropped; 182f844a0eaSJeff Kirsher 183f844a0eaSJeff Kirsher u64 link_toggle; 184078086f3SRasesh Mody u64 cee_toggle; 185f844a0eaSJeff Kirsher 186f844a0eaSJeff Kirsher u64 rxp_info_alloc_failed; 187f844a0eaSJeff Kirsher u64 mbox_intr_disabled; 188f844a0eaSJeff Kirsher u64 mbox_intr_enabled; 189f844a0eaSJeff Kirsher u64 tx_unmap_q_alloc_failed; 190f844a0eaSJeff Kirsher u64 rx_unmap_q_alloc_failed; 191f844a0eaSJeff Kirsher 192f844a0eaSJeff Kirsher u64 rxbuf_alloc_failed; 193ba5ca784SIvan Vecera u64 rxbuf_map_failed; 194f844a0eaSJeff Kirsher }; 195f844a0eaSJeff Kirsher 196f844a0eaSJeff Kirsher /* Complete driver stats */ 197f844a0eaSJeff Kirsher struct bnad_stats { 198f844a0eaSJeff Kirsher struct bnad_drv_stats drv_stats; 199f844a0eaSJeff Kirsher struct bna_stats *bna_stats; 200f844a0eaSJeff Kirsher }; 201f844a0eaSJeff Kirsher 202f844a0eaSJeff Kirsher /* Tx / Rx Resources */ 203f844a0eaSJeff Kirsher struct bnad_tx_res_info { 204f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_TX_RES_T_MAX]; 205f844a0eaSJeff Kirsher }; 206f844a0eaSJeff Kirsher 207f844a0eaSJeff Kirsher struct bnad_rx_res_info { 208f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_RX_RES_T_MAX]; 209f844a0eaSJeff Kirsher }; 210f844a0eaSJeff Kirsher 211f844a0eaSJeff Kirsher struct bnad_tx_info { 212f844a0eaSJeff Kirsher struct bna_tx *tx; /* 1:1 between tx_info & tx */ 213f844a0eaSJeff Kirsher struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX]; 214078086f3SRasesh Mody u32 tx_id; 21501b54b14SJing Huang struct delayed_work tx_cleanup_work; 216f844a0eaSJeff Kirsher } ____cacheline_aligned; 217f844a0eaSJeff Kirsher 218f844a0eaSJeff Kirsher struct bnad_rx_info { 219f844a0eaSJeff Kirsher struct bna_rx *rx; /* 1:1 between rx_info & rx */ 220f844a0eaSJeff Kirsher 221772b5235SRasesh Mody struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX]; 222078086f3SRasesh Mody u32 rx_id; 22301b54b14SJing Huang struct work_struct rx_cleanup_work; 224f844a0eaSJeff Kirsher } ____cacheline_aligned; 225f844a0eaSJeff Kirsher 2265216562aSRasesh Mody struct bnad_tx_vector { 227f844a0eaSJeff Kirsher DEFINE_DMA_UNMAP_ADDR(dma_addr); 22824f5d33dSRasesh Mody DEFINE_DMA_UNMAP_LEN(dma_len); 229f844a0eaSJeff Kirsher }; 230f844a0eaSJeff Kirsher 2315216562aSRasesh Mody struct bnad_tx_unmap { 2325216562aSRasesh Mody struct sk_buff *skb; 2335216562aSRasesh Mody u32 nvecs; 2345216562aSRasesh Mody struct bnad_tx_vector vectors[BFI_TX_MAX_VECTORS_PER_WI]; 2355216562aSRasesh Mody }; 2365216562aSRasesh Mody 2375216562aSRasesh Mody struct bnad_rx_vector { 2385216562aSRasesh Mody DEFINE_DMA_UNMAP_ADDR(dma_addr); 2395216562aSRasesh Mody u32 len; 2405216562aSRasesh Mody }; 2415216562aSRasesh Mody 2425216562aSRasesh Mody struct bnad_rx_unmap { 24330f9fc94SRasesh Mody struct page *page; 2445216562aSRasesh Mody struct sk_buff *skb; 2455216562aSRasesh Mody struct bnad_rx_vector vector; 24666f9513aSRasesh Mody u32 page_offset; 247f844a0eaSJeff Kirsher }; 248f844a0eaSJeff Kirsher 24930f9fc94SRasesh Mody enum bnad_rxbuf_type { 25030f9fc94SRasesh Mody BNAD_RXBUF_NONE = 0, 251e29aa339SRasesh Mody BNAD_RXBUF_SK_BUFF = 1, 25230f9fc94SRasesh Mody BNAD_RXBUF_PAGE = 2, 253e29aa339SRasesh Mody BNAD_RXBUF_MULTI_BUFF = 3 25430f9fc94SRasesh Mody }; 25530f9fc94SRasesh Mody 256e29aa339SRasesh Mody #define BNAD_RXBUF_IS_SK_BUFF(_type) ((_type) == BNAD_RXBUF_SK_BUFF) 257e29aa339SRasesh Mody #define BNAD_RXBUF_IS_MULTI_BUFF(_type) ((_type) == BNAD_RXBUF_MULTI_BUFF) 25830f9fc94SRasesh Mody 25930f9fc94SRasesh Mody struct bnad_rx_unmap_q { 26030f9fc94SRasesh Mody int reuse_pi; 26130f9fc94SRasesh Mody int alloc_order; 26230f9fc94SRasesh Mody u32 map_size; 26330f9fc94SRasesh Mody enum bnad_rxbuf_type type; 26466f9513aSRasesh Mody struct bnad_rx_unmap unmap[0] ____cacheline_aligned; 26530f9fc94SRasesh Mody }; 26630f9fc94SRasesh Mody 267e29aa339SRasesh Mody #define BNAD_PCI_DEV_IS_CAT2(_bnad) \ 268e29aa339SRasesh Mody ((_bnad)->pcidev->device == BFA_PCI_DEVICE_ID_CT2) 269e29aa339SRasesh Mody 270f844a0eaSJeff Kirsher /* Bit mask values for bnad->cfg_flags */ 271f844a0eaSJeff Kirsher #define BNAD_CF_DIM_ENABLED 0x01 /* DIM */ 272f844a0eaSJeff Kirsher #define BNAD_CF_PROMISC 0x02 273f844a0eaSJeff Kirsher #define BNAD_CF_ALLMULTI 0x04 274fe1624cfSRasesh Mody #define BNAD_CF_DEFAULT 0x08 275fe1624cfSRasesh Mody #define BNAD_CF_MSIX 0x10 /* If in MSIx mode */ 276f844a0eaSJeff Kirsher 277f844a0eaSJeff Kirsher /* Defines for run_flags bit-mask */ 278f844a0eaSJeff Kirsher /* Set, tested & cleared using xxx_bit() functions */ 279f844a0eaSJeff Kirsher /* Values indicated bit positions */ 280078086f3SRasesh Mody #define BNAD_RF_CEE_RUNNING 0 281078086f3SRasesh Mody #define BNAD_RF_MTU_SET 1 282f844a0eaSJeff Kirsher #define BNAD_RF_MBOX_IRQ_DISABLED 2 283078086f3SRasesh Mody #define BNAD_RF_NETDEV_REGISTERED 3 284f844a0eaSJeff Kirsher #define BNAD_RF_DIM_TIMER_RUNNING 4 285f844a0eaSJeff Kirsher #define BNAD_RF_STATS_TIMER_RUNNING 5 286078086f3SRasesh Mody #define BNAD_RF_TX_PRIO_SET 6 287078086f3SRasesh Mody 288f844a0eaSJeff Kirsher struct bnad { 289f844a0eaSJeff Kirsher struct net_device *netdev; 29072a9730bSKrishna Gudipati u32 id; 29172a9730bSKrishna Gudipati struct list_head list_entry; 292f844a0eaSJeff Kirsher 293f844a0eaSJeff Kirsher /* Data path */ 294772b5235SRasesh Mody struct bnad_tx_info tx_info[BNAD_MAX_TX]; 295772b5235SRasesh Mody struct bnad_rx_info rx_info[BNAD_MAX_RX]; 296f844a0eaSJeff Kirsher 297f844a0eaSJeff Kirsher unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 298f844a0eaSJeff Kirsher /* 299f844a0eaSJeff Kirsher * These q numbers are global only because 300f844a0eaSJeff Kirsher * they are used to calculate MSIx vectors. 301f844a0eaSJeff Kirsher * Actually the exact # of queues are per Tx/Rx 302f844a0eaSJeff Kirsher * object. 303f844a0eaSJeff Kirsher */ 304f844a0eaSJeff Kirsher u32 num_tx; 305f844a0eaSJeff Kirsher u32 num_rx; 306f844a0eaSJeff Kirsher u32 num_txq_per_tx; 307f844a0eaSJeff Kirsher u32 num_rxp_per_rx; 308f844a0eaSJeff Kirsher 309f844a0eaSJeff Kirsher u32 txq_depth; 310f844a0eaSJeff Kirsher u32 rxq_depth; 311f844a0eaSJeff Kirsher 312f844a0eaSJeff Kirsher u8 tx_coalescing_timeo; 313f844a0eaSJeff Kirsher u8 rx_coalescing_timeo; 314f844a0eaSJeff Kirsher 3155e46631fSRasesh Mody struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned; 3165e46631fSRasesh Mody struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned; 317f844a0eaSJeff Kirsher 318f844a0eaSJeff Kirsher void __iomem *bar0; /* BAR0 address */ 319f844a0eaSJeff Kirsher 320f844a0eaSJeff Kirsher struct bna bna; 321f844a0eaSJeff Kirsher 322f844a0eaSJeff Kirsher u32 cfg_flags; 323f844a0eaSJeff Kirsher unsigned long run_flags; 324f844a0eaSJeff Kirsher 325f844a0eaSJeff Kirsher struct pci_dev *pcidev; 326f844a0eaSJeff Kirsher u64 mmio_start; 327f844a0eaSJeff Kirsher u64 mmio_len; 328f844a0eaSJeff Kirsher 329f844a0eaSJeff Kirsher u32 msix_num; 330f844a0eaSJeff Kirsher struct msix_entry *msix_table; 331f844a0eaSJeff Kirsher 332f844a0eaSJeff Kirsher struct mutex conf_mutex; 333f844a0eaSJeff Kirsher spinlock_t bna_lock ____cacheline_aligned; 334f844a0eaSJeff Kirsher 335f844a0eaSJeff Kirsher /* Timers */ 336f844a0eaSJeff Kirsher struct timer_list ioc_timer; 337f844a0eaSJeff Kirsher struct timer_list dim_timer; 338f844a0eaSJeff Kirsher struct timer_list stats_timer; 339f844a0eaSJeff Kirsher 340f844a0eaSJeff Kirsher /* Control path resources, memory & irq */ 341f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_RES_T_MAX]; 342078086f3SRasesh Mody struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX]; 343772b5235SRasesh Mody struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX]; 344772b5235SRasesh Mody struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX]; 345f844a0eaSJeff Kirsher 346f844a0eaSJeff Kirsher struct bnad_completion bnad_completions; 347f844a0eaSJeff Kirsher 348f844a0eaSJeff Kirsher /* Burnt in MAC address */ 349d6b30598SIvan Vecera u8 perm_addr[ETH_ALEN]; 350f844a0eaSJeff Kirsher 35101b54b14SJing Huang struct workqueue_struct *work_q; 352f844a0eaSJeff Kirsher 353f844a0eaSJeff Kirsher /* Statistics */ 354f844a0eaSJeff Kirsher struct bnad_stats stats; 355f844a0eaSJeff Kirsher 356f844a0eaSJeff Kirsher struct bnad_diag *diag; 357f844a0eaSJeff Kirsher 358f844a0eaSJeff Kirsher char adapter_name[BNAD_NAME_LEN]; 359f844a0eaSJeff Kirsher char port_name[BNAD_NAME_LEN]; 360f844a0eaSJeff Kirsher char mbox_irq_name[BNAD_NAME_LEN]; 36101b54b14SJing Huang char wq_name[BNAD_NAME_LEN]; 3627afc5dbdSKrishna Gudipati 3637afc5dbdSKrishna Gudipati /* debugfs specific data */ 3647afc5dbdSKrishna Gudipati char *regdata; 3657afc5dbdSKrishna Gudipati u32 reglen; 3667afc5dbdSKrishna Gudipati struct dentry *bnad_dentry_files[5]; 3677afc5dbdSKrishna Gudipati struct dentry *port_debugfs_root; 3687afc5dbdSKrishna Gudipati }; 3697afc5dbdSKrishna Gudipati 3707afc5dbdSKrishna Gudipati struct bnad_drvinfo { 3717afc5dbdSKrishna Gudipati struct bfa_ioc_attr ioc_attr; 3727afc5dbdSKrishna Gudipati struct bfa_cee_attr cee_attr; 3737afc5dbdSKrishna Gudipati struct bfa_flash_attr flash_attr; 3747afc5dbdSKrishna Gudipati u32 cee_status; 3757afc5dbdSKrishna Gudipati u32 flash_status; 376f844a0eaSJeff Kirsher }; 377f844a0eaSJeff Kirsher 378f844a0eaSJeff Kirsher /* 379f844a0eaSJeff Kirsher * EXTERN VARIABLES 380f844a0eaSJeff Kirsher */ 381e1e0918fSstephen hemminger extern const struct firmware *bfi_fw; 382f844a0eaSJeff Kirsher 383f844a0eaSJeff Kirsher /* 384f844a0eaSJeff Kirsher * EXTERN PROTOTYPES 385f844a0eaSJeff Kirsher */ 38649ca19bdSJoe Perches u32 *cna_get_firmware_buf(struct pci_dev *pdev); 387f844a0eaSJeff Kirsher /* Netdev entry point prototypes */ 38849ca19bdSJoe Perches void bnad_set_rx_mode(struct net_device *netdev); 38949ca19bdSJoe Perches struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev); 390558caad7SIvan Vecera int bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr); 39149ca19bdSJoe Perches int bnad_enable_default_bcast(struct bnad *bnad); 39249ca19bdSJoe Perches void bnad_restore_vlans(struct bnad *bnad, u32 rx_id); 39349ca19bdSJoe Perches void bnad_set_ethtool_ops(struct net_device *netdev); 39449ca19bdSJoe Perches void bnad_cb_completion(void *arg, enum bfa_status status); 395f844a0eaSJeff Kirsher 396f844a0eaSJeff Kirsher /* Configuration & setup */ 39749ca19bdSJoe Perches void bnad_tx_coalescing_timeo_set(struct bnad *bnad); 39849ca19bdSJoe Perches void bnad_rx_coalescing_timeo_set(struct bnad *bnad); 399f844a0eaSJeff Kirsher 40049ca19bdSJoe Perches int bnad_setup_rx(struct bnad *bnad, u32 rx_id); 40149ca19bdSJoe Perches int bnad_setup_tx(struct bnad *bnad, u32 tx_id); 40249ca19bdSJoe Perches void bnad_destroy_tx(struct bnad *bnad, u32 tx_id); 40349ca19bdSJoe Perches void bnad_destroy_rx(struct bnad *bnad, u32 rx_id); 404f844a0eaSJeff Kirsher 405f844a0eaSJeff Kirsher /* Timer start/stop protos */ 40649ca19bdSJoe Perches void bnad_dim_timer_start(struct bnad *bnad); 407f844a0eaSJeff Kirsher 408f844a0eaSJeff Kirsher /* Statistics */ 40949ca19bdSJoe Perches void bnad_netdev_qstats_fill(struct bnad *bnad, 410f844a0eaSJeff Kirsher struct rtnl_link_stats64 *stats); 41149ca19bdSJoe Perches void bnad_netdev_hwstats_fill(struct bnad *bnad, 412f844a0eaSJeff Kirsher struct rtnl_link_stats64 *stats); 413f844a0eaSJeff Kirsher 4147afc5dbdSKrishna Gudipati /* Debugfs */ 4157afc5dbdSKrishna Gudipati void bnad_debugfs_init(struct bnad *bnad); 4167afc5dbdSKrishna Gudipati void bnad_debugfs_uninit(struct bnad *bnad); 4177afc5dbdSKrishna Gudipati 4181aa8b471SBen Hutchings /* MACROS */ 419f844a0eaSJeff Kirsher /* To set & get the stats counters */ 420f844a0eaSJeff Kirsher #define BNAD_UPDATE_CTR(_bnad, _ctr) \ 421f844a0eaSJeff Kirsher (((_bnad)->stats.drv_stats._ctr)++) 422f844a0eaSJeff Kirsher 423f844a0eaSJeff Kirsher #define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr) 424f844a0eaSJeff Kirsher 425f844a0eaSJeff Kirsher #define bnad_enable_rx_irq_unsafe(_ccb) \ 426f844a0eaSJeff Kirsher { \ 427271e8b79SRasesh Mody if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\ 428f844a0eaSJeff Kirsher bna_ib_coalescing_timer_set((_ccb)->i_dbell, \ 429f844a0eaSJeff Kirsher (_ccb)->rx_coalescing_timeo); \ 430f844a0eaSJeff Kirsher bna_ib_ack((_ccb)->i_dbell, 0); \ 431f844a0eaSJeff Kirsher } \ 432f844a0eaSJeff Kirsher } 433f844a0eaSJeff Kirsher 434f844a0eaSJeff Kirsher #endif /* __BNAD_H__ */ 435