1f844a0eaSJeff Kirsher /* 2f844a0eaSJeff Kirsher * Linux network driver for Brocade Converged Network Adapter. 3f844a0eaSJeff Kirsher * 4f844a0eaSJeff Kirsher * This program is free software; you can redistribute it and/or modify it 5f844a0eaSJeff Kirsher * under the terms of the GNU General Public License (GPL) Version 2 as 6f844a0eaSJeff Kirsher * published by the Free Software Foundation 7f844a0eaSJeff Kirsher * 8f844a0eaSJeff Kirsher * This program is distributed in the hope that it will be useful, but 9f844a0eaSJeff Kirsher * WITHOUT ANY WARRANTY; without even the implied warranty of 10f844a0eaSJeff Kirsher * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11f844a0eaSJeff Kirsher * General Public License for more details. 12f844a0eaSJeff Kirsher */ 13f844a0eaSJeff Kirsher /* 14f844a0eaSJeff Kirsher * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 15f844a0eaSJeff Kirsher * All rights reserved 16f844a0eaSJeff Kirsher * www.brocade.com 17f844a0eaSJeff Kirsher */ 18f844a0eaSJeff Kirsher #ifndef __BNAD_H__ 19f844a0eaSJeff Kirsher #define __BNAD_H__ 20f844a0eaSJeff Kirsher 21f844a0eaSJeff Kirsher #include <linux/rtnetlink.h> 22f844a0eaSJeff Kirsher #include <linux/workqueue.h> 23f844a0eaSJeff Kirsher #include <linux/ipv6.h> 24f844a0eaSJeff Kirsher #include <linux/etherdevice.h> 25f844a0eaSJeff Kirsher #include <linux/mutex.h> 26f844a0eaSJeff Kirsher #include <linux/firmware.h> 27f844a0eaSJeff Kirsher #include <linux/if_vlan.h> 28f844a0eaSJeff Kirsher 29f844a0eaSJeff Kirsher /* Fix for IA64 */ 30f844a0eaSJeff Kirsher #include <asm/checksum.h> 31f844a0eaSJeff Kirsher #include <net/ip6_checksum.h> 32f844a0eaSJeff Kirsher 33f844a0eaSJeff Kirsher #include <net/ip.h> 34f844a0eaSJeff Kirsher #include <net/tcp.h> 35f844a0eaSJeff Kirsher 36f844a0eaSJeff Kirsher #include "bna.h" 37f844a0eaSJeff Kirsher 38f844a0eaSJeff Kirsher #define BNAD_TXQ_DEPTH 2048 39f844a0eaSJeff Kirsher #define BNAD_RXQ_DEPTH 2048 40f844a0eaSJeff Kirsher 41772b5235SRasesh Mody #define BNAD_MAX_TX 1 42f844a0eaSJeff Kirsher #define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */ 43f844a0eaSJeff Kirsher #define BNAD_TXQ_NUM 1 44f844a0eaSJeff Kirsher 45772b5235SRasesh Mody #define BNAD_MAX_RX 1 46772b5235SRasesh Mody #define BNAD_MAX_RXP_PER_RX 16 47078086f3SRasesh Mody #define BNAD_MAX_RXQ_PER_RXP 2 48f844a0eaSJeff Kirsher 49f844a0eaSJeff Kirsher /* 50f844a0eaSJeff Kirsher * Control structure pointed to ccb->ctrl, which 51f844a0eaSJeff Kirsher * determines the NAPI / LRO behavior CCB 52f844a0eaSJeff Kirsher * There is 1:1 corres. between ccb & ctrl 53f844a0eaSJeff Kirsher */ 54f844a0eaSJeff Kirsher struct bnad_rx_ctrl { 55f844a0eaSJeff Kirsher struct bna_ccb *ccb; 562be67144SRasesh Mody struct bnad *bnad; 57f844a0eaSJeff Kirsher unsigned long flags; 58f844a0eaSJeff Kirsher struct napi_struct napi; 59271e8b79SRasesh Mody u64 rx_intr_ctr; 60271e8b79SRasesh Mody u64 rx_poll_ctr; 61271e8b79SRasesh Mody u64 rx_schedule; 62271e8b79SRasesh Mody u64 rx_keep_poll; 63271e8b79SRasesh Mody u64 rx_complete; 64f844a0eaSJeff Kirsher }; 65f844a0eaSJeff Kirsher 66f844a0eaSJeff Kirsher #define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC 67f844a0eaSJeff Kirsher 68f844a0eaSJeff Kirsher /* 69f844a0eaSJeff Kirsher * GLOBAL #defines (CONSTANTS) 70f844a0eaSJeff Kirsher */ 71f844a0eaSJeff Kirsher #define BNAD_NAME "bna" 72f844a0eaSJeff Kirsher #define BNAD_NAME_LEN 64 73f844a0eaSJeff Kirsher 7445e98341SRasesh Mody #define BNAD_VERSION "3.2.21.1" 75f844a0eaSJeff Kirsher 76f844a0eaSJeff Kirsher #define BNAD_MAILBOX_MSIX_INDEX 0 77f844a0eaSJeff Kirsher #define BNAD_MAILBOX_MSIX_VECTORS 1 78f844a0eaSJeff Kirsher #define BNAD_INTX_TX_IB_BITMASK 0x1 79f844a0eaSJeff Kirsher #define BNAD_INTX_RX_IB_BITMASK 0x2 80f844a0eaSJeff Kirsher 81f844a0eaSJeff Kirsher #define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */ 82f844a0eaSJeff Kirsher #define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */ 83f844a0eaSJeff Kirsher 84078086f3SRasesh Mody #define BNAD_IOCETH_TIMEOUT 10000 85078086f3SRasesh Mody 865216562aSRasesh Mody #define BNAD_MIN_Q_DEPTH 512 8766f9513aSRasesh Mody #define BNAD_MAX_RXQ_DEPTH 16384 885216562aSRasesh Mody #define BNAD_MAX_TXQ_DEPTH 2048 8941eb5ba4SRasesh Mody 90f844a0eaSJeff Kirsher #define BNAD_JUMBO_MTU 9000 91f844a0eaSJeff Kirsher 92f844a0eaSJeff Kirsher #define BNAD_NETIF_WAKE_THRESHOLD 8 93f844a0eaSJeff Kirsher 94f844a0eaSJeff Kirsher #define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3 95f844a0eaSJeff Kirsher 96f844a0eaSJeff Kirsher /* Bit positions for tcb->flags */ 97f844a0eaSJeff Kirsher #define BNAD_TXQ_FREE_SENT 0 98f844a0eaSJeff Kirsher #define BNAD_TXQ_TX_STARTED 1 99f844a0eaSJeff Kirsher 100f844a0eaSJeff Kirsher /* Bit positions for rcb->flags */ 1015216562aSRasesh Mody #define BNAD_RXQ_STARTED 0 1025216562aSRasesh Mody #define BNAD_RXQ_POST_OK 1 103f844a0eaSJeff Kirsher 104078086f3SRasesh Mody /* Resource limits */ 105078086f3SRasesh Mody #define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx) 106078086f3SRasesh Mody #define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx) 107078086f3SRasesh Mody 108e29aa339SRasesh Mody #define BNAD_FRAME_SIZE(_mtu) \ 109e29aa339SRasesh Mody (ETH_HLEN + VLAN_HLEN + (_mtu) + ETH_FCS_LEN) 110e29aa339SRasesh Mody 111f844a0eaSJeff Kirsher /* 112f844a0eaSJeff Kirsher * DATA STRUCTURES 113f844a0eaSJeff Kirsher */ 114f844a0eaSJeff Kirsher 115f844a0eaSJeff Kirsher /* enums */ 116f844a0eaSJeff Kirsher enum bnad_intr_source { 117f844a0eaSJeff Kirsher BNAD_INTR_TX = 1, 118f844a0eaSJeff Kirsher BNAD_INTR_RX = 2 119f844a0eaSJeff Kirsher }; 120f844a0eaSJeff Kirsher 121f844a0eaSJeff Kirsher enum bnad_link_state { 122f844a0eaSJeff Kirsher BNAD_LS_DOWN = 0, 123f844a0eaSJeff Kirsher BNAD_LS_UP = 1 124f844a0eaSJeff Kirsher }; 125f844a0eaSJeff Kirsher 12672a9730bSKrishna Gudipati struct bnad_iocmd_comp { 12772a9730bSKrishna Gudipati struct bnad *bnad; 12872a9730bSKrishna Gudipati struct completion comp; 12972a9730bSKrishna Gudipati int comp_status; 13072a9730bSKrishna Gudipati }; 13172a9730bSKrishna Gudipati 132f844a0eaSJeff Kirsher struct bnad_completion { 133f844a0eaSJeff Kirsher struct completion ioc_comp; 134f844a0eaSJeff Kirsher struct completion ucast_comp; 135f844a0eaSJeff Kirsher struct completion mcast_comp; 136f844a0eaSJeff Kirsher struct completion tx_comp; 137f844a0eaSJeff Kirsher struct completion rx_comp; 138f844a0eaSJeff Kirsher struct completion stats_comp; 139078086f3SRasesh Mody struct completion enet_comp; 140078086f3SRasesh Mody struct completion mtu_comp; 141f844a0eaSJeff Kirsher 142f844a0eaSJeff Kirsher u8 ioc_comp_status; 143f844a0eaSJeff Kirsher u8 ucast_comp_status; 144f844a0eaSJeff Kirsher u8 mcast_comp_status; 145f844a0eaSJeff Kirsher u8 tx_comp_status; 146f844a0eaSJeff Kirsher u8 rx_comp_status; 147f844a0eaSJeff Kirsher u8 stats_comp_status; 148f844a0eaSJeff Kirsher u8 port_comp_status; 149078086f3SRasesh Mody u8 mtu_comp_status; 150f844a0eaSJeff Kirsher }; 151f844a0eaSJeff Kirsher 152f844a0eaSJeff Kirsher /* Tx Rx Control Stats */ 153f844a0eaSJeff Kirsher struct bnad_drv_stats { 154f844a0eaSJeff Kirsher u64 netif_queue_stop; 155f844a0eaSJeff Kirsher u64 netif_queue_wakeup; 156f844a0eaSJeff Kirsher u64 netif_queue_stopped; 157f844a0eaSJeff Kirsher u64 tso4; 158f844a0eaSJeff Kirsher u64 tso6; 159f844a0eaSJeff Kirsher u64 tso_err; 160f844a0eaSJeff Kirsher u64 tcpcsum_offload; 161f844a0eaSJeff Kirsher u64 udpcsum_offload; 162f844a0eaSJeff Kirsher u64 csum_help; 163271e8b79SRasesh Mody u64 tx_skb_too_short; 164271e8b79SRasesh Mody u64 tx_skb_stopping; 165271e8b79SRasesh Mody u64 tx_skb_max_vectors; 166271e8b79SRasesh Mody u64 tx_skb_mss_too_long; 167271e8b79SRasesh Mody u64 tx_skb_tso_too_short; 168271e8b79SRasesh Mody u64 tx_skb_tso_prepare; 169271e8b79SRasesh Mody u64 tx_skb_non_tso_too_long; 170271e8b79SRasesh Mody u64 tx_skb_tcp_hdr; 171271e8b79SRasesh Mody u64 tx_skb_udp_hdr; 172271e8b79SRasesh Mody u64 tx_skb_csum_err; 173271e8b79SRasesh Mody u64 tx_skb_headlen_too_long; 174271e8b79SRasesh Mody u64 tx_skb_headlen_zero; 175271e8b79SRasesh Mody u64 tx_skb_frag_zero; 176271e8b79SRasesh Mody u64 tx_skb_len_mismatch; 177f844a0eaSJeff Kirsher 178f844a0eaSJeff Kirsher u64 hw_stats_updates; 179f844a0eaSJeff Kirsher u64 netif_rx_dropped; 180f844a0eaSJeff Kirsher 181f844a0eaSJeff Kirsher u64 link_toggle; 182078086f3SRasesh Mody u64 cee_toggle; 183f844a0eaSJeff Kirsher 184f844a0eaSJeff Kirsher u64 rxp_info_alloc_failed; 185f844a0eaSJeff Kirsher u64 mbox_intr_disabled; 186f844a0eaSJeff Kirsher u64 mbox_intr_enabled; 187f844a0eaSJeff Kirsher u64 tx_unmap_q_alloc_failed; 188f844a0eaSJeff Kirsher u64 rx_unmap_q_alloc_failed; 189f844a0eaSJeff Kirsher 190f844a0eaSJeff Kirsher u64 rxbuf_alloc_failed; 191f844a0eaSJeff Kirsher }; 192f844a0eaSJeff Kirsher 193f844a0eaSJeff Kirsher /* Complete driver stats */ 194f844a0eaSJeff Kirsher struct bnad_stats { 195f844a0eaSJeff Kirsher struct bnad_drv_stats drv_stats; 196f844a0eaSJeff Kirsher struct bna_stats *bna_stats; 197f844a0eaSJeff Kirsher }; 198f844a0eaSJeff Kirsher 199f844a0eaSJeff Kirsher /* Tx / Rx Resources */ 200f844a0eaSJeff Kirsher struct bnad_tx_res_info { 201f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_TX_RES_T_MAX]; 202f844a0eaSJeff Kirsher }; 203f844a0eaSJeff Kirsher 204f844a0eaSJeff Kirsher struct bnad_rx_res_info { 205f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_RX_RES_T_MAX]; 206f844a0eaSJeff Kirsher }; 207f844a0eaSJeff Kirsher 208f844a0eaSJeff Kirsher struct bnad_tx_info { 209f844a0eaSJeff Kirsher struct bna_tx *tx; /* 1:1 between tx_info & tx */ 210f844a0eaSJeff Kirsher struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX]; 211078086f3SRasesh Mody u32 tx_id; 21201b54b14SJing Huang struct delayed_work tx_cleanup_work; 213f844a0eaSJeff Kirsher } ____cacheline_aligned; 214f844a0eaSJeff Kirsher 215f844a0eaSJeff Kirsher struct bnad_rx_info { 216f844a0eaSJeff Kirsher struct bna_rx *rx; /* 1:1 between rx_info & rx */ 217f844a0eaSJeff Kirsher 218772b5235SRasesh Mody struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX]; 219078086f3SRasesh Mody u32 rx_id; 22001b54b14SJing Huang struct work_struct rx_cleanup_work; 221f844a0eaSJeff Kirsher } ____cacheline_aligned; 222f844a0eaSJeff Kirsher 2235216562aSRasesh Mody struct bnad_tx_vector { 224f844a0eaSJeff Kirsher DEFINE_DMA_UNMAP_ADDR(dma_addr); 225f844a0eaSJeff Kirsher }; 226f844a0eaSJeff Kirsher 2275216562aSRasesh Mody struct bnad_tx_unmap { 2285216562aSRasesh Mody struct sk_buff *skb; 2295216562aSRasesh Mody u32 nvecs; 2305216562aSRasesh Mody struct bnad_tx_vector vectors[BFI_TX_MAX_VECTORS_PER_WI]; 2315216562aSRasesh Mody }; 2325216562aSRasesh Mody 2335216562aSRasesh Mody struct bnad_rx_vector { 2345216562aSRasesh Mody DEFINE_DMA_UNMAP_ADDR(dma_addr); 2355216562aSRasesh Mody u32 len; 2365216562aSRasesh Mody }; 2375216562aSRasesh Mody 2385216562aSRasesh Mody struct bnad_rx_unmap { 23930f9fc94SRasesh Mody struct page *page; 2405216562aSRasesh Mody struct sk_buff *skb; 2415216562aSRasesh Mody struct bnad_rx_vector vector; 24266f9513aSRasesh Mody u32 page_offset; 243f844a0eaSJeff Kirsher }; 244f844a0eaSJeff Kirsher 24530f9fc94SRasesh Mody enum bnad_rxbuf_type { 24630f9fc94SRasesh Mody BNAD_RXBUF_NONE = 0, 247e29aa339SRasesh Mody BNAD_RXBUF_SK_BUFF = 1, 24830f9fc94SRasesh Mody BNAD_RXBUF_PAGE = 2, 249e29aa339SRasesh Mody BNAD_RXBUF_MULTI_BUFF = 3 25030f9fc94SRasesh Mody }; 25130f9fc94SRasesh Mody 252e29aa339SRasesh Mody #define BNAD_RXBUF_IS_SK_BUFF(_type) ((_type) == BNAD_RXBUF_SK_BUFF) 253e29aa339SRasesh Mody #define BNAD_RXBUF_IS_MULTI_BUFF(_type) ((_type) == BNAD_RXBUF_MULTI_BUFF) 25430f9fc94SRasesh Mody 25530f9fc94SRasesh Mody struct bnad_rx_unmap_q { 25630f9fc94SRasesh Mody int reuse_pi; 25730f9fc94SRasesh Mody int alloc_order; 25830f9fc94SRasesh Mody u32 map_size; 25930f9fc94SRasesh Mody enum bnad_rxbuf_type type; 26066f9513aSRasesh Mody struct bnad_rx_unmap unmap[0] ____cacheline_aligned; 26130f9fc94SRasesh Mody }; 26230f9fc94SRasesh Mody 263e29aa339SRasesh Mody #define BNAD_PCI_DEV_IS_CAT2(_bnad) \ 264e29aa339SRasesh Mody ((_bnad)->pcidev->device == BFA_PCI_DEVICE_ID_CT2) 265e29aa339SRasesh Mody 266f844a0eaSJeff Kirsher /* Bit mask values for bnad->cfg_flags */ 267f844a0eaSJeff Kirsher #define BNAD_CF_DIM_ENABLED 0x01 /* DIM */ 268f844a0eaSJeff Kirsher #define BNAD_CF_PROMISC 0x02 269f844a0eaSJeff Kirsher #define BNAD_CF_ALLMULTI 0x04 270fe1624cfSRasesh Mody #define BNAD_CF_DEFAULT 0x08 271fe1624cfSRasesh Mody #define BNAD_CF_MSIX 0x10 /* If in MSIx mode */ 272f844a0eaSJeff Kirsher 273f844a0eaSJeff Kirsher /* Defines for run_flags bit-mask */ 274f844a0eaSJeff Kirsher /* Set, tested & cleared using xxx_bit() functions */ 275f844a0eaSJeff Kirsher /* Values indicated bit positions */ 276078086f3SRasesh Mody #define BNAD_RF_CEE_RUNNING 0 277078086f3SRasesh Mody #define BNAD_RF_MTU_SET 1 278f844a0eaSJeff Kirsher #define BNAD_RF_MBOX_IRQ_DISABLED 2 279078086f3SRasesh Mody #define BNAD_RF_NETDEV_REGISTERED 3 280f844a0eaSJeff Kirsher #define BNAD_RF_DIM_TIMER_RUNNING 4 281f844a0eaSJeff Kirsher #define BNAD_RF_STATS_TIMER_RUNNING 5 282078086f3SRasesh Mody #define BNAD_RF_TX_PRIO_SET 6 283078086f3SRasesh Mody 284f844a0eaSJeff Kirsher struct bnad { 285f844a0eaSJeff Kirsher struct net_device *netdev; 28672a9730bSKrishna Gudipati u32 id; 28772a9730bSKrishna Gudipati struct list_head list_entry; 288f844a0eaSJeff Kirsher 289f844a0eaSJeff Kirsher /* Data path */ 290772b5235SRasesh Mody struct bnad_tx_info tx_info[BNAD_MAX_TX]; 291772b5235SRasesh Mody struct bnad_rx_info rx_info[BNAD_MAX_RX]; 292f844a0eaSJeff Kirsher 293f844a0eaSJeff Kirsher unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 294f844a0eaSJeff Kirsher /* 295f844a0eaSJeff Kirsher * These q numbers are global only because 296f844a0eaSJeff Kirsher * they are used to calculate MSIx vectors. 297f844a0eaSJeff Kirsher * Actually the exact # of queues are per Tx/Rx 298f844a0eaSJeff Kirsher * object. 299f844a0eaSJeff Kirsher */ 300f844a0eaSJeff Kirsher u32 num_tx; 301f844a0eaSJeff Kirsher u32 num_rx; 302f844a0eaSJeff Kirsher u32 num_txq_per_tx; 303f844a0eaSJeff Kirsher u32 num_rxp_per_rx; 304f844a0eaSJeff Kirsher 305f844a0eaSJeff Kirsher u32 txq_depth; 306f844a0eaSJeff Kirsher u32 rxq_depth; 307f844a0eaSJeff Kirsher 308f844a0eaSJeff Kirsher u8 tx_coalescing_timeo; 309f844a0eaSJeff Kirsher u8 rx_coalescing_timeo; 310f844a0eaSJeff Kirsher 3115e46631fSRasesh Mody struct bna_rx_config rx_config[BNAD_MAX_RX] ____cacheline_aligned; 3125e46631fSRasesh Mody struct bna_tx_config tx_config[BNAD_MAX_TX] ____cacheline_aligned; 313f844a0eaSJeff Kirsher 314f844a0eaSJeff Kirsher void __iomem *bar0; /* BAR0 address */ 315f844a0eaSJeff Kirsher 316f844a0eaSJeff Kirsher struct bna bna; 317f844a0eaSJeff Kirsher 318f844a0eaSJeff Kirsher u32 cfg_flags; 319f844a0eaSJeff Kirsher unsigned long run_flags; 320f844a0eaSJeff Kirsher 321f844a0eaSJeff Kirsher struct pci_dev *pcidev; 322f844a0eaSJeff Kirsher u64 mmio_start; 323f844a0eaSJeff Kirsher u64 mmio_len; 324f844a0eaSJeff Kirsher 325f844a0eaSJeff Kirsher u32 msix_num; 326f844a0eaSJeff Kirsher struct msix_entry *msix_table; 327f844a0eaSJeff Kirsher 328f844a0eaSJeff Kirsher struct mutex conf_mutex; 329f844a0eaSJeff Kirsher spinlock_t bna_lock ____cacheline_aligned; 330f844a0eaSJeff Kirsher 331f844a0eaSJeff Kirsher /* Timers */ 332f844a0eaSJeff Kirsher struct timer_list ioc_timer; 333f844a0eaSJeff Kirsher struct timer_list dim_timer; 334f844a0eaSJeff Kirsher struct timer_list stats_timer; 335f844a0eaSJeff Kirsher 336f844a0eaSJeff Kirsher /* Control path resources, memory & irq */ 337f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_RES_T_MAX]; 338078086f3SRasesh Mody struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX]; 339772b5235SRasesh Mody struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX]; 340772b5235SRasesh Mody struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX]; 341f844a0eaSJeff Kirsher 342f844a0eaSJeff Kirsher struct bnad_completion bnad_completions; 343f844a0eaSJeff Kirsher 344f844a0eaSJeff Kirsher /* Burnt in MAC address */ 345f844a0eaSJeff Kirsher mac_t perm_addr; 346f844a0eaSJeff Kirsher 34701b54b14SJing Huang struct workqueue_struct *work_q; 348f844a0eaSJeff Kirsher 349f844a0eaSJeff Kirsher /* Statistics */ 350f844a0eaSJeff Kirsher struct bnad_stats stats; 351f844a0eaSJeff Kirsher 352f844a0eaSJeff Kirsher struct bnad_diag *diag; 353f844a0eaSJeff Kirsher 354f844a0eaSJeff Kirsher char adapter_name[BNAD_NAME_LEN]; 355f844a0eaSJeff Kirsher char port_name[BNAD_NAME_LEN]; 356f844a0eaSJeff Kirsher char mbox_irq_name[BNAD_NAME_LEN]; 35701b54b14SJing Huang char wq_name[BNAD_NAME_LEN]; 3587afc5dbdSKrishna Gudipati 3597afc5dbdSKrishna Gudipati /* debugfs specific data */ 3607afc5dbdSKrishna Gudipati char *regdata; 3617afc5dbdSKrishna Gudipati u32 reglen; 3627afc5dbdSKrishna Gudipati struct dentry *bnad_dentry_files[5]; 3637afc5dbdSKrishna Gudipati struct dentry *port_debugfs_root; 3647afc5dbdSKrishna Gudipati }; 3657afc5dbdSKrishna Gudipati 3667afc5dbdSKrishna Gudipati struct bnad_drvinfo { 3677afc5dbdSKrishna Gudipati struct bfa_ioc_attr ioc_attr; 3687afc5dbdSKrishna Gudipati struct bfa_cee_attr cee_attr; 3697afc5dbdSKrishna Gudipati struct bfa_flash_attr flash_attr; 3707afc5dbdSKrishna Gudipati u32 cee_status; 3717afc5dbdSKrishna Gudipati u32 flash_status; 372f844a0eaSJeff Kirsher }; 373f844a0eaSJeff Kirsher 374f844a0eaSJeff Kirsher /* 375f844a0eaSJeff Kirsher * EXTERN VARIABLES 376f844a0eaSJeff Kirsher */ 377e1e0918fSstephen hemminger extern const struct firmware *bfi_fw; 378f844a0eaSJeff Kirsher 379f844a0eaSJeff Kirsher /* 380f844a0eaSJeff Kirsher * EXTERN PROTOTYPES 381f844a0eaSJeff Kirsher */ 38249ca19bdSJoe Perches u32 *cna_get_firmware_buf(struct pci_dev *pdev); 383f844a0eaSJeff Kirsher /* Netdev entry point prototypes */ 38449ca19bdSJoe Perches void bnad_set_rx_mode(struct net_device *netdev); 38549ca19bdSJoe Perches struct net_device_stats *bnad_get_netdev_stats(struct net_device *netdev); 38649ca19bdSJoe Perches int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr); 38749ca19bdSJoe Perches int bnad_enable_default_bcast(struct bnad *bnad); 38849ca19bdSJoe Perches void bnad_restore_vlans(struct bnad *bnad, u32 rx_id); 38949ca19bdSJoe Perches void bnad_set_ethtool_ops(struct net_device *netdev); 39049ca19bdSJoe Perches void bnad_cb_completion(void *arg, enum bfa_status status); 391f844a0eaSJeff Kirsher 392f844a0eaSJeff Kirsher /* Configuration & setup */ 39349ca19bdSJoe Perches void bnad_tx_coalescing_timeo_set(struct bnad *bnad); 39449ca19bdSJoe Perches void bnad_rx_coalescing_timeo_set(struct bnad *bnad); 395f844a0eaSJeff Kirsher 39649ca19bdSJoe Perches int bnad_setup_rx(struct bnad *bnad, u32 rx_id); 39749ca19bdSJoe Perches int bnad_setup_tx(struct bnad *bnad, u32 tx_id); 39849ca19bdSJoe Perches void bnad_destroy_tx(struct bnad *bnad, u32 tx_id); 39949ca19bdSJoe Perches void bnad_destroy_rx(struct bnad *bnad, u32 rx_id); 400f844a0eaSJeff Kirsher 401f844a0eaSJeff Kirsher /* Timer start/stop protos */ 40249ca19bdSJoe Perches void bnad_dim_timer_start(struct bnad *bnad); 403f844a0eaSJeff Kirsher 404f844a0eaSJeff Kirsher /* Statistics */ 40549ca19bdSJoe Perches void bnad_netdev_qstats_fill(struct bnad *bnad, 406f844a0eaSJeff Kirsher struct rtnl_link_stats64 *stats); 40749ca19bdSJoe Perches void bnad_netdev_hwstats_fill(struct bnad *bnad, 408f844a0eaSJeff Kirsher struct rtnl_link_stats64 *stats); 409f844a0eaSJeff Kirsher 4107afc5dbdSKrishna Gudipati /* Debugfs */ 4117afc5dbdSKrishna Gudipati void bnad_debugfs_init(struct bnad *bnad); 4127afc5dbdSKrishna Gudipati void bnad_debugfs_uninit(struct bnad *bnad); 4137afc5dbdSKrishna Gudipati 4141aa8b471SBen Hutchings /* MACROS */ 415f844a0eaSJeff Kirsher /* To set & get the stats counters */ 416f844a0eaSJeff Kirsher #define BNAD_UPDATE_CTR(_bnad, _ctr) \ 417f844a0eaSJeff Kirsher (((_bnad)->stats.drv_stats._ctr)++) 418f844a0eaSJeff Kirsher 419f844a0eaSJeff Kirsher #define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr) 420f844a0eaSJeff Kirsher 421f844a0eaSJeff Kirsher #define bnad_enable_rx_irq_unsafe(_ccb) \ 422f844a0eaSJeff Kirsher { \ 423271e8b79SRasesh Mody if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\ 424f844a0eaSJeff Kirsher bna_ib_coalescing_timer_set((_ccb)->i_dbell, \ 425f844a0eaSJeff Kirsher (_ccb)->rx_coalescing_timeo); \ 426f844a0eaSJeff Kirsher bna_ib_ack((_ccb)->i_dbell, 0); \ 427f844a0eaSJeff Kirsher } \ 428f844a0eaSJeff Kirsher } 429f844a0eaSJeff Kirsher 430f844a0eaSJeff Kirsher #endif /* __BNAD_H__ */ 431