1f844a0eaSJeff Kirsher /* 2f844a0eaSJeff Kirsher * Linux network driver for Brocade Converged Network Adapter. 3f844a0eaSJeff Kirsher * 4f844a0eaSJeff Kirsher * This program is free software; you can redistribute it and/or modify it 5f844a0eaSJeff Kirsher * under the terms of the GNU General Public License (GPL) Version 2 as 6f844a0eaSJeff Kirsher * published by the Free Software Foundation 7f844a0eaSJeff Kirsher * 8f844a0eaSJeff Kirsher * This program is distributed in the hope that it will be useful, but 9f844a0eaSJeff Kirsher * WITHOUT ANY WARRANTY; without even the implied warranty of 10f844a0eaSJeff Kirsher * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11f844a0eaSJeff Kirsher * General Public License for more details. 12f844a0eaSJeff Kirsher */ 13f844a0eaSJeff Kirsher /* 14f844a0eaSJeff Kirsher * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 15f844a0eaSJeff Kirsher * All rights reserved 16f844a0eaSJeff Kirsher * www.brocade.com 17f844a0eaSJeff Kirsher */ 18f844a0eaSJeff Kirsher #ifndef __BNAD_H__ 19f844a0eaSJeff Kirsher #define __BNAD_H__ 20f844a0eaSJeff Kirsher 21f844a0eaSJeff Kirsher #include <linux/rtnetlink.h> 22f844a0eaSJeff Kirsher #include <linux/workqueue.h> 23f844a0eaSJeff Kirsher #include <linux/ipv6.h> 24f844a0eaSJeff Kirsher #include <linux/etherdevice.h> 25f844a0eaSJeff Kirsher #include <linux/mutex.h> 26f844a0eaSJeff Kirsher #include <linux/firmware.h> 27f844a0eaSJeff Kirsher #include <linux/if_vlan.h> 28f844a0eaSJeff Kirsher 29f844a0eaSJeff Kirsher /* Fix for IA64 */ 30f844a0eaSJeff Kirsher #include <asm/checksum.h> 31f844a0eaSJeff Kirsher #include <net/ip6_checksum.h> 32f844a0eaSJeff Kirsher 33f844a0eaSJeff Kirsher #include <net/ip.h> 34f844a0eaSJeff Kirsher #include <net/tcp.h> 35f844a0eaSJeff Kirsher 36f844a0eaSJeff Kirsher #include "bna.h" 37f844a0eaSJeff Kirsher 38f844a0eaSJeff Kirsher #define BNAD_TXQ_DEPTH 2048 39f844a0eaSJeff Kirsher #define BNAD_RXQ_DEPTH 2048 40f844a0eaSJeff Kirsher 41772b5235SRasesh Mody #define BNAD_MAX_TX 1 42f844a0eaSJeff Kirsher #define BNAD_MAX_TXQ_PER_TX 8 /* 8 priority queues */ 43f844a0eaSJeff Kirsher #define BNAD_TXQ_NUM 1 44f844a0eaSJeff Kirsher 45772b5235SRasesh Mody #define BNAD_MAX_RX 1 46772b5235SRasesh Mody #define BNAD_MAX_RXP_PER_RX 16 47078086f3SRasesh Mody #define BNAD_MAX_RXQ_PER_RXP 2 48f844a0eaSJeff Kirsher 49f844a0eaSJeff Kirsher /* 50f844a0eaSJeff Kirsher * Control structure pointed to ccb->ctrl, which 51f844a0eaSJeff Kirsher * determines the NAPI / LRO behavior CCB 52f844a0eaSJeff Kirsher * There is 1:1 corres. between ccb & ctrl 53f844a0eaSJeff Kirsher */ 54f844a0eaSJeff Kirsher struct bnad_rx_ctrl { 55f844a0eaSJeff Kirsher struct bna_ccb *ccb; 562be67144SRasesh Mody struct bnad *bnad; 57f844a0eaSJeff Kirsher unsigned long flags; 58f844a0eaSJeff Kirsher struct napi_struct napi; 59271e8b79SRasesh Mody u64 rx_intr_ctr; 60271e8b79SRasesh Mody u64 rx_poll_ctr; 61271e8b79SRasesh Mody u64 rx_schedule; 62271e8b79SRasesh Mody u64 rx_keep_poll; 63271e8b79SRasesh Mody u64 rx_complete; 64f844a0eaSJeff Kirsher }; 65f844a0eaSJeff Kirsher 66f844a0eaSJeff Kirsher #define BNAD_RXMODE_PROMISC_DEFAULT BNA_RXMODE_PROMISC 67f844a0eaSJeff Kirsher 68f844a0eaSJeff Kirsher /* 69f844a0eaSJeff Kirsher * GLOBAL #defines (CONSTANTS) 70f844a0eaSJeff Kirsher */ 71f844a0eaSJeff Kirsher #define BNAD_NAME "bna" 72f844a0eaSJeff Kirsher #define BNAD_NAME_LEN 64 73f844a0eaSJeff Kirsher 749450f750SJing Huang #define BNAD_VERSION "3.0.23.0" 75f844a0eaSJeff Kirsher 76f844a0eaSJeff Kirsher #define BNAD_MAILBOX_MSIX_INDEX 0 77f844a0eaSJeff Kirsher #define BNAD_MAILBOX_MSIX_VECTORS 1 78f844a0eaSJeff Kirsher #define BNAD_INTX_TX_IB_BITMASK 0x1 79f844a0eaSJeff Kirsher #define BNAD_INTX_RX_IB_BITMASK 0x2 80f844a0eaSJeff Kirsher 81f844a0eaSJeff Kirsher #define BNAD_STATS_TIMER_FREQ 1000 /* in msecs */ 82f844a0eaSJeff Kirsher #define BNAD_DIM_TIMER_FREQ 1000 /* in msecs */ 83f844a0eaSJeff Kirsher 84078086f3SRasesh Mody #define BNAD_IOCETH_TIMEOUT 10000 85078086f3SRasesh Mody 86f844a0eaSJeff Kirsher #define BNAD_MAX_Q_DEPTH 0x10000 87f844a0eaSJeff Kirsher #define BNAD_MIN_Q_DEPTH 0x200 88f844a0eaSJeff Kirsher 8941eb5ba4SRasesh Mody #define BNAD_MAX_RXQ_DEPTH (BNAD_MAX_Q_DEPTH / bnad_rxqs_per_cq) 9041eb5ba4SRasesh Mody /* keeping MAX TX and RX Q depth equal */ 9141eb5ba4SRasesh Mody #define BNAD_MAX_TXQ_DEPTH BNAD_MAX_RXQ_DEPTH 9241eb5ba4SRasesh Mody 93f844a0eaSJeff Kirsher #define BNAD_JUMBO_MTU 9000 94f844a0eaSJeff Kirsher 95f844a0eaSJeff Kirsher #define BNAD_NETIF_WAKE_THRESHOLD 8 96f844a0eaSJeff Kirsher 97f844a0eaSJeff Kirsher #define BNAD_RXQ_REFILL_THRESHOLD_SHIFT 3 98f844a0eaSJeff Kirsher 99f844a0eaSJeff Kirsher /* Bit positions for tcb->flags */ 100f844a0eaSJeff Kirsher #define BNAD_TXQ_FREE_SENT 0 101f844a0eaSJeff Kirsher #define BNAD_TXQ_TX_STARTED 1 102f844a0eaSJeff Kirsher 103f844a0eaSJeff Kirsher /* Bit positions for rcb->flags */ 104f844a0eaSJeff Kirsher #define BNAD_RXQ_REFILL 0 105f844a0eaSJeff Kirsher #define BNAD_RXQ_STARTED 1 1065bcf6ac0SRasesh Mody #define BNAD_RXQ_POST_OK 2 107f844a0eaSJeff Kirsher 108078086f3SRasesh Mody /* Resource limits */ 109078086f3SRasesh Mody #define BNAD_NUM_TXQ (bnad->num_tx * bnad->num_txq_per_tx) 110078086f3SRasesh Mody #define BNAD_NUM_RXP (bnad->num_rx * bnad->num_rxp_per_rx) 111078086f3SRasesh Mody 112f844a0eaSJeff Kirsher /* 113f844a0eaSJeff Kirsher * DATA STRUCTURES 114f844a0eaSJeff Kirsher */ 115f844a0eaSJeff Kirsher 116f844a0eaSJeff Kirsher /* enums */ 117f844a0eaSJeff Kirsher enum bnad_intr_source { 118f844a0eaSJeff Kirsher BNAD_INTR_TX = 1, 119f844a0eaSJeff Kirsher BNAD_INTR_RX = 2 120f844a0eaSJeff Kirsher }; 121f844a0eaSJeff Kirsher 122f844a0eaSJeff Kirsher enum bnad_link_state { 123f844a0eaSJeff Kirsher BNAD_LS_DOWN = 0, 124f844a0eaSJeff Kirsher BNAD_LS_UP = 1 125f844a0eaSJeff Kirsher }; 126f844a0eaSJeff Kirsher 12772a9730bSKrishna Gudipati struct bnad_iocmd_comp { 12872a9730bSKrishna Gudipati struct bnad *bnad; 12972a9730bSKrishna Gudipati struct completion comp; 13072a9730bSKrishna Gudipati int comp_status; 13172a9730bSKrishna Gudipati }; 13272a9730bSKrishna Gudipati 133f844a0eaSJeff Kirsher struct bnad_completion { 134f844a0eaSJeff Kirsher struct completion ioc_comp; 135f844a0eaSJeff Kirsher struct completion ucast_comp; 136f844a0eaSJeff Kirsher struct completion mcast_comp; 137f844a0eaSJeff Kirsher struct completion tx_comp; 138f844a0eaSJeff Kirsher struct completion rx_comp; 139f844a0eaSJeff Kirsher struct completion stats_comp; 140078086f3SRasesh Mody struct completion enet_comp; 141078086f3SRasesh Mody struct completion mtu_comp; 142f844a0eaSJeff Kirsher 143f844a0eaSJeff Kirsher u8 ioc_comp_status; 144f844a0eaSJeff Kirsher u8 ucast_comp_status; 145f844a0eaSJeff Kirsher u8 mcast_comp_status; 146f844a0eaSJeff Kirsher u8 tx_comp_status; 147f844a0eaSJeff Kirsher u8 rx_comp_status; 148f844a0eaSJeff Kirsher u8 stats_comp_status; 149f844a0eaSJeff Kirsher u8 port_comp_status; 150078086f3SRasesh Mody u8 mtu_comp_status; 151f844a0eaSJeff Kirsher }; 152f844a0eaSJeff Kirsher 153f844a0eaSJeff Kirsher /* Tx Rx Control Stats */ 154f844a0eaSJeff Kirsher struct bnad_drv_stats { 155f844a0eaSJeff Kirsher u64 netif_queue_stop; 156f844a0eaSJeff Kirsher u64 netif_queue_wakeup; 157f844a0eaSJeff Kirsher u64 netif_queue_stopped; 158f844a0eaSJeff Kirsher u64 tso4; 159f844a0eaSJeff Kirsher u64 tso6; 160f844a0eaSJeff Kirsher u64 tso_err; 161f844a0eaSJeff Kirsher u64 tcpcsum_offload; 162f844a0eaSJeff Kirsher u64 udpcsum_offload; 163f844a0eaSJeff Kirsher u64 csum_help; 164271e8b79SRasesh Mody u64 tx_skb_too_short; 165271e8b79SRasesh Mody u64 tx_skb_stopping; 166271e8b79SRasesh Mody u64 tx_skb_max_vectors; 167271e8b79SRasesh Mody u64 tx_skb_mss_too_long; 168271e8b79SRasesh Mody u64 tx_skb_tso_too_short; 169271e8b79SRasesh Mody u64 tx_skb_tso_prepare; 170271e8b79SRasesh Mody u64 tx_skb_non_tso_too_long; 171271e8b79SRasesh Mody u64 tx_skb_tcp_hdr; 172271e8b79SRasesh Mody u64 tx_skb_udp_hdr; 173271e8b79SRasesh Mody u64 tx_skb_csum_err; 174271e8b79SRasesh Mody u64 tx_skb_headlen_too_long; 175271e8b79SRasesh Mody u64 tx_skb_headlen_zero; 176271e8b79SRasesh Mody u64 tx_skb_frag_zero; 177271e8b79SRasesh Mody u64 tx_skb_len_mismatch; 178f844a0eaSJeff Kirsher 179f844a0eaSJeff Kirsher u64 hw_stats_updates; 180f844a0eaSJeff Kirsher u64 netif_rx_dropped; 181f844a0eaSJeff Kirsher 182f844a0eaSJeff Kirsher u64 link_toggle; 183078086f3SRasesh Mody u64 cee_toggle; 184f844a0eaSJeff Kirsher 185f844a0eaSJeff Kirsher u64 rxp_info_alloc_failed; 186f844a0eaSJeff Kirsher u64 mbox_intr_disabled; 187f844a0eaSJeff Kirsher u64 mbox_intr_enabled; 188f844a0eaSJeff Kirsher u64 tx_unmap_q_alloc_failed; 189f844a0eaSJeff Kirsher u64 rx_unmap_q_alloc_failed; 190f844a0eaSJeff Kirsher 191f844a0eaSJeff Kirsher u64 rxbuf_alloc_failed; 192f844a0eaSJeff Kirsher }; 193f844a0eaSJeff Kirsher 194f844a0eaSJeff Kirsher /* Complete driver stats */ 195f844a0eaSJeff Kirsher struct bnad_stats { 196f844a0eaSJeff Kirsher struct bnad_drv_stats drv_stats; 197f844a0eaSJeff Kirsher struct bna_stats *bna_stats; 198f844a0eaSJeff Kirsher }; 199f844a0eaSJeff Kirsher 200f844a0eaSJeff Kirsher /* Tx / Rx Resources */ 201f844a0eaSJeff Kirsher struct bnad_tx_res_info { 202f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_TX_RES_T_MAX]; 203f844a0eaSJeff Kirsher }; 204f844a0eaSJeff Kirsher 205f844a0eaSJeff Kirsher struct bnad_rx_res_info { 206f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_RX_RES_T_MAX]; 207f844a0eaSJeff Kirsher }; 208f844a0eaSJeff Kirsher 209f844a0eaSJeff Kirsher struct bnad_tx_info { 210f844a0eaSJeff Kirsher struct bna_tx *tx; /* 1:1 between tx_info & tx */ 211f844a0eaSJeff Kirsher struct bna_tcb *tcb[BNAD_MAX_TXQ_PER_TX]; 212078086f3SRasesh Mody u32 tx_id; 21301b54b14SJing Huang struct delayed_work tx_cleanup_work; 214f844a0eaSJeff Kirsher } ____cacheline_aligned; 215f844a0eaSJeff Kirsher 216f844a0eaSJeff Kirsher struct bnad_rx_info { 217f844a0eaSJeff Kirsher struct bna_rx *rx; /* 1:1 between rx_info & rx */ 218f844a0eaSJeff Kirsher 219772b5235SRasesh Mody struct bnad_rx_ctrl rx_ctrl[BNAD_MAX_RXP_PER_RX]; 220078086f3SRasesh Mody u32 rx_id; 22101b54b14SJing Huang struct work_struct rx_cleanup_work; 222f844a0eaSJeff Kirsher } ____cacheline_aligned; 223f844a0eaSJeff Kirsher 224f844a0eaSJeff Kirsher /* Unmap queues for Tx / Rx cleanup */ 225f844a0eaSJeff Kirsher struct bnad_skb_unmap { 226f844a0eaSJeff Kirsher struct sk_buff *skb; 227f844a0eaSJeff Kirsher DEFINE_DMA_UNMAP_ADDR(dma_addr); 228f844a0eaSJeff Kirsher }; 229f844a0eaSJeff Kirsher 230f844a0eaSJeff Kirsher struct bnad_unmap_q { 231f844a0eaSJeff Kirsher u32 producer_index; 232f844a0eaSJeff Kirsher u32 consumer_index; 233f844a0eaSJeff Kirsher u32 q_depth; 234f844a0eaSJeff Kirsher /* This should be the last one */ 235f844a0eaSJeff Kirsher struct bnad_skb_unmap unmap_array[1]; 236f844a0eaSJeff Kirsher }; 237f844a0eaSJeff Kirsher 238f844a0eaSJeff Kirsher /* Bit mask values for bnad->cfg_flags */ 239f844a0eaSJeff Kirsher #define BNAD_CF_DIM_ENABLED 0x01 /* DIM */ 240f844a0eaSJeff Kirsher #define BNAD_CF_PROMISC 0x02 241f844a0eaSJeff Kirsher #define BNAD_CF_ALLMULTI 0x04 242f844a0eaSJeff Kirsher #define BNAD_CF_MSIX 0x08 /* If in MSIx mode */ 243f844a0eaSJeff Kirsher 244f844a0eaSJeff Kirsher /* Defines for run_flags bit-mask */ 245f844a0eaSJeff Kirsher /* Set, tested & cleared using xxx_bit() functions */ 246f844a0eaSJeff Kirsher /* Values indicated bit positions */ 247078086f3SRasesh Mody #define BNAD_RF_CEE_RUNNING 0 248078086f3SRasesh Mody #define BNAD_RF_MTU_SET 1 249f844a0eaSJeff Kirsher #define BNAD_RF_MBOX_IRQ_DISABLED 2 250078086f3SRasesh Mody #define BNAD_RF_NETDEV_REGISTERED 3 251f844a0eaSJeff Kirsher #define BNAD_RF_DIM_TIMER_RUNNING 4 252f844a0eaSJeff Kirsher #define BNAD_RF_STATS_TIMER_RUNNING 5 253078086f3SRasesh Mody #define BNAD_RF_TX_PRIO_SET 6 254078086f3SRasesh Mody 255078086f3SRasesh Mody 256078086f3SRasesh Mody /* Define for Fast Path flags */ 257078086f3SRasesh Mody /* Defined as bit positions */ 258078086f3SRasesh Mody #define BNAD_FP_IN_RX_PATH 0 259f844a0eaSJeff Kirsher 260f844a0eaSJeff Kirsher struct bnad { 261f844a0eaSJeff Kirsher struct net_device *netdev; 26272a9730bSKrishna Gudipati u32 id; 26372a9730bSKrishna Gudipati struct list_head list_entry; 264f844a0eaSJeff Kirsher 265f844a0eaSJeff Kirsher /* Data path */ 266772b5235SRasesh Mody struct bnad_tx_info tx_info[BNAD_MAX_TX]; 267772b5235SRasesh Mody struct bnad_rx_info rx_info[BNAD_MAX_RX]; 268f844a0eaSJeff Kirsher 269f844a0eaSJeff Kirsher unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 270f844a0eaSJeff Kirsher /* 271f844a0eaSJeff Kirsher * These q numbers are global only because 272f844a0eaSJeff Kirsher * they are used to calculate MSIx vectors. 273f844a0eaSJeff Kirsher * Actually the exact # of queues are per Tx/Rx 274f844a0eaSJeff Kirsher * object. 275f844a0eaSJeff Kirsher */ 276f844a0eaSJeff Kirsher u32 num_tx; 277f844a0eaSJeff Kirsher u32 num_rx; 278f844a0eaSJeff Kirsher u32 num_txq_per_tx; 279f844a0eaSJeff Kirsher u32 num_rxp_per_rx; 280f844a0eaSJeff Kirsher 281f844a0eaSJeff Kirsher u32 txq_depth; 282f844a0eaSJeff Kirsher u32 rxq_depth; 283f844a0eaSJeff Kirsher 284f844a0eaSJeff Kirsher u8 tx_coalescing_timeo; 285f844a0eaSJeff Kirsher u8 rx_coalescing_timeo; 286f844a0eaSJeff Kirsher 287772b5235SRasesh Mody struct bna_rx_config rx_config[BNAD_MAX_RX]; 288772b5235SRasesh Mody struct bna_tx_config tx_config[BNAD_MAX_TX]; 289f844a0eaSJeff Kirsher 290f844a0eaSJeff Kirsher void __iomem *bar0; /* BAR0 address */ 291f844a0eaSJeff Kirsher 292f844a0eaSJeff Kirsher struct bna bna; 293f844a0eaSJeff Kirsher 294f844a0eaSJeff Kirsher u32 cfg_flags; 295f844a0eaSJeff Kirsher unsigned long run_flags; 296f844a0eaSJeff Kirsher 297f844a0eaSJeff Kirsher struct pci_dev *pcidev; 298f844a0eaSJeff Kirsher u64 mmio_start; 299f844a0eaSJeff Kirsher u64 mmio_len; 300f844a0eaSJeff Kirsher 301f844a0eaSJeff Kirsher u32 msix_num; 302f844a0eaSJeff Kirsher struct msix_entry *msix_table; 303f844a0eaSJeff Kirsher 304f844a0eaSJeff Kirsher struct mutex conf_mutex; 305f844a0eaSJeff Kirsher spinlock_t bna_lock ____cacheline_aligned; 306f844a0eaSJeff Kirsher 307f844a0eaSJeff Kirsher /* Timers */ 308f844a0eaSJeff Kirsher struct timer_list ioc_timer; 309f844a0eaSJeff Kirsher struct timer_list dim_timer; 310f844a0eaSJeff Kirsher struct timer_list stats_timer; 311f844a0eaSJeff Kirsher 312f844a0eaSJeff Kirsher /* Control path resources, memory & irq */ 313f844a0eaSJeff Kirsher struct bna_res_info res_info[BNA_RES_T_MAX]; 314078086f3SRasesh Mody struct bna_res_info mod_res_info[BNA_MOD_RES_T_MAX]; 315772b5235SRasesh Mody struct bnad_tx_res_info tx_res_info[BNAD_MAX_TX]; 316772b5235SRasesh Mody struct bnad_rx_res_info rx_res_info[BNAD_MAX_RX]; 317f844a0eaSJeff Kirsher 318f844a0eaSJeff Kirsher struct bnad_completion bnad_completions; 319f844a0eaSJeff Kirsher 320f844a0eaSJeff Kirsher /* Burnt in MAC address */ 321f844a0eaSJeff Kirsher mac_t perm_addr; 322f844a0eaSJeff Kirsher 32301b54b14SJing Huang struct workqueue_struct *work_q; 324f844a0eaSJeff Kirsher 325f844a0eaSJeff Kirsher /* Statistics */ 326f844a0eaSJeff Kirsher struct bnad_stats stats; 327f844a0eaSJeff Kirsher 328f844a0eaSJeff Kirsher struct bnad_diag *diag; 329f844a0eaSJeff Kirsher 330f844a0eaSJeff Kirsher char adapter_name[BNAD_NAME_LEN]; 331f844a0eaSJeff Kirsher char port_name[BNAD_NAME_LEN]; 332f844a0eaSJeff Kirsher char mbox_irq_name[BNAD_NAME_LEN]; 33301b54b14SJing Huang char wq_name[BNAD_NAME_LEN]; 3347afc5dbdSKrishna Gudipati 3357afc5dbdSKrishna Gudipati /* debugfs specific data */ 3367afc5dbdSKrishna Gudipati char *regdata; 3377afc5dbdSKrishna Gudipati u32 reglen; 3387afc5dbdSKrishna Gudipati struct dentry *bnad_dentry_files[5]; 3397afc5dbdSKrishna Gudipati struct dentry *port_debugfs_root; 3407afc5dbdSKrishna Gudipati }; 3417afc5dbdSKrishna Gudipati 3427afc5dbdSKrishna Gudipati struct bnad_drvinfo { 3437afc5dbdSKrishna Gudipati struct bfa_ioc_attr ioc_attr; 3447afc5dbdSKrishna Gudipati struct bfa_cee_attr cee_attr; 3457afc5dbdSKrishna Gudipati struct bfa_flash_attr flash_attr; 3467afc5dbdSKrishna Gudipati u32 cee_status; 3477afc5dbdSKrishna Gudipati u32 flash_status; 348f844a0eaSJeff Kirsher }; 349f844a0eaSJeff Kirsher 350f844a0eaSJeff Kirsher /* 351f844a0eaSJeff Kirsher * EXTERN VARIABLES 352f844a0eaSJeff Kirsher */ 353e1e0918fSstephen hemminger extern const struct firmware *bfi_fw; 354f844a0eaSJeff Kirsher extern u32 bnad_rxqs_per_cq; 355f844a0eaSJeff Kirsher 356f844a0eaSJeff Kirsher /* 357f844a0eaSJeff Kirsher * EXTERN PROTOTYPES 358f844a0eaSJeff Kirsher */ 359f844a0eaSJeff Kirsher extern u32 *cna_get_firmware_buf(struct pci_dev *pdev); 360f844a0eaSJeff Kirsher /* Netdev entry point prototypes */ 361a2122d95SRasesh Mody extern void bnad_set_rx_mode(struct net_device *netdev); 362a2122d95SRasesh Mody extern struct net_device_stats *bnad_get_netdev_stats( 363a2122d95SRasesh Mody struct net_device *netdev); 364a2122d95SRasesh Mody extern int bnad_mac_addr_set_locked(struct bnad *bnad, u8 *mac_addr); 365a2122d95SRasesh Mody extern int bnad_enable_default_bcast(struct bnad *bnad); 366a2122d95SRasesh Mody extern void bnad_restore_vlans(struct bnad *bnad, u32 rx_id); 367f844a0eaSJeff Kirsher extern void bnad_set_ethtool_ops(struct net_device *netdev); 36872a9730bSKrishna Gudipati extern void bnad_cb_completion(void *arg, enum bfa_status status); 369f844a0eaSJeff Kirsher 370f844a0eaSJeff Kirsher /* Configuration & setup */ 371f844a0eaSJeff Kirsher extern void bnad_tx_coalescing_timeo_set(struct bnad *bnad); 372f844a0eaSJeff Kirsher extern void bnad_rx_coalescing_timeo_set(struct bnad *bnad); 373f844a0eaSJeff Kirsher 374078086f3SRasesh Mody extern int bnad_setup_rx(struct bnad *bnad, u32 rx_id); 375078086f3SRasesh Mody extern int bnad_setup_tx(struct bnad *bnad, u32 tx_id); 376b3cc6e88SJing Huang extern void bnad_destroy_tx(struct bnad *bnad, u32 tx_id); 377b3cc6e88SJing Huang extern void bnad_destroy_rx(struct bnad *bnad, u32 rx_id); 378f844a0eaSJeff Kirsher 379f844a0eaSJeff Kirsher /* Timer start/stop protos */ 380f844a0eaSJeff Kirsher extern void bnad_dim_timer_start(struct bnad *bnad); 381f844a0eaSJeff Kirsher 382f844a0eaSJeff Kirsher /* Statistics */ 383f844a0eaSJeff Kirsher extern void bnad_netdev_qstats_fill(struct bnad *bnad, 384f844a0eaSJeff Kirsher struct rtnl_link_stats64 *stats); 385f844a0eaSJeff Kirsher extern void bnad_netdev_hwstats_fill(struct bnad *bnad, 386f844a0eaSJeff Kirsher struct rtnl_link_stats64 *stats); 387f844a0eaSJeff Kirsher 3887afc5dbdSKrishna Gudipati /* Debugfs */ 3897afc5dbdSKrishna Gudipati void bnad_debugfs_init(struct bnad *bnad); 3907afc5dbdSKrishna Gudipati void bnad_debugfs_uninit(struct bnad *bnad); 3917afc5dbdSKrishna Gudipati 3921aa8b471SBen Hutchings /* MACROS */ 393f844a0eaSJeff Kirsher /* To set & get the stats counters */ 394f844a0eaSJeff Kirsher #define BNAD_UPDATE_CTR(_bnad, _ctr) \ 395f844a0eaSJeff Kirsher (((_bnad)->stats.drv_stats._ctr)++) 396f844a0eaSJeff Kirsher 397f844a0eaSJeff Kirsher #define BNAD_GET_CTR(_bnad, _ctr) ((_bnad)->stats.drv_stats._ctr) 398f844a0eaSJeff Kirsher 399f844a0eaSJeff Kirsher #define bnad_enable_rx_irq_unsafe(_ccb) \ 400f844a0eaSJeff Kirsher { \ 401271e8b79SRasesh Mody if (likely(test_bit(BNAD_RXQ_STARTED, &(_ccb)->rcb[0]->flags))) {\ 402f844a0eaSJeff Kirsher bna_ib_coalescing_timer_set((_ccb)->i_dbell, \ 403f844a0eaSJeff Kirsher (_ccb)->rx_coalescing_timeo); \ 404f844a0eaSJeff Kirsher bna_ib_ack((_ccb)->i_dbell, 0); \ 405f844a0eaSJeff Kirsher } \ 406f844a0eaSJeff Kirsher } 407f844a0eaSJeff Kirsher 408f844a0eaSJeff Kirsher #endif /* __BNAD_H__ */ 409