1 /* 2 * Linux network driver for Brocade Converged Network Adapter. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License (GPL) Version 2 as 6 * published by the Free Software Foundation 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 /* 14 * Copyright (c) 2005-2011 Brocade Communications Systems, Inc. 15 * All rights reserved 16 * www.brocade.com 17 */ 18 19 /** 20 * File for interrupt macros and functions 21 */ 22 23 #ifndef __BNA_HW_DEFS_H__ 24 #define __BNA_HW_DEFS_H__ 25 26 #include "bfi_reg.h" 27 28 /** 29 * 30 * SW imposed limits 31 * 32 */ 33 #define BFI_ENET_DEF_TXQ 1 34 #define BFI_ENET_DEF_RXP 1 35 #define BFI_ENET_DEF_UCAM 1 36 #define BFI_ENET_DEF_RITSZ 1 37 38 #define BFI_ENET_MAX_MCAM 256 39 40 #define BFI_INVALID_RID -1 41 42 #define BFI_IBIDX_SIZE 4 43 44 #define BFI_VLAN_WORD_SHIFT 5 /* 32 bits */ 45 #define BFI_VLAN_WORD_MASK 0x1F 46 #define BFI_VLAN_BLOCK_SHIFT 9 /* 512 bits */ 47 #define BFI_VLAN_BMASK_ALL 0xFF 48 49 #define BFI_COALESCING_TIMER_UNIT 5 /* 5us */ 50 #define BFI_MAX_COALESCING_TIMEO 0xFF /* in 5us units */ 51 #define BFI_MAX_INTERPKT_COUNT 0xFF 52 #define BFI_MAX_INTERPKT_TIMEO 0xF /* in 0.5us units */ 53 #define BFI_TX_COALESCING_TIMEO 20 /* 20 * 5 = 100us */ 54 #define BFI_TX_INTERPKT_COUNT 32 55 #define BFI_RX_COALESCING_TIMEO 12 /* 12 * 5 = 60us */ 56 #define BFI_RX_INTERPKT_COUNT 6 /* Pkt Cnt = 6 */ 57 #define BFI_RX_INTERPKT_TIMEO 3 /* 3 * 0.5 = 1.5us */ 58 59 #define BFI_TXQ_WI_SIZE 64 /* bytes */ 60 #define BFI_RXQ_WI_SIZE 8 /* bytes */ 61 #define BFI_CQ_WI_SIZE 16 /* bytes */ 62 #define BFI_TX_MAX_WRR_QUOTA 0xFFF 63 64 #define BFI_TX_MAX_VECTORS_PER_WI 4 65 #define BFI_TX_MAX_VECTORS_PER_PKT 0xFF 66 #define BFI_TX_MAX_DATA_PER_VECTOR 0xFFFF 67 #define BFI_TX_MAX_DATA_PER_PKT 0xFFFFFF 68 69 /* Small Q buffer size */ 70 #define BFI_SMALL_RXBUF_SIZE 128 71 72 #define BFI_TX_MAX_PRIO 8 73 #define BFI_TX_PRIO_MAP_ALL 0xFF 74 75 /* 76 * 77 * Register definitions and macros 78 * 79 */ 80 81 #define BNA_PCI_REG_CT_ADDRSZ (0x40000) 82 83 #define ct_reg_addr_init(_bna, _pcidev) \ 84 { \ 85 struct bna_reg_offset reg_offset[] = \ 86 {{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK}, \ 87 {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK}, \ 88 {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK}, \ 89 {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} }; \ 90 \ 91 (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \ 92 reg_offset[(_pcidev)->pci_func].fn_int_status;\ 93 (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \ 94 reg_offset[(_pcidev)->pci_func].fn_int_mask;\ 95 } 96 97 #define ct_bit_defn_init(_bna, _pcidev) \ 98 { \ 99 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 | \ 100 __HFN_INT_MBOX_LPU1); \ 101 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 | \ 102 __HFN_INT_MBOX_LPU1); \ 103 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK); \ 104 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK); \ 105 (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT; \ 106 (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT; \ 107 } 108 109 #define ct2_reg_addr_init(_bna, _pcidev) \ 110 { \ 111 (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva + \ 112 CT2_HOSTFN_INT_STATUS; \ 113 (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva + \ 114 CT2_HOSTFN_INTR_MASK; \ 115 } 116 117 #define ct2_bit_defn_init(_bna, _pcidev) \ 118 { \ 119 (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 | \ 120 __HFN_INT_MBOX_LPU1_CT2); \ 121 (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 | \ 122 __HFN_INT_MBOX_LPU1_CT2); \ 123 (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2); \ 124 (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2); \ 125 (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2; \ 126 (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2; \ 127 } 128 129 #define bna_reg_addr_init(_bna, _pcidev) \ 130 { \ 131 switch ((_pcidev)->device_id) { \ 132 case PCI_DEVICE_ID_BROCADE_CT: \ 133 ct_reg_addr_init((_bna), (_pcidev)); \ 134 ct_bit_defn_init((_bna), (_pcidev)); \ 135 break; \ 136 case BFA_PCI_DEVICE_ID_CT2: \ 137 ct2_reg_addr_init((_bna), (_pcidev)); \ 138 ct2_bit_defn_init((_bna), (_pcidev)); \ 139 break; \ 140 } \ 141 } 142 143 #define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id) 144 /** 145 * 146 * Interrupt related bits, flags and macros 147 * 148 */ 149 150 #define IB_STATUS_BITS 0x0000ffff 151 152 #define BNA_IS_MBOX_INTR(_bna, _intr_status) \ 153 ((_intr_status) & (_bna)->bits.mbox_status_bits) 154 155 #define BNA_IS_HALT_INTR(_bna, _intr_status) \ 156 ((_intr_status) & (_bna)->bits.halt_status_bits) 157 158 #define BNA_IS_ERR_INTR(_bna, _intr_status) \ 159 ((_intr_status) & (_bna)->bits.error_status_bits) 160 161 #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status) \ 162 (BNA_IS_MBOX_INTR(_bna, _intr_status) | \ 163 BNA_IS_ERR_INTR(_bna, _intr_status)) 164 165 #define BNA_IS_INTX_DATA_INTR(_intr_status) \ 166 ((_intr_status) & IB_STATUS_BITS) 167 168 #define bna_halt_clear(_bna) \ 169 do { \ 170 u32 init_halt; \ 171 init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \ 172 init_halt &= ~__FW_INIT_HALT_P; \ 173 writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \ 174 init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \ 175 } while (0) 176 177 #define bna_intx_disable(_bna, _cur_mask) \ 178 { \ 179 (_cur_mask) = readl((_bna)->regs.fn_int_mask); \ 180 writel(0xffffffff, (_bna)->regs.fn_int_mask); \ 181 } 182 183 #define bna_intx_enable(bna, new_mask) \ 184 writel((new_mask), (bna)->regs.fn_int_mask) 185 #define bna_mbox_intr_disable(bna) \ 186 do { \ 187 u32 mask; \ 188 mask = readl((bna)->regs.fn_int_mask); \ 189 writel((mask | (bna)->bits.mbox_mask_bits | \ 190 (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \ 191 mask = readl((bna)->regs.fn_int_mask); \ 192 } while (0) 193 194 #define bna_mbox_intr_enable(bna) \ 195 do { \ 196 u32 mask; \ 197 mask = readl((bna)->regs.fn_int_mask); \ 198 writel((mask & ~((bna)->bits.mbox_mask_bits | \ 199 (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\ 200 mask = readl((bna)->regs.fn_int_mask); \ 201 } while (0) 202 203 #define bna_intr_status_get(_bna, _status) \ 204 { \ 205 (_status) = readl((_bna)->regs.fn_int_status); \ 206 if (_status) { \ 207 writel(((_status) & ~(_bna)->bits.mbox_status_bits), \ 208 (_bna)->regs.fn_int_status); \ 209 } \ 210 } 211 212 /* 213 * MAX ACK EVENTS : No. of acks that can be accumulated in driver, 214 * before acking to h/w. The no. of bits is 16 in the doorbell register, 215 * however we keep this limited to 15 bits. 216 * This is because around the edge of 64K boundary (16 bits), one 217 * single poll can make the accumulated ACK counter cross the 64K boundary, 218 * causing problems, when we try to ack with a value greater than 64K. 219 * 15 bits (32K) should be large enough to accumulate, anyways, and the max. 220 * acked events to h/w can be (32K + max poll weight) (currently 64). 221 */ 222 #define BNA_IB_MAX_ACK_EVENTS (1 << 15) 223 224 /* These macros build the data portion of the TxQ/RxQ doorbell */ 225 #define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi)) 226 #define BNA_DOORBELL_Q_STOP (0x40000000) 227 228 /* These macros build the data portion of the IB doorbell */ 229 #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events) \ 230 (0x80000000 | ((_timeout) << 16) | (_events)) 231 #define BNA_DOORBELL_IB_INT_DISABLE (0x40000000) 232 233 /* Set the coalescing timer for the given ib */ 234 #define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer) \ 235 ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0)); 236 237 /* Acks 'events' # of events for a given ib while disabling interrupts */ 238 #define bna_ib_ack_disable_irq(_i_dbell, _events) \ 239 (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \ 240 (_i_dbell)->doorbell_addr)); 241 242 /* Acks 'events' # of events for a given ib */ 243 #define bna_ib_ack(_i_dbell, _events) \ 244 (writel(((_i_dbell)->doorbell_ack | (_events)), \ 245 (_i_dbell)->doorbell_addr)); 246 247 #define bna_ib_start(_bna, _ib, _is_regular) \ 248 { \ 249 u32 intx_mask; \ 250 struct bna_ib *ib = _ib; \ 251 if ((ib->intr_type == BNA_INTR_T_INTX)) { \ 252 bna_intx_disable((_bna), intx_mask); \ 253 intx_mask &= ~(ib->intr_vector); \ 254 bna_intx_enable((_bna), intx_mask); \ 255 } \ 256 bna_ib_coalescing_timer_set(&ib->door_bell, \ 257 ib->coalescing_timeo); \ 258 if (_is_regular) \ 259 bna_ib_ack(&ib->door_bell, 0); \ 260 } 261 262 #define bna_ib_stop(_bna, _ib) \ 263 { \ 264 u32 intx_mask; \ 265 struct bna_ib *ib = _ib; \ 266 writel(BNA_DOORBELL_IB_INT_DISABLE, \ 267 ib->door_bell.doorbell_addr); \ 268 if (ib->intr_type == BNA_INTR_T_INTX) { \ 269 bna_intx_disable((_bna), intx_mask); \ 270 intx_mask |= ib->intr_vector; \ 271 bna_intx_enable((_bna), intx_mask); \ 272 } \ 273 } 274 275 #define bna_txq_prod_indx_doorbell(_tcb) \ 276 (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \ 277 (_tcb)->q_dbell)); 278 279 #define bna_rxq_prod_indx_doorbell(_rcb) \ 280 (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \ 281 (_rcb)->q_dbell)); 282 283 /** 284 * 285 * TxQ, RxQ, CQ related bits, offsets, macros 286 * 287 */ 288 289 /* TxQ Entry Opcodes */ 290 #define BNA_TXQ_WI_SEND (0x402) /* Single Frame Transmission */ 291 #define BNA_TXQ_WI_SEND_LSO (0x403) /* Multi-Frame Transmission */ 292 #define BNA_TXQ_WI_EXTENSION (0x104) /* Extension WI */ 293 294 /* TxQ Entry Control Flags */ 295 #define BNA_TXQ_WI_CF_FCOE_CRC (1 << 8) 296 #define BNA_TXQ_WI_CF_IPID_MODE (1 << 5) 297 #define BNA_TXQ_WI_CF_INS_PRIO (1 << 4) 298 #define BNA_TXQ_WI_CF_INS_VLAN (1 << 3) 299 #define BNA_TXQ_WI_CF_UDP_CKSUM (1 << 2) 300 #define BNA_TXQ_WI_CF_TCP_CKSUM (1 << 1) 301 #define BNA_TXQ_WI_CF_IP_CKSUM (1 << 0) 302 303 #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \ 304 (((_hdr_size) << 10) | ((_offset) & 0x3FF)) 305 306 /* 307 * Completion Q defines 308 */ 309 /* CQ Entry Flags */ 310 #define BNA_CQ_EF_MAC_ERROR (1 << 0) 311 #define BNA_CQ_EF_FCS_ERROR (1 << 1) 312 #define BNA_CQ_EF_TOO_LONG (1 << 2) 313 #define BNA_CQ_EF_FC_CRC_OK (1 << 3) 314 315 #define BNA_CQ_EF_RSVD1 (1 << 4) 316 #define BNA_CQ_EF_L4_CKSUM_OK (1 << 5) 317 #define BNA_CQ_EF_L3_CKSUM_OK (1 << 6) 318 #define BNA_CQ_EF_HDS_HEADER (1 << 7) 319 320 #define BNA_CQ_EF_UDP (1 << 8) 321 #define BNA_CQ_EF_TCP (1 << 9) 322 #define BNA_CQ_EF_IP_OPTIONS (1 << 10) 323 #define BNA_CQ_EF_IPV6 (1 << 11) 324 325 #define BNA_CQ_EF_IPV4 (1 << 12) 326 #define BNA_CQ_EF_VLAN (1 << 13) 327 #define BNA_CQ_EF_RSS (1 << 14) 328 #define BNA_CQ_EF_RSVD2 (1 << 15) 329 330 #define BNA_CQ_EF_MCAST_MATCH (1 << 16) 331 #define BNA_CQ_EF_MCAST (1 << 17) 332 #define BNA_CQ_EF_BCAST (1 << 18) 333 #define BNA_CQ_EF_REMOTE (1 << 19) 334 335 #define BNA_CQ_EF_LOCAL (1 << 20) 336 337 /** 338 * 339 * Data structures 340 * 341 */ 342 343 struct bna_reg_offset { 344 u32 fn_int_status; 345 u32 fn_int_mask; 346 }; 347 348 struct bna_bit_defn { 349 u32 mbox_status_bits; 350 u32 mbox_mask_bits; 351 u32 error_status_bits; 352 u32 error_mask_bits; 353 u32 halt_status_bits; 354 u32 halt_mask_bits; 355 }; 356 357 struct bna_reg { 358 void __iomem *fn_int_status; 359 void __iomem *fn_int_mask; 360 }; 361 362 /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */ 363 struct bna_dma_addr { 364 u32 msb; 365 u32 lsb; 366 }; 367 368 struct bna_txq_wi_vector { 369 u16 reserved; 370 u16 length; /* Only 14 LSB are valid */ 371 struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */ 372 }; 373 374 /** 375 * TxQ Entry Structure 376 * 377 * BEWARE: Load values into this structure with correct endianess. 378 */ 379 struct bna_txq_entry { 380 union { 381 struct { 382 u8 reserved; 383 u8 num_vectors; /* number of vectors present */ 384 u16 opcode; /* Either */ 385 /* BNA_TXQ_WI_SEND or */ 386 /* BNA_TXQ_WI_SEND_LSO */ 387 u16 flags; /* OR of all the flags */ 388 u16 l4_hdr_size_n_offset; 389 u16 vlan_tag; 390 u16 lso_mss; /* Only 14 LSB are valid */ 391 u32 frame_length; /* Only 24 LSB are valid */ 392 } wi; 393 394 struct { 395 u16 reserved; 396 u16 opcode; /* Must be */ 397 /* BNA_TXQ_WI_EXTENSION */ 398 u32 reserved2[3]; /* Place holder for */ 399 /* removed vector (12 bytes) */ 400 } wi_ext; 401 } hdr; 402 struct bna_txq_wi_vector vector[4]; 403 }; 404 405 /* RxQ Entry Structure */ 406 struct bna_rxq_entry { /* Rx-Buffer */ 407 struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */ 408 }; 409 410 /* CQ Entry Structure */ 411 struct bna_cq_entry { 412 u32 flags; 413 u16 vlan_tag; 414 u16 length; 415 u32 rss_hash; 416 u8 valid; 417 u8 reserved1; 418 u8 reserved2; 419 u8 rxq_id; 420 }; 421 422 #endif /* __BNA_HW_DEFS_H__ */ 423