1 /*
2  * Linux network driver for QLogic BR-series Converged Network Adapter.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License (GPL) Version 2 as
6  * published by the Free Software Foundation
7  *
8  * This program is distributed in the hope that it will be useful, but
9  * WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
11  * General Public License for more details.
12  */
13 /*
14  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15  * Copyright (c) 2014-2015 QLogic Corporation
16  * All rights reserved
17  * www.qlogic.com
18  */
19 
20 /* File for interrupt macros and functions */
21 
22 #ifndef __BNA_HW_DEFS_H__
23 #define __BNA_HW_DEFS_H__
24 
25 #include "bfi_reg.h"
26 
27 /* SW imposed limits */
28 
29 #define BFI_ENET_DEF_TXQ		1
30 #define BFI_ENET_DEF_RXP		1
31 #define BFI_ENET_DEF_UCAM		1
32 #define BFI_ENET_DEF_RITSZ		1
33 
34 #define BFI_ENET_MAX_MCAM		256
35 
36 #define BFI_INVALID_RID			-1
37 
38 #define BFI_IBIDX_SIZE			4
39 
40 #define BFI_VLAN_WORD_SHIFT		5	/* 32 bits */
41 #define BFI_VLAN_WORD_MASK		0x1F
42 #define BFI_VLAN_BLOCK_SHIFT		9	/* 512 bits */
43 #define BFI_VLAN_BMASK_ALL		0xFF
44 
45 #define BFI_COALESCING_TIMER_UNIT	5	/* 5us */
46 #define BFI_MAX_COALESCING_TIMEO	0xFF	/* in 5us units */
47 #define BFI_MAX_INTERPKT_COUNT		0xFF
48 #define BFI_MAX_INTERPKT_TIMEO		0xF	/* in 0.5us units */
49 #define BFI_TX_COALESCING_TIMEO		20	/* 20 * 5 = 100us */
50 #define BFI_TX_INTERPKT_COUNT		12	/* Pkt Cnt = 12 */
51 #define BFI_TX_INTERPKT_TIMEO		15	/* 15 * 0.5 = 7.5us */
52 #define	BFI_RX_COALESCING_TIMEO		12	/* 12 * 5 = 60us */
53 #define	BFI_RX_INTERPKT_COUNT		6	/* Pkt Cnt = 6 */
54 #define	BFI_RX_INTERPKT_TIMEO		3	/* 3 * 0.5 = 1.5us */
55 
56 #define BFI_TXQ_WI_SIZE			64	/* bytes */
57 #define BFI_RXQ_WI_SIZE			8	/* bytes */
58 #define BFI_CQ_WI_SIZE			16	/* bytes */
59 #define BFI_TX_MAX_WRR_QUOTA		0xFFF
60 
61 #define BFI_TX_MAX_VECTORS_PER_WI	4
62 #define BFI_TX_MAX_VECTORS_PER_PKT	0xFF
63 #define BFI_TX_MAX_DATA_PER_VECTOR	0xFFFF
64 #define BFI_TX_MAX_DATA_PER_PKT		0xFFFFFF
65 
66 /* Small Q buffer size */
67 #define BFI_SMALL_RXBUF_SIZE		128
68 
69 #define BFI_TX_MAX_PRIO			8
70 #define BFI_TX_PRIO_MAP_ALL		0xFF
71 
72 /*
73  *
74  * Register definitions and macros
75  *
76  */
77 
78 #define BNA_PCI_REG_CT_ADDRSZ		(0x40000)
79 
80 #define ct_reg_addr_init(_bna, _pcidev)					\
81 {									\
82 	struct bna_reg_offset reg_offset[] =				\
83 	{{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK},				\
84 	 {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK},				\
85 	 {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK},				\
86 	 {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} };			\
87 									\
88 	(_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +		\
89 				reg_offset[(_pcidev)->pci_func].fn_int_status;\
90 	(_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +		\
91 				reg_offset[(_pcidev)->pci_func].fn_int_mask;\
92 }
93 
94 #define ct_bit_defn_init(_bna, _pcidev)					\
95 {									\
96 	(_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 |		\
97 					__HFN_INT_MBOX_LPU1);		\
98 	(_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 |		\
99 					__HFN_INT_MBOX_LPU1);		\
100 	(_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK);		\
101 	(_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK);		\
102 	(_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT;		\
103 	(_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT;		\
104 }
105 
106 #define ct2_reg_addr_init(_bna, _pcidev)				\
107 {									\
108 	(_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +		\
109 				CT2_HOSTFN_INT_STATUS;			\
110 	(_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +		\
111 				CT2_HOSTFN_INTR_MASK;			\
112 }
113 
114 #define ct2_bit_defn_init(_bna, _pcidev)				\
115 {									\
116 	(_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 |	\
117 					__HFN_INT_MBOX_LPU1_CT2);	\
118 	(_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 |	\
119 					__HFN_INT_MBOX_LPU1_CT2);	\
120 	(_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2);	\
121 	(_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2);	\
122 	(_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2;		\
123 	(_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2;		\
124 }
125 
126 #define bna_reg_addr_init(_bna, _pcidev)				\
127 {									\
128 	switch ((_pcidev)->device_id) {					\
129 	case PCI_DEVICE_ID_BROCADE_CT:					\
130 		ct_reg_addr_init((_bna), (_pcidev));			\
131 		ct_bit_defn_init((_bna), (_pcidev));			\
132 		break;							\
133 	case BFA_PCI_DEVICE_ID_CT2:					\
134 		ct2_reg_addr_init((_bna), (_pcidev));			\
135 		ct2_bit_defn_init((_bna), (_pcidev));			\
136 		break;							\
137 	}								\
138 }
139 
140 #define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id)
141 
142 /*  Interrupt related bits, flags and macros  */
143 
144 #define IB_STATUS_BITS		0x0000ffff
145 
146 #define BNA_IS_MBOX_INTR(_bna, _intr_status)				\
147 	((_intr_status) & (_bna)->bits.mbox_status_bits)
148 
149 #define BNA_IS_HALT_INTR(_bna, _intr_status)				\
150 	((_intr_status) & (_bna)->bits.halt_status_bits)
151 
152 #define BNA_IS_ERR_INTR(_bna, _intr_status)	\
153 	((_intr_status) & (_bna)->bits.error_status_bits)
154 
155 #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status)	\
156 	(BNA_IS_MBOX_INTR(_bna, _intr_status) |		\
157 	BNA_IS_ERR_INTR(_bna, _intr_status))
158 
159 #define BNA_IS_INTX_DATA_INTR(_intr_status)		\
160 		((_intr_status) & IB_STATUS_BITS)
161 
162 #define bna_halt_clear(_bna)						\
163 do {									\
164 	u32 init_halt;						\
165 	init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt);	\
166 	init_halt &= ~__FW_INIT_HALT_P;					\
167 	writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt);	\
168 	init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt);	\
169 } while (0)
170 
171 #define bna_intx_disable(_bna, _cur_mask)				\
172 {									\
173 	(_cur_mask) = readl((_bna)->regs.fn_int_mask);		\
174 	writel(0xffffffff, (_bna)->regs.fn_int_mask);		\
175 }
176 
177 #define bna_intx_enable(bna, new_mask)					\
178 	writel((new_mask), (bna)->regs.fn_int_mask)
179 #define bna_mbox_intr_disable(bna)					\
180 do {									\
181 	u32 mask;							\
182 	mask = readl((bna)->regs.fn_int_mask);				\
183 	writel((mask | (bna)->bits.mbox_mask_bits |			\
184 		(bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \
185 	mask = readl((bna)->regs.fn_int_mask);				\
186 } while (0)
187 
188 #define bna_mbox_intr_enable(bna)					\
189 do {									\
190 	u32 mask;							\
191 	mask = readl((bna)->regs.fn_int_mask);				\
192 	writel((mask & ~((bna)->bits.mbox_mask_bits |			\
193 		(bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\
194 	mask = readl((bna)->regs.fn_int_mask);				\
195 } while (0)
196 
197 #define bna_intr_status_get(_bna, _status)				\
198 {									\
199 	(_status) = readl((_bna)->regs.fn_int_status);			\
200 	if (_status) {							\
201 		writel(((_status) & ~(_bna)->bits.mbox_status_bits),	\
202 			(_bna)->regs.fn_int_status);			\
203 	}								\
204 }
205 
206 /*
207  * MAX ACK EVENTS : No. of acks that can be accumulated in driver,
208  * before acking to h/w. The no. of bits is 16 in the doorbell register,
209  * however we keep this limited to 15 bits.
210  * This is because around the edge of 64K boundary (16 bits), one
211  * single poll can make the accumulated ACK counter cross the 64K boundary,
212  * causing problems, when we try to ack with a value greater than 64K.
213  * 15 bits (32K) should  be large enough to accumulate, anyways, and the max.
214  * acked events to h/w can be (32K + max poll weight) (currently 64).
215  */
216 #define	BNA_IB_MAX_ACK_EVENTS		(1 << 15)
217 
218 /* These macros build the data portion of the TxQ/RxQ doorbell */
219 #define BNA_DOORBELL_Q_PRD_IDX(_pi)	(0x80000000 | (_pi))
220 #define BNA_DOORBELL_Q_STOP		(0x40000000)
221 
222 /* These macros build the data portion of the IB doorbell */
223 #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events)			\
224 	(0x80000000 | ((_timeout) << 16) | (_events))
225 #define BNA_DOORBELL_IB_INT_DISABLE	(0x40000000)
226 
227 /* Set the coalescing timer for the given ib */
228 #define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer)		\
229 	((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0));
230 
231 /* Acks 'events' # of events for a given ib while disabling interrupts */
232 #define bna_ib_ack_disable_irq(_i_dbell, _events)			\
233 	(writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \
234 		(_i_dbell)->doorbell_addr));
235 
236 /* Acks 'events' # of events for a given ib */
237 #define bna_ib_ack(_i_dbell, _events)					\
238 	(writel(((_i_dbell)->doorbell_ack | (_events)), \
239 		(_i_dbell)->doorbell_addr));
240 
241 #define bna_ib_start(_bna, _ib, _is_regular)				\
242 {									\
243 	u32 intx_mask;						\
244 	struct bna_ib *ib = _ib;					\
245 	if ((ib->intr_type == BNA_INTR_T_INTX)) {			\
246 		bna_intx_disable((_bna), intx_mask);			\
247 		intx_mask &= ~(ib->intr_vector);			\
248 		bna_intx_enable((_bna), intx_mask);			\
249 	}								\
250 	bna_ib_coalescing_timer_set(&ib->door_bell,			\
251 			ib->coalescing_timeo);				\
252 	if (_is_regular)						\
253 		bna_ib_ack(&ib->door_bell, 0);				\
254 }
255 
256 #define bna_ib_stop(_bna, _ib)						\
257 {									\
258 	u32 intx_mask;						\
259 	struct bna_ib *ib = _ib;					\
260 	writel(BNA_DOORBELL_IB_INT_DISABLE,				\
261 		ib->door_bell.doorbell_addr);				\
262 	if (ib->intr_type == BNA_INTR_T_INTX) {				\
263 		bna_intx_disable((_bna), intx_mask);			\
264 		intx_mask |= ib->intr_vector;				\
265 		bna_intx_enable((_bna), intx_mask);			\
266 	}								\
267 }
268 
269 #define bna_txq_prod_indx_doorbell(_tcb)				\
270 	(writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
271 		(_tcb)->q_dbell));
272 
273 #define bna_rxq_prod_indx_doorbell(_rcb)				\
274 	(writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \
275 		(_rcb)->q_dbell));
276 
277 /* TxQ, RxQ, CQ related bits, offsets, macros */
278 
279 /* TxQ Entry Opcodes */
280 #define BNA_TXQ_WI_SEND			(0x402)	/* Single Frame Transmission */
281 #define BNA_TXQ_WI_SEND_LSO		(0x403)	/* Multi-Frame Transmission */
282 #define BNA_TXQ_WI_EXTENSION		(0x104)	/* Extension WI */
283 
284 /* TxQ Entry Control Flags */
285 #define BNA_TXQ_WI_CF_FCOE_CRC		(1 << 8)
286 #define BNA_TXQ_WI_CF_IPID_MODE		(1 << 5)
287 #define BNA_TXQ_WI_CF_INS_PRIO		(1 << 4)
288 #define BNA_TXQ_WI_CF_INS_VLAN		(1 << 3)
289 #define BNA_TXQ_WI_CF_UDP_CKSUM		(1 << 2)
290 #define BNA_TXQ_WI_CF_TCP_CKSUM		(1 << 1)
291 #define BNA_TXQ_WI_CF_IP_CKSUM		(1 << 0)
292 
293 #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
294 		(((_hdr_size) << 10) | ((_offset) & 0x3FF))
295 
296 /*
297  * Completion Q defines
298  */
299 /* CQ Entry Flags */
300 #define	BNA_CQ_EF_MAC_ERROR	(1 <<  0)
301 #define	BNA_CQ_EF_FCS_ERROR	(1 <<  1)
302 #define	BNA_CQ_EF_TOO_LONG	(1 <<  2)
303 #define	BNA_CQ_EF_FC_CRC_OK	(1 <<  3)
304 
305 #define	BNA_CQ_EF_RSVD1		(1 <<  4)
306 #define	BNA_CQ_EF_L4_CKSUM_OK	(1 <<  5)
307 #define	BNA_CQ_EF_L3_CKSUM_OK	(1 <<  6)
308 #define	BNA_CQ_EF_HDS_HEADER	(1 <<  7)
309 
310 #define	BNA_CQ_EF_UDP		(1 <<  8)
311 #define	BNA_CQ_EF_TCP		(1 <<  9)
312 #define	BNA_CQ_EF_IP_OPTIONS	(1 << 10)
313 #define	BNA_CQ_EF_IPV6		(1 << 11)
314 
315 #define	BNA_CQ_EF_IPV4		(1 << 12)
316 #define	BNA_CQ_EF_VLAN		(1 << 13)
317 #define	BNA_CQ_EF_RSS		(1 << 14)
318 #define	BNA_CQ_EF_RSVD2		(1 << 15)
319 
320 #define	BNA_CQ_EF_MCAST_MATCH   (1 << 16)
321 #define	BNA_CQ_EF_MCAST		(1 << 17)
322 #define BNA_CQ_EF_BCAST		(1 << 18)
323 #define	BNA_CQ_EF_REMOTE	(1 << 19)
324 
325 #define	BNA_CQ_EF_LOCAL		(1 << 20)
326 /* CAT2 ASIC does not use bit 21 as per the SPEC.
327  * Bit 31 is set in every end of frame completion
328  */
329 #define BNA_CQ_EF_EOP		(1 << 31)
330 
331 /* Data structures */
332 
333 struct bna_reg_offset {
334 	u32 fn_int_status;
335 	u32 fn_int_mask;
336 };
337 
338 struct bna_bit_defn {
339 	u32 mbox_status_bits;
340 	u32 mbox_mask_bits;
341 	u32 error_status_bits;
342 	u32 error_mask_bits;
343 	u32 halt_status_bits;
344 	u32 halt_mask_bits;
345 };
346 
347 struct bna_reg {
348 	void __iomem *fn_int_status;
349 	void __iomem *fn_int_mask;
350 };
351 
352 /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
353 struct bna_dma_addr {
354 	u32		msb;
355 	u32		lsb;
356 };
357 
358 struct bna_txq_wi_vector {
359 	u16		reserved;
360 	u16		length;		/* Only 14 LSB are valid */
361 	struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
362 };
363 
364 /*  TxQ Entry Structure
365  *
366  *  BEWARE:  Load values into this structure with correct endianness.
367  */
368 struct bna_txq_entry {
369 	union {
370 		struct {
371 			u8 reserved;
372 			u8 num_vectors;	/* number of vectors present */
373 			u16 opcode; /* Either */
374 						    /* BNA_TXQ_WI_SEND or */
375 						    /* BNA_TXQ_WI_SEND_LSO */
376 			u16 flags; /* OR of all the flags */
377 			u16 l4_hdr_size_n_offset;
378 			u16 vlan_tag;
379 			u16 lso_mss;	/* Only 14 LSB are valid */
380 			u32 frame_length;	/* Only 24 LSB are valid */
381 		} wi;
382 
383 		struct {
384 			u16 reserved;
385 			u16 opcode; /* Must be */
386 						    /* BNA_TXQ_WI_EXTENSION */
387 			u32 reserved2[3];	/* Place holder for */
388 						/* removed vector (12 bytes) */
389 		} wi_ext;
390 	} hdr;
391 	struct bna_txq_wi_vector vector[4];
392 };
393 
394 /* RxQ Entry Structure */
395 struct bna_rxq_entry {		/* Rx-Buffer */
396 	struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
397 };
398 
399 /* CQ Entry Structure */
400 struct bna_cq_entry {
401 	u32 flags;
402 	u16 vlan_tag;
403 	u16 length;
404 	u32 rss_hash;
405 	u8 valid;
406 	u8 reserved1;
407 	u8 reserved2;
408 	u8 rxq_id;
409 };
410 
411 #endif /* __BNA_HW_DEFS_H__ */
412