1 /* 2 * Linux network driver for Brocade Converged Network Adapter. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License (GPL) Version 2 as 6 * published by the Free Software Foundation 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 11 * General Public License for more details. 12 */ 13 /* 14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 15 * All rights reserved 16 * www.brocade.com 17 */ 18 #ifndef __BFI_H__ 19 #define __BFI_H__ 20 21 #include "bfa_defs.h" 22 23 #pragma pack(1) 24 25 /* BFI FW image type */ 26 #define BFI_FLASH_CHUNK_SZ 256 /*!< Flash chunk size */ 27 #define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32)) 28 #define BFI_FLASH_IMAGE_SZ 0x100000 29 30 /* Msg header common to all msgs */ 31 struct bfi_mhdr { 32 u8 msg_class; /*!< @ref enum bfi_mclass */ 33 u8 msg_id; /*!< msg opcode with in the class */ 34 union { 35 struct { 36 u8 qid; 37 u8 fn_lpu; /*!< msg destination */ 38 } h2i; 39 u16 i2htok; /*!< token in msgs to host */ 40 } mtag; 41 }; 42 43 #define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu)) 44 #define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1) 45 #define bfi_mhdr_2_qid(_mh) ((_mh)->mtag.h2i.qid) 46 47 #define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \ 48 (_mh).msg_class = (_mc); \ 49 (_mh).msg_id = (_op); \ 50 (_mh).mtag.h2i.fn_lpu = (_fn_lpu); \ 51 } while (0) 52 53 #define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \ 54 (_mh).msg_class = (_mc); \ 55 (_mh).msg_id = (_op); \ 56 (_mh).mtag.i2htok = (_i2htok); \ 57 } while (0) 58 59 /* 60 * Message opcodes: 0-127 to firmware, 128-255 to host 61 */ 62 #define BFI_I2H_OPCODE_BASE 128 63 #define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE) 64 65 /**************************************************************************** 66 * 67 * Scatter Gather Element and Page definition 68 * 69 **************************************************************************** 70 */ 71 72 /* DMA addresses */ 73 union bfi_addr_u { 74 struct { 75 u32 addr_lo; 76 u32 addr_hi; 77 } a32; 78 }; 79 80 /* Generic DMA addr-len pair. */ 81 struct bfi_alen { 82 union bfi_addr_u al_addr; /* DMA addr of buffer */ 83 u32 al_len; /* length of buffer */ 84 }; 85 86 /* 87 * Large Message structure - 128 Bytes size Msgs 88 */ 89 #define BFI_LMSG_SZ 128 90 #define BFI_LMSG_PL_WSZ \ 91 ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4) 92 93 /* Mailbox message structure */ 94 #define BFI_MBMSG_SZ 7 95 struct bfi_mbmsg { 96 struct bfi_mhdr mh; 97 u32 pl[BFI_MBMSG_SZ]; 98 }; 99 100 /* Supported PCI function class codes (personality) */ 101 enum bfi_pcifn_class { 102 BFI_PCIFN_CLASS_FC = 0x0c04, 103 BFI_PCIFN_CLASS_ETH = 0x0200, 104 }; 105 106 /* Message Classes */ 107 enum bfi_mclass { 108 BFI_MC_IOC = 1, /*!< IO Controller (IOC) */ 109 BFI_MC_DIAG = 2, /*!< Diagnostic Msgs */ 110 BFI_MC_FLASH = 3, /*!< Flash message class */ 111 BFI_MC_CEE = 4, /*!< CEE */ 112 BFI_MC_FCPORT = 5, /*!< FC port */ 113 BFI_MC_IOCFC = 6, /*!< FC - IO Controller (IOC) */ 114 BFI_MC_LL = 7, /*!< Link Layer */ 115 BFI_MC_UF = 8, /*!< Unsolicited frame receive */ 116 BFI_MC_FCXP = 9, /*!< FC Transport */ 117 BFI_MC_LPS = 10, /*!< lport fc login services */ 118 BFI_MC_RPORT = 11, /*!< Remote port */ 119 BFI_MC_ITNIM = 12, /*!< I-T nexus (Initiator mode) */ 120 BFI_MC_IOIM_READ = 13, /*!< read IO (Initiator mode) */ 121 BFI_MC_IOIM_WRITE = 14, /*!< write IO (Initiator mode) */ 122 BFI_MC_IOIM_IO = 15, /*!< IO (Initiator mode) */ 123 BFI_MC_IOIM = 16, /*!< IO (Initiator mode) */ 124 BFI_MC_IOIM_IOCOM = 17, /*!< good IO completion */ 125 BFI_MC_TSKIM = 18, /*!< Initiator Task management */ 126 BFI_MC_SBOOT = 19, /*!< SAN boot services */ 127 BFI_MC_IPFC = 20, /*!< IP over FC Msgs */ 128 BFI_MC_PORT = 21, /*!< Physical port */ 129 BFI_MC_SFP = 22, /*!< SFP module */ 130 BFI_MC_MSGQ = 23, /*!< MSGQ */ 131 BFI_MC_ENET = 24, /*!< ENET commands/responses */ 132 BFI_MC_PHY = 25, /*!< External PHY message class */ 133 BFI_MC_NBOOT = 26, /*!< Network Boot */ 134 BFI_MC_TIO_READ = 27, /*!< read IO (Target mode) */ 135 BFI_MC_TIO_WRITE = 28, /*!< write IO (Target mode) */ 136 BFI_MC_TIO_DATA_XFERED = 29, /*!< ds transferred (target mode) */ 137 BFI_MC_TIO_IO = 30, /*!< IO (Target mode) */ 138 BFI_MC_TIO = 31, /*!< IO (target mode) */ 139 BFI_MC_MFG = 32, /*!< MFG/ASIC block commands */ 140 BFI_MC_EDMA = 33, /*!< EDMA copy commands */ 141 BFI_MC_MAX = 34 142 }; 143 144 #define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */ 145 146 #define BFI_FWBOOT_ENV_OS 0 147 148 /*---------------------------------------------------------------------- 149 * IOC 150 *---------------------------------------------------------------------- 151 */ 152 153 /* Different asic generations */ 154 enum bfi_asic_gen { 155 BFI_ASIC_GEN_CB = 1, 156 BFI_ASIC_GEN_CT = 2, 157 BFI_ASIC_GEN_CT2 = 3, 158 }; 159 160 enum bfi_asic_mode { 161 BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */ 162 BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */ 163 BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */ 164 BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */ 165 }; 166 167 enum bfi_ioc_h2i_msgs { 168 BFI_IOC_H2I_ENABLE_REQ = 1, 169 BFI_IOC_H2I_DISABLE_REQ = 2, 170 BFI_IOC_H2I_GETATTR_REQ = 3, 171 BFI_IOC_H2I_DBG_SYNC = 4, 172 BFI_IOC_H2I_DBG_DUMP = 5, 173 }; 174 175 enum bfi_ioc_i2h_msgs { 176 BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1), 177 BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2), 178 BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3), 179 BFI_IOC_I2H_HBEAT = BFA_I2HM(4), 180 }; 181 182 /* BFI_IOC_H2I_GETATTR_REQ message */ 183 struct bfi_ioc_getattr_req { 184 struct bfi_mhdr mh; 185 union bfi_addr_u attr_addr; 186 }; 187 188 struct bfi_ioc_attr { 189 u64 mfg_pwwn; /*!< Mfg port wwn */ 190 u64 mfg_nwwn; /*!< Mfg node wwn */ 191 mac_t mfg_mac; /*!< Mfg mac */ 192 u8 port_mode; /* enum bfi_port_mode */ 193 u8 rsvd_a; 194 u64 pwwn; 195 u64 nwwn; 196 mac_t mac; /*!< PBC or Mfg mac */ 197 u16 rsvd_b; 198 mac_t fcoe_mac; 199 u16 rsvd_c; 200 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; 201 u8 pcie_gen; 202 u8 pcie_lanes_orig; 203 u8 pcie_lanes; 204 u8 rx_bbcredit; /*!< receive buffer credits */ 205 u32 adapter_prop; /*!< adapter properties */ 206 u16 maxfrsize; /*!< max receive frame size */ 207 char asic_rev; 208 u8 rsvd_d; 209 char fw_version[BFA_VERSION_LEN]; 210 char optrom_version[BFA_VERSION_LEN]; 211 struct bfa_mfg_vpd vpd; 212 u32 card_type; /*!< card type */ 213 }; 214 215 /* BFI_IOC_I2H_GETATTR_REPLY message */ 216 struct bfi_ioc_getattr_reply { 217 struct bfi_mhdr mh; /*!< Common msg header */ 218 u8 status; /*!< cfg reply status */ 219 u8 rsvd[3]; 220 }; 221 222 /* Firmware memory page offsets */ 223 #define BFI_IOC_SMEM_PG0_CB (0x40) 224 #define BFI_IOC_SMEM_PG0_CT (0x180) 225 226 /* Firmware statistic offset */ 227 #define BFI_IOC_FWSTATS_OFF (0x6B40) 228 #define BFI_IOC_FWSTATS_SZ (4096) 229 230 /* Firmware trace offset */ 231 #define BFI_IOC_TRC_OFF (0x4b00) 232 #define BFI_IOC_TRC_ENTS 256 233 #define BFI_IOC_TRC_ENT_SZ 16 234 #define BFI_IOC_TRC_HDR_SZ 32 235 236 #define BFI_IOC_FW_SIGNATURE (0xbfadbfad) 237 #define BFI_IOC_FW_INV_SIGN (0xdeaddead) 238 #define BFI_IOC_MD5SUM_SZ 4 239 240 struct bfi_ioc_fwver { 241 #ifdef __BIG_ENDIAN 242 u8 patch; 243 u8 maint; 244 u8 minor; 245 u8 major; 246 u8 rsvd[2]; 247 u8 build; 248 u8 phase; 249 #else 250 u8 major; 251 u8 minor; 252 u8 maint; 253 u8 patch; 254 u8 phase; 255 u8 build; 256 u8 rsvd[2]; 257 #endif 258 }; 259 260 struct bfi_ioc_image_hdr { 261 u32 signature; /*!< constant signature */ 262 u8 asic_gen; /*!< asic generation */ 263 u8 asic_mode; 264 u8 port0_mode; /*!< device mode for port 0 */ 265 u8 port1_mode; /*!< device mode for port 1 */ 266 u32 exec; /*!< exec vector */ 267 u32 bootenv; /*!< firmware boot env */ 268 u32 rsvd_b[2]; 269 struct bfi_ioc_fwver fwver; 270 u32 md5sum[BFI_IOC_MD5SUM_SZ]; 271 }; 272 273 enum bfi_ioc_img_ver_cmp { 274 BFI_IOC_IMG_VER_INCOMP, 275 BFI_IOC_IMG_VER_OLD, 276 BFI_IOC_IMG_VER_SAME, 277 BFI_IOC_IMG_VER_BETTER 278 }; 279 280 #define BFI_FWBOOT_DEVMODE_OFF 4 281 #define BFI_FWBOOT_TYPE_OFF 8 282 #define BFI_FWBOOT_ENV_OFF 12 283 #define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \ 284 (((u32)(__asic_gen)) << 24 | \ 285 ((u32)(__asic_mode)) << 16 | \ 286 ((u32)(__p0_mode)) << 8 | \ 287 ((u32)(__p1_mode))) 288 289 enum bfi_fwboot_type { 290 BFI_FWBOOT_TYPE_NORMAL = 0, 291 BFI_FWBOOT_TYPE_FLASH = 1, 292 BFI_FWBOOT_TYPE_MEMTEST = 2, 293 }; 294 295 enum bfi_port_mode { 296 BFI_PORT_MODE_FC = 1, 297 BFI_PORT_MODE_ETH = 2, 298 }; 299 300 struct bfi_ioc_hbeat { 301 struct bfi_mhdr mh; /*!< common msg header */ 302 u32 hb_count; /*!< current heart beat count */ 303 }; 304 305 /* IOC hardware/firmware state */ 306 enum bfi_ioc_state { 307 BFI_IOC_UNINIT = 0, /*!< not initialized */ 308 BFI_IOC_INITING = 1, /*!< h/w is being initialized */ 309 BFI_IOC_HWINIT = 2, /*!< h/w is initialized */ 310 BFI_IOC_CFG = 3, /*!< IOC configuration in progress */ 311 BFI_IOC_OP = 4, /*!< IOC is operational */ 312 BFI_IOC_DISABLING = 5, /*!< IOC is being disabled */ 313 BFI_IOC_DISABLED = 6, /*!< IOC is disabled */ 314 BFI_IOC_CFG_DISABLED = 7, /*!< IOC is being disabled;transient */ 315 BFI_IOC_FAIL = 8, /*!< IOC heart-beat failure */ 316 BFI_IOC_MEMTEST = 9, /*!< IOC is doing memtest */ 317 }; 318 319 #define BFI_IOC_ENDIAN_SIG 0x12345678 320 321 enum { 322 BFI_ADAPTER_TYPE_FC = 0x01, /*!< FC adapters */ 323 BFI_ADAPTER_TYPE_MK = 0x0f0000, /*!< adapter type mask */ 324 BFI_ADAPTER_TYPE_SH = 16, /*!< adapter type shift */ 325 BFI_ADAPTER_NPORTS_MK = 0xff00, /*!< number of ports mask */ 326 BFI_ADAPTER_NPORTS_SH = 8, /*!< number of ports shift */ 327 BFI_ADAPTER_SPEED_MK = 0xff, /*!< adapter speed mask */ 328 BFI_ADAPTER_SPEED_SH = 0, /*!< adapter speed shift */ 329 BFI_ADAPTER_PROTO = 0x100000, /*!< prototype adapaters */ 330 BFI_ADAPTER_TTV = 0x200000, /*!< TTV debug capable */ 331 BFI_ADAPTER_UNSUPP = 0x400000, /*!< unknown adapter type */ 332 }; 333 334 #define BFI_ADAPTER_GETP(__prop, __adap_prop) \ 335 (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \ 336 BFI_ADAPTER_ ## __prop ## _SH) 337 #define BFI_ADAPTER_SETP(__prop, __val) \ 338 ((__val) << BFI_ADAPTER_ ## __prop ## _SH) 339 #define BFI_ADAPTER_IS_PROTO(__adap_type) \ 340 ((__adap_type) & BFI_ADAPTER_PROTO) 341 #define BFI_ADAPTER_IS_TTV(__adap_type) \ 342 ((__adap_type) & BFI_ADAPTER_TTV) 343 #define BFI_ADAPTER_IS_UNSUPP(__adap_type) \ 344 ((__adap_type) & BFI_ADAPTER_UNSUPP) 345 #define BFI_ADAPTER_IS_SPECIAL(__adap_type) \ 346 ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \ 347 BFI_ADAPTER_UNSUPP)) 348 349 /* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages */ 350 struct bfi_ioc_ctrl_req { 351 struct bfi_mhdr mh; 352 u16 clscode; 353 u16 rsvd; 354 u32 tv_sec; 355 }; 356 357 /* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */ 358 struct bfi_ioc_ctrl_reply { 359 struct bfi_mhdr mh; /*!< Common msg header */ 360 u8 status; /*!< enable/disable status */ 361 u8 port_mode; /*!< enum bfa_mode */ 362 u8 cap_bm; /*!< capability bit mask */ 363 u8 rsvd; 364 }; 365 366 #define BFI_IOC_MSGSZ 8 367 /* H2I Messages */ 368 union bfi_ioc_h2i_msg_u { 369 struct bfi_mhdr mh; 370 struct bfi_ioc_ctrl_req enable_req; 371 struct bfi_ioc_ctrl_req disable_req; 372 struct bfi_ioc_getattr_req getattr_req; 373 u32 mboxmsg[BFI_IOC_MSGSZ]; 374 }; 375 376 /* I2H Messages */ 377 union bfi_ioc_i2h_msg_u { 378 struct bfi_mhdr mh; 379 struct bfi_ioc_ctrl_reply fw_event; 380 u32 mboxmsg[BFI_IOC_MSGSZ]; 381 }; 382 383 /*---------------------------------------------------------------------- 384 * MSGQ 385 *---------------------------------------------------------------------- 386 */ 387 388 enum bfi_msgq_h2i_msgs { 389 BFI_MSGQ_H2I_INIT_REQ = 1, 390 BFI_MSGQ_H2I_DOORBELL_PI = 2, 391 BFI_MSGQ_H2I_DOORBELL_CI = 3, 392 BFI_MSGQ_H2I_CMDQ_COPY_RSP = 4, 393 }; 394 395 enum bfi_msgq_i2h_msgs { 396 BFI_MSGQ_I2H_INIT_RSP = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ), 397 BFI_MSGQ_I2H_DOORBELL_PI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI), 398 BFI_MSGQ_I2H_DOORBELL_CI = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI), 399 BFI_MSGQ_I2H_CMDQ_COPY_REQ = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP), 400 }; 401 402 /* Messages(commands/responsed/AENS will have the following header */ 403 struct bfi_msgq_mhdr { 404 u8 msg_class; 405 u8 msg_id; 406 u16 msg_token; 407 u16 num_entries; 408 u8 enet_id; 409 u8 rsvd[1]; 410 }; 411 412 #define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \ 413 (_mh).msg_class = (_mc); \ 414 (_mh).msg_id = (_mid); \ 415 (_mh).msg_token = (_tok); \ 416 (_mh).enet_id = (_enet_id); \ 417 } while (0) 418 419 /* 420 * Mailbox for messaging interface 421 */ 422 #define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */ 423 #define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */ 424 425 #define bfi_msgq_num_cmd_entries(_size) \ 426 (((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE) 427 428 struct bfi_msgq { 429 union bfi_addr_u addr; 430 u16 q_depth; /* Total num of entries in the queue */ 431 u8 rsvd[2]; 432 }; 433 434 /* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */ 435 struct bfi_msgq_cfg_req { 436 struct bfi_mhdr mh; 437 struct bfi_msgq cmdq; 438 struct bfi_msgq rspq; 439 }; 440 441 /* BFI_ENET_MSGQ_CFG_RSP */ 442 struct bfi_msgq_cfg_rsp { 443 struct bfi_mhdr mh; 444 u8 cmd_status; 445 u8 rsvd[3]; 446 }; 447 448 /* BFI_MSGQ_H2I_DOORBELL */ 449 struct bfi_msgq_h2i_db { 450 struct bfi_mhdr mh; 451 union { 452 u16 cmdq_pi; 453 u16 rspq_ci; 454 } idx; 455 }; 456 457 /* BFI_MSGQ_I2H_DOORBELL */ 458 struct bfi_msgq_i2h_db { 459 struct bfi_mhdr mh; 460 union { 461 u16 rspq_pi; 462 u16 cmdq_ci; 463 } idx; 464 }; 465 466 #define BFI_CMD_COPY_SZ 28 467 468 /* BFI_MSGQ_H2I_CMD_COPY_RSP */ 469 struct bfi_msgq_h2i_cmdq_copy_rsp { 470 struct bfi_mhdr mh; 471 u8 data[BFI_CMD_COPY_SZ]; 472 }; 473 474 /* BFI_MSGQ_I2H_CMD_COPY_REQ */ 475 struct bfi_msgq_i2h_cmdq_copy_req { 476 struct bfi_mhdr mh; 477 u16 offset; 478 u16 len; 479 }; 480 481 /* 482 * FLASH module specific 483 */ 484 enum bfi_flash_h2i_msgs { 485 BFI_FLASH_H2I_QUERY_REQ = 1, 486 BFI_FLASH_H2I_ERASE_REQ = 2, 487 BFI_FLASH_H2I_WRITE_REQ = 3, 488 BFI_FLASH_H2I_READ_REQ = 4, 489 BFI_FLASH_H2I_BOOT_VER_REQ = 5, 490 }; 491 492 enum bfi_flash_i2h_msgs { 493 BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1), 494 BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2), 495 BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3), 496 BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4), 497 BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5), 498 BFI_FLASH_I2H_EVENT = BFA_I2HM(127), 499 }; 500 501 /* 502 * Flash query request 503 */ 504 struct bfi_flash_query_req { 505 struct bfi_mhdr mh; /* Common msg header */ 506 struct bfi_alen alen; 507 }; 508 509 /* 510 * Flash write request 511 */ 512 struct bfi_flash_write_req { 513 struct bfi_mhdr mh; /* Common msg header */ 514 struct bfi_alen alen; 515 u32 type; /* partition type */ 516 u8 instance; /* partition instance */ 517 u8 last; 518 u8 rsv[2]; 519 u32 offset; 520 u32 length; 521 }; 522 523 /* 524 * Flash read request 525 */ 526 struct bfi_flash_read_req { 527 struct bfi_mhdr mh; /* Common msg header */ 528 u32 type; /* partition type */ 529 u8 instance; /* partition instance */ 530 u8 rsv[3]; 531 u32 offset; 532 u32 length; 533 struct bfi_alen alen; 534 }; 535 536 /* 537 * Flash query response 538 */ 539 struct bfi_flash_query_rsp { 540 struct bfi_mhdr mh; /* Common msg header */ 541 u32 status; 542 }; 543 544 /* 545 * Flash read response 546 */ 547 struct bfi_flash_read_rsp { 548 struct bfi_mhdr mh; /* Common msg header */ 549 u32 type; /* partition type */ 550 u8 instance; /* partition instance */ 551 u8 rsv[3]; 552 u32 status; 553 u32 length; 554 }; 555 556 /* 557 * Flash write response 558 */ 559 struct bfi_flash_write_rsp { 560 struct bfi_mhdr mh; /* Common msg header */ 561 u32 type; /* partition type */ 562 u8 instance; /* partition instance */ 563 u8 rsv[3]; 564 u32 status; 565 u32 length; 566 }; 567 568 #pragma pack() 569 570 #endif /* __BFI_H__ */ 571