1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Linux network driver for QLogic BR-series Converged Network Adapter. 4 */ 5 /* 6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 7 * Copyright (c) 2014-2015 QLogic Corporation 8 * All rights reserved 9 * www.qlogic.com 10 */ 11 12 #include "bfa_ioc.h" 13 #include "bfi_reg.h" 14 #include "bfa_defs.h" 15 16 /* IOC local definitions */ 17 18 /* Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details. */ 19 20 #define bfa_ioc_firmware_lock(__ioc) \ 21 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc)) 22 #define bfa_ioc_firmware_unlock(__ioc) \ 23 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc)) 24 #define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc)) 25 #define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc)) 26 #define bfa_ioc_notify_fail(__ioc) \ 27 ((__ioc)->ioc_hwif->ioc_notify_fail(__ioc)) 28 #define bfa_ioc_sync_start(__ioc) \ 29 ((__ioc)->ioc_hwif->ioc_sync_start(__ioc)) 30 #define bfa_ioc_sync_join(__ioc) \ 31 ((__ioc)->ioc_hwif->ioc_sync_join(__ioc)) 32 #define bfa_ioc_sync_leave(__ioc) \ 33 ((__ioc)->ioc_hwif->ioc_sync_leave(__ioc)) 34 #define bfa_ioc_sync_ack(__ioc) \ 35 ((__ioc)->ioc_hwif->ioc_sync_ack(__ioc)) 36 #define bfa_ioc_sync_complete(__ioc) \ 37 ((__ioc)->ioc_hwif->ioc_sync_complete(__ioc)) 38 #define bfa_ioc_set_cur_ioc_fwstate(__ioc, __fwstate) \ 39 ((__ioc)->ioc_hwif->ioc_set_fwstate(__ioc, __fwstate)) 40 #define bfa_ioc_get_cur_ioc_fwstate(__ioc) \ 41 ((__ioc)->ioc_hwif->ioc_get_fwstate(__ioc)) 42 #define bfa_ioc_set_alt_ioc_fwstate(__ioc, __fwstate) \ 43 ((__ioc)->ioc_hwif->ioc_set_alt_fwstate(__ioc, __fwstate)) 44 45 static bool bfa_nw_auto_recover = true; 46 47 /* 48 * forward declarations 49 */ 50 static void bfa_ioc_hw_sem_init(struct bfa_ioc *ioc); 51 static void bfa_ioc_hw_sem_get(struct bfa_ioc *ioc); 52 static void bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc); 53 static void bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force); 54 static void bfa_ioc_poll_fwinit(struct bfa_ioc *ioc); 55 static void bfa_ioc_send_enable(struct bfa_ioc *ioc); 56 static void bfa_ioc_send_disable(struct bfa_ioc *ioc); 57 static void bfa_ioc_send_getattr(struct bfa_ioc *ioc); 58 static void bfa_ioc_hb_monitor(struct bfa_ioc *ioc); 59 static void bfa_ioc_hb_stop(struct bfa_ioc *ioc); 60 static void bfa_ioc_reset(struct bfa_ioc *ioc, bool force); 61 static void bfa_ioc_mbox_poll(struct bfa_ioc *ioc); 62 static void bfa_ioc_mbox_flush(struct bfa_ioc *ioc); 63 static void bfa_ioc_recover(struct bfa_ioc *ioc); 64 static void bfa_ioc_event_notify(struct bfa_ioc *, enum bfa_ioc_event); 65 static void bfa_ioc_disable_comp(struct bfa_ioc *ioc); 66 static void bfa_ioc_lpu_stop(struct bfa_ioc *ioc); 67 static void bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc); 68 static void bfa_ioc_fail_notify(struct bfa_ioc *ioc); 69 static void bfa_ioc_pf_enabled(struct bfa_ioc *ioc); 70 static void bfa_ioc_pf_disabled(struct bfa_ioc *ioc); 71 static void bfa_ioc_pf_failed(struct bfa_ioc *ioc); 72 static void bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc); 73 static void bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc); 74 static enum bfa_status bfa_ioc_boot(struct bfa_ioc *ioc, 75 enum bfi_fwboot_type boot_type, u32 boot_param); 76 static u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr); 77 static void bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, 78 char *serial_num); 79 static void bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, 80 char *fw_ver); 81 static void bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, 82 char *chip_rev); 83 static void bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, 84 char *optrom_ver); 85 static void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc, 86 char *manufacturer); 87 static void bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model); 88 static u64 bfa_ioc_get_pwwn(struct bfa_ioc *ioc); 89 90 /* IOC state machine definitions/declarations */ 91 enum ioc_event { 92 IOC_E_RESET = 1, /*!< IOC reset request */ 93 IOC_E_ENABLE = 2, /*!< IOC enable request */ 94 IOC_E_DISABLE = 3, /*!< IOC disable request */ 95 IOC_E_DETACH = 4, /*!< driver detach cleanup */ 96 IOC_E_ENABLED = 5, /*!< f/w enabled */ 97 IOC_E_FWRSP_GETATTR = 6, /*!< IOC get attribute response */ 98 IOC_E_DISABLED = 7, /*!< f/w disabled */ 99 IOC_E_PFFAILED = 8, /*!< failure notice by iocpf sm */ 100 IOC_E_HBFAIL = 9, /*!< heartbeat failure */ 101 IOC_E_HWERROR = 10, /*!< hardware error interrupt */ 102 IOC_E_TIMEOUT = 11, /*!< timeout */ 103 IOC_E_HWFAILED = 12, /*!< PCI mapping failure notice */ 104 }; 105 106 bfa_fsm_state_decl(bfa_ioc, uninit, struct bfa_ioc, enum ioc_event); 107 bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc, enum ioc_event); 108 bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc, enum ioc_event); 109 bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc, enum ioc_event); 110 bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc, enum ioc_event); 111 bfa_fsm_state_decl(bfa_ioc, fail_retry, struct bfa_ioc, enum ioc_event); 112 bfa_fsm_state_decl(bfa_ioc, fail, struct bfa_ioc, enum ioc_event); 113 bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc, enum ioc_event); 114 bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc, enum ioc_event); 115 bfa_fsm_state_decl(bfa_ioc, hwfail, struct bfa_ioc, enum ioc_event); 116 117 static struct bfa_sm_table ioc_sm_table[] = { 118 {BFA_SM(bfa_ioc_sm_uninit), BFA_IOC_UNINIT}, 119 {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET}, 120 {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_ENABLING}, 121 {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR}, 122 {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL}, 123 {BFA_SM(bfa_ioc_sm_fail_retry), BFA_IOC_INITFAIL}, 124 {BFA_SM(bfa_ioc_sm_fail), BFA_IOC_FAIL}, 125 {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING}, 126 {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED}, 127 {BFA_SM(bfa_ioc_sm_hwfail), BFA_IOC_HWFAIL}, 128 }; 129 130 /* 131 * Forward declareations for iocpf state machine 132 */ 133 static void bfa_iocpf_enable(struct bfa_ioc *ioc); 134 static void bfa_iocpf_disable(struct bfa_ioc *ioc); 135 static void bfa_iocpf_fail(struct bfa_ioc *ioc); 136 static void bfa_iocpf_initfail(struct bfa_ioc *ioc); 137 static void bfa_iocpf_getattrfail(struct bfa_ioc *ioc); 138 static void bfa_iocpf_stop(struct bfa_ioc *ioc); 139 140 /* IOCPF state machine events */ 141 enum iocpf_event { 142 IOCPF_E_ENABLE = 1, /*!< IOCPF enable request */ 143 IOCPF_E_DISABLE = 2, /*!< IOCPF disable request */ 144 IOCPF_E_STOP = 3, /*!< stop on driver detach */ 145 IOCPF_E_FWREADY = 4, /*!< f/w initialization done */ 146 IOCPF_E_FWRSP_ENABLE = 5, /*!< enable f/w response */ 147 IOCPF_E_FWRSP_DISABLE = 6, /*!< disable f/w response */ 148 IOCPF_E_FAIL = 7, /*!< failure notice by ioc sm */ 149 IOCPF_E_INITFAIL = 8, /*!< init fail notice by ioc sm */ 150 IOCPF_E_GETATTRFAIL = 9, /*!< init fail notice by ioc sm */ 151 IOCPF_E_SEMLOCKED = 10, /*!< h/w semaphore is locked */ 152 IOCPF_E_TIMEOUT = 11, /*!< f/w response timeout */ 153 IOCPF_E_SEM_ERROR = 12, /*!< h/w sem mapping error */ 154 }; 155 156 /* IOCPF states */ 157 enum bfa_iocpf_state { 158 BFA_IOCPF_RESET = 1, /*!< IOC is in reset state */ 159 BFA_IOCPF_SEMWAIT = 2, /*!< Waiting for IOC h/w semaphore */ 160 BFA_IOCPF_HWINIT = 3, /*!< IOC h/w is being initialized */ 161 BFA_IOCPF_READY = 4, /*!< IOCPF is initialized */ 162 BFA_IOCPF_INITFAIL = 5, /*!< IOCPF failed */ 163 BFA_IOCPF_FAIL = 6, /*!< IOCPF failed */ 164 BFA_IOCPF_DISABLING = 7, /*!< IOCPF is being disabled */ 165 BFA_IOCPF_DISABLED = 8, /*!< IOCPF is disabled */ 166 BFA_IOCPF_FWMISMATCH = 9, /*!< IOC f/w different from drivers */ 167 }; 168 169 bfa_fsm_state_decl(bfa_iocpf, reset, struct bfa_iocpf, enum iocpf_event); 170 bfa_fsm_state_decl(bfa_iocpf, fwcheck, struct bfa_iocpf, enum iocpf_event); 171 bfa_fsm_state_decl(bfa_iocpf, mismatch, struct bfa_iocpf, enum iocpf_event); 172 bfa_fsm_state_decl(bfa_iocpf, semwait, struct bfa_iocpf, enum iocpf_event); 173 bfa_fsm_state_decl(bfa_iocpf, hwinit, struct bfa_iocpf, enum iocpf_event); 174 bfa_fsm_state_decl(bfa_iocpf, enabling, struct bfa_iocpf, enum iocpf_event); 175 bfa_fsm_state_decl(bfa_iocpf, ready, struct bfa_iocpf, enum iocpf_event); 176 bfa_fsm_state_decl(bfa_iocpf, initfail_sync, struct bfa_iocpf, 177 enum iocpf_event); 178 bfa_fsm_state_decl(bfa_iocpf, initfail, struct bfa_iocpf, enum iocpf_event); 179 bfa_fsm_state_decl(bfa_iocpf, fail_sync, struct bfa_iocpf, enum iocpf_event); 180 bfa_fsm_state_decl(bfa_iocpf, fail, struct bfa_iocpf, enum iocpf_event); 181 bfa_fsm_state_decl(bfa_iocpf, disabling, struct bfa_iocpf, enum iocpf_event); 182 bfa_fsm_state_decl(bfa_iocpf, disabling_sync, struct bfa_iocpf, 183 enum iocpf_event); 184 bfa_fsm_state_decl(bfa_iocpf, disabled, struct bfa_iocpf, enum iocpf_event); 185 186 static struct bfa_sm_table iocpf_sm_table[] = { 187 {BFA_SM(bfa_iocpf_sm_reset), BFA_IOCPF_RESET}, 188 {BFA_SM(bfa_iocpf_sm_fwcheck), BFA_IOCPF_FWMISMATCH}, 189 {BFA_SM(bfa_iocpf_sm_mismatch), BFA_IOCPF_FWMISMATCH}, 190 {BFA_SM(bfa_iocpf_sm_semwait), BFA_IOCPF_SEMWAIT}, 191 {BFA_SM(bfa_iocpf_sm_hwinit), BFA_IOCPF_HWINIT}, 192 {BFA_SM(bfa_iocpf_sm_enabling), BFA_IOCPF_HWINIT}, 193 {BFA_SM(bfa_iocpf_sm_ready), BFA_IOCPF_READY}, 194 {BFA_SM(bfa_iocpf_sm_initfail_sync), BFA_IOCPF_INITFAIL}, 195 {BFA_SM(bfa_iocpf_sm_initfail), BFA_IOCPF_INITFAIL}, 196 {BFA_SM(bfa_iocpf_sm_fail_sync), BFA_IOCPF_FAIL}, 197 {BFA_SM(bfa_iocpf_sm_fail), BFA_IOCPF_FAIL}, 198 {BFA_SM(bfa_iocpf_sm_disabling), BFA_IOCPF_DISABLING}, 199 {BFA_SM(bfa_iocpf_sm_disabling_sync), BFA_IOCPF_DISABLING}, 200 {BFA_SM(bfa_iocpf_sm_disabled), BFA_IOCPF_DISABLED}, 201 }; 202 203 /* IOC State Machine */ 204 205 /* Beginning state. IOC uninit state. */ 206 static void 207 bfa_ioc_sm_uninit_entry(struct bfa_ioc *ioc) 208 { 209 } 210 211 /* IOC is in uninit state. */ 212 static void 213 bfa_ioc_sm_uninit(struct bfa_ioc *ioc, enum ioc_event event) 214 { 215 switch (event) { 216 case IOC_E_RESET: 217 bfa_fsm_set_state(ioc, bfa_ioc_sm_reset); 218 break; 219 220 default: 221 bfa_sm_fault(event); 222 } 223 } 224 225 /* Reset entry actions -- initialize state machine */ 226 static void 227 bfa_ioc_sm_reset_entry(struct bfa_ioc *ioc) 228 { 229 bfa_fsm_set_state(&ioc->iocpf, bfa_iocpf_sm_reset); 230 } 231 232 /* IOC is in reset state. */ 233 static void 234 bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event) 235 { 236 switch (event) { 237 case IOC_E_ENABLE: 238 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling); 239 break; 240 241 case IOC_E_DISABLE: 242 bfa_ioc_disable_comp(ioc); 243 break; 244 245 case IOC_E_DETACH: 246 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit); 247 break; 248 249 default: 250 bfa_sm_fault(event); 251 } 252 } 253 254 static void 255 bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc) 256 { 257 bfa_iocpf_enable(ioc); 258 } 259 260 /* Host IOC function is being enabled, awaiting response from firmware. 261 * Semaphore is acquired. 262 */ 263 static void 264 bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event) 265 { 266 switch (event) { 267 case IOC_E_ENABLED: 268 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr); 269 break; 270 271 case IOC_E_PFFAILED: 272 /* !!! fall through !!! */ 273 case IOC_E_HWERROR: 274 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 275 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail); 276 if (event != IOC_E_PFFAILED) 277 bfa_iocpf_initfail(ioc); 278 break; 279 280 case IOC_E_HWFAILED: 281 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 282 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail); 283 break; 284 285 case IOC_E_DISABLE: 286 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling); 287 break; 288 289 case IOC_E_DETACH: 290 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit); 291 bfa_iocpf_stop(ioc); 292 break; 293 294 case IOC_E_ENABLE: 295 break; 296 297 default: 298 bfa_sm_fault(event); 299 } 300 } 301 302 /* Semaphore should be acquired for version check. */ 303 static void 304 bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc) 305 { 306 mod_timer(&ioc->ioc_timer, jiffies + 307 msecs_to_jiffies(BFA_IOC_TOV)); 308 bfa_ioc_send_getattr(ioc); 309 } 310 311 /* IOC configuration in progress. Timer is active. */ 312 static void 313 bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event) 314 { 315 switch (event) { 316 case IOC_E_FWRSP_GETATTR: 317 del_timer(&ioc->ioc_timer); 318 bfa_fsm_set_state(ioc, bfa_ioc_sm_op); 319 break; 320 321 case IOC_E_PFFAILED: 322 case IOC_E_HWERROR: 323 del_timer(&ioc->ioc_timer); 324 /* fall through */ 325 case IOC_E_TIMEOUT: 326 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 327 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail); 328 if (event != IOC_E_PFFAILED) 329 bfa_iocpf_getattrfail(ioc); 330 break; 331 332 case IOC_E_DISABLE: 333 del_timer(&ioc->ioc_timer); 334 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling); 335 break; 336 337 case IOC_E_ENABLE: 338 break; 339 340 default: 341 bfa_sm_fault(event); 342 } 343 } 344 345 static void 346 bfa_ioc_sm_op_entry(struct bfa_ioc *ioc) 347 { 348 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK); 349 bfa_ioc_event_notify(ioc, BFA_IOC_E_ENABLED); 350 bfa_ioc_hb_monitor(ioc); 351 } 352 353 static void 354 bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event) 355 { 356 switch (event) { 357 case IOC_E_ENABLE: 358 break; 359 360 case IOC_E_DISABLE: 361 bfa_ioc_hb_stop(ioc); 362 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling); 363 break; 364 365 case IOC_E_PFFAILED: 366 case IOC_E_HWERROR: 367 bfa_ioc_hb_stop(ioc); 368 /* !!! fall through !!! */ 369 case IOC_E_HBFAIL: 370 if (ioc->iocpf.auto_recover) 371 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry); 372 else 373 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail); 374 375 bfa_ioc_fail_notify(ioc); 376 377 if (event != IOC_E_PFFAILED) 378 bfa_iocpf_fail(ioc); 379 break; 380 381 default: 382 bfa_sm_fault(event); 383 } 384 } 385 386 static void 387 bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc) 388 { 389 bfa_iocpf_disable(ioc); 390 } 391 392 /* IOC is being disabled */ 393 static void 394 bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event) 395 { 396 switch (event) { 397 case IOC_E_DISABLED: 398 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled); 399 break; 400 401 case IOC_E_HWERROR: 402 /* 403 * No state change. Will move to disabled state 404 * after iocpf sm completes failure processing and 405 * moves to disabled state. 406 */ 407 bfa_iocpf_fail(ioc); 408 break; 409 410 case IOC_E_HWFAILED: 411 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail); 412 bfa_ioc_disable_comp(ioc); 413 break; 414 415 default: 416 bfa_sm_fault(event); 417 } 418 } 419 420 /* IOC disable completion entry. */ 421 static void 422 bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc) 423 { 424 bfa_ioc_disable_comp(ioc); 425 } 426 427 static void 428 bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event) 429 { 430 switch (event) { 431 case IOC_E_ENABLE: 432 bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling); 433 break; 434 435 case IOC_E_DISABLE: 436 ioc->cbfn->disable_cbfn(ioc->bfa); 437 break; 438 439 case IOC_E_DETACH: 440 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit); 441 bfa_iocpf_stop(ioc); 442 break; 443 444 default: 445 bfa_sm_fault(event); 446 } 447 } 448 449 static void 450 bfa_ioc_sm_fail_retry_entry(struct bfa_ioc *ioc) 451 { 452 } 453 454 /* Hardware initialization retry. */ 455 static void 456 bfa_ioc_sm_fail_retry(struct bfa_ioc *ioc, enum ioc_event event) 457 { 458 switch (event) { 459 case IOC_E_ENABLED: 460 bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr); 461 break; 462 463 case IOC_E_PFFAILED: 464 case IOC_E_HWERROR: 465 /** 466 * Initialization retry failed. 467 */ 468 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 469 bfa_fsm_set_state(ioc, bfa_ioc_sm_fail); 470 if (event != IOC_E_PFFAILED) 471 bfa_iocpf_initfail(ioc); 472 break; 473 474 case IOC_E_HWFAILED: 475 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 476 bfa_fsm_set_state(ioc, bfa_ioc_sm_hwfail); 477 break; 478 479 case IOC_E_ENABLE: 480 break; 481 482 case IOC_E_DISABLE: 483 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling); 484 break; 485 486 case IOC_E_DETACH: 487 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit); 488 bfa_iocpf_stop(ioc); 489 break; 490 491 default: 492 bfa_sm_fault(event); 493 } 494 } 495 496 static void 497 bfa_ioc_sm_fail_entry(struct bfa_ioc *ioc) 498 { 499 } 500 501 /* IOC failure. */ 502 static void 503 bfa_ioc_sm_fail(struct bfa_ioc *ioc, enum ioc_event event) 504 { 505 switch (event) { 506 case IOC_E_ENABLE: 507 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 508 break; 509 510 case IOC_E_DISABLE: 511 bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling); 512 break; 513 514 case IOC_E_DETACH: 515 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit); 516 bfa_iocpf_stop(ioc); 517 break; 518 519 case IOC_E_HWERROR: 520 /* HB failure notification, ignore. */ 521 break; 522 523 default: 524 bfa_sm_fault(event); 525 } 526 } 527 528 static void 529 bfa_ioc_sm_hwfail_entry(struct bfa_ioc *ioc) 530 { 531 } 532 533 /* IOC failure. */ 534 static void 535 bfa_ioc_sm_hwfail(struct bfa_ioc *ioc, enum ioc_event event) 536 { 537 switch (event) { 538 539 case IOC_E_ENABLE: 540 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 541 break; 542 543 case IOC_E_DISABLE: 544 ioc->cbfn->disable_cbfn(ioc->bfa); 545 break; 546 547 case IOC_E_DETACH: 548 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit); 549 break; 550 551 default: 552 bfa_sm_fault(event); 553 } 554 } 555 556 /* IOCPF State Machine */ 557 558 /* Reset entry actions -- initialize state machine */ 559 static void 560 bfa_iocpf_sm_reset_entry(struct bfa_iocpf *iocpf) 561 { 562 iocpf->fw_mismatch_notified = false; 563 iocpf->auto_recover = bfa_nw_auto_recover; 564 } 565 566 /* Beginning state. IOC is in reset state. */ 567 static void 568 bfa_iocpf_sm_reset(struct bfa_iocpf *iocpf, enum iocpf_event event) 569 { 570 switch (event) { 571 case IOCPF_E_ENABLE: 572 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck); 573 break; 574 575 case IOCPF_E_STOP: 576 break; 577 578 default: 579 bfa_sm_fault(event); 580 } 581 } 582 583 /* Semaphore should be acquired for version check. */ 584 static void 585 bfa_iocpf_sm_fwcheck_entry(struct bfa_iocpf *iocpf) 586 { 587 bfa_ioc_hw_sem_init(iocpf->ioc); 588 bfa_ioc_hw_sem_get(iocpf->ioc); 589 } 590 591 /* Awaiting h/w semaphore to continue with version check. */ 592 static void 593 bfa_iocpf_sm_fwcheck(struct bfa_iocpf *iocpf, enum iocpf_event event) 594 { 595 struct bfa_ioc *ioc = iocpf->ioc; 596 597 switch (event) { 598 case IOCPF_E_SEMLOCKED: 599 if (bfa_ioc_firmware_lock(ioc)) { 600 if (bfa_ioc_sync_start(ioc)) { 601 bfa_ioc_sync_join(ioc); 602 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit); 603 } else { 604 bfa_ioc_firmware_unlock(ioc); 605 bfa_nw_ioc_hw_sem_release(ioc); 606 mod_timer(&ioc->sem_timer, jiffies + 607 msecs_to_jiffies(BFA_IOC_HWSEM_TOV)); 608 } 609 } else { 610 bfa_nw_ioc_hw_sem_release(ioc); 611 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_mismatch); 612 } 613 break; 614 615 case IOCPF_E_SEM_ERROR: 616 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail); 617 bfa_ioc_pf_hwfailed(ioc); 618 break; 619 620 case IOCPF_E_DISABLE: 621 bfa_ioc_hw_sem_get_cancel(ioc); 622 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset); 623 bfa_ioc_pf_disabled(ioc); 624 break; 625 626 case IOCPF_E_STOP: 627 bfa_ioc_hw_sem_get_cancel(ioc); 628 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset); 629 break; 630 631 default: 632 bfa_sm_fault(event); 633 } 634 } 635 636 /* Notify enable completion callback */ 637 static void 638 bfa_iocpf_sm_mismatch_entry(struct bfa_iocpf *iocpf) 639 { 640 /* Call only the first time sm enters fwmismatch state. */ 641 if (!iocpf->fw_mismatch_notified) 642 bfa_ioc_pf_fwmismatch(iocpf->ioc); 643 644 iocpf->fw_mismatch_notified = true; 645 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies + 646 msecs_to_jiffies(BFA_IOC_TOV)); 647 } 648 649 /* Awaiting firmware version match. */ 650 static void 651 bfa_iocpf_sm_mismatch(struct bfa_iocpf *iocpf, enum iocpf_event event) 652 { 653 struct bfa_ioc *ioc = iocpf->ioc; 654 655 switch (event) { 656 case IOCPF_E_TIMEOUT: 657 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck); 658 break; 659 660 case IOCPF_E_DISABLE: 661 del_timer(&ioc->iocpf_timer); 662 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset); 663 bfa_ioc_pf_disabled(ioc); 664 break; 665 666 case IOCPF_E_STOP: 667 del_timer(&ioc->iocpf_timer); 668 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset); 669 break; 670 671 default: 672 bfa_sm_fault(event); 673 } 674 } 675 676 /* Request for semaphore. */ 677 static void 678 bfa_iocpf_sm_semwait_entry(struct bfa_iocpf *iocpf) 679 { 680 bfa_ioc_hw_sem_get(iocpf->ioc); 681 } 682 683 /* Awaiting semaphore for h/w initialzation. */ 684 static void 685 bfa_iocpf_sm_semwait(struct bfa_iocpf *iocpf, enum iocpf_event event) 686 { 687 struct bfa_ioc *ioc = iocpf->ioc; 688 689 switch (event) { 690 case IOCPF_E_SEMLOCKED: 691 if (bfa_ioc_sync_complete(ioc)) { 692 bfa_ioc_sync_join(ioc); 693 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit); 694 } else { 695 bfa_nw_ioc_hw_sem_release(ioc); 696 mod_timer(&ioc->sem_timer, jiffies + 697 msecs_to_jiffies(BFA_IOC_HWSEM_TOV)); 698 } 699 break; 700 701 case IOCPF_E_SEM_ERROR: 702 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail); 703 bfa_ioc_pf_hwfailed(ioc); 704 break; 705 706 case IOCPF_E_DISABLE: 707 bfa_ioc_hw_sem_get_cancel(ioc); 708 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync); 709 break; 710 711 default: 712 bfa_sm_fault(event); 713 } 714 } 715 716 static void 717 bfa_iocpf_sm_hwinit_entry(struct bfa_iocpf *iocpf) 718 { 719 iocpf->poll_time = 0; 720 bfa_ioc_reset(iocpf->ioc, false); 721 } 722 723 /* Hardware is being initialized. Interrupts are enabled. 724 * Holding hardware semaphore lock. 725 */ 726 static void 727 bfa_iocpf_sm_hwinit(struct bfa_iocpf *iocpf, enum iocpf_event event) 728 { 729 struct bfa_ioc *ioc = iocpf->ioc; 730 731 switch (event) { 732 case IOCPF_E_FWREADY: 733 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_enabling); 734 break; 735 736 case IOCPF_E_TIMEOUT: 737 bfa_nw_ioc_hw_sem_release(ioc); 738 bfa_ioc_pf_failed(ioc); 739 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync); 740 break; 741 742 case IOCPF_E_DISABLE: 743 del_timer(&ioc->iocpf_timer); 744 bfa_ioc_sync_leave(ioc); 745 bfa_nw_ioc_hw_sem_release(ioc); 746 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled); 747 break; 748 749 default: 750 bfa_sm_fault(event); 751 } 752 } 753 754 static void 755 bfa_iocpf_sm_enabling_entry(struct bfa_iocpf *iocpf) 756 { 757 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies + 758 msecs_to_jiffies(BFA_IOC_TOV)); 759 /** 760 * Enable Interrupts before sending fw IOC ENABLE cmd. 761 */ 762 iocpf->ioc->cbfn->reset_cbfn(iocpf->ioc->bfa); 763 bfa_ioc_send_enable(iocpf->ioc); 764 } 765 766 /* Host IOC function is being enabled, awaiting response from firmware. 767 * Semaphore is acquired. 768 */ 769 static void 770 bfa_iocpf_sm_enabling(struct bfa_iocpf *iocpf, enum iocpf_event event) 771 { 772 struct bfa_ioc *ioc = iocpf->ioc; 773 774 switch (event) { 775 case IOCPF_E_FWRSP_ENABLE: 776 del_timer(&ioc->iocpf_timer); 777 bfa_nw_ioc_hw_sem_release(ioc); 778 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_ready); 779 break; 780 781 case IOCPF_E_INITFAIL: 782 del_timer(&ioc->iocpf_timer); 783 /* fall through */ 784 785 case IOCPF_E_TIMEOUT: 786 bfa_nw_ioc_hw_sem_release(ioc); 787 if (event == IOCPF_E_TIMEOUT) 788 bfa_ioc_pf_failed(ioc); 789 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync); 790 break; 791 792 case IOCPF_E_DISABLE: 793 del_timer(&ioc->iocpf_timer); 794 bfa_nw_ioc_hw_sem_release(ioc); 795 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling); 796 break; 797 798 default: 799 bfa_sm_fault(event); 800 } 801 } 802 803 static void 804 bfa_iocpf_sm_ready_entry(struct bfa_iocpf *iocpf) 805 { 806 bfa_ioc_pf_enabled(iocpf->ioc); 807 } 808 809 static void 810 bfa_iocpf_sm_ready(struct bfa_iocpf *iocpf, enum iocpf_event event) 811 { 812 switch (event) { 813 case IOCPF_E_DISABLE: 814 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling); 815 break; 816 817 case IOCPF_E_GETATTRFAIL: 818 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync); 819 break; 820 821 case IOCPF_E_FAIL: 822 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail_sync); 823 break; 824 825 default: 826 bfa_sm_fault(event); 827 } 828 } 829 830 static void 831 bfa_iocpf_sm_disabling_entry(struct bfa_iocpf *iocpf) 832 { 833 mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies + 834 msecs_to_jiffies(BFA_IOC_TOV)); 835 bfa_ioc_send_disable(iocpf->ioc); 836 } 837 838 /* IOC is being disabled */ 839 static void 840 bfa_iocpf_sm_disabling(struct bfa_iocpf *iocpf, enum iocpf_event event) 841 { 842 struct bfa_ioc *ioc = iocpf->ioc; 843 844 switch (event) { 845 case IOCPF_E_FWRSP_DISABLE: 846 del_timer(&ioc->iocpf_timer); 847 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync); 848 break; 849 850 case IOCPF_E_FAIL: 851 del_timer(&ioc->iocpf_timer); 852 /* fall through*/ 853 854 case IOCPF_E_TIMEOUT: 855 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL); 856 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync); 857 break; 858 859 case IOCPF_E_FWRSP_ENABLE: 860 break; 861 862 default: 863 bfa_sm_fault(event); 864 } 865 } 866 867 static void 868 bfa_iocpf_sm_disabling_sync_entry(struct bfa_iocpf *iocpf) 869 { 870 bfa_ioc_hw_sem_get(iocpf->ioc); 871 } 872 873 /* IOC hb ack request is being removed. */ 874 static void 875 bfa_iocpf_sm_disabling_sync(struct bfa_iocpf *iocpf, enum iocpf_event event) 876 { 877 struct bfa_ioc *ioc = iocpf->ioc; 878 879 switch (event) { 880 case IOCPF_E_SEMLOCKED: 881 bfa_ioc_sync_leave(ioc); 882 bfa_nw_ioc_hw_sem_release(ioc); 883 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled); 884 break; 885 886 case IOCPF_E_SEM_ERROR: 887 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail); 888 bfa_ioc_pf_hwfailed(ioc); 889 break; 890 891 case IOCPF_E_FAIL: 892 break; 893 894 default: 895 bfa_sm_fault(event); 896 } 897 } 898 899 /* IOC disable completion entry. */ 900 static void 901 bfa_iocpf_sm_disabled_entry(struct bfa_iocpf *iocpf) 902 { 903 bfa_ioc_mbox_flush(iocpf->ioc); 904 bfa_ioc_pf_disabled(iocpf->ioc); 905 } 906 907 static void 908 bfa_iocpf_sm_disabled(struct bfa_iocpf *iocpf, enum iocpf_event event) 909 { 910 struct bfa_ioc *ioc = iocpf->ioc; 911 912 switch (event) { 913 case IOCPF_E_ENABLE: 914 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait); 915 break; 916 917 case IOCPF_E_STOP: 918 bfa_ioc_firmware_unlock(ioc); 919 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset); 920 break; 921 922 default: 923 bfa_sm_fault(event); 924 } 925 } 926 927 static void 928 bfa_iocpf_sm_initfail_sync_entry(struct bfa_iocpf *iocpf) 929 { 930 bfa_nw_ioc_debug_save_ftrc(iocpf->ioc); 931 bfa_ioc_hw_sem_get(iocpf->ioc); 932 } 933 934 /* Hardware initialization failed. */ 935 static void 936 bfa_iocpf_sm_initfail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event) 937 { 938 struct bfa_ioc *ioc = iocpf->ioc; 939 940 switch (event) { 941 case IOCPF_E_SEMLOCKED: 942 bfa_ioc_notify_fail(ioc); 943 bfa_ioc_sync_leave(ioc); 944 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL); 945 bfa_nw_ioc_hw_sem_release(ioc); 946 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail); 947 break; 948 949 case IOCPF_E_SEM_ERROR: 950 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail); 951 bfa_ioc_pf_hwfailed(ioc); 952 break; 953 954 case IOCPF_E_DISABLE: 955 bfa_ioc_hw_sem_get_cancel(ioc); 956 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync); 957 break; 958 959 case IOCPF_E_STOP: 960 bfa_ioc_hw_sem_get_cancel(ioc); 961 bfa_ioc_firmware_unlock(ioc); 962 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset); 963 break; 964 965 case IOCPF_E_FAIL: 966 break; 967 968 default: 969 bfa_sm_fault(event); 970 } 971 } 972 973 static void 974 bfa_iocpf_sm_initfail_entry(struct bfa_iocpf *iocpf) 975 { 976 } 977 978 /* Hardware initialization failed. */ 979 static void 980 bfa_iocpf_sm_initfail(struct bfa_iocpf *iocpf, enum iocpf_event event) 981 { 982 struct bfa_ioc *ioc = iocpf->ioc; 983 984 switch (event) { 985 case IOCPF_E_DISABLE: 986 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled); 987 break; 988 989 case IOCPF_E_STOP: 990 bfa_ioc_firmware_unlock(ioc); 991 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset); 992 break; 993 994 default: 995 bfa_sm_fault(event); 996 } 997 } 998 999 static void 1000 bfa_iocpf_sm_fail_sync_entry(struct bfa_iocpf *iocpf) 1001 { 1002 /** 1003 * Mark IOC as failed in hardware and stop firmware. 1004 */ 1005 bfa_ioc_lpu_stop(iocpf->ioc); 1006 1007 /** 1008 * Flush any queued up mailbox requests. 1009 */ 1010 bfa_ioc_mbox_flush(iocpf->ioc); 1011 bfa_ioc_hw_sem_get(iocpf->ioc); 1012 } 1013 1014 /* IOC is in failed state. */ 1015 static void 1016 bfa_iocpf_sm_fail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event) 1017 { 1018 struct bfa_ioc *ioc = iocpf->ioc; 1019 1020 switch (event) { 1021 case IOCPF_E_SEMLOCKED: 1022 bfa_ioc_sync_ack(ioc); 1023 bfa_ioc_notify_fail(ioc); 1024 if (!iocpf->auto_recover) { 1025 bfa_ioc_sync_leave(ioc); 1026 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL); 1027 bfa_nw_ioc_hw_sem_release(ioc); 1028 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail); 1029 } else { 1030 if (bfa_ioc_sync_complete(ioc)) 1031 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit); 1032 else { 1033 bfa_nw_ioc_hw_sem_release(ioc); 1034 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait); 1035 } 1036 } 1037 break; 1038 1039 case IOCPF_E_SEM_ERROR: 1040 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail); 1041 bfa_ioc_pf_hwfailed(ioc); 1042 break; 1043 1044 case IOCPF_E_DISABLE: 1045 bfa_ioc_hw_sem_get_cancel(ioc); 1046 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync); 1047 break; 1048 1049 case IOCPF_E_FAIL: 1050 break; 1051 1052 default: 1053 bfa_sm_fault(event); 1054 } 1055 } 1056 1057 static void 1058 bfa_iocpf_sm_fail_entry(struct bfa_iocpf *iocpf) 1059 { 1060 } 1061 1062 /* IOC is in failed state. */ 1063 static void 1064 bfa_iocpf_sm_fail(struct bfa_iocpf *iocpf, enum iocpf_event event) 1065 { 1066 switch (event) { 1067 case IOCPF_E_DISABLE: 1068 bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled); 1069 break; 1070 1071 default: 1072 bfa_sm_fault(event); 1073 } 1074 } 1075 1076 /* BFA IOC private functions */ 1077 1078 /* Notify common modules registered for notification. */ 1079 static void 1080 bfa_ioc_event_notify(struct bfa_ioc *ioc, enum bfa_ioc_event event) 1081 { 1082 struct bfa_ioc_notify *notify; 1083 1084 list_for_each_entry(notify, &ioc->notify_q, qe) 1085 notify->cbfn(notify->cbarg, event); 1086 } 1087 1088 static void 1089 bfa_ioc_disable_comp(struct bfa_ioc *ioc) 1090 { 1091 ioc->cbfn->disable_cbfn(ioc->bfa); 1092 bfa_ioc_event_notify(ioc, BFA_IOC_E_DISABLED); 1093 } 1094 1095 bool 1096 bfa_nw_ioc_sem_get(void __iomem *sem_reg) 1097 { 1098 u32 r32; 1099 int cnt = 0; 1100 #define BFA_SEM_SPINCNT 3000 1101 1102 r32 = readl(sem_reg); 1103 1104 while ((r32 & 1) && (cnt < BFA_SEM_SPINCNT)) { 1105 cnt++; 1106 udelay(2); 1107 r32 = readl(sem_reg); 1108 } 1109 1110 if (!(r32 & 1)) 1111 return true; 1112 1113 return false; 1114 } 1115 1116 void 1117 bfa_nw_ioc_sem_release(void __iomem *sem_reg) 1118 { 1119 readl(sem_reg); 1120 writel(1, sem_reg); 1121 } 1122 1123 /* Clear fwver hdr */ 1124 static void 1125 bfa_ioc_fwver_clear(struct bfa_ioc *ioc) 1126 { 1127 u32 pgnum, loff = 0; 1128 int i; 1129 1130 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, loff); 1131 writel(pgnum, ioc->ioc_regs.host_page_num_fn); 1132 1133 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32)); i++) { 1134 writel(0, ioc->ioc_regs.smem_page_start + loff); 1135 loff += sizeof(u32); 1136 } 1137 } 1138 1139 1140 static void 1141 bfa_ioc_hw_sem_init(struct bfa_ioc *ioc) 1142 { 1143 struct bfi_ioc_image_hdr fwhdr; 1144 u32 fwstate, r32; 1145 1146 /* Spin on init semaphore to serialize. */ 1147 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg); 1148 while (r32 & 0x1) { 1149 udelay(20); 1150 r32 = readl(ioc->ioc_regs.ioc_init_sem_reg); 1151 } 1152 1153 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc); 1154 if (fwstate == BFI_IOC_UNINIT) { 1155 writel(1, ioc->ioc_regs.ioc_init_sem_reg); 1156 return; 1157 } 1158 1159 bfa_nw_ioc_fwver_get(ioc, &fwhdr); 1160 1161 if (swab32(fwhdr.exec) == BFI_FWBOOT_TYPE_NORMAL) { 1162 writel(1, ioc->ioc_regs.ioc_init_sem_reg); 1163 return; 1164 } 1165 1166 bfa_ioc_fwver_clear(ioc); 1167 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_UNINIT); 1168 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_UNINIT); 1169 1170 /* 1171 * Try to lock and then unlock the semaphore. 1172 */ 1173 readl(ioc->ioc_regs.ioc_sem_reg); 1174 writel(1, ioc->ioc_regs.ioc_sem_reg); 1175 1176 /* Unlock init semaphore */ 1177 writel(1, ioc->ioc_regs.ioc_init_sem_reg); 1178 } 1179 1180 static void 1181 bfa_ioc_hw_sem_get(struct bfa_ioc *ioc) 1182 { 1183 u32 r32; 1184 1185 /** 1186 * First read to the semaphore register will return 0, subsequent reads 1187 * will return 1. Semaphore is released by writing 1 to the register 1188 */ 1189 r32 = readl(ioc->ioc_regs.ioc_sem_reg); 1190 if (r32 == ~0) { 1191 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEM_ERROR); 1192 return; 1193 } 1194 if (!(r32 & 1)) { 1195 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED); 1196 return; 1197 } 1198 1199 mod_timer(&ioc->sem_timer, jiffies + 1200 msecs_to_jiffies(BFA_IOC_HWSEM_TOV)); 1201 } 1202 1203 void 1204 bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc) 1205 { 1206 writel(1, ioc->ioc_regs.ioc_sem_reg); 1207 } 1208 1209 static void 1210 bfa_ioc_hw_sem_get_cancel(struct bfa_ioc *ioc) 1211 { 1212 del_timer(&ioc->sem_timer); 1213 } 1214 1215 /* Initialize LPU local memory (aka secondary memory / SRAM) */ 1216 static void 1217 bfa_ioc_lmem_init(struct bfa_ioc *ioc) 1218 { 1219 u32 pss_ctl; 1220 int i; 1221 #define PSS_LMEM_INIT_TIME 10000 1222 1223 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg); 1224 pss_ctl &= ~__PSS_LMEM_RESET; 1225 pss_ctl |= __PSS_LMEM_INIT_EN; 1226 1227 /* 1228 * i2c workaround 12.5khz clock 1229 */ 1230 pss_ctl |= __PSS_I2C_CLK_DIV(3UL); 1231 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg); 1232 1233 /** 1234 * wait for memory initialization to be complete 1235 */ 1236 i = 0; 1237 do { 1238 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg); 1239 i++; 1240 } while (!(pss_ctl & __PSS_LMEM_INIT_DONE) && (i < PSS_LMEM_INIT_TIME)); 1241 1242 /** 1243 * If memory initialization is not successful, IOC timeout will catch 1244 * such failures. 1245 */ 1246 BUG_ON(!(pss_ctl & __PSS_LMEM_INIT_DONE)); 1247 1248 pss_ctl &= ~(__PSS_LMEM_INIT_DONE | __PSS_LMEM_INIT_EN); 1249 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg); 1250 } 1251 1252 static void 1253 bfa_ioc_lpu_start(struct bfa_ioc *ioc) 1254 { 1255 u32 pss_ctl; 1256 1257 /** 1258 * Take processor out of reset. 1259 */ 1260 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg); 1261 pss_ctl &= ~__PSS_LPU0_RESET; 1262 1263 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg); 1264 } 1265 1266 static void 1267 bfa_ioc_lpu_stop(struct bfa_ioc *ioc) 1268 { 1269 u32 pss_ctl; 1270 1271 /** 1272 * Put processors in reset. 1273 */ 1274 pss_ctl = readl(ioc->ioc_regs.pss_ctl_reg); 1275 pss_ctl |= (__PSS_LPU0_RESET | __PSS_LPU1_RESET); 1276 1277 writel(pss_ctl, ioc->ioc_regs.pss_ctl_reg); 1278 } 1279 1280 /* Get driver and firmware versions. */ 1281 void 1282 bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr) 1283 { 1284 u32 pgnum; 1285 u32 loff = 0; 1286 int i; 1287 u32 *fwsig = (u32 *) fwhdr; 1288 1289 pgnum = bfa_ioc_smem_pgnum(ioc, loff); 1290 writel(pgnum, ioc->ioc_regs.host_page_num_fn); 1291 1292 for (i = 0; i < (sizeof(struct bfi_ioc_image_hdr) / sizeof(u32)); 1293 i++) { 1294 fwsig[i] = 1295 swab32(readl(loff + ioc->ioc_regs.smem_page_start)); 1296 loff += sizeof(u32); 1297 } 1298 } 1299 1300 static bool 1301 bfa_ioc_fwver_md5_check(struct bfi_ioc_image_hdr *fwhdr_1, 1302 struct bfi_ioc_image_hdr *fwhdr_2) 1303 { 1304 int i; 1305 1306 for (i = 0; i < BFI_IOC_MD5SUM_SZ; i++) { 1307 if (fwhdr_1->md5sum[i] != fwhdr_2->md5sum[i]) 1308 return false; 1309 } 1310 1311 return true; 1312 } 1313 1314 /* Returns TRUE if major minor and maintenance are same. 1315 * If patch version are same, check for MD5 Checksum to be same. 1316 */ 1317 static bool 1318 bfa_ioc_fw_ver_compatible(struct bfi_ioc_image_hdr *drv_fwhdr, 1319 struct bfi_ioc_image_hdr *fwhdr_to_cmp) 1320 { 1321 if (drv_fwhdr->signature != fwhdr_to_cmp->signature) 1322 return false; 1323 if (drv_fwhdr->fwver.major != fwhdr_to_cmp->fwver.major) 1324 return false; 1325 if (drv_fwhdr->fwver.minor != fwhdr_to_cmp->fwver.minor) 1326 return false; 1327 if (drv_fwhdr->fwver.maint != fwhdr_to_cmp->fwver.maint) 1328 return false; 1329 if (drv_fwhdr->fwver.patch == fwhdr_to_cmp->fwver.patch && 1330 drv_fwhdr->fwver.phase == fwhdr_to_cmp->fwver.phase && 1331 drv_fwhdr->fwver.build == fwhdr_to_cmp->fwver.build) 1332 return bfa_ioc_fwver_md5_check(drv_fwhdr, fwhdr_to_cmp); 1333 1334 return true; 1335 } 1336 1337 static bool 1338 bfa_ioc_flash_fwver_valid(struct bfi_ioc_image_hdr *flash_fwhdr) 1339 { 1340 if (flash_fwhdr->fwver.major == 0 || flash_fwhdr->fwver.major == 0xFF) 1341 return false; 1342 1343 return true; 1344 } 1345 1346 static bool 1347 fwhdr_is_ga(struct bfi_ioc_image_hdr *fwhdr) 1348 { 1349 if (fwhdr->fwver.phase == 0 && 1350 fwhdr->fwver.build == 0) 1351 return false; 1352 1353 return true; 1354 } 1355 1356 /* Returns TRUE if both are compatible and patch of fwhdr_to_cmp is better. */ 1357 static enum bfi_ioc_img_ver_cmp 1358 bfa_ioc_fw_ver_patch_cmp(struct bfi_ioc_image_hdr *base_fwhdr, 1359 struct bfi_ioc_image_hdr *fwhdr_to_cmp) 1360 { 1361 if (!bfa_ioc_fw_ver_compatible(base_fwhdr, fwhdr_to_cmp)) 1362 return BFI_IOC_IMG_VER_INCOMP; 1363 1364 if (fwhdr_to_cmp->fwver.patch > base_fwhdr->fwver.patch) 1365 return BFI_IOC_IMG_VER_BETTER; 1366 else if (fwhdr_to_cmp->fwver.patch < base_fwhdr->fwver.patch) 1367 return BFI_IOC_IMG_VER_OLD; 1368 1369 /* GA takes priority over internal builds of the same patch stream. 1370 * At this point major minor maint and patch numbers are same. 1371 */ 1372 if (fwhdr_is_ga(base_fwhdr)) 1373 if (fwhdr_is_ga(fwhdr_to_cmp)) 1374 return BFI_IOC_IMG_VER_SAME; 1375 else 1376 return BFI_IOC_IMG_VER_OLD; 1377 else 1378 if (fwhdr_is_ga(fwhdr_to_cmp)) 1379 return BFI_IOC_IMG_VER_BETTER; 1380 1381 if (fwhdr_to_cmp->fwver.phase > base_fwhdr->fwver.phase) 1382 return BFI_IOC_IMG_VER_BETTER; 1383 else if (fwhdr_to_cmp->fwver.phase < base_fwhdr->fwver.phase) 1384 return BFI_IOC_IMG_VER_OLD; 1385 1386 if (fwhdr_to_cmp->fwver.build > base_fwhdr->fwver.build) 1387 return BFI_IOC_IMG_VER_BETTER; 1388 else if (fwhdr_to_cmp->fwver.build < base_fwhdr->fwver.build) 1389 return BFI_IOC_IMG_VER_OLD; 1390 1391 /* All Version Numbers are equal. 1392 * Md5 check to be done as a part of compatibility check. 1393 */ 1394 return BFI_IOC_IMG_VER_SAME; 1395 } 1396 1397 /* register definitions */ 1398 #define FLI_CMD_REG 0x0001d000 1399 #define FLI_WRDATA_REG 0x0001d00c 1400 #define FLI_RDDATA_REG 0x0001d010 1401 #define FLI_ADDR_REG 0x0001d004 1402 #define FLI_DEV_STATUS_REG 0x0001d014 1403 1404 #define BFA_FLASH_FIFO_SIZE 128 /* fifo size */ 1405 #define BFA_FLASH_CHECK_MAX 10000 /* max # of status check */ 1406 #define BFA_FLASH_BLOCKING_OP_MAX 1000000 /* max # of blocking op check */ 1407 #define BFA_FLASH_WIP_MASK 0x01 /* write in progress bit mask */ 1408 1409 #define NFC_STATE_RUNNING 0x20000001 1410 #define NFC_STATE_PAUSED 0x00004560 1411 #define NFC_VER_VALID 0x147 1412 1413 enum bfa_flash_cmd { 1414 BFA_FLASH_FAST_READ = 0x0b, /* fast read */ 1415 BFA_FLASH_WRITE_ENABLE = 0x06, /* write enable */ 1416 BFA_FLASH_SECTOR_ERASE = 0xd8, /* sector erase */ 1417 BFA_FLASH_WRITE = 0x02, /* write */ 1418 BFA_FLASH_READ_STATUS = 0x05, /* read status */ 1419 }; 1420 1421 /* hardware error definition */ 1422 enum bfa_flash_err { 1423 BFA_FLASH_NOT_PRESENT = -1, /*!< flash not present */ 1424 BFA_FLASH_UNINIT = -2, /*!< flash not initialized */ 1425 BFA_FLASH_BAD = -3, /*!< flash bad */ 1426 BFA_FLASH_BUSY = -4, /*!< flash busy */ 1427 BFA_FLASH_ERR_CMD_ACT = -5, /*!< command active never cleared */ 1428 BFA_FLASH_ERR_FIFO_CNT = -6, /*!< fifo count never cleared */ 1429 BFA_FLASH_ERR_WIP = -7, /*!< write-in-progress never cleared */ 1430 BFA_FLASH_ERR_TIMEOUT = -8, /*!< fli timeout */ 1431 BFA_FLASH_ERR_LEN = -9, /*!< invalid length */ 1432 }; 1433 1434 /* flash command register data structure */ 1435 union bfa_flash_cmd_reg { 1436 struct { 1437 #ifdef __BIG_ENDIAN 1438 u32 act:1; 1439 u32 rsv:1; 1440 u32 write_cnt:9; 1441 u32 read_cnt:9; 1442 u32 addr_cnt:4; 1443 u32 cmd:8; 1444 #else 1445 u32 cmd:8; 1446 u32 addr_cnt:4; 1447 u32 read_cnt:9; 1448 u32 write_cnt:9; 1449 u32 rsv:1; 1450 u32 act:1; 1451 #endif 1452 } r; 1453 u32 i; 1454 }; 1455 1456 /* flash device status register data structure */ 1457 union bfa_flash_dev_status_reg { 1458 struct { 1459 #ifdef __BIG_ENDIAN 1460 u32 rsv:21; 1461 u32 fifo_cnt:6; 1462 u32 busy:1; 1463 u32 init_status:1; 1464 u32 present:1; 1465 u32 bad:1; 1466 u32 good:1; 1467 #else 1468 u32 good:1; 1469 u32 bad:1; 1470 u32 present:1; 1471 u32 init_status:1; 1472 u32 busy:1; 1473 u32 fifo_cnt:6; 1474 u32 rsv:21; 1475 #endif 1476 } r; 1477 u32 i; 1478 }; 1479 1480 /* flash address register data structure */ 1481 union bfa_flash_addr_reg { 1482 struct { 1483 #ifdef __BIG_ENDIAN 1484 u32 addr:24; 1485 u32 dummy:8; 1486 #else 1487 u32 dummy:8; 1488 u32 addr:24; 1489 #endif 1490 } r; 1491 u32 i; 1492 }; 1493 1494 /* Flash raw private functions */ 1495 static void 1496 bfa_flash_set_cmd(void __iomem *pci_bar, u8 wr_cnt, 1497 u8 rd_cnt, u8 ad_cnt, u8 op) 1498 { 1499 union bfa_flash_cmd_reg cmd; 1500 1501 cmd.i = 0; 1502 cmd.r.act = 1; 1503 cmd.r.write_cnt = wr_cnt; 1504 cmd.r.read_cnt = rd_cnt; 1505 cmd.r.addr_cnt = ad_cnt; 1506 cmd.r.cmd = op; 1507 writel(cmd.i, (pci_bar + FLI_CMD_REG)); 1508 } 1509 1510 static void 1511 bfa_flash_set_addr(void __iomem *pci_bar, u32 address) 1512 { 1513 union bfa_flash_addr_reg addr; 1514 1515 addr.r.addr = address & 0x00ffffff; 1516 addr.r.dummy = 0; 1517 writel(addr.i, (pci_bar + FLI_ADDR_REG)); 1518 } 1519 1520 static int 1521 bfa_flash_cmd_act_check(void __iomem *pci_bar) 1522 { 1523 union bfa_flash_cmd_reg cmd; 1524 1525 cmd.i = readl(pci_bar + FLI_CMD_REG); 1526 1527 if (cmd.r.act) 1528 return BFA_FLASH_ERR_CMD_ACT; 1529 1530 return 0; 1531 } 1532 1533 /* Flush FLI data fifo. */ 1534 static int 1535 bfa_flash_fifo_flush(void __iomem *pci_bar) 1536 { 1537 u32 i; 1538 union bfa_flash_dev_status_reg dev_status; 1539 1540 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG); 1541 1542 if (!dev_status.r.fifo_cnt) 1543 return 0; 1544 1545 /* fifo counter in terms of words */ 1546 for (i = 0; i < dev_status.r.fifo_cnt; i++) 1547 readl(pci_bar + FLI_RDDATA_REG); 1548 1549 /* Check the device status. It may take some time. */ 1550 for (i = 0; i < BFA_FLASH_CHECK_MAX; i++) { 1551 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG); 1552 if (!dev_status.r.fifo_cnt) 1553 break; 1554 } 1555 1556 if (dev_status.r.fifo_cnt) 1557 return BFA_FLASH_ERR_FIFO_CNT; 1558 1559 return 0; 1560 } 1561 1562 /* Read flash status. */ 1563 static int 1564 bfa_flash_status_read(void __iomem *pci_bar) 1565 { 1566 union bfa_flash_dev_status_reg dev_status; 1567 int status; 1568 u32 ret_status; 1569 int i; 1570 1571 status = bfa_flash_fifo_flush(pci_bar); 1572 if (status < 0) 1573 return status; 1574 1575 bfa_flash_set_cmd(pci_bar, 0, 4, 0, BFA_FLASH_READ_STATUS); 1576 1577 for (i = 0; i < BFA_FLASH_CHECK_MAX; i++) { 1578 status = bfa_flash_cmd_act_check(pci_bar); 1579 if (!status) 1580 break; 1581 } 1582 1583 if (status) 1584 return status; 1585 1586 dev_status.i = readl(pci_bar + FLI_DEV_STATUS_REG); 1587 if (!dev_status.r.fifo_cnt) 1588 return BFA_FLASH_BUSY; 1589 1590 ret_status = readl(pci_bar + FLI_RDDATA_REG); 1591 ret_status >>= 24; 1592 1593 status = bfa_flash_fifo_flush(pci_bar); 1594 if (status < 0) 1595 return status; 1596 1597 return ret_status; 1598 } 1599 1600 /* Start flash read operation. */ 1601 static int 1602 bfa_flash_read_start(void __iomem *pci_bar, u32 offset, u32 len, 1603 char *buf) 1604 { 1605 int status; 1606 1607 /* len must be mutiple of 4 and not exceeding fifo size */ 1608 if (len == 0 || len > BFA_FLASH_FIFO_SIZE || (len & 0x03) != 0) 1609 return BFA_FLASH_ERR_LEN; 1610 1611 /* check status */ 1612 status = bfa_flash_status_read(pci_bar); 1613 if (status == BFA_FLASH_BUSY) 1614 status = bfa_flash_status_read(pci_bar); 1615 1616 if (status < 0) 1617 return status; 1618 1619 /* check if write-in-progress bit is cleared */ 1620 if (status & BFA_FLASH_WIP_MASK) 1621 return BFA_FLASH_ERR_WIP; 1622 1623 bfa_flash_set_addr(pci_bar, offset); 1624 1625 bfa_flash_set_cmd(pci_bar, 0, (u8)len, 4, BFA_FLASH_FAST_READ); 1626 1627 return 0; 1628 } 1629 1630 /* Check flash read operation. */ 1631 static u32 1632 bfa_flash_read_check(void __iomem *pci_bar) 1633 { 1634 if (bfa_flash_cmd_act_check(pci_bar)) 1635 return 1; 1636 1637 return 0; 1638 } 1639 1640 /* End flash read operation. */ 1641 static void 1642 bfa_flash_read_end(void __iomem *pci_bar, u32 len, char *buf) 1643 { 1644 u32 i; 1645 1646 /* read data fifo up to 32 words */ 1647 for (i = 0; i < len; i += 4) { 1648 u32 w = readl(pci_bar + FLI_RDDATA_REG); 1649 *((u32 *)(buf + i)) = swab32(w); 1650 } 1651 1652 bfa_flash_fifo_flush(pci_bar); 1653 } 1654 1655 /* Perform flash raw read. */ 1656 1657 #define FLASH_BLOCKING_OP_MAX 500 1658 #define FLASH_SEM_LOCK_REG 0x18820 1659 1660 static int 1661 bfa_raw_sem_get(void __iomem *bar) 1662 { 1663 int locked; 1664 1665 locked = readl(bar + FLASH_SEM_LOCK_REG); 1666 1667 return !locked; 1668 } 1669 1670 static enum bfa_status 1671 bfa_flash_sem_get(void __iomem *bar) 1672 { 1673 u32 n = FLASH_BLOCKING_OP_MAX; 1674 1675 while (!bfa_raw_sem_get(bar)) { 1676 if (--n <= 0) 1677 return BFA_STATUS_BADFLASH; 1678 mdelay(10); 1679 } 1680 return BFA_STATUS_OK; 1681 } 1682 1683 static void 1684 bfa_flash_sem_put(void __iomem *bar) 1685 { 1686 writel(0, (bar + FLASH_SEM_LOCK_REG)); 1687 } 1688 1689 static enum bfa_status 1690 bfa_flash_raw_read(void __iomem *pci_bar, u32 offset, char *buf, 1691 u32 len) 1692 { 1693 u32 n; 1694 int status; 1695 u32 off, l, s, residue, fifo_sz; 1696 1697 residue = len; 1698 off = 0; 1699 fifo_sz = BFA_FLASH_FIFO_SIZE; 1700 status = bfa_flash_sem_get(pci_bar); 1701 if (status != BFA_STATUS_OK) 1702 return status; 1703 1704 while (residue) { 1705 s = offset + off; 1706 n = s / fifo_sz; 1707 l = (n + 1) * fifo_sz - s; 1708 if (l > residue) 1709 l = residue; 1710 1711 status = bfa_flash_read_start(pci_bar, offset + off, l, 1712 &buf[off]); 1713 if (status < 0) { 1714 bfa_flash_sem_put(pci_bar); 1715 return BFA_STATUS_FAILED; 1716 } 1717 1718 n = BFA_FLASH_BLOCKING_OP_MAX; 1719 while (bfa_flash_read_check(pci_bar)) { 1720 if (--n <= 0) { 1721 bfa_flash_sem_put(pci_bar); 1722 return BFA_STATUS_FAILED; 1723 } 1724 } 1725 1726 bfa_flash_read_end(pci_bar, l, &buf[off]); 1727 1728 residue -= l; 1729 off += l; 1730 } 1731 bfa_flash_sem_put(pci_bar); 1732 1733 return BFA_STATUS_OK; 1734 } 1735 1736 #define BFA_FLASH_PART_FWIMG_ADDR 0x100000 /* fw image address */ 1737 1738 static enum bfa_status 1739 bfa_nw_ioc_flash_img_get_chnk(struct bfa_ioc *ioc, u32 off, 1740 u32 *fwimg) 1741 { 1742 return bfa_flash_raw_read(ioc->pcidev.pci_bar_kva, 1743 BFA_FLASH_PART_FWIMG_ADDR + (off * sizeof(u32)), 1744 (char *)fwimg, BFI_FLASH_CHUNK_SZ); 1745 } 1746 1747 static enum bfi_ioc_img_ver_cmp 1748 bfa_ioc_flash_fwver_cmp(struct bfa_ioc *ioc, 1749 struct bfi_ioc_image_hdr *base_fwhdr) 1750 { 1751 struct bfi_ioc_image_hdr *flash_fwhdr; 1752 enum bfa_status status; 1753 u32 fwimg[BFI_FLASH_CHUNK_SZ_WORDS]; 1754 1755 status = bfa_nw_ioc_flash_img_get_chnk(ioc, 0, fwimg); 1756 if (status != BFA_STATUS_OK) 1757 return BFI_IOC_IMG_VER_INCOMP; 1758 1759 flash_fwhdr = (struct bfi_ioc_image_hdr *)fwimg; 1760 if (bfa_ioc_flash_fwver_valid(flash_fwhdr)) 1761 return bfa_ioc_fw_ver_patch_cmp(base_fwhdr, flash_fwhdr); 1762 else 1763 return BFI_IOC_IMG_VER_INCOMP; 1764 } 1765 1766 /** 1767 * Returns TRUE if driver is willing to work with current smem f/w version. 1768 */ 1769 bool 1770 bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc, struct bfi_ioc_image_hdr *fwhdr) 1771 { 1772 struct bfi_ioc_image_hdr *drv_fwhdr; 1773 enum bfi_ioc_img_ver_cmp smem_flash_cmp, drv_smem_cmp; 1774 1775 drv_fwhdr = (struct bfi_ioc_image_hdr *) 1776 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0); 1777 1778 /* If smem is incompatible or old, driver should not work with it. */ 1779 drv_smem_cmp = bfa_ioc_fw_ver_patch_cmp(drv_fwhdr, fwhdr); 1780 if (drv_smem_cmp == BFI_IOC_IMG_VER_INCOMP || 1781 drv_smem_cmp == BFI_IOC_IMG_VER_OLD) { 1782 return false; 1783 } 1784 1785 /* IF Flash has a better F/W than smem do not work with smem. 1786 * If smem f/w == flash f/w, as smem f/w not old | incmp, work with it. 1787 * If Flash is old or incomp work with smem iff smem f/w == drv f/w. 1788 */ 1789 smem_flash_cmp = bfa_ioc_flash_fwver_cmp(ioc, fwhdr); 1790 1791 if (smem_flash_cmp == BFI_IOC_IMG_VER_BETTER) 1792 return false; 1793 else if (smem_flash_cmp == BFI_IOC_IMG_VER_SAME) 1794 return true; 1795 else 1796 return (drv_smem_cmp == BFI_IOC_IMG_VER_SAME) ? 1797 true : false; 1798 } 1799 1800 /* Return true if current running version is valid. Firmware signature and 1801 * execution context (driver/bios) must match. 1802 */ 1803 static bool 1804 bfa_ioc_fwver_valid(struct bfa_ioc *ioc, u32 boot_env) 1805 { 1806 struct bfi_ioc_image_hdr fwhdr; 1807 1808 bfa_nw_ioc_fwver_get(ioc, &fwhdr); 1809 if (swab32(fwhdr.bootenv) != boot_env) 1810 return false; 1811 1812 return bfa_nw_ioc_fwver_cmp(ioc, &fwhdr); 1813 } 1814 1815 /* Conditionally flush any pending message from firmware at start. */ 1816 static void 1817 bfa_ioc_msgflush(struct bfa_ioc *ioc) 1818 { 1819 u32 r32; 1820 1821 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd); 1822 if (r32) 1823 writel(1, ioc->ioc_regs.lpu_mbox_cmd); 1824 } 1825 1826 static void 1827 bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force) 1828 { 1829 enum bfi_ioc_state ioc_fwstate; 1830 bool fwvalid; 1831 u32 boot_env; 1832 1833 ioc_fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc); 1834 1835 if (force) 1836 ioc_fwstate = BFI_IOC_UNINIT; 1837 1838 boot_env = BFI_FWBOOT_ENV_OS; 1839 1840 /** 1841 * check if firmware is valid 1842 */ 1843 fwvalid = (ioc_fwstate == BFI_IOC_UNINIT) ? 1844 false : bfa_ioc_fwver_valid(ioc, boot_env); 1845 1846 if (!fwvalid) { 1847 if (bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env) == 1848 BFA_STATUS_OK) 1849 bfa_ioc_poll_fwinit(ioc); 1850 1851 return; 1852 } 1853 1854 /** 1855 * If hardware initialization is in progress (initialized by other IOC), 1856 * just wait for an initialization completion interrupt. 1857 */ 1858 if (ioc_fwstate == BFI_IOC_INITING) { 1859 bfa_ioc_poll_fwinit(ioc); 1860 return; 1861 } 1862 1863 /** 1864 * If IOC function is disabled and firmware version is same, 1865 * just re-enable IOC. 1866 */ 1867 if (ioc_fwstate == BFI_IOC_DISABLED || ioc_fwstate == BFI_IOC_OP) { 1868 /** 1869 * When using MSI-X any pending firmware ready event should 1870 * be flushed. Otherwise MSI-X interrupts are not delivered. 1871 */ 1872 bfa_ioc_msgflush(ioc); 1873 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY); 1874 return; 1875 } 1876 1877 /** 1878 * Initialize the h/w for any other states. 1879 */ 1880 if (bfa_ioc_boot(ioc, BFI_FWBOOT_TYPE_NORMAL, boot_env) == 1881 BFA_STATUS_OK) 1882 bfa_ioc_poll_fwinit(ioc); 1883 } 1884 1885 void 1886 bfa_nw_ioc_timeout(struct bfa_ioc *ioc) 1887 { 1888 bfa_fsm_send_event(ioc, IOC_E_TIMEOUT); 1889 } 1890 1891 static void 1892 bfa_ioc_mbox_send(struct bfa_ioc *ioc, void *ioc_msg, int len) 1893 { 1894 u32 *msgp = (u32 *) ioc_msg; 1895 u32 i; 1896 1897 BUG_ON(!(len <= BFI_IOC_MSGLEN_MAX)); 1898 1899 /* 1900 * first write msg to mailbox registers 1901 */ 1902 for (i = 0; i < len / sizeof(u32); i++) 1903 writel(cpu_to_le32(msgp[i]), 1904 ioc->ioc_regs.hfn_mbox + i * sizeof(u32)); 1905 1906 for (; i < BFI_IOC_MSGLEN_MAX / sizeof(u32); i++) 1907 writel(0, ioc->ioc_regs.hfn_mbox + i * sizeof(u32)); 1908 1909 /* 1910 * write 1 to mailbox CMD to trigger LPU event 1911 */ 1912 writel(1, ioc->ioc_regs.hfn_mbox_cmd); 1913 (void) readl(ioc->ioc_regs.hfn_mbox_cmd); 1914 } 1915 1916 static void 1917 bfa_ioc_send_enable(struct bfa_ioc *ioc) 1918 { 1919 struct bfi_ioc_ctrl_req enable_req; 1920 1921 bfi_h2i_set(enable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_ENABLE_REQ, 1922 bfa_ioc_portid(ioc)); 1923 enable_req.clscode = htons(ioc->clscode); 1924 enable_req.rsvd = htons(0); 1925 /* overflow in 2106 */ 1926 enable_req.tv_sec = ntohl(ktime_get_real_seconds()); 1927 bfa_ioc_mbox_send(ioc, &enable_req, sizeof(struct bfi_ioc_ctrl_req)); 1928 } 1929 1930 static void 1931 bfa_ioc_send_disable(struct bfa_ioc *ioc) 1932 { 1933 struct bfi_ioc_ctrl_req disable_req; 1934 1935 bfi_h2i_set(disable_req.mh, BFI_MC_IOC, BFI_IOC_H2I_DISABLE_REQ, 1936 bfa_ioc_portid(ioc)); 1937 disable_req.clscode = htons(ioc->clscode); 1938 disable_req.rsvd = htons(0); 1939 /* overflow in 2106 */ 1940 disable_req.tv_sec = ntohl(ktime_get_real_seconds()); 1941 bfa_ioc_mbox_send(ioc, &disable_req, sizeof(struct bfi_ioc_ctrl_req)); 1942 } 1943 1944 static void 1945 bfa_ioc_send_getattr(struct bfa_ioc *ioc) 1946 { 1947 struct bfi_ioc_getattr_req attr_req; 1948 1949 bfi_h2i_set(attr_req.mh, BFI_MC_IOC, BFI_IOC_H2I_GETATTR_REQ, 1950 bfa_ioc_portid(ioc)); 1951 bfa_dma_be_addr_set(attr_req.attr_addr, ioc->attr_dma.pa); 1952 bfa_ioc_mbox_send(ioc, &attr_req, sizeof(attr_req)); 1953 } 1954 1955 void 1956 bfa_nw_ioc_hb_check(struct bfa_ioc *ioc) 1957 { 1958 u32 hb_count; 1959 1960 hb_count = readl(ioc->ioc_regs.heartbeat); 1961 if (ioc->hb_count == hb_count) { 1962 bfa_ioc_recover(ioc); 1963 return; 1964 } else { 1965 ioc->hb_count = hb_count; 1966 } 1967 1968 bfa_ioc_mbox_poll(ioc); 1969 mod_timer(&ioc->hb_timer, jiffies + 1970 msecs_to_jiffies(BFA_IOC_HB_TOV)); 1971 } 1972 1973 static void 1974 bfa_ioc_hb_monitor(struct bfa_ioc *ioc) 1975 { 1976 ioc->hb_count = readl(ioc->ioc_regs.heartbeat); 1977 mod_timer(&ioc->hb_timer, jiffies + 1978 msecs_to_jiffies(BFA_IOC_HB_TOV)); 1979 } 1980 1981 static void 1982 bfa_ioc_hb_stop(struct bfa_ioc *ioc) 1983 { 1984 del_timer(&ioc->hb_timer); 1985 } 1986 1987 /* Initiate a full firmware download. */ 1988 static enum bfa_status 1989 bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type, 1990 u32 boot_env) 1991 { 1992 u32 *fwimg; 1993 u32 pgnum; 1994 u32 loff = 0; 1995 u32 chunkno = 0; 1996 u32 i; 1997 u32 asicmode; 1998 u32 fwimg_size; 1999 u32 fwimg_buf[BFI_FLASH_CHUNK_SZ_WORDS]; 2000 enum bfa_status status; 2001 2002 if (boot_env == BFI_FWBOOT_ENV_OS && 2003 boot_type == BFI_FWBOOT_TYPE_FLASH) { 2004 fwimg_size = BFI_FLASH_IMAGE_SZ/sizeof(u32); 2005 2006 status = bfa_nw_ioc_flash_img_get_chnk(ioc, 2007 BFA_IOC_FLASH_CHUNK_ADDR(chunkno), fwimg_buf); 2008 if (status != BFA_STATUS_OK) 2009 return status; 2010 2011 fwimg = fwimg_buf; 2012 } else { 2013 fwimg_size = bfa_cb_image_get_size(bfa_ioc_asic_gen(ioc)); 2014 fwimg = bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 2015 BFA_IOC_FLASH_CHUNK_ADDR(chunkno)); 2016 } 2017 2018 pgnum = bfa_ioc_smem_pgnum(ioc, loff); 2019 2020 writel(pgnum, ioc->ioc_regs.host_page_num_fn); 2021 2022 for (i = 0; i < fwimg_size; i++) { 2023 if (BFA_IOC_FLASH_CHUNK_NO(i) != chunkno) { 2024 chunkno = BFA_IOC_FLASH_CHUNK_NO(i); 2025 if (boot_env == BFI_FWBOOT_ENV_OS && 2026 boot_type == BFI_FWBOOT_TYPE_FLASH) { 2027 status = bfa_nw_ioc_flash_img_get_chnk(ioc, 2028 BFA_IOC_FLASH_CHUNK_ADDR(chunkno), 2029 fwimg_buf); 2030 if (status != BFA_STATUS_OK) 2031 return status; 2032 2033 fwimg = fwimg_buf; 2034 } else { 2035 fwimg = bfa_cb_image_get_chunk( 2036 bfa_ioc_asic_gen(ioc), 2037 BFA_IOC_FLASH_CHUNK_ADDR(chunkno)); 2038 } 2039 } 2040 2041 /** 2042 * write smem 2043 */ 2044 writel(swab32(fwimg[BFA_IOC_FLASH_OFFSET_IN_CHUNK(i)]), 2045 ioc->ioc_regs.smem_page_start + loff); 2046 2047 loff += sizeof(u32); 2048 2049 /** 2050 * handle page offset wrap around 2051 */ 2052 loff = PSS_SMEM_PGOFF(loff); 2053 if (loff == 0) { 2054 pgnum++; 2055 writel(pgnum, 2056 ioc->ioc_regs.host_page_num_fn); 2057 } 2058 } 2059 2060 writel(bfa_ioc_smem_pgnum(ioc, 0), 2061 ioc->ioc_regs.host_page_num_fn); 2062 2063 /* 2064 * Set boot type, env and device mode at the end. 2065 */ 2066 if (boot_env == BFI_FWBOOT_ENV_OS && 2067 boot_type == BFI_FWBOOT_TYPE_FLASH) { 2068 boot_type = BFI_FWBOOT_TYPE_NORMAL; 2069 } 2070 asicmode = BFI_FWBOOT_DEVMODE(ioc->asic_gen, ioc->asic_mode, 2071 ioc->port0_mode, ioc->port1_mode); 2072 writel(asicmode, ((ioc->ioc_regs.smem_page_start) 2073 + BFI_FWBOOT_DEVMODE_OFF)); 2074 writel(boot_type, ((ioc->ioc_regs.smem_page_start) 2075 + (BFI_FWBOOT_TYPE_OFF))); 2076 writel(boot_env, ((ioc->ioc_regs.smem_page_start) 2077 + (BFI_FWBOOT_ENV_OFF))); 2078 return BFA_STATUS_OK; 2079 } 2080 2081 static void 2082 bfa_ioc_reset(struct bfa_ioc *ioc, bool force) 2083 { 2084 bfa_ioc_hwinit(ioc, force); 2085 } 2086 2087 /* BFA ioc enable reply by firmware */ 2088 static void 2089 bfa_ioc_enable_reply(struct bfa_ioc *ioc, enum bfa_mode port_mode, 2090 u8 cap_bm) 2091 { 2092 struct bfa_iocpf *iocpf = &ioc->iocpf; 2093 2094 ioc->port_mode = ioc->port_mode_cfg = port_mode; 2095 ioc->ad_cap_bm = cap_bm; 2096 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_ENABLE); 2097 } 2098 2099 /* Update BFA configuration from firmware configuration. */ 2100 static void 2101 bfa_ioc_getattr_reply(struct bfa_ioc *ioc) 2102 { 2103 struct bfi_ioc_attr *attr = ioc->attr; 2104 2105 attr->adapter_prop = ntohl(attr->adapter_prop); 2106 attr->card_type = ntohl(attr->card_type); 2107 attr->maxfrsize = ntohs(attr->maxfrsize); 2108 2109 bfa_fsm_send_event(ioc, IOC_E_FWRSP_GETATTR); 2110 } 2111 2112 /* Attach time initialization of mbox logic. */ 2113 static void 2114 bfa_ioc_mbox_attach(struct bfa_ioc *ioc) 2115 { 2116 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod; 2117 int mc; 2118 2119 INIT_LIST_HEAD(&mod->cmd_q); 2120 for (mc = 0; mc < BFI_MC_MAX; mc++) { 2121 mod->mbhdlr[mc].cbfn = NULL; 2122 mod->mbhdlr[mc].cbarg = ioc->bfa; 2123 } 2124 } 2125 2126 /* Mbox poll timer -- restarts any pending mailbox requests. */ 2127 static void 2128 bfa_ioc_mbox_poll(struct bfa_ioc *ioc) 2129 { 2130 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod; 2131 struct bfa_mbox_cmd *cmd; 2132 bfa_mbox_cmd_cbfn_t cbfn; 2133 void *cbarg; 2134 u32 stat; 2135 2136 /** 2137 * If no command pending, do nothing 2138 */ 2139 if (list_empty(&mod->cmd_q)) 2140 return; 2141 2142 /** 2143 * If previous command is not yet fetched by firmware, do nothing 2144 */ 2145 stat = readl(ioc->ioc_regs.hfn_mbox_cmd); 2146 if (stat) 2147 return; 2148 2149 /** 2150 * Enqueue command to firmware. 2151 */ 2152 cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe); 2153 list_del(&cmd->qe); 2154 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg)); 2155 2156 /** 2157 * Give a callback to the client, indicating that the command is sent 2158 */ 2159 if (cmd->cbfn) { 2160 cbfn = cmd->cbfn; 2161 cbarg = cmd->cbarg; 2162 cmd->cbfn = NULL; 2163 cbfn(cbarg); 2164 } 2165 } 2166 2167 /* Cleanup any pending requests. */ 2168 static void 2169 bfa_ioc_mbox_flush(struct bfa_ioc *ioc) 2170 { 2171 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod; 2172 struct bfa_mbox_cmd *cmd; 2173 2174 while (!list_empty(&mod->cmd_q)) { 2175 cmd = list_first_entry(&mod->cmd_q, struct bfa_mbox_cmd, qe); 2176 list_del(&cmd->qe); 2177 } 2178 } 2179 2180 /** 2181 * bfa_nw_ioc_smem_read - Read data from SMEM to host through PCI memmap 2182 * 2183 * @ioc: memory for IOC 2184 * @tbuf: app memory to store data from smem 2185 * @soff: smem offset 2186 * @sz: size of smem in bytes 2187 */ 2188 static int 2189 bfa_nw_ioc_smem_read(struct bfa_ioc *ioc, void *tbuf, u32 soff, u32 sz) 2190 { 2191 u32 pgnum, loff, r32; 2192 int i, len; 2193 u32 *buf = tbuf; 2194 2195 pgnum = PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, soff); 2196 loff = PSS_SMEM_PGOFF(soff); 2197 2198 /* 2199 * Hold semaphore to serialize pll init and fwtrc. 2200 */ 2201 if (!bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg)) 2202 return 1; 2203 2204 writel(pgnum, ioc->ioc_regs.host_page_num_fn); 2205 2206 len = sz/sizeof(u32); 2207 for (i = 0; i < len; i++) { 2208 r32 = swab32(readl(loff + ioc->ioc_regs.smem_page_start)); 2209 buf[i] = be32_to_cpu(r32); 2210 loff += sizeof(u32); 2211 2212 /** 2213 * handle page offset wrap around 2214 */ 2215 loff = PSS_SMEM_PGOFF(loff); 2216 if (loff == 0) { 2217 pgnum++; 2218 writel(pgnum, ioc->ioc_regs.host_page_num_fn); 2219 } 2220 } 2221 2222 writel(PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, 0), 2223 ioc->ioc_regs.host_page_num_fn); 2224 2225 /* 2226 * release semaphore 2227 */ 2228 readl(ioc->ioc_regs.ioc_init_sem_reg); 2229 writel(1, ioc->ioc_regs.ioc_init_sem_reg); 2230 return 0; 2231 } 2232 2233 /* Retrieve saved firmware trace from a prior IOC failure. */ 2234 int 2235 bfa_nw_ioc_debug_fwtrc(struct bfa_ioc *ioc, void *trcdata, int *trclen) 2236 { 2237 u32 loff = BFI_IOC_TRC_OFF + BNA_DBG_FWTRC_LEN * ioc->port_id; 2238 int tlen, status = 0; 2239 2240 tlen = *trclen; 2241 if (tlen > BNA_DBG_FWTRC_LEN) 2242 tlen = BNA_DBG_FWTRC_LEN; 2243 2244 status = bfa_nw_ioc_smem_read(ioc, trcdata, loff, tlen); 2245 *trclen = tlen; 2246 return status; 2247 } 2248 2249 /* Save firmware trace if configured. */ 2250 static void 2251 bfa_nw_ioc_debug_save_ftrc(struct bfa_ioc *ioc) 2252 { 2253 int tlen; 2254 2255 if (ioc->dbg_fwsave_once) { 2256 ioc->dbg_fwsave_once = false; 2257 if (ioc->dbg_fwsave_len) { 2258 tlen = ioc->dbg_fwsave_len; 2259 bfa_nw_ioc_debug_fwtrc(ioc, ioc->dbg_fwsave, &tlen); 2260 } 2261 } 2262 } 2263 2264 /* Retrieve saved firmware trace from a prior IOC failure. */ 2265 int 2266 bfa_nw_ioc_debug_fwsave(struct bfa_ioc *ioc, void *trcdata, int *trclen) 2267 { 2268 int tlen; 2269 2270 if (ioc->dbg_fwsave_len == 0) 2271 return BFA_STATUS_ENOFSAVE; 2272 2273 tlen = *trclen; 2274 if (tlen > ioc->dbg_fwsave_len) 2275 tlen = ioc->dbg_fwsave_len; 2276 2277 memcpy(trcdata, ioc->dbg_fwsave, tlen); 2278 *trclen = tlen; 2279 return BFA_STATUS_OK; 2280 } 2281 2282 static void 2283 bfa_ioc_fail_notify(struct bfa_ioc *ioc) 2284 { 2285 /** 2286 * Notify driver and common modules registered for notification. 2287 */ 2288 ioc->cbfn->hbfail_cbfn(ioc->bfa); 2289 bfa_ioc_event_notify(ioc, BFA_IOC_E_FAILED); 2290 bfa_nw_ioc_debug_save_ftrc(ioc); 2291 } 2292 2293 /* IOCPF to IOC interface */ 2294 static void 2295 bfa_ioc_pf_enabled(struct bfa_ioc *ioc) 2296 { 2297 bfa_fsm_send_event(ioc, IOC_E_ENABLED); 2298 } 2299 2300 static void 2301 bfa_ioc_pf_disabled(struct bfa_ioc *ioc) 2302 { 2303 bfa_fsm_send_event(ioc, IOC_E_DISABLED); 2304 } 2305 2306 static void 2307 bfa_ioc_pf_failed(struct bfa_ioc *ioc) 2308 { 2309 bfa_fsm_send_event(ioc, IOC_E_PFFAILED); 2310 } 2311 2312 static void 2313 bfa_ioc_pf_hwfailed(struct bfa_ioc *ioc) 2314 { 2315 bfa_fsm_send_event(ioc, IOC_E_HWFAILED); 2316 } 2317 2318 static void 2319 bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc) 2320 { 2321 /** 2322 * Provide enable completion callback and AEN notification. 2323 */ 2324 ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE); 2325 } 2326 2327 /* IOC public */ 2328 static enum bfa_status 2329 bfa_ioc_pll_init(struct bfa_ioc *ioc) 2330 { 2331 /* 2332 * Hold semaphore so that nobody can access the chip during init. 2333 */ 2334 bfa_nw_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg); 2335 2336 bfa_ioc_pll_init_asic(ioc); 2337 2338 ioc->pllinit = true; 2339 2340 /* Initialize LMEM */ 2341 bfa_ioc_lmem_init(ioc); 2342 2343 /* 2344 * release semaphore. 2345 */ 2346 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg); 2347 2348 return BFA_STATUS_OK; 2349 } 2350 2351 /* Interface used by diag module to do firmware boot with memory test 2352 * as the entry vector. 2353 */ 2354 static enum bfa_status 2355 bfa_ioc_boot(struct bfa_ioc *ioc, enum bfi_fwboot_type boot_type, 2356 u32 boot_env) 2357 { 2358 struct bfi_ioc_image_hdr *drv_fwhdr; 2359 enum bfa_status status; 2360 bfa_ioc_stats(ioc, ioc_boots); 2361 2362 if (bfa_ioc_pll_init(ioc) != BFA_STATUS_OK) 2363 return BFA_STATUS_FAILED; 2364 if (boot_env == BFI_FWBOOT_ENV_OS && 2365 boot_type == BFI_FWBOOT_TYPE_NORMAL) { 2366 drv_fwhdr = (struct bfi_ioc_image_hdr *) 2367 bfa_cb_image_get_chunk(bfa_ioc_asic_gen(ioc), 0); 2368 /* Work with Flash iff flash f/w is better than driver f/w. 2369 * Otherwise push drivers firmware. 2370 */ 2371 if (bfa_ioc_flash_fwver_cmp(ioc, drv_fwhdr) == 2372 BFI_IOC_IMG_VER_BETTER) 2373 boot_type = BFI_FWBOOT_TYPE_FLASH; 2374 } 2375 2376 /** 2377 * Initialize IOC state of all functions on a chip reset. 2378 */ 2379 if (boot_type == BFI_FWBOOT_TYPE_MEMTEST) { 2380 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_MEMTEST); 2381 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_MEMTEST); 2382 } else { 2383 bfa_ioc_set_cur_ioc_fwstate(ioc, BFI_IOC_INITING); 2384 bfa_ioc_set_alt_ioc_fwstate(ioc, BFI_IOC_INITING); 2385 } 2386 2387 bfa_ioc_msgflush(ioc); 2388 status = bfa_ioc_download_fw(ioc, boot_type, boot_env); 2389 if (status == BFA_STATUS_OK) 2390 bfa_ioc_lpu_start(ioc); 2391 else 2392 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT); 2393 2394 return status; 2395 } 2396 2397 /* Enable/disable IOC failure auto recovery. */ 2398 void 2399 bfa_nw_ioc_auto_recover(bool auto_recover) 2400 { 2401 bfa_nw_auto_recover = auto_recover; 2402 } 2403 2404 static bool 2405 bfa_ioc_msgget(struct bfa_ioc *ioc, void *mbmsg) 2406 { 2407 u32 *msgp = mbmsg; 2408 u32 r32; 2409 int i; 2410 2411 r32 = readl(ioc->ioc_regs.lpu_mbox_cmd); 2412 if ((r32 & 1) == 0) 2413 return false; 2414 2415 /** 2416 * read the MBOX msg 2417 */ 2418 for (i = 0; i < (sizeof(union bfi_ioc_i2h_msg_u) / sizeof(u32)); 2419 i++) { 2420 r32 = readl(ioc->ioc_regs.lpu_mbox + 2421 i * sizeof(u32)); 2422 msgp[i] = htonl(r32); 2423 } 2424 2425 /** 2426 * turn off mailbox interrupt by clearing mailbox status 2427 */ 2428 writel(1, ioc->ioc_regs.lpu_mbox_cmd); 2429 readl(ioc->ioc_regs.lpu_mbox_cmd); 2430 2431 return true; 2432 } 2433 2434 static void 2435 bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m) 2436 { 2437 union bfi_ioc_i2h_msg_u *msg; 2438 struct bfa_iocpf *iocpf = &ioc->iocpf; 2439 2440 msg = (union bfi_ioc_i2h_msg_u *) m; 2441 2442 bfa_ioc_stats(ioc, ioc_isrs); 2443 2444 switch (msg->mh.msg_id) { 2445 case BFI_IOC_I2H_HBEAT: 2446 break; 2447 2448 case BFI_IOC_I2H_ENABLE_REPLY: 2449 bfa_ioc_enable_reply(ioc, 2450 (enum bfa_mode)msg->fw_event.port_mode, 2451 msg->fw_event.cap_bm); 2452 break; 2453 2454 case BFI_IOC_I2H_DISABLE_REPLY: 2455 bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_DISABLE); 2456 break; 2457 2458 case BFI_IOC_I2H_GETATTR_REPLY: 2459 bfa_ioc_getattr_reply(ioc); 2460 break; 2461 2462 default: 2463 BUG_ON(1); 2464 } 2465 } 2466 2467 /** 2468 * bfa_nw_ioc_attach - IOC attach time initialization and setup. 2469 * 2470 * @ioc: memory for IOC 2471 * @bfa: driver instance structure 2472 */ 2473 void 2474 bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa, struct bfa_ioc_cbfn *cbfn) 2475 { 2476 ioc->bfa = bfa; 2477 ioc->cbfn = cbfn; 2478 ioc->fcmode = false; 2479 ioc->pllinit = false; 2480 ioc->dbg_fwsave_once = true; 2481 ioc->iocpf.ioc = ioc; 2482 2483 bfa_ioc_mbox_attach(ioc); 2484 INIT_LIST_HEAD(&ioc->notify_q); 2485 2486 bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit); 2487 bfa_fsm_send_event(ioc, IOC_E_RESET); 2488 } 2489 2490 /* Driver detach time IOC cleanup. */ 2491 void 2492 bfa_nw_ioc_detach(struct bfa_ioc *ioc) 2493 { 2494 bfa_fsm_send_event(ioc, IOC_E_DETACH); 2495 2496 /* Done with detach, empty the notify_q. */ 2497 INIT_LIST_HEAD(&ioc->notify_q); 2498 } 2499 2500 /** 2501 * bfa_nw_ioc_pci_init - Setup IOC PCI properties. 2502 * 2503 * @pcidev: PCI device information for this IOC 2504 */ 2505 void 2506 bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev, 2507 enum bfi_pcifn_class clscode) 2508 { 2509 ioc->clscode = clscode; 2510 ioc->pcidev = *pcidev; 2511 2512 /** 2513 * Initialize IOC and device personality 2514 */ 2515 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_FC; 2516 ioc->asic_mode = BFI_ASIC_MODE_FC; 2517 2518 switch (pcidev->device_id) { 2519 case PCI_DEVICE_ID_BROCADE_CT: 2520 ioc->asic_gen = BFI_ASIC_GEN_CT; 2521 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH; 2522 ioc->asic_mode = BFI_ASIC_MODE_ETH; 2523 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_CNA; 2524 ioc->ad_cap_bm = BFA_CM_CNA; 2525 break; 2526 2527 case BFA_PCI_DEVICE_ID_CT2: 2528 ioc->asic_gen = BFI_ASIC_GEN_CT2; 2529 if (clscode == BFI_PCIFN_CLASS_FC && 2530 pcidev->ssid == BFA_PCI_CT2_SSID_FC) { 2531 ioc->asic_mode = BFI_ASIC_MODE_FC16; 2532 ioc->fcmode = true; 2533 ioc->port_mode = ioc->port_mode_cfg = BFA_MODE_HBA; 2534 ioc->ad_cap_bm = BFA_CM_HBA; 2535 } else { 2536 ioc->port0_mode = ioc->port1_mode = BFI_PORT_MODE_ETH; 2537 ioc->asic_mode = BFI_ASIC_MODE_ETH; 2538 if (pcidev->ssid == BFA_PCI_CT2_SSID_FCoE) { 2539 ioc->port_mode = 2540 ioc->port_mode_cfg = BFA_MODE_CNA; 2541 ioc->ad_cap_bm = BFA_CM_CNA; 2542 } else { 2543 ioc->port_mode = 2544 ioc->port_mode_cfg = BFA_MODE_NIC; 2545 ioc->ad_cap_bm = BFA_CM_NIC; 2546 } 2547 } 2548 break; 2549 2550 default: 2551 BUG_ON(1); 2552 } 2553 2554 /** 2555 * Set asic specific interfaces. 2556 */ 2557 if (ioc->asic_gen == BFI_ASIC_GEN_CT) 2558 bfa_nw_ioc_set_ct_hwif(ioc); 2559 else { 2560 WARN_ON(ioc->asic_gen != BFI_ASIC_GEN_CT2); 2561 bfa_nw_ioc_set_ct2_hwif(ioc); 2562 bfa_nw_ioc_ct2_poweron(ioc); 2563 } 2564 2565 bfa_ioc_map_port(ioc); 2566 bfa_ioc_reg_init(ioc); 2567 } 2568 2569 /** 2570 * bfa_nw_ioc_mem_claim - Initialize IOC dma memory 2571 * 2572 * @dm_kva: kernel virtual address of IOC dma memory 2573 * @dm_pa: physical address of IOC dma memory 2574 */ 2575 void 2576 bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa) 2577 { 2578 /** 2579 * dma memory for firmware attribute 2580 */ 2581 ioc->attr_dma.kva = dm_kva; 2582 ioc->attr_dma.pa = dm_pa; 2583 ioc->attr = (struct bfi_ioc_attr *) dm_kva; 2584 } 2585 2586 /* Return size of dma memory required. */ 2587 u32 2588 bfa_nw_ioc_meminfo(void) 2589 { 2590 return roundup(sizeof(struct bfi_ioc_attr), BFA_DMA_ALIGN_SZ); 2591 } 2592 2593 void 2594 bfa_nw_ioc_enable(struct bfa_ioc *ioc) 2595 { 2596 bfa_ioc_stats(ioc, ioc_enables); 2597 ioc->dbg_fwsave_once = true; 2598 2599 bfa_fsm_send_event(ioc, IOC_E_ENABLE); 2600 } 2601 2602 void 2603 bfa_nw_ioc_disable(struct bfa_ioc *ioc) 2604 { 2605 bfa_ioc_stats(ioc, ioc_disables); 2606 bfa_fsm_send_event(ioc, IOC_E_DISABLE); 2607 } 2608 2609 /* Initialize memory for saving firmware trace. */ 2610 void 2611 bfa_nw_ioc_debug_memclaim(struct bfa_ioc *ioc, void *dbg_fwsave) 2612 { 2613 ioc->dbg_fwsave = dbg_fwsave; 2614 ioc->dbg_fwsave_len = ioc->iocpf.auto_recover ? BNA_DBG_FWTRC_LEN : 0; 2615 } 2616 2617 static u32 2618 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr) 2619 { 2620 return PSS_SMEM_PGNUM(ioc->ioc_regs.smem_pg0, fmaddr); 2621 } 2622 2623 /* Register mailbox message handler function, to be called by common modules */ 2624 void 2625 bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc, 2626 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg) 2627 { 2628 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod; 2629 2630 mod->mbhdlr[mc].cbfn = cbfn; 2631 mod->mbhdlr[mc].cbarg = cbarg; 2632 } 2633 2634 /** 2635 * bfa_nw_ioc_mbox_queue - Queue a mailbox command request to firmware. 2636 * 2637 * @ioc: IOC instance 2638 * @cmd: Mailbox command 2639 * 2640 * Waits if mailbox is busy. Responsibility of caller to serialize 2641 */ 2642 bool 2643 bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc, struct bfa_mbox_cmd *cmd, 2644 bfa_mbox_cmd_cbfn_t cbfn, void *cbarg) 2645 { 2646 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod; 2647 u32 stat; 2648 2649 cmd->cbfn = cbfn; 2650 cmd->cbarg = cbarg; 2651 2652 /** 2653 * If a previous command is pending, queue new command 2654 */ 2655 if (!list_empty(&mod->cmd_q)) { 2656 list_add_tail(&cmd->qe, &mod->cmd_q); 2657 return true; 2658 } 2659 2660 /** 2661 * If mailbox is busy, queue command for poll timer 2662 */ 2663 stat = readl(ioc->ioc_regs.hfn_mbox_cmd); 2664 if (stat) { 2665 list_add_tail(&cmd->qe, &mod->cmd_q); 2666 return true; 2667 } 2668 2669 /** 2670 * mailbox is free -- queue command to firmware 2671 */ 2672 bfa_ioc_mbox_send(ioc, cmd->msg, sizeof(cmd->msg)); 2673 2674 return false; 2675 } 2676 2677 /* Handle mailbox interrupts */ 2678 void 2679 bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc) 2680 { 2681 struct bfa_ioc_mbox_mod *mod = &ioc->mbox_mod; 2682 struct bfi_mbmsg m; 2683 int mc; 2684 2685 if (bfa_ioc_msgget(ioc, &m)) { 2686 /** 2687 * Treat IOC message class as special. 2688 */ 2689 mc = m.mh.msg_class; 2690 if (mc == BFI_MC_IOC) { 2691 bfa_ioc_isr(ioc, &m); 2692 return; 2693 } 2694 2695 if ((mc >= BFI_MC_MAX) || (mod->mbhdlr[mc].cbfn == NULL)) 2696 return; 2697 2698 mod->mbhdlr[mc].cbfn(mod->mbhdlr[mc].cbarg, &m); 2699 } 2700 2701 bfa_ioc_lpu_read_stat(ioc); 2702 2703 /** 2704 * Try to send pending mailbox commands 2705 */ 2706 bfa_ioc_mbox_poll(ioc); 2707 } 2708 2709 void 2710 bfa_nw_ioc_error_isr(struct bfa_ioc *ioc) 2711 { 2712 bfa_ioc_stats(ioc, ioc_hbfails); 2713 bfa_ioc_stats_hb_count(ioc, ioc->hb_count); 2714 bfa_fsm_send_event(ioc, IOC_E_HWERROR); 2715 } 2716 2717 /* return true if IOC is disabled */ 2718 bool 2719 bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc) 2720 { 2721 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabling) || 2722 bfa_fsm_cmp_state(ioc, bfa_ioc_sm_disabled); 2723 } 2724 2725 /* return true if IOC is operational */ 2726 bool 2727 bfa_nw_ioc_is_operational(struct bfa_ioc *ioc) 2728 { 2729 return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op); 2730 } 2731 2732 /* Add to IOC heartbeat failure notification queue. To be used by common 2733 * modules such as cee, port, diag. 2734 */ 2735 void 2736 bfa_nw_ioc_notify_register(struct bfa_ioc *ioc, 2737 struct bfa_ioc_notify *notify) 2738 { 2739 list_add_tail(¬ify->qe, &ioc->notify_q); 2740 } 2741 2742 #define BFA_MFG_NAME "QLogic" 2743 static void 2744 bfa_ioc_get_adapter_attr(struct bfa_ioc *ioc, 2745 struct bfa_adapter_attr *ad_attr) 2746 { 2747 struct bfi_ioc_attr *ioc_attr; 2748 2749 ioc_attr = ioc->attr; 2750 2751 bfa_ioc_get_adapter_serial_num(ioc, ad_attr->serial_num); 2752 bfa_ioc_get_adapter_fw_ver(ioc, ad_attr->fw_ver); 2753 bfa_ioc_get_adapter_optrom_ver(ioc, ad_attr->optrom_ver); 2754 bfa_ioc_get_adapter_manufacturer(ioc, ad_attr->manufacturer); 2755 memcpy(&ad_attr->vpd, &ioc_attr->vpd, 2756 sizeof(struct bfa_mfg_vpd)); 2757 2758 ad_attr->nports = bfa_ioc_get_nports(ioc); 2759 ad_attr->max_speed = bfa_ioc_speed_sup(ioc); 2760 2761 bfa_ioc_get_adapter_model(ioc, ad_attr->model); 2762 /* For now, model descr uses same model string */ 2763 bfa_ioc_get_adapter_model(ioc, ad_attr->model_descr); 2764 2765 ad_attr->card_type = ioc_attr->card_type; 2766 ad_attr->is_mezz = bfa_mfg_is_mezz(ioc_attr->card_type); 2767 2768 if (BFI_ADAPTER_IS_SPECIAL(ioc_attr->adapter_prop)) 2769 ad_attr->prototype = 1; 2770 else 2771 ad_attr->prototype = 0; 2772 2773 ad_attr->pwwn = bfa_ioc_get_pwwn(ioc); 2774 bfa_nw_ioc_get_mac(ioc, ad_attr->mac); 2775 2776 ad_attr->pcie_gen = ioc_attr->pcie_gen; 2777 ad_attr->pcie_lanes = ioc_attr->pcie_lanes; 2778 ad_attr->pcie_lanes_orig = ioc_attr->pcie_lanes_orig; 2779 ad_attr->asic_rev = ioc_attr->asic_rev; 2780 2781 bfa_ioc_get_pci_chip_rev(ioc, ad_attr->hw_ver); 2782 } 2783 2784 static enum bfa_ioc_type 2785 bfa_ioc_get_type(struct bfa_ioc *ioc) 2786 { 2787 if (ioc->clscode == BFI_PCIFN_CLASS_ETH) 2788 return BFA_IOC_TYPE_LL; 2789 2790 BUG_ON(!(ioc->clscode == BFI_PCIFN_CLASS_FC)); 2791 2792 return (ioc->attr->port_mode == BFI_PORT_MODE_FC) 2793 ? BFA_IOC_TYPE_FC : BFA_IOC_TYPE_FCoE; 2794 } 2795 2796 static void 2797 bfa_ioc_get_adapter_serial_num(struct bfa_ioc *ioc, char *serial_num) 2798 { 2799 memcpy(serial_num, 2800 (void *)ioc->attr->brcd_serialnum, 2801 BFA_ADAPTER_SERIAL_NUM_LEN); 2802 } 2803 2804 static void 2805 bfa_ioc_get_adapter_fw_ver(struct bfa_ioc *ioc, char *fw_ver) 2806 { 2807 memcpy(fw_ver, ioc->attr->fw_version, BFA_VERSION_LEN); 2808 } 2809 2810 static void 2811 bfa_ioc_get_pci_chip_rev(struct bfa_ioc *ioc, char *chip_rev) 2812 { 2813 BUG_ON(!(chip_rev)); 2814 2815 memset(chip_rev, 0, BFA_IOC_CHIP_REV_LEN); 2816 2817 chip_rev[0] = 'R'; 2818 chip_rev[1] = 'e'; 2819 chip_rev[2] = 'v'; 2820 chip_rev[3] = '-'; 2821 chip_rev[4] = ioc->attr->asic_rev; 2822 chip_rev[5] = '\0'; 2823 } 2824 2825 static void 2826 bfa_ioc_get_adapter_optrom_ver(struct bfa_ioc *ioc, char *optrom_ver) 2827 { 2828 memcpy(optrom_ver, ioc->attr->optrom_version, 2829 BFA_VERSION_LEN); 2830 } 2831 2832 static void 2833 bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc, char *manufacturer) 2834 { 2835 strncpy(manufacturer, BFA_MFG_NAME, BFA_ADAPTER_MFG_NAME_LEN); 2836 } 2837 2838 static void 2839 bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model) 2840 { 2841 struct bfi_ioc_attr *ioc_attr; 2842 2843 BUG_ON(!(model)); 2844 memset(model, 0, BFA_ADAPTER_MODEL_NAME_LEN); 2845 2846 ioc_attr = ioc->attr; 2847 2848 snprintf(model, BFA_ADAPTER_MODEL_NAME_LEN, "%s-%u", 2849 BFA_MFG_NAME, ioc_attr->card_type); 2850 } 2851 2852 static enum bfa_ioc_state 2853 bfa_ioc_get_state(struct bfa_ioc *ioc) 2854 { 2855 enum bfa_iocpf_state iocpf_st; 2856 enum bfa_ioc_state ioc_st = bfa_sm_to_state(ioc_sm_table, ioc->fsm); 2857 2858 if (ioc_st == BFA_IOC_ENABLING || 2859 ioc_st == BFA_IOC_FAIL || ioc_st == BFA_IOC_INITFAIL) { 2860 2861 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm); 2862 2863 switch (iocpf_st) { 2864 case BFA_IOCPF_SEMWAIT: 2865 ioc_st = BFA_IOC_SEMWAIT; 2866 break; 2867 2868 case BFA_IOCPF_HWINIT: 2869 ioc_st = BFA_IOC_HWINIT; 2870 break; 2871 2872 case BFA_IOCPF_FWMISMATCH: 2873 ioc_st = BFA_IOC_FWMISMATCH; 2874 break; 2875 2876 case BFA_IOCPF_FAIL: 2877 ioc_st = BFA_IOC_FAIL; 2878 break; 2879 2880 case BFA_IOCPF_INITFAIL: 2881 ioc_st = BFA_IOC_INITFAIL; 2882 break; 2883 2884 default: 2885 break; 2886 } 2887 } 2888 return ioc_st; 2889 } 2890 2891 void 2892 bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr) 2893 { 2894 memset((void *)ioc_attr, 0, sizeof(struct bfa_ioc_attr)); 2895 2896 ioc_attr->state = bfa_ioc_get_state(ioc); 2897 ioc_attr->port_id = bfa_ioc_portid(ioc); 2898 ioc_attr->port_mode = ioc->port_mode; 2899 2900 ioc_attr->port_mode_cfg = ioc->port_mode_cfg; 2901 ioc_attr->cap_bm = ioc->ad_cap_bm; 2902 2903 ioc_attr->ioc_type = bfa_ioc_get_type(ioc); 2904 2905 bfa_ioc_get_adapter_attr(ioc, &ioc_attr->adapter_attr); 2906 2907 ioc_attr->pci_attr.device_id = bfa_ioc_devid(ioc); 2908 ioc_attr->pci_attr.pcifn = bfa_ioc_pcifn(ioc); 2909 ioc_attr->def_fn = bfa_ioc_is_default(ioc); 2910 bfa_ioc_get_pci_chip_rev(ioc, ioc_attr->pci_attr.chip_rev); 2911 } 2912 2913 /* WWN public */ 2914 static u64 2915 bfa_ioc_get_pwwn(struct bfa_ioc *ioc) 2916 { 2917 return ioc->attr->pwwn; 2918 } 2919 2920 void 2921 bfa_nw_ioc_get_mac(struct bfa_ioc *ioc, u8 *mac) 2922 { 2923 ether_addr_copy(mac, ioc->attr->mac); 2924 } 2925 2926 /* Firmware failure detected. Start recovery actions. */ 2927 static void 2928 bfa_ioc_recover(struct bfa_ioc *ioc) 2929 { 2930 pr_crit("Heart Beat of IOC has failed\n"); 2931 bfa_ioc_stats(ioc, ioc_hbfails); 2932 bfa_ioc_stats_hb_count(ioc, ioc->hb_count); 2933 bfa_fsm_send_event(ioc, IOC_E_HBFAIL); 2934 } 2935 2936 /* BFA IOC PF private functions */ 2937 2938 static void 2939 bfa_iocpf_enable(struct bfa_ioc *ioc) 2940 { 2941 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_ENABLE); 2942 } 2943 2944 static void 2945 bfa_iocpf_disable(struct bfa_ioc *ioc) 2946 { 2947 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_DISABLE); 2948 } 2949 2950 static void 2951 bfa_iocpf_fail(struct bfa_ioc *ioc) 2952 { 2953 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FAIL); 2954 } 2955 2956 static void 2957 bfa_iocpf_initfail(struct bfa_ioc *ioc) 2958 { 2959 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_INITFAIL); 2960 } 2961 2962 static void 2963 bfa_iocpf_getattrfail(struct bfa_ioc *ioc) 2964 { 2965 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_GETATTRFAIL); 2966 } 2967 2968 static void 2969 bfa_iocpf_stop(struct bfa_ioc *ioc) 2970 { 2971 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP); 2972 } 2973 2974 void 2975 bfa_nw_iocpf_timeout(struct bfa_ioc *ioc) 2976 { 2977 enum bfa_iocpf_state iocpf_st; 2978 2979 iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm); 2980 2981 if (iocpf_st == BFA_IOCPF_HWINIT) 2982 bfa_ioc_poll_fwinit(ioc); 2983 else 2984 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT); 2985 } 2986 2987 void 2988 bfa_nw_iocpf_sem_timeout(struct bfa_ioc *ioc) 2989 { 2990 bfa_ioc_hw_sem_get(ioc); 2991 } 2992 2993 static void 2994 bfa_ioc_poll_fwinit(struct bfa_ioc *ioc) 2995 { 2996 u32 fwstate = bfa_ioc_get_cur_ioc_fwstate(ioc); 2997 2998 if (fwstate == BFI_IOC_DISABLED) { 2999 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY); 3000 return; 3001 } 3002 3003 if (ioc->iocpf.poll_time >= BFA_IOC_TOV) { 3004 bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT); 3005 } else { 3006 ioc->iocpf.poll_time += BFA_IOC_POLL_TOV; 3007 mod_timer(&ioc->iocpf_timer, jiffies + 3008 msecs_to_jiffies(BFA_IOC_POLL_TOV)); 3009 } 3010 } 3011 3012 /* 3013 * Flash module specific 3014 */ 3015 3016 /* 3017 * FLASH DMA buffer should be big enough to hold both MFG block and 3018 * asic block(64k) at the same time and also should be 2k aligned to 3019 * avoid write segement to cross sector boundary. 3020 */ 3021 #define BFA_FLASH_SEG_SZ 2048 3022 #define BFA_FLASH_DMA_BUF_SZ \ 3023 roundup(0x010000 + sizeof(struct bfa_mfg_block), BFA_FLASH_SEG_SZ) 3024 3025 static void 3026 bfa_flash_cb(struct bfa_flash *flash) 3027 { 3028 flash->op_busy = 0; 3029 if (flash->cbfn) 3030 flash->cbfn(flash->cbarg, flash->status); 3031 } 3032 3033 static void 3034 bfa_flash_notify(void *cbarg, enum bfa_ioc_event event) 3035 { 3036 struct bfa_flash *flash = cbarg; 3037 3038 switch (event) { 3039 case BFA_IOC_E_DISABLED: 3040 case BFA_IOC_E_FAILED: 3041 if (flash->op_busy) { 3042 flash->status = BFA_STATUS_IOC_FAILURE; 3043 flash->cbfn(flash->cbarg, flash->status); 3044 flash->op_busy = 0; 3045 } 3046 break; 3047 default: 3048 break; 3049 } 3050 } 3051 3052 /* 3053 * Send flash write request. 3054 */ 3055 static void 3056 bfa_flash_write_send(struct bfa_flash *flash) 3057 { 3058 struct bfi_flash_write_req *msg = 3059 (struct bfi_flash_write_req *) flash->mb.msg; 3060 u32 len; 3061 3062 msg->type = be32_to_cpu(flash->type); 3063 msg->instance = flash->instance; 3064 msg->offset = be32_to_cpu(flash->addr_off + flash->offset); 3065 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ? 3066 flash->residue : BFA_FLASH_DMA_BUF_SZ; 3067 msg->length = be32_to_cpu(len); 3068 3069 /* indicate if it's the last msg of the whole write operation */ 3070 msg->last = (len == flash->residue) ? 1 : 0; 3071 3072 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_WRITE_REQ, 3073 bfa_ioc_portid(flash->ioc)); 3074 bfa_alen_set(&msg->alen, len, flash->dbuf_pa); 3075 memcpy(flash->dbuf_kva, flash->ubuf + flash->offset, len); 3076 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL); 3077 3078 flash->residue -= len; 3079 flash->offset += len; 3080 } 3081 3082 /** 3083 * bfa_flash_read_send - Send flash read request. 3084 * 3085 * @cbarg: callback argument 3086 */ 3087 static void 3088 bfa_flash_read_send(void *cbarg) 3089 { 3090 struct bfa_flash *flash = cbarg; 3091 struct bfi_flash_read_req *msg = 3092 (struct bfi_flash_read_req *) flash->mb.msg; 3093 u32 len; 3094 3095 msg->type = be32_to_cpu(flash->type); 3096 msg->instance = flash->instance; 3097 msg->offset = be32_to_cpu(flash->addr_off + flash->offset); 3098 len = (flash->residue < BFA_FLASH_DMA_BUF_SZ) ? 3099 flash->residue : BFA_FLASH_DMA_BUF_SZ; 3100 msg->length = be32_to_cpu(len); 3101 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_READ_REQ, 3102 bfa_ioc_portid(flash->ioc)); 3103 bfa_alen_set(&msg->alen, len, flash->dbuf_pa); 3104 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL); 3105 } 3106 3107 /** 3108 * bfa_flash_intr - Process flash response messages upon receiving interrupts. 3109 * 3110 * @flasharg: flash structure 3111 * @msg: message structure 3112 */ 3113 static void 3114 bfa_flash_intr(void *flasharg, struct bfi_mbmsg *msg) 3115 { 3116 struct bfa_flash *flash = flasharg; 3117 u32 status; 3118 3119 union { 3120 struct bfi_flash_query_rsp *query; 3121 struct bfi_flash_write_rsp *write; 3122 struct bfi_flash_read_rsp *read; 3123 struct bfi_mbmsg *msg; 3124 } m; 3125 3126 m.msg = msg; 3127 3128 /* receiving response after ioc failure */ 3129 if (!flash->op_busy && msg->mh.msg_id != BFI_FLASH_I2H_EVENT) 3130 return; 3131 3132 switch (msg->mh.msg_id) { 3133 case BFI_FLASH_I2H_QUERY_RSP: 3134 status = be32_to_cpu(m.query->status); 3135 if (status == BFA_STATUS_OK) { 3136 u32 i; 3137 struct bfa_flash_attr *attr, *f; 3138 3139 attr = (struct bfa_flash_attr *) flash->ubuf; 3140 f = (struct bfa_flash_attr *) flash->dbuf_kva; 3141 attr->status = be32_to_cpu(f->status); 3142 attr->npart = be32_to_cpu(f->npart); 3143 for (i = 0; i < attr->npart; i++) { 3144 attr->part[i].part_type = 3145 be32_to_cpu(f->part[i].part_type); 3146 attr->part[i].part_instance = 3147 be32_to_cpu(f->part[i].part_instance); 3148 attr->part[i].part_off = 3149 be32_to_cpu(f->part[i].part_off); 3150 attr->part[i].part_size = 3151 be32_to_cpu(f->part[i].part_size); 3152 attr->part[i].part_len = 3153 be32_to_cpu(f->part[i].part_len); 3154 attr->part[i].part_status = 3155 be32_to_cpu(f->part[i].part_status); 3156 } 3157 } 3158 flash->status = status; 3159 bfa_flash_cb(flash); 3160 break; 3161 case BFI_FLASH_I2H_WRITE_RSP: 3162 status = be32_to_cpu(m.write->status); 3163 if (status != BFA_STATUS_OK || flash->residue == 0) { 3164 flash->status = status; 3165 bfa_flash_cb(flash); 3166 } else 3167 bfa_flash_write_send(flash); 3168 break; 3169 case BFI_FLASH_I2H_READ_RSP: 3170 status = be32_to_cpu(m.read->status); 3171 if (status != BFA_STATUS_OK) { 3172 flash->status = status; 3173 bfa_flash_cb(flash); 3174 } else { 3175 u32 len = be32_to_cpu(m.read->length); 3176 memcpy(flash->ubuf + flash->offset, 3177 flash->dbuf_kva, len); 3178 flash->residue -= len; 3179 flash->offset += len; 3180 if (flash->residue == 0) { 3181 flash->status = status; 3182 bfa_flash_cb(flash); 3183 } else 3184 bfa_flash_read_send(flash); 3185 } 3186 break; 3187 case BFI_FLASH_I2H_BOOT_VER_RSP: 3188 case BFI_FLASH_I2H_EVENT: 3189 break; 3190 default: 3191 WARN_ON(1); 3192 } 3193 } 3194 3195 /* 3196 * Flash memory info API. 3197 */ 3198 u32 3199 bfa_nw_flash_meminfo(void) 3200 { 3201 return roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ); 3202 } 3203 3204 /** 3205 * bfa_nw_flash_attach - Flash attach API. 3206 * 3207 * @flash: flash structure 3208 * @ioc: ioc structure 3209 * @dev: device structure 3210 */ 3211 void 3212 bfa_nw_flash_attach(struct bfa_flash *flash, struct bfa_ioc *ioc, void *dev) 3213 { 3214 flash->ioc = ioc; 3215 flash->cbfn = NULL; 3216 flash->cbarg = NULL; 3217 flash->op_busy = 0; 3218 3219 bfa_nw_ioc_mbox_regisr(flash->ioc, BFI_MC_FLASH, bfa_flash_intr, flash); 3220 bfa_ioc_notify_init(&flash->ioc_notify, bfa_flash_notify, flash); 3221 list_add_tail(&flash->ioc_notify.qe, &flash->ioc->notify_q); 3222 } 3223 3224 /** 3225 * bfa_nw_flash_memclaim - Claim memory for flash 3226 * 3227 * @flash: flash structure 3228 * @dm_kva: pointer to virtual memory address 3229 * @dm_pa: physical memory address 3230 */ 3231 void 3232 bfa_nw_flash_memclaim(struct bfa_flash *flash, u8 *dm_kva, u64 dm_pa) 3233 { 3234 flash->dbuf_kva = dm_kva; 3235 flash->dbuf_pa = dm_pa; 3236 memset(flash->dbuf_kva, 0, BFA_FLASH_DMA_BUF_SZ); 3237 dm_kva += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ); 3238 dm_pa += roundup(BFA_FLASH_DMA_BUF_SZ, BFA_DMA_ALIGN_SZ); 3239 } 3240 3241 /** 3242 * bfa_nw_flash_get_attr - Get flash attribute. 3243 * 3244 * @flash: flash structure 3245 * @attr: flash attribute structure 3246 * @cbfn: callback function 3247 * @cbarg: callback argument 3248 * 3249 * Return status. 3250 */ 3251 enum bfa_status 3252 bfa_nw_flash_get_attr(struct bfa_flash *flash, struct bfa_flash_attr *attr, 3253 bfa_cb_flash cbfn, void *cbarg) 3254 { 3255 struct bfi_flash_query_req *msg = 3256 (struct bfi_flash_query_req *) flash->mb.msg; 3257 3258 if (!bfa_nw_ioc_is_operational(flash->ioc)) 3259 return BFA_STATUS_IOC_NON_OP; 3260 3261 if (flash->op_busy) 3262 return BFA_STATUS_DEVBUSY; 3263 3264 flash->op_busy = 1; 3265 flash->cbfn = cbfn; 3266 flash->cbarg = cbarg; 3267 flash->ubuf = (u8 *) attr; 3268 3269 bfi_h2i_set(msg->mh, BFI_MC_FLASH, BFI_FLASH_H2I_QUERY_REQ, 3270 bfa_ioc_portid(flash->ioc)); 3271 bfa_alen_set(&msg->alen, sizeof(struct bfa_flash_attr), flash->dbuf_pa); 3272 bfa_nw_ioc_mbox_queue(flash->ioc, &flash->mb, NULL, NULL); 3273 3274 return BFA_STATUS_OK; 3275 } 3276 3277 /** 3278 * bfa_nw_flash_update_part - Update flash partition. 3279 * 3280 * @flash: flash structure 3281 * @type: flash partition type 3282 * @instance: flash partition instance 3283 * @buf: update data buffer 3284 * @len: data buffer length 3285 * @offset: offset relative to the partition starting address 3286 * @cbfn: callback function 3287 * @cbarg: callback argument 3288 * 3289 * Return status. 3290 */ 3291 enum bfa_status 3292 bfa_nw_flash_update_part(struct bfa_flash *flash, u32 type, u8 instance, 3293 void *buf, u32 len, u32 offset, 3294 bfa_cb_flash cbfn, void *cbarg) 3295 { 3296 if (!bfa_nw_ioc_is_operational(flash->ioc)) 3297 return BFA_STATUS_IOC_NON_OP; 3298 3299 /* 3300 * 'len' must be in word (4-byte) boundary 3301 */ 3302 if (!len || (len & 0x03)) 3303 return BFA_STATUS_FLASH_BAD_LEN; 3304 3305 if (type == BFA_FLASH_PART_MFG) 3306 return BFA_STATUS_EINVAL; 3307 3308 if (flash->op_busy) 3309 return BFA_STATUS_DEVBUSY; 3310 3311 flash->op_busy = 1; 3312 flash->cbfn = cbfn; 3313 flash->cbarg = cbarg; 3314 flash->type = type; 3315 flash->instance = instance; 3316 flash->residue = len; 3317 flash->offset = 0; 3318 flash->addr_off = offset; 3319 flash->ubuf = buf; 3320 3321 bfa_flash_write_send(flash); 3322 3323 return BFA_STATUS_OK; 3324 } 3325 3326 /** 3327 * bfa_nw_flash_read_part - Read flash partition. 3328 * 3329 * @flash: flash structure 3330 * @type: flash partition type 3331 * @instance: flash partition instance 3332 * @buf: read data buffer 3333 * @len: data buffer length 3334 * @offset: offset relative to the partition starting address 3335 * @cbfn: callback function 3336 * @cbarg: callback argument 3337 * 3338 * Return status. 3339 */ 3340 enum bfa_status 3341 bfa_nw_flash_read_part(struct bfa_flash *flash, u32 type, u8 instance, 3342 void *buf, u32 len, u32 offset, 3343 bfa_cb_flash cbfn, void *cbarg) 3344 { 3345 if (!bfa_nw_ioc_is_operational(flash->ioc)) 3346 return BFA_STATUS_IOC_NON_OP; 3347 3348 /* 3349 * 'len' must be in word (4-byte) boundary 3350 */ 3351 if (!len || (len & 0x03)) 3352 return BFA_STATUS_FLASH_BAD_LEN; 3353 3354 if (flash->op_busy) 3355 return BFA_STATUS_DEVBUSY; 3356 3357 flash->op_busy = 1; 3358 flash->cbfn = cbfn; 3359 flash->cbarg = cbarg; 3360 flash->type = type; 3361 flash->instance = instance; 3362 flash->residue = len; 3363 flash->offset = 0; 3364 flash->addr_off = offset; 3365 flash->ubuf = buf; 3366 3367 bfa_flash_read_send(flash); 3368 3369 return BFA_STATUS_OK; 3370 } 3371