1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ 2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 6 * Copyright (C) 2004 Sun Microsystems Inc. 7 * Copyright (C) 2007-2011 Broadcom Corporation. 8 */ 9 10 #ifndef _T3_H 11 #define _T3_H 12 13 #define TG3_64BIT_REG_HIGH 0x00UL 14 #define TG3_64BIT_REG_LOW 0x04UL 15 16 /* Descriptor block info. */ 17 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 18 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 19 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 20 #define BDINFO_FLAGS_DISABLED 0x00000002 21 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 22 #define BDINFO_FLAGS_MAXLEN_SHIFT 16 23 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 24 #define TG3_BDINFO_SIZE 0x10UL 25 26 #define TG3_RX_STD_MAX_SIZE_5700 512 27 #define TG3_RX_STD_MAX_SIZE_5717 2048 28 #define TG3_RX_JMB_MAX_SIZE_5700 256 29 #define TG3_RX_JMB_MAX_SIZE_5717 1024 30 #define TG3_RX_RET_MAX_SIZE_5700 1024 31 #define TG3_RX_RET_MAX_SIZE_5705 512 32 #define TG3_RX_RET_MAX_SIZE_5717 4096 33 34 /* First 256 bytes are a mirror of PCI config space. */ 35 #define TG3PCI_VENDOR 0x00000000 36 #define TG3PCI_VENDOR_BROADCOM 0x14e4 37 #define TG3PCI_DEVICE 0x00000002 38 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 39 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 40 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 41 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 42 #define TG3PCI_DEVICE_TIGON3_5761S 0x1688 43 #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 44 #define TG3PCI_DEVICE_TIGON3_57780 0x1692 45 #define TG3PCI_DEVICE_TIGON3_57760 0x1690 46 #define TG3PCI_DEVICE_TIGON3_57790 0x1694 47 #define TG3PCI_DEVICE_TIGON3_57788 0x1691 48 #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ 49 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ 50 #define TG3PCI_DEVICE_TIGON3_5717 0x1655 51 #define TG3PCI_DEVICE_TIGON3_5718 0x1656 52 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1 53 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5 54 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0 55 #define TG3PCI_DEVICE_TIGON3_57765 0x16b4 56 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2 57 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6 58 #define TG3PCI_DEVICE_TIGON3_5719 0x1657 59 #define TG3PCI_DEVICE_TIGON3_5720 0x165f 60 /* 0x04 --> 0x2c unused */ 61 #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM 62 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 63 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 64 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 65 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 66 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 67 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 68 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 69 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 70 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 71 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 72 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 73 #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM 74 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 75 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 76 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 77 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 78 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 79 #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL 80 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 81 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 82 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 83 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a 84 #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ 85 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c 86 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a 87 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d 88 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 89 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 90 #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM 91 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 92 /* 0x30 --> 0x64 unused */ 93 #define TG3PCI_MSI_DATA 0x00000064 94 /* 0x66 --> 0x68 unused */ 95 #define TG3PCI_MISC_HOST_CTRL 0x00000068 96 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 97 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 98 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 99 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 100 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 101 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 102 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 103 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 104 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 105 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 106 #define MISC_HOST_CTRL_CHIPREV 0xffff0000 107 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 108 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \ 109 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \ 110 MISC_HOST_CTRL_CHIPREV_SHIFT) 111 #define CHIPREV_ID_5700_A0 0x7000 112 #define CHIPREV_ID_5700_A1 0x7001 113 #define CHIPREV_ID_5700_B0 0x7100 114 #define CHIPREV_ID_5700_B1 0x7101 115 #define CHIPREV_ID_5700_B3 0x7102 116 #define CHIPREV_ID_5700_ALTIMA 0x7104 117 #define CHIPREV_ID_5700_C0 0x7200 118 #define CHIPREV_ID_5701_A0 0x0000 119 #define CHIPREV_ID_5701_B0 0x0100 120 #define CHIPREV_ID_5701_B2 0x0102 121 #define CHIPREV_ID_5701_B5 0x0105 122 #define CHIPREV_ID_5703_A0 0x1000 123 #define CHIPREV_ID_5703_A1 0x1001 124 #define CHIPREV_ID_5703_A2 0x1002 125 #define CHIPREV_ID_5703_A3 0x1003 126 #define CHIPREV_ID_5704_A0 0x2000 127 #define CHIPREV_ID_5704_A1 0x2001 128 #define CHIPREV_ID_5704_A2 0x2002 129 #define CHIPREV_ID_5704_A3 0x2003 130 #define CHIPREV_ID_5705_A0 0x3000 131 #define CHIPREV_ID_5705_A1 0x3001 132 #define CHIPREV_ID_5705_A2 0x3002 133 #define CHIPREV_ID_5705_A3 0x3003 134 #define CHIPREV_ID_5750_A0 0x4000 135 #define CHIPREV_ID_5750_A1 0x4001 136 #define CHIPREV_ID_5750_A3 0x4003 137 #define CHIPREV_ID_5750_C2 0x4202 138 #define CHIPREV_ID_5752_A0_HW 0x5000 139 #define CHIPREV_ID_5752_A0 0x6000 140 #define CHIPREV_ID_5752_A1 0x6001 141 #define CHIPREV_ID_5714_A2 0x9002 142 #define CHIPREV_ID_5906_A1 0xc001 143 #define CHIPREV_ID_57780_A0 0x57780000 144 #define CHIPREV_ID_57780_A1 0x57780001 145 #define CHIPREV_ID_5717_A0 0x05717000 146 #define CHIPREV_ID_57765_A0 0x57785000 147 #define CHIPREV_ID_5719_A0 0x05719000 148 #define CHIPREV_ID_5720_A0 0x05720000 149 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) 150 #define ASIC_REV_5700 0x07 151 #define ASIC_REV_5701 0x00 152 #define ASIC_REV_5703 0x01 153 #define ASIC_REV_5704 0x02 154 #define ASIC_REV_5705 0x03 155 #define ASIC_REV_5750 0x04 156 #define ASIC_REV_5752 0x06 157 #define ASIC_REV_5780 0x08 158 #define ASIC_REV_5714 0x09 159 #define ASIC_REV_5755 0x0a 160 #define ASIC_REV_5787 0x0b 161 #define ASIC_REV_5906 0x0c 162 #define ASIC_REV_USE_PROD_ID_REG 0x0f 163 #define ASIC_REV_5784 0x5784 164 #define ASIC_REV_5761 0x5761 165 #define ASIC_REV_5785 0x5785 166 #define ASIC_REV_57780 0x57780 167 #define ASIC_REV_5717 0x5717 168 #define ASIC_REV_57765 0x57785 169 #define ASIC_REV_5719 0x5719 170 #define ASIC_REV_5720 0x5720 171 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) 172 #define CHIPREV_5700_AX 0x70 173 #define CHIPREV_5700_BX 0x71 174 #define CHIPREV_5700_CX 0x72 175 #define CHIPREV_5701_AX 0x00 176 #define CHIPREV_5703_AX 0x10 177 #define CHIPREV_5704_AX 0x20 178 #define CHIPREV_5704_BX 0x21 179 #define CHIPREV_5750_AX 0x40 180 #define CHIPREV_5750_BX 0x41 181 #define CHIPREV_5784_AX 0x57840 182 #define CHIPREV_5761_AX 0x57610 183 #define CHIPREV_57765_AX 0x577650 184 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) 185 #define METAL_REV_A0 0x00 186 #define METAL_REV_A1 0x01 187 #define METAL_REV_B0 0x00 188 #define METAL_REV_B1 0x01 189 #define METAL_REV_B2 0x02 190 #define TG3PCI_DMA_RW_CTRL 0x0000006c 191 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 192 #define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 193 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 194 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 195 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 196 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 197 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 198 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 199 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 200 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 201 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 202 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 203 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 204 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 205 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 206 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 207 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 208 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 209 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 210 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 211 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 212 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 213 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 214 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 215 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 216 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 217 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 218 #define DMA_RWCTRL_ONE_DMA 0x00004000 219 #define DMA_RWCTRL_READ_WATER 0x00070000 220 #define DMA_RWCTRL_READ_WATER_SHIFT 16 221 #define DMA_RWCTRL_WRITE_WATER 0x00380000 222 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 223 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 224 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 225 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 226 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 227 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 228 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 229 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 230 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 231 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 232 #define TG3PCI_PCISTATE 0x00000070 233 #define PCISTATE_FORCE_RESET 0x00000001 234 #define PCISTATE_INT_NOT_ACTIVE 0x00000002 235 #define PCISTATE_CONV_PCI_MODE 0x00000004 236 #define PCISTATE_BUS_SPEED_HIGH 0x00000008 237 #define PCISTATE_BUS_32BIT 0x00000010 238 #define PCISTATE_ROM_ENABLE 0x00000020 239 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 240 #define PCISTATE_FLAT_VIEW 0x00000100 241 #define PCISTATE_RETRY_SAME_DMA 0x00002000 242 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 243 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 244 #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 245 #define TG3PCI_CLOCK_CTRL 0x00000074 246 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 247 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 248 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 249 #define CLOCK_CTRL_ALTCLK 0x00001000 250 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 251 #define CLOCK_CTRL_44MHZ_CORE 0x00040000 252 #define CLOCK_CTRL_625_CORE 0x00100000 253 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 254 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 255 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 256 #define TG3PCI_REG_BASE_ADDR 0x00000078 257 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 258 #define TG3PCI_REG_DATA 0x00000080 259 #define TG3PCI_MEM_WIN_DATA 0x00000084 260 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 261 /* 0x94 --> 0x98 unused */ 262 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 263 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 264 /* 0xa8 --> 0xb8 unused */ 265 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8 266 #define DUAL_MAC_CTRL_CH_MASK 0x00000003 267 #define DUAL_MAC_CTRL_ID 0x00000004 268 #define TG3PCI_PRODID_ASICREV 0x000000bc 269 #define PROD_ID_ASIC_REV_MASK 0x0fffffff 270 /* 0xc0 --> 0xf4 unused */ 271 272 #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 273 #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc 274 /* 0xf8 --> 0x200 unused */ 275 276 #define TG3_CORR_ERR_STAT 0x00000110 277 #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff 278 /* 0x114 --> 0x200 unused */ 279 280 /* Mailbox registers */ 281 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 282 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 283 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 284 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 285 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 286 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 287 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 288 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 289 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 290 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 291 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 292 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 293 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 294 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 295 #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ 296 TG3_64BIT_REG_LOW) 297 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 298 #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ 299 TG3_64BIT_REG_LOW) 300 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 301 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 302 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 303 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 304 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 305 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 306 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 307 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 308 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 309 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 310 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 311 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 312 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 313 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 314 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 315 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 316 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 317 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 318 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 319 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 320 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 321 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 322 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 323 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 324 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 325 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 326 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 327 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 328 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 329 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 330 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 331 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 332 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 333 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 334 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 335 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 336 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 337 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 338 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 339 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 340 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 341 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 342 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 343 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 344 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 345 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 346 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 347 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 348 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 349 350 /* MAC control registers */ 351 #define MAC_MODE 0x00000400 352 #define MAC_MODE_RESET 0x00000001 353 #define MAC_MODE_HALF_DUPLEX 0x00000002 354 #define MAC_MODE_PORT_MODE_MASK 0x0000000c 355 #define MAC_MODE_PORT_MODE_TBI 0x0000000c 356 #define MAC_MODE_PORT_MODE_GMII 0x00000008 357 #define MAC_MODE_PORT_MODE_MII 0x00000004 358 #define MAC_MODE_PORT_MODE_NONE 0x00000000 359 #define MAC_MODE_PORT_INT_LPBACK 0x00000010 360 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 361 #define MAC_MODE_TX_BURSTING 0x00000100 362 #define MAC_MODE_MAX_DEFER 0x00000200 363 #define MAC_MODE_LINK_POLARITY 0x00000400 364 #define MAC_MODE_RXSTAT_ENABLE 0x00000800 365 #define MAC_MODE_RXSTAT_CLEAR 0x00001000 366 #define MAC_MODE_RXSTAT_FLUSH 0x00002000 367 #define MAC_MODE_TXSTAT_ENABLE 0x00004000 368 #define MAC_MODE_TXSTAT_CLEAR 0x00008000 369 #define MAC_MODE_TXSTAT_FLUSH 0x00010000 370 #define MAC_MODE_SEND_CONFIGS 0x00020000 371 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 372 #define MAC_MODE_ACPI_ENABLE 0x00080000 373 #define MAC_MODE_MIP_ENABLE 0x00100000 374 #define MAC_MODE_TDE_ENABLE 0x00200000 375 #define MAC_MODE_RDE_ENABLE 0x00400000 376 #define MAC_MODE_FHDE_ENABLE 0x00800000 377 #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 378 #define MAC_MODE_APE_RX_EN 0x08000000 379 #define MAC_MODE_APE_TX_EN 0x10000000 380 #define MAC_STATUS 0x00000404 381 #define MAC_STATUS_PCS_SYNCED 0x00000001 382 #define MAC_STATUS_SIGNAL_DET 0x00000002 383 #define MAC_STATUS_RCVD_CFG 0x00000004 384 #define MAC_STATUS_CFG_CHANGED 0x00000008 385 #define MAC_STATUS_SYNC_CHANGED 0x00000010 386 #define MAC_STATUS_PORT_DEC_ERR 0x00000400 387 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 388 #define MAC_STATUS_MI_COMPLETION 0x00400000 389 #define MAC_STATUS_MI_INTERRUPT 0x00800000 390 #define MAC_STATUS_AP_ERROR 0x01000000 391 #define MAC_STATUS_ODI_ERROR 0x02000000 392 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 393 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 394 #define MAC_EVENT 0x00000408 395 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 396 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 397 #define MAC_EVENT_MI_COMPLETION 0x00400000 398 #define MAC_EVENT_MI_INTERRUPT 0x00800000 399 #define MAC_EVENT_AP_ERROR 0x01000000 400 #define MAC_EVENT_ODI_ERROR 0x02000000 401 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 402 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 403 #define MAC_LED_CTRL 0x0000040c 404 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 405 #define LED_CTRL_1000MBPS_ON 0x00000002 406 #define LED_CTRL_100MBPS_ON 0x00000004 407 #define LED_CTRL_10MBPS_ON 0x00000008 408 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 409 #define LED_CTRL_TRAFFIC_BLINK 0x00000020 410 #define LED_CTRL_TRAFFIC_LED 0x00000040 411 #define LED_CTRL_1000MBPS_STATUS 0x00000080 412 #define LED_CTRL_100MBPS_STATUS 0x00000100 413 #define LED_CTRL_10MBPS_STATUS 0x00000200 414 #define LED_CTRL_TRAFFIC_STATUS 0x00000400 415 #define LED_CTRL_MODE_MAC 0x00000000 416 #define LED_CTRL_MODE_PHY_1 0x00000800 417 #define LED_CTRL_MODE_PHY_2 0x00001000 418 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000 419 #define LED_CTRL_MODE_SHARED 0x00004000 420 #define LED_CTRL_MODE_COMBO 0x00008000 421 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 422 #define LED_CTRL_BLINK_RATE_SHIFT 19 423 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 424 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 425 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 426 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 427 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 428 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 429 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 430 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 431 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 432 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 433 #define MAC_ACPI_MBUF_PTR 0x00000430 434 #define MAC_ACPI_LEN_OFFSET 0x00000434 435 #define ACPI_LENOFF_LEN_MASK 0x0000ffff 436 #define ACPI_LENOFF_LEN_SHIFT 0 437 #define ACPI_LENOFF_OFF_MASK 0x0fff0000 438 #define ACPI_LENOFF_OFF_SHIFT 16 439 #define MAC_TX_BACKOFF_SEED 0x00000438 440 #define TX_BACKOFF_SEED_MASK 0x000003ff 441 #define MAC_RX_MTU_SIZE 0x0000043c 442 #define RX_MTU_SIZE_MASK 0x0000ffff 443 #define MAC_PCS_TEST 0x00000440 444 #define PCS_TEST_PATTERN_MASK 0x000fffff 445 #define PCS_TEST_PATTERN_SHIFT 0 446 #define PCS_TEST_ENABLE 0x00100000 447 #define MAC_TX_AUTO_NEG 0x00000444 448 #define TX_AUTO_NEG_MASK 0x0000ffff 449 #define TX_AUTO_NEG_SHIFT 0 450 #define MAC_RX_AUTO_NEG 0x00000448 451 #define RX_AUTO_NEG_MASK 0x0000ffff 452 #define RX_AUTO_NEG_SHIFT 0 453 #define MAC_MI_COM 0x0000044c 454 #define MI_COM_CMD_MASK 0x0c000000 455 #define MI_COM_CMD_WRITE 0x04000000 456 #define MI_COM_CMD_READ 0x08000000 457 #define MI_COM_READ_FAILED 0x10000000 458 #define MI_COM_START 0x20000000 459 #define MI_COM_BUSY 0x20000000 460 #define MI_COM_PHY_ADDR_MASK 0x03e00000 461 #define MI_COM_PHY_ADDR_SHIFT 21 462 #define MI_COM_REG_ADDR_MASK 0x001f0000 463 #define MI_COM_REG_ADDR_SHIFT 16 464 #define MI_COM_DATA_MASK 0x0000ffff 465 #define MAC_MI_STAT 0x00000450 466 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 467 #define MAC_MI_STAT_10MBPS_MODE 0x00000002 468 #define MAC_MI_MODE 0x00000454 469 #define MAC_MI_MODE_CLK_10MHZ 0x00000001 470 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 471 #define MAC_MI_MODE_AUTO_POLL 0x00000010 472 #define MAC_MI_MODE_500KHZ_CONST 0x00008000 473 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 474 #define MAC_AUTO_POLL_STATUS 0x00000458 475 #define MAC_AUTO_POLL_ERROR 0x00000001 476 #define MAC_TX_MODE 0x0000045c 477 #define TX_MODE_RESET 0x00000001 478 #define TX_MODE_ENABLE 0x00000002 479 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 480 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 481 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 482 #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 483 #define TX_MODE_JMB_FRM_LEN 0x00400000 484 #define TX_MODE_CNT_DN_MODE 0x00800000 485 #define MAC_TX_STATUS 0x00000460 486 #define TX_STATUS_XOFFED 0x00000001 487 #define TX_STATUS_SENT_XOFF 0x00000002 488 #define TX_STATUS_SENT_XON 0x00000004 489 #define TX_STATUS_LINK_UP 0x00000008 490 #define TX_STATUS_ODI_UNDERRUN 0x00000010 491 #define TX_STATUS_ODI_OVERRUN 0x00000020 492 #define MAC_TX_LENGTHS 0x00000464 493 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 494 #define TX_LENGTHS_SLOT_TIME_SHIFT 0 495 #define TX_LENGTHS_IPG_MASK 0x00000f00 496 #define TX_LENGTHS_IPG_SHIFT 8 497 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 498 #define TX_LENGTHS_IPG_CRS_SHIFT 12 499 #define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000 500 #define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000 501 #define MAC_RX_MODE 0x00000468 502 #define RX_MODE_RESET 0x00000001 503 #define RX_MODE_ENABLE 0x00000002 504 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 505 #define RX_MODE_KEEP_MAC_CTRL 0x00000008 506 #define RX_MODE_KEEP_PAUSE 0x00000010 507 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 508 #define RX_MODE_ACCEPT_RUNTS 0x00000040 509 #define RX_MODE_LEN_CHECK 0x00000080 510 #define RX_MODE_PROMISC 0x00000100 511 #define RX_MODE_NO_CRC_CHECK 0x00000200 512 #define RX_MODE_KEEP_VLAN_TAG 0x00000400 513 #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 514 #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 515 #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 516 #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 517 #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 518 #define RX_MODE_RSS_ENABLE 0x00800000 519 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 520 #define MAC_RX_STATUS 0x0000046c 521 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 522 #define RX_STATUS_XOFF_RCVD 0x00000002 523 #define RX_STATUS_XON_RCVD 0x00000004 524 #define MAC_HASH_REG_0 0x00000470 525 #define MAC_HASH_REG_1 0x00000474 526 #define MAC_HASH_REG_2 0x00000478 527 #define MAC_HASH_REG_3 0x0000047c 528 #define MAC_RCV_RULE_0 0x00000480 529 #define MAC_RCV_VALUE_0 0x00000484 530 #define MAC_RCV_RULE_1 0x00000488 531 #define MAC_RCV_VALUE_1 0x0000048c 532 #define MAC_RCV_RULE_2 0x00000490 533 #define MAC_RCV_VALUE_2 0x00000494 534 #define MAC_RCV_RULE_3 0x00000498 535 #define MAC_RCV_VALUE_3 0x0000049c 536 #define MAC_RCV_RULE_4 0x000004a0 537 #define MAC_RCV_VALUE_4 0x000004a4 538 #define MAC_RCV_RULE_5 0x000004a8 539 #define MAC_RCV_VALUE_5 0x000004ac 540 #define MAC_RCV_RULE_6 0x000004b0 541 #define MAC_RCV_VALUE_6 0x000004b4 542 #define MAC_RCV_RULE_7 0x000004b8 543 #define MAC_RCV_VALUE_7 0x000004bc 544 #define MAC_RCV_RULE_8 0x000004c0 545 #define MAC_RCV_VALUE_8 0x000004c4 546 #define MAC_RCV_RULE_9 0x000004c8 547 #define MAC_RCV_VALUE_9 0x000004cc 548 #define MAC_RCV_RULE_10 0x000004d0 549 #define MAC_RCV_VALUE_10 0x000004d4 550 #define MAC_RCV_RULE_11 0x000004d8 551 #define MAC_RCV_VALUE_11 0x000004dc 552 #define MAC_RCV_RULE_12 0x000004e0 553 #define MAC_RCV_VALUE_12 0x000004e4 554 #define MAC_RCV_RULE_13 0x000004e8 555 #define MAC_RCV_VALUE_13 0x000004ec 556 #define MAC_RCV_RULE_14 0x000004f0 557 #define MAC_RCV_VALUE_14 0x000004f4 558 #define MAC_RCV_RULE_15 0x000004f8 559 #define MAC_RCV_VALUE_15 0x000004fc 560 #define RCV_RULE_DISABLE_MASK 0x7fffffff 561 #define MAC_RCV_RULE_CFG 0x00000500 562 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 563 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 564 /* 0x508 --> 0x520 unused */ 565 #define MAC_HASHREGU_0 0x00000520 566 #define MAC_HASHREGU_1 0x00000524 567 #define MAC_HASHREGU_2 0x00000528 568 #define MAC_HASHREGU_3 0x0000052c 569 #define MAC_EXTADDR_0_HIGH 0x00000530 570 #define MAC_EXTADDR_0_LOW 0x00000534 571 #define MAC_EXTADDR_1_HIGH 0x00000538 572 #define MAC_EXTADDR_1_LOW 0x0000053c 573 #define MAC_EXTADDR_2_HIGH 0x00000540 574 #define MAC_EXTADDR_2_LOW 0x00000544 575 #define MAC_EXTADDR_3_HIGH 0x00000548 576 #define MAC_EXTADDR_3_LOW 0x0000054c 577 #define MAC_EXTADDR_4_HIGH 0x00000550 578 #define MAC_EXTADDR_4_LOW 0x00000554 579 #define MAC_EXTADDR_5_HIGH 0x00000558 580 #define MAC_EXTADDR_5_LOW 0x0000055c 581 #define MAC_EXTADDR_6_HIGH 0x00000560 582 #define MAC_EXTADDR_6_LOW 0x00000564 583 #define MAC_EXTADDR_7_HIGH 0x00000568 584 #define MAC_EXTADDR_7_LOW 0x0000056c 585 #define MAC_EXTADDR_8_HIGH 0x00000570 586 #define MAC_EXTADDR_8_LOW 0x00000574 587 #define MAC_EXTADDR_9_HIGH 0x00000578 588 #define MAC_EXTADDR_9_LOW 0x0000057c 589 #define MAC_EXTADDR_10_HIGH 0x00000580 590 #define MAC_EXTADDR_10_LOW 0x00000584 591 #define MAC_EXTADDR_11_HIGH 0x00000588 592 #define MAC_EXTADDR_11_LOW 0x0000058c 593 #define MAC_SERDES_CFG 0x00000590 594 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 595 #define MAC_SERDES_STAT 0x00000594 596 /* 0x598 --> 0x5a0 unused */ 597 #define MAC_PHYCFG1 0x000005a0 598 #define MAC_PHYCFG1_RGMII_INT 0x00000001 599 #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 600 #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 601 #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 602 #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 603 #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 604 #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 605 #define MAC_PHYCFG1_TXC_DRV 0x20000000 606 #define MAC_PHYCFG2 0x000005a4 607 #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 608 #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 609 #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 610 #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 611 #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 612 #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 613 #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 614 #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 615 #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 616 #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 617 #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 618 #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 619 #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 620 #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 621 #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 622 #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 623 #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 624 #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 625 #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 626 #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 627 #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 628 #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 629 #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 630 #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 631 #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 632 #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 633 #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 634 #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 635 #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 636 #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 637 #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 638 #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 639 #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 640 #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 641 #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 642 #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 643 #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 644 #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 645 #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 646 #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 647 #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 648 #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 649 #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 650 #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 651 #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 652 #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 653 #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 654 #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 655 #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 656 #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 657 #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 658 #define MAC_PHYCFG2_50610_LED_MODES \ 659 (MAC_PHYCFG2_EMODE_MASK_50610 | \ 660 MAC_PHYCFG2_EMODE_COMP_50610 | \ 661 MAC_PHYCFG2_FMODE_MASK_50610 | \ 662 MAC_PHYCFG2_FMODE_COMP_50610 | \ 663 MAC_PHYCFG2_GMODE_MASK_50610 | \ 664 MAC_PHYCFG2_GMODE_COMP_50610 | \ 665 MAC_PHYCFG2_ACT_MASK_50610 | \ 666 MAC_PHYCFG2_ACT_COMP_50610 | \ 667 MAC_PHYCFG2_QUAL_MASK_50610 | \ 668 MAC_PHYCFG2_QUAL_COMP_50610) 669 #define MAC_PHYCFG2_AC131_LED_MODES \ 670 (MAC_PHYCFG2_EMODE_MASK_AC131 | \ 671 MAC_PHYCFG2_EMODE_COMP_AC131 | \ 672 MAC_PHYCFG2_FMODE_MASK_AC131 | \ 673 MAC_PHYCFG2_FMODE_COMP_AC131 | \ 674 MAC_PHYCFG2_GMODE_MASK_AC131 | \ 675 MAC_PHYCFG2_GMODE_COMP_AC131 | \ 676 MAC_PHYCFG2_ACT_MASK_AC131 | \ 677 MAC_PHYCFG2_ACT_COMP_AC131 | \ 678 MAC_PHYCFG2_QUAL_MASK_AC131 | \ 679 MAC_PHYCFG2_QUAL_COMP_AC131) 680 #define MAC_PHYCFG2_RTL8211C_LED_MODES \ 681 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ 682 MAC_PHYCFG2_EMODE_COMP_RT8211 | \ 683 MAC_PHYCFG2_FMODE_MASK_RT8211 | \ 684 MAC_PHYCFG2_FMODE_COMP_RT8211 | \ 685 MAC_PHYCFG2_GMODE_MASK_RT8211 | \ 686 MAC_PHYCFG2_GMODE_COMP_RT8211 | \ 687 MAC_PHYCFG2_ACT_MASK_RT8211 | \ 688 MAC_PHYCFG2_ACT_COMP_RT8211 | \ 689 MAC_PHYCFG2_QUAL_MASK_RT8211 | \ 690 MAC_PHYCFG2_QUAL_COMP_RT8211) 691 #define MAC_PHYCFG2_RTL8201E_LED_MODES \ 692 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ 693 MAC_PHYCFG2_EMODE_COMP_RT8201 | \ 694 MAC_PHYCFG2_FMODE_MASK_RT8201 | \ 695 MAC_PHYCFG2_FMODE_COMP_RT8201 | \ 696 MAC_PHYCFG2_GMODE_MASK_RT8201 | \ 697 MAC_PHYCFG2_GMODE_COMP_RT8201 | \ 698 MAC_PHYCFG2_ACT_MASK_RT8201 | \ 699 MAC_PHYCFG2_ACT_COMP_RT8201 | \ 700 MAC_PHYCFG2_QUAL_MASK_RT8201 | \ 701 MAC_PHYCFG2_QUAL_COMP_RT8201) 702 #define MAC_EXT_RGMII_MODE 0x000005a8 703 #define MAC_RGMII_MODE_TX_ENABLE 0x00000001 704 #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 705 #define MAC_RGMII_MODE_TX_RESET 0x00000004 706 #define MAC_RGMII_MODE_RX_INT_B 0x00000100 707 #define MAC_RGMII_MODE_RX_QUALITY 0x00000200 708 #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 709 #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 710 /* 0x5ac --> 0x5b0 unused */ 711 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 712 #define SERDES_RX_SIG_DETECT 0x00000400 713 #define SG_DIG_CTRL 0x000005b0 714 #define SG_DIG_USING_HW_AUTONEG 0x80000000 715 #define SG_DIG_SOFT_RESET 0x40000000 716 #define SG_DIG_DISABLE_LINKRDY 0x20000000 717 #define SG_DIG_CRC16_CLEAR_N 0x01000000 718 #define SG_DIG_EN10B 0x00800000 719 #define SG_DIG_CLEAR_STATUS 0x00400000 720 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 721 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000 722 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000 723 #define SG_DIG_SPEED_STATUS_SHIFT 18 724 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 725 #define SG_DIG_RESTART_AUTONEG 0x00010000 726 #define SG_DIG_FIBER_MODE 0x00008000 727 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000 728 #define SG_DIG_PAUSE_MASK 0x00001800 729 #define SG_DIG_PAUSE_CAP 0x00000800 730 #define SG_DIG_ASYM_PAUSE 0x00001000 731 #define SG_DIG_GBIC_ENABLE 0x00000400 732 #define SG_DIG_CHECK_END_ENABLE 0x00000200 733 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 734 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 735 #define SG_DIG_GMII_INPUT_SELECT 0x00000040 736 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020 737 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 738 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 739 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 740 #define SG_DIG_REMOTE_LOOPBACK 0x00000002 741 #define SG_DIG_LOOPBACK 0x00000001 742 #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ 743 SG_DIG_LOCAL_DUPLEX_STATUS | \ 744 SG_DIG_LOCAL_LINK_STATUS | \ 745 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ 746 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) 747 #define SG_DIG_STATUS 0x000005b4 748 #define SG_DIG_CRC16_BUS_MASK 0xffff0000 749 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 750 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 751 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 752 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 753 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 754 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 755 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 756 #define SG_DIG_IS_SERDES 0x00000100 757 #define SG_DIG_COMMA_DETECTOR 0x00000008 758 #define SG_DIG_MAC_ACK_STATUS 0x00000004 759 #define SG_DIG_AUTONEG_COMPLETE 0x00000002 760 #define SG_DIG_AUTONEG_ERROR 0x00000001 761 /* 0x5b8 --> 0x600 unused */ 762 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 763 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 764 /* 0x624 --> 0x670 unused */ 765 766 #define MAC_RSS_INDIR_TBL_0 0x00000630 767 768 #define MAC_RSS_HASH_KEY_0 0x00000670 769 #define MAC_RSS_HASH_KEY_1 0x00000674 770 #define MAC_RSS_HASH_KEY_2 0x00000678 771 #define MAC_RSS_HASH_KEY_3 0x0000067c 772 #define MAC_RSS_HASH_KEY_4 0x00000680 773 #define MAC_RSS_HASH_KEY_5 0x00000684 774 #define MAC_RSS_HASH_KEY_6 0x00000688 775 #define MAC_RSS_HASH_KEY_7 0x0000068c 776 #define MAC_RSS_HASH_KEY_8 0x00000690 777 #define MAC_RSS_HASH_KEY_9 0x00000694 778 /* 0x698 --> 0x800 unused */ 779 780 #define MAC_TX_STATS_OCTETS 0x00000800 781 #define MAC_TX_STATS_RESV1 0x00000804 782 #define MAC_TX_STATS_COLLISIONS 0x00000808 783 #define MAC_TX_STATS_XON_SENT 0x0000080c 784 #define MAC_TX_STATS_XOFF_SENT 0x00000810 785 #define MAC_TX_STATS_RESV2 0x00000814 786 #define MAC_TX_STATS_MAC_ERRORS 0x00000818 787 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 788 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 789 #define MAC_TX_STATS_DEFERRED 0x00000824 790 #define MAC_TX_STATS_RESV3 0x00000828 791 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 792 #define MAC_TX_STATS_LATE_COL 0x00000830 793 #define MAC_TX_STATS_RESV4_1 0x00000834 794 #define MAC_TX_STATS_RESV4_2 0x00000838 795 #define MAC_TX_STATS_RESV4_3 0x0000083c 796 #define MAC_TX_STATS_RESV4_4 0x00000840 797 #define MAC_TX_STATS_RESV4_5 0x00000844 798 #define MAC_TX_STATS_RESV4_6 0x00000848 799 #define MAC_TX_STATS_RESV4_7 0x0000084c 800 #define MAC_TX_STATS_RESV4_8 0x00000850 801 #define MAC_TX_STATS_RESV4_9 0x00000854 802 #define MAC_TX_STATS_RESV4_10 0x00000858 803 #define MAC_TX_STATS_RESV4_11 0x0000085c 804 #define MAC_TX_STATS_RESV4_12 0x00000860 805 #define MAC_TX_STATS_RESV4_13 0x00000864 806 #define MAC_TX_STATS_RESV4_14 0x00000868 807 #define MAC_TX_STATS_UCAST 0x0000086c 808 #define MAC_TX_STATS_MCAST 0x00000870 809 #define MAC_TX_STATS_BCAST 0x00000874 810 #define MAC_TX_STATS_RESV5_1 0x00000878 811 #define MAC_TX_STATS_RESV5_2 0x0000087c 812 #define MAC_RX_STATS_OCTETS 0x00000880 813 #define MAC_RX_STATS_RESV1 0x00000884 814 #define MAC_RX_STATS_FRAGMENTS 0x00000888 815 #define MAC_RX_STATS_UCAST 0x0000088c 816 #define MAC_RX_STATS_MCAST 0x00000890 817 #define MAC_RX_STATS_BCAST 0x00000894 818 #define MAC_RX_STATS_FCS_ERRORS 0x00000898 819 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 820 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 821 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 822 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 823 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 824 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 825 #define MAC_RX_STATS_JABBERS 0x000008b4 826 #define MAC_RX_STATS_UNDERSIZE 0x000008b8 827 /* 0x8bc --> 0xc00 unused */ 828 829 /* Send data initiator control registers */ 830 #define SNDDATAI_MODE 0x00000c00 831 #define SNDDATAI_MODE_RESET 0x00000001 832 #define SNDDATAI_MODE_ENABLE 0x00000002 833 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 834 #define SNDDATAI_STATUS 0x00000c04 835 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 836 #define SNDDATAI_STATSCTRL 0x00000c08 837 #define SNDDATAI_SCTRL_ENABLE 0x00000001 838 #define SNDDATAI_SCTRL_FASTUPD 0x00000002 839 #define SNDDATAI_SCTRL_CLEAR 0x00000004 840 #define SNDDATAI_SCTRL_FLUSH 0x00000008 841 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 842 #define SNDDATAI_STATSENAB 0x00000c0c 843 #define SNDDATAI_STATSINCMASK 0x00000c10 844 #define ISO_PKT_TX 0x00000c20 845 /* 0xc24 --> 0xc80 unused */ 846 #define SNDDATAI_COS_CNT_0 0x00000c80 847 #define SNDDATAI_COS_CNT_1 0x00000c84 848 #define SNDDATAI_COS_CNT_2 0x00000c88 849 #define SNDDATAI_COS_CNT_3 0x00000c8c 850 #define SNDDATAI_COS_CNT_4 0x00000c90 851 #define SNDDATAI_COS_CNT_5 0x00000c94 852 #define SNDDATAI_COS_CNT_6 0x00000c98 853 #define SNDDATAI_COS_CNT_7 0x00000c9c 854 #define SNDDATAI_COS_CNT_8 0x00000ca0 855 #define SNDDATAI_COS_CNT_9 0x00000ca4 856 #define SNDDATAI_COS_CNT_10 0x00000ca8 857 #define SNDDATAI_COS_CNT_11 0x00000cac 858 #define SNDDATAI_COS_CNT_12 0x00000cb0 859 #define SNDDATAI_COS_CNT_13 0x00000cb4 860 #define SNDDATAI_COS_CNT_14 0x00000cb8 861 #define SNDDATAI_COS_CNT_15 0x00000cbc 862 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 863 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 864 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 865 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 866 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 867 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 868 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 869 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 870 /* 0xce0 --> 0x1000 unused */ 871 872 /* Send data completion control registers */ 873 #define SNDDATAC_MODE 0x00001000 874 #define SNDDATAC_MODE_RESET 0x00000001 875 #define SNDDATAC_MODE_ENABLE 0x00000002 876 #define SNDDATAC_MODE_CDELAY 0x00000010 877 /* 0x1004 --> 0x1400 unused */ 878 879 /* Send BD ring selector */ 880 #define SNDBDS_MODE 0x00001400 881 #define SNDBDS_MODE_RESET 0x00000001 882 #define SNDBDS_MODE_ENABLE 0x00000002 883 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 884 #define SNDBDS_STATUS 0x00001404 885 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 886 #define SNDBDS_HWDIAG 0x00001408 887 /* 0x140c --> 0x1440 */ 888 #define SNDBDS_SEL_CON_IDX_0 0x00001440 889 #define SNDBDS_SEL_CON_IDX_1 0x00001444 890 #define SNDBDS_SEL_CON_IDX_2 0x00001448 891 #define SNDBDS_SEL_CON_IDX_3 0x0000144c 892 #define SNDBDS_SEL_CON_IDX_4 0x00001450 893 #define SNDBDS_SEL_CON_IDX_5 0x00001454 894 #define SNDBDS_SEL_CON_IDX_6 0x00001458 895 #define SNDBDS_SEL_CON_IDX_7 0x0000145c 896 #define SNDBDS_SEL_CON_IDX_8 0x00001460 897 #define SNDBDS_SEL_CON_IDX_9 0x00001464 898 #define SNDBDS_SEL_CON_IDX_10 0x00001468 899 #define SNDBDS_SEL_CON_IDX_11 0x0000146c 900 #define SNDBDS_SEL_CON_IDX_12 0x00001470 901 #define SNDBDS_SEL_CON_IDX_13 0x00001474 902 #define SNDBDS_SEL_CON_IDX_14 0x00001478 903 #define SNDBDS_SEL_CON_IDX_15 0x0000147c 904 /* 0x1480 --> 0x1800 unused */ 905 906 /* Send BD initiator control registers */ 907 #define SNDBDI_MODE 0x00001800 908 #define SNDBDI_MODE_RESET 0x00000001 909 #define SNDBDI_MODE_ENABLE 0x00000002 910 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 911 #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 912 #define SNDBDI_STATUS 0x00001804 913 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 914 #define SNDBDI_IN_PROD_IDX_0 0x00001808 915 #define SNDBDI_IN_PROD_IDX_1 0x0000180c 916 #define SNDBDI_IN_PROD_IDX_2 0x00001810 917 #define SNDBDI_IN_PROD_IDX_3 0x00001814 918 #define SNDBDI_IN_PROD_IDX_4 0x00001818 919 #define SNDBDI_IN_PROD_IDX_5 0x0000181c 920 #define SNDBDI_IN_PROD_IDX_6 0x00001820 921 #define SNDBDI_IN_PROD_IDX_7 0x00001824 922 #define SNDBDI_IN_PROD_IDX_8 0x00001828 923 #define SNDBDI_IN_PROD_IDX_9 0x0000182c 924 #define SNDBDI_IN_PROD_IDX_10 0x00001830 925 #define SNDBDI_IN_PROD_IDX_11 0x00001834 926 #define SNDBDI_IN_PROD_IDX_12 0x00001838 927 #define SNDBDI_IN_PROD_IDX_13 0x0000183c 928 #define SNDBDI_IN_PROD_IDX_14 0x00001840 929 #define SNDBDI_IN_PROD_IDX_15 0x00001844 930 /* 0x1848 --> 0x1c00 unused */ 931 932 /* Send BD completion control registers */ 933 #define SNDBDC_MODE 0x00001c00 934 #define SNDBDC_MODE_RESET 0x00000001 935 #define SNDBDC_MODE_ENABLE 0x00000002 936 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 937 /* 0x1c04 --> 0x2000 unused */ 938 939 /* Receive list placement control registers */ 940 #define RCVLPC_MODE 0x00002000 941 #define RCVLPC_MODE_RESET 0x00000001 942 #define RCVLPC_MODE_ENABLE 0x00000002 943 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 944 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 945 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 946 #define RCVLPC_STATUS 0x00002004 947 #define RCVLPC_STATUS_CLASS0 0x00000004 948 #define RCVLPC_STATUS_MAPOOR 0x00000008 949 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 950 #define RCVLPC_LOCK 0x00002008 951 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff 952 #define RCVLPC_LOCK_REQ_SHIFT 0 953 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 954 #define RCVLPC_LOCK_GRANT_SHIFT 16 955 #define RCVLPC_NON_EMPTY_BITS 0x0000200c 956 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 957 #define RCVLPC_CONFIG 0x00002010 958 #define RCVLPC_STATSCTRL 0x00002014 959 #define RCVLPC_STATSCTRL_ENABLE 0x00000001 960 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 961 #define RCVLPC_STATS_ENABLE 0x00002018 962 #define RCVLPC_STATSENAB_ASF_FIX 0x00000002 963 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 964 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 965 #define RCVLPC_STATS_INCMASK 0x0000201c 966 /* 0x2020 --> 0x2100 unused */ 967 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 968 #define SELLST_TAIL 0x00000004 969 #define SELLST_CONT 0x00000008 970 #define SELLST_UNUSED 0x0000000c 971 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 972 #define RCVLPC_DROP_FILTER_CNT 0x00002240 973 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 974 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 975 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c 976 #define RCVLPC_IN_DISCARDS_CNT 0x00002250 977 #define RCVLPC_IN_ERRORS_CNT 0x00002254 978 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 979 /* 0x225c --> 0x2400 unused */ 980 981 /* Receive Data and Receive BD Initiator Control */ 982 #define RCVDBDI_MODE 0x00002400 983 #define RCVDBDI_MODE_RESET 0x00000001 984 #define RCVDBDI_MODE_ENABLE 0x00000002 985 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 986 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 987 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 988 #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000 989 #define RCVDBDI_STATUS 0x00002404 990 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 991 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 992 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 993 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 994 /* 0x240c --> 0x2440 unused */ 995 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 996 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 997 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 998 #define RCVDBDI_JUMBO_CON_IDX 0x00002470 999 #define RCVDBDI_STD_CON_IDX 0x00002474 1000 #define RCVDBDI_MINI_CON_IDX 0x00002478 1001 /* 0x247c --> 0x2480 unused */ 1002 #define RCVDBDI_BD_PROD_IDX_0 0x00002480 1003 #define RCVDBDI_BD_PROD_IDX_1 0x00002484 1004 #define RCVDBDI_BD_PROD_IDX_2 0x00002488 1005 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c 1006 #define RCVDBDI_BD_PROD_IDX_4 0x00002490 1007 #define RCVDBDI_BD_PROD_IDX_5 0x00002494 1008 #define RCVDBDI_BD_PROD_IDX_6 0x00002498 1009 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c 1010 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 1011 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 1012 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 1013 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac 1014 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 1015 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 1016 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 1017 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc 1018 #define RCVDBDI_HWDIAG 0x000024c0 1019 /* 0x24c4 --> 0x2800 unused */ 1020 1021 /* Receive Data Completion Control */ 1022 #define RCVDCC_MODE 0x00002800 1023 #define RCVDCC_MODE_RESET 0x00000001 1024 #define RCVDCC_MODE_ENABLE 0x00000002 1025 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 1026 /* 0x2804 --> 0x2c00 unused */ 1027 1028 /* Receive BD Initiator Control Registers */ 1029 #define RCVBDI_MODE 0x00002c00 1030 #define RCVBDI_MODE_RESET 0x00000001 1031 #define RCVBDI_MODE_ENABLE 0x00000002 1032 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 1033 #define RCVBDI_STATUS 0x00002c04 1034 #define RCVBDI_STATUS_RCB_ATTN 0x00000004 1035 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 1036 #define RCVBDI_STD_PROD_IDX 0x00002c0c 1037 #define RCVBDI_MINI_PROD_IDX 0x00002c10 1038 #define RCVBDI_MINI_THRESH 0x00002c14 1039 #define RCVBDI_STD_THRESH 0x00002c18 1040 #define RCVBDI_JUMBO_THRESH 0x00002c1c 1041 /* 0x2c20 --> 0x2d00 unused */ 1042 1043 #define STD_REPLENISH_LWM 0x00002d00 1044 #define JMB_REPLENISH_LWM 0x00002d04 1045 /* 0x2d08 --> 0x3000 unused */ 1046 1047 /* Receive BD Completion Control Registers */ 1048 #define RCVCC_MODE 0x00003000 1049 #define RCVCC_MODE_RESET 0x00000001 1050 #define RCVCC_MODE_ENABLE 0x00000002 1051 #define RCVCC_MODE_ATTN_ENABLE 0x00000004 1052 #define RCVCC_STATUS 0x00003004 1053 #define RCVCC_STATUS_ERROR_ATTN 0x00000004 1054 #define RCVCC_JUMP_PROD_IDX 0x00003008 1055 #define RCVCC_STD_PROD_IDX 0x0000300c 1056 #define RCVCC_MINI_PROD_IDX 0x00003010 1057 /* 0x3014 --> 0x3400 unused */ 1058 1059 /* Receive list selector control registers */ 1060 #define RCVLSC_MODE 0x00003400 1061 #define RCVLSC_MODE_RESET 0x00000001 1062 #define RCVLSC_MODE_ENABLE 0x00000002 1063 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 1064 #define RCVLSC_STATUS 0x00003404 1065 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 1066 /* 0x3408 --> 0x3600 unused */ 1067 1068 #define TG3_CPMU_DRV_STATUS 0x0000344c 1069 1070 /* CPMU registers */ 1071 #define TG3_CPMU_CTRL 0x00003600 1072 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1073 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1074 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1075 #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1076 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604 1077 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 1078 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1079 /* 0x3608 --> 0x360c unused */ 1080 1081 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c 1082 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1083 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1084 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 1085 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 1086 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 1087 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1088 /* 0x3614 --> 0x361c unused */ 1089 1090 #define TG3_CPMU_HST_ACC 0x0000361c 1091 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 1092 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 1093 /* 0x3620 --> 0x3630 unused */ 1094 1095 #define TG3_CPMU_CLCK_ORIDE 0x00003624 1096 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1097 1098 #define TG3_CPMU_CLCK_STAT 0x00003630 1099 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1100 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1101 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1102 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1103 /* 0x3634 --> 0x365c unused */ 1104 1105 #define TG3_CPMU_MUTEX_REQ 0x0000365c 1106 #define CPMU_MUTEX_REQ_DRIVER 0x00001000 1107 #define TG3_CPMU_MUTEX_GNT 0x00003660 1108 #define CPMU_MUTEX_GNT_DRIVER 0x00001000 1109 #define TG3_CPMU_PHY_STRAP 0x00003664 1110 #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1111 /* 0x3664 --> 0x36b0 unused */ 1112 1113 #define TG3_CPMU_EEE_MODE 0x000036b0 1114 #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 1115 #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 1116 #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 1117 #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 1118 #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 1119 #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 1120 #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 1121 #define TG3_CPMU_EEE_DBTMR1 0x000036b4 1122 #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 1123 #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff 1124 #define TG3_CPMU_EEE_DBTMR2 0x000036b8 1125 #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000 1126 #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff 1127 #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc 1128 #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 1129 #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 1130 /* 0x36c0 --> 0x36d0 unused */ 1131 1132 #define TG3_CPMU_EEE_CTRL 0x000036d0 1133 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d 1134 #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384 1135 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8 1136 /* 0x36d4 --> 0x3800 unused */ 1137 1138 /* Mbuf cluster free registers */ 1139 #define MBFREE_MODE 0x00003800 1140 #define MBFREE_MODE_RESET 0x00000001 1141 #define MBFREE_MODE_ENABLE 0x00000002 1142 #define MBFREE_STATUS 0x00003804 1143 /* 0x3808 --> 0x3c00 unused */ 1144 1145 /* Host coalescing control registers */ 1146 #define HOSTCC_MODE 0x00003c00 1147 #define HOSTCC_MODE_RESET 0x00000001 1148 #define HOSTCC_MODE_ENABLE 0x00000002 1149 #define HOSTCC_MODE_ATTN 0x00000004 1150 #define HOSTCC_MODE_NOW 0x00000008 1151 #define HOSTCC_MODE_FULL_STATUS 0x00000000 1152 #define HOSTCC_MODE_64BYTE 0x00000080 1153 #define HOSTCC_MODE_32BYTE 0x00000100 1154 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 1155 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 1156 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 1157 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 1158 #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 1159 #define HOSTCC_STATUS 0x00003c04 1160 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 1161 #define HOSTCC_RXCOL_TICKS 0x00003c08 1162 #define LOW_RXCOL_TICKS 0x00000032 1163 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 1164 #define DEFAULT_RXCOL_TICKS 0x00000048 1165 #define HIGH_RXCOL_TICKS 0x00000096 1166 #define MAX_RXCOL_TICKS 0x000003ff 1167 #define HOSTCC_TXCOL_TICKS 0x00003c0c 1168 #define LOW_TXCOL_TICKS 0x00000096 1169 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 1170 #define DEFAULT_TXCOL_TICKS 0x0000012c 1171 #define HIGH_TXCOL_TICKS 0x00000145 1172 #define MAX_TXCOL_TICKS 0x000003ff 1173 #define HOSTCC_RXMAX_FRAMES 0x00003c10 1174 #define LOW_RXMAX_FRAMES 0x00000005 1175 #define DEFAULT_RXMAX_FRAMES 0x00000008 1176 #define HIGH_RXMAX_FRAMES 0x00000012 1177 #define MAX_RXMAX_FRAMES 0x000000ff 1178 #define HOSTCC_TXMAX_FRAMES 0x00003c14 1179 #define LOW_TXMAX_FRAMES 0x00000035 1180 #define DEFAULT_TXMAX_FRAMES 0x0000004b 1181 #define HIGH_TXMAX_FRAMES 0x00000052 1182 #define MAX_TXMAX_FRAMES 0x000000ff 1183 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 1184 #define DEFAULT_RXCOAL_TICK_INT 0x00000019 1185 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 1186 #define MAX_RXCOAL_TICK_INT 0x000003ff 1187 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 1188 #define DEFAULT_TXCOAL_TICK_INT 0x00000019 1189 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 1190 #define MAX_TXCOAL_TICK_INT 0x000003ff 1191 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 1192 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 1193 #define MAX_RXCOAL_MAXF_INT 0x000000ff 1194 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 1195 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 1196 #define MAX_TXCOAL_MAXF_INT 0x000000ff 1197 #define HOSTCC_STAT_COAL_TICKS 0x00003c28 1198 #define DEFAULT_STAT_COAL_TICKS 0x000f4240 1199 #define MAX_STAT_COAL_TICKS 0xd693d400 1200 #define MIN_STAT_COAL_TICKS 0x00000064 1201 /* 0x3c2c --> 0x3c30 unused */ 1202 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 1203 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 1204 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 1205 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 1206 #define HOSTCC_FLOW_ATTN 0x00003c48 1207 #define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040 1208 /* 0x3c4c --> 0x3c50 unused */ 1209 #define HOSTCC_JUMBO_CON_IDX 0x00003c50 1210 #define HOSTCC_STD_CON_IDX 0x00003c54 1211 #define HOSTCC_MINI_CON_IDX 0x00003c58 1212 /* 0x3c5c --> 0x3c80 unused */ 1213 #define HOSTCC_RET_PROD_IDX_0 0x00003c80 1214 #define HOSTCC_RET_PROD_IDX_1 0x00003c84 1215 #define HOSTCC_RET_PROD_IDX_2 0x00003c88 1216 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c 1217 #define HOSTCC_RET_PROD_IDX_4 0x00003c90 1218 #define HOSTCC_RET_PROD_IDX_5 0x00003c94 1219 #define HOSTCC_RET_PROD_IDX_6 0x00003c98 1220 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c 1221 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 1222 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 1223 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 1224 #define HOSTCC_RET_PROD_IDX_11 0x00003cac 1225 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 1226 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 1227 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 1228 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc 1229 #define HOSTCC_SND_CON_IDX_0 0x00003cc0 1230 #define HOSTCC_SND_CON_IDX_1 0x00003cc4 1231 #define HOSTCC_SND_CON_IDX_2 0x00003cc8 1232 #define HOSTCC_SND_CON_IDX_3 0x00003ccc 1233 #define HOSTCC_SND_CON_IDX_4 0x00003cd0 1234 #define HOSTCC_SND_CON_IDX_5 0x00003cd4 1235 #define HOSTCC_SND_CON_IDX_6 0x00003cd8 1236 #define HOSTCC_SND_CON_IDX_7 0x00003cdc 1237 #define HOSTCC_SND_CON_IDX_8 0x00003ce0 1238 #define HOSTCC_SND_CON_IDX_9 0x00003ce4 1239 #define HOSTCC_SND_CON_IDX_10 0x00003ce8 1240 #define HOSTCC_SND_CON_IDX_11 0x00003cec 1241 #define HOSTCC_SND_CON_IDX_12 0x00003cf0 1242 #define HOSTCC_SND_CON_IDX_13 0x00003cf4 1243 #define HOSTCC_SND_CON_IDX_14 0x00003cf8 1244 #define HOSTCC_SND_CON_IDX_15 0x00003cfc 1245 #define HOSTCC_STATBLCK_RING1 0x00003d00 1246 /* 0x3d00 --> 0x3d80 unused */ 1247 1248 #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80 1249 #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84 1250 #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88 1251 #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c 1252 #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90 1253 #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94 1254 /* 0x3d98 --> 0x4000 unused */ 1255 1256 /* Memory arbiter control registers */ 1257 #define MEMARB_MODE 0x00004000 1258 #define MEMARB_MODE_RESET 0x00000001 1259 #define MEMARB_MODE_ENABLE 0x00000002 1260 #define MEMARB_STATUS 0x00004004 1261 #define MEMARB_TRAP_ADDR_LOW 0x00004008 1262 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c 1263 /* 0x4010 --> 0x4400 unused */ 1264 1265 /* Buffer manager control registers */ 1266 #define BUFMGR_MODE 0x00004400 1267 #define BUFMGR_MODE_RESET 0x00000001 1268 #define BUFMGR_MODE_ENABLE 0x00000002 1269 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 1270 #define BUFMGR_MODE_BM_TEST 0x00000008 1271 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 1272 #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000 1273 #define BUFMGR_STATUS 0x00004404 1274 #define BUFMGR_STATUS_ERROR 0x00000004 1275 #define BUFMGR_STATUS_MBLOW 0x00000010 1276 #define BUFMGR_MB_POOL_ADDR 0x00004408 1277 #define BUFMGR_MB_POOL_SIZE 0x0000440c 1278 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 1279 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1280 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1281 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1282 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 1283 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1284 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1285 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1286 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 1287 #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a 1288 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1289 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b 1290 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e 1291 #define BUFMGR_MB_HIGH_WATER 0x00004418 1292 #define DEFAULT_MB_HIGH_WATER 0x00000060 1293 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1294 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010 1295 #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0 1296 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1297 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 1298 #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea 1299 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1300 #define BUFMGR_MB_ALLOC_BIT 0x10000000 1301 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1302 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1303 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1304 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1305 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1306 #define BUFMGR_DMA_LOW_WATER 0x00004434 1307 #define DEFAULT_DMA_LOW_WATER 0x00000005 1308 #define BUFMGR_DMA_HIGH_WATER 0x00004438 1309 #define DEFAULT_DMA_HIGH_WATER 0x0000000a 1310 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1311 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1312 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1313 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1314 #define BUFMGR_HWDIAG_0 0x0000444c 1315 #define BUFMGR_HWDIAG_1 0x00004450 1316 #define BUFMGR_HWDIAG_2 0x00004454 1317 /* 0x4458 --> 0x4800 unused */ 1318 1319 /* Read DMA control registers */ 1320 #define RDMAC_MODE 0x00004800 1321 #define RDMAC_MODE_RESET 0x00000001 1322 #define RDMAC_MODE_ENABLE 0x00000002 1323 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1324 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1325 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1326 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1327 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1328 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1329 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1330 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1331 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1332 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 1333 #define RDMAC_MODE_SPLIT_RESET 0x00001000 1334 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 1335 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 1336 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1337 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 1338 #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000 1339 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000 1340 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000 1341 #define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000 1342 #define RDMAC_STATUS 0x00004804 1343 #define RDMAC_STATUS_TGTABORT 0x00000004 1344 #define RDMAC_STATUS_MSTABORT 0x00000008 1345 #define RDMAC_STATUS_PARITYERR 0x00000010 1346 #define RDMAC_STATUS_ADDROFLOW 0x00000020 1347 #define RDMAC_STATUS_FIFOOFLOW 0x00000040 1348 #define RDMAC_STATUS_FIFOURUN 0x00000080 1349 #define RDMAC_STATUS_FIFOOREAD 0x00000100 1350 #define RDMAC_STATUS_LNGREAD 0x00000200 1351 /* 0x4808 --> 0x4900 unused */ 1352 1353 #define TG3_RDMA_RSRVCTRL_REG 0x00004900 1354 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1355 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00 1356 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0 1357 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000 1358 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000 1359 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1360 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 1361 /* 0x4904 --> 0x4910 unused */ 1362 1363 #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 1364 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1365 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 1366 /* 0x4914 --> 0x4c00 unused */ 1367 1368 /* Write DMA control registers */ 1369 #define WDMAC_MODE 0x00004c00 1370 #define WDMAC_MODE_RESET 0x00000001 1371 #define WDMAC_MODE_ENABLE 0x00000002 1372 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1373 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1374 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1375 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1376 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1377 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1378 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1379 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1380 #define WDMAC_MODE_RX_ACCEL 0x00000400 1381 #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 1382 #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 1383 #define WDMAC_STATUS 0x00004c04 1384 #define WDMAC_STATUS_TGTABORT 0x00000004 1385 #define WDMAC_STATUS_MSTABORT 0x00000008 1386 #define WDMAC_STATUS_PARITYERR 0x00000010 1387 #define WDMAC_STATUS_ADDROFLOW 0x00000020 1388 #define WDMAC_STATUS_FIFOOFLOW 0x00000040 1389 #define WDMAC_STATUS_FIFOURUN 0x00000080 1390 #define WDMAC_STATUS_FIFOOREAD 0x00000100 1391 #define WDMAC_STATUS_LNGREAD 0x00000200 1392 /* 0x4c08 --> 0x5000 unused */ 1393 1394 /* Per-cpu register offsets (arm9) */ 1395 #define CPU_MODE 0x00000000 1396 #define CPU_MODE_RESET 0x00000001 1397 #define CPU_MODE_HALT 0x00000400 1398 #define CPU_STATE 0x00000004 1399 #define CPU_EVTMASK 0x00000008 1400 /* 0xc --> 0x1c reserved */ 1401 #define CPU_PC 0x0000001c 1402 #define CPU_INSN 0x00000020 1403 #define CPU_SPAD_UFLOW 0x00000024 1404 #define CPU_WDOG_CLEAR 0x00000028 1405 #define CPU_WDOG_VECTOR 0x0000002c 1406 #define CPU_WDOG_PC 0x00000030 1407 #define CPU_HW_BP 0x00000034 1408 /* 0x38 --> 0x44 unused */ 1409 #define CPU_WDOG_SAVED_STATE 0x00000044 1410 #define CPU_LAST_BRANCH_ADDR 0x00000048 1411 #define CPU_SPAD_UFLOW_SET 0x0000004c 1412 /* 0x50 --> 0x200 unused */ 1413 #define CPU_R0 0x00000200 1414 #define CPU_R1 0x00000204 1415 #define CPU_R2 0x00000208 1416 #define CPU_R3 0x0000020c 1417 #define CPU_R4 0x00000210 1418 #define CPU_R5 0x00000214 1419 #define CPU_R6 0x00000218 1420 #define CPU_R7 0x0000021c 1421 #define CPU_R8 0x00000220 1422 #define CPU_R9 0x00000224 1423 #define CPU_R10 0x00000228 1424 #define CPU_R11 0x0000022c 1425 #define CPU_R12 0x00000230 1426 #define CPU_R13 0x00000234 1427 #define CPU_R14 0x00000238 1428 #define CPU_R15 0x0000023c 1429 #define CPU_R16 0x00000240 1430 #define CPU_R17 0x00000244 1431 #define CPU_R18 0x00000248 1432 #define CPU_R19 0x0000024c 1433 #define CPU_R20 0x00000250 1434 #define CPU_R21 0x00000254 1435 #define CPU_R22 0x00000258 1436 #define CPU_R23 0x0000025c 1437 #define CPU_R24 0x00000260 1438 #define CPU_R25 0x00000264 1439 #define CPU_R26 0x00000268 1440 #define CPU_R27 0x0000026c 1441 #define CPU_R28 0x00000270 1442 #define CPU_R29 0x00000274 1443 #define CPU_R30 0x00000278 1444 #define CPU_R31 0x0000027c 1445 /* 0x280 --> 0x400 unused */ 1446 1447 #define RX_CPU_BASE 0x00005000 1448 #define RX_CPU_MODE 0x00005000 1449 #define RX_CPU_STATE 0x00005004 1450 #define RX_CPU_PGMCTR 0x0000501c 1451 #define RX_CPU_HWBKPT 0x00005034 1452 #define TX_CPU_BASE 0x00005400 1453 #define TX_CPU_MODE 0x00005400 1454 #define TX_CPU_STATE 0x00005404 1455 #define TX_CPU_PGMCTR 0x0000541c 1456 1457 #define VCPU_STATUS 0x00005100 1458 #define VCPU_STATUS_INIT_DONE 0x04000000 1459 #define VCPU_STATUS_DRV_RESET 0x08000000 1460 1461 #define VCPU_CFGSHDW 0x00005104 1462 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 1463 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 1464 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 1465 1466 /* Mailboxes */ 1467 #define GRCMBOX_BASE 0x00005600 1468 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1469 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1470 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1471 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1472 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1473 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1474 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1475 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1476 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1477 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1478 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1479 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1480 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1481 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1482 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1483 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1484 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1485 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1486 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1487 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1488 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1489 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1490 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1491 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1492 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1493 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1494 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1495 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1496 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1497 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1498 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1499 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1500 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1501 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1502 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1503 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1504 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1505 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1506 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1507 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1508 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1509 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1510 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1511 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1512 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1513 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1514 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1515 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1516 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1517 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1518 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1519 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1520 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1521 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1522 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1523 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1524 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1525 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1526 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1527 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1528 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1529 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1530 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1531 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1532 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1533 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1534 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1535 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1536 /* 0x5a10 --> 0x5c00 */ 1537 1538 /* Flow Through queues */ 1539 #define FTQ_RESET 0x00005c00 1540 /* 0x5c04 --> 0x5c10 unused */ 1541 #define FTQ_DMA_NORM_READ_CTL 0x00005c10 1542 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1543 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1544 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1545 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1546 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1547 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1548 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1549 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1550 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1551 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1552 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1553 #define FTQ_SEND_BD_COMP_CTL 0x00005c40 1554 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1555 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1556 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1557 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1558 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1559 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1560 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1561 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1562 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1563 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1564 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1565 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1566 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1567 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1568 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1569 #define FTQ_SWTYPE1_CTL 0x00005c80 1570 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1571 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1572 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1573 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1574 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1575 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1576 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1577 #define FTQ_HOST_COAL_CTL 0x00005ca0 1578 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1579 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1580 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1581 #define FTQ_MAC_TX_CTL 0x00005cb0 1582 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1583 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1584 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1585 #define FTQ_MB_FREE_CTL 0x00005cc0 1586 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1587 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1588 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1589 #define FTQ_RCVBD_COMP_CTL 0x00005cd0 1590 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1591 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1592 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1593 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1594 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1595 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1596 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1597 #define FTQ_RCVDATA_INI_CTL 0x00005cf0 1598 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1599 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1600 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1601 #define FTQ_RCVDATA_COMP_CTL 0x00005d00 1602 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1603 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1604 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1605 #define FTQ_SWTYPE2_CTL 0x00005d10 1606 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1607 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1608 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1609 /* 0x5d20 --> 0x6000 unused */ 1610 1611 /* Message signaled interrupt registers */ 1612 #define MSGINT_MODE 0x00006000 1613 #define MSGINT_MODE_RESET 0x00000001 1614 #define MSGINT_MODE_ENABLE 0x00000002 1615 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020 1616 #define MSGINT_MODE_MULTIVEC_EN 0x00000080 1617 #define MSGINT_STATUS 0x00006004 1618 #define MSGINT_STATUS_MSI_REQ 0x00000001 1619 #define MSGINT_FIFO 0x00006008 1620 /* 0x600c --> 0x6400 unused */ 1621 1622 /* DMA completion registers */ 1623 #define DMAC_MODE 0x00006400 1624 #define DMAC_MODE_RESET 0x00000001 1625 #define DMAC_MODE_ENABLE 0x00000002 1626 /* 0x6404 --> 0x6800 unused */ 1627 1628 /* GRC registers */ 1629 #define GRC_MODE 0x00006800 1630 #define GRC_MODE_UPD_ON_COAL 0x00000001 1631 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1632 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1633 #define GRC_MODE_BSWAP_DATA 0x00000010 1634 #define GRC_MODE_WSWAP_DATA 0x00000020 1635 #define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040 1636 #define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080 1637 #define GRC_MODE_SPLITHDR 0x00000100 1638 #define GRC_MODE_NOFRM_CRACKING 0x00000200 1639 #define GRC_MODE_INCL_CRC 0x00000400 1640 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1641 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1642 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1643 #define GRC_MODE_FORCE_PCI32BIT 0x00008000 1644 #define GRC_MODE_B2HRX_ENABLE 0x00008000 1645 #define GRC_MODE_HOST_STACKUP 0x00010000 1646 #define GRC_MODE_HOST_SENDBDS 0x00020000 1647 #define GRC_MODE_HTX2B_ENABLE 0x00040000 1648 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1649 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1650 #define GRC_MODE_PCIE_TL_SEL 0x00000000 1651 #define GRC_MODE_PCIE_PL_SEL 0x00400000 1652 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1653 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1654 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1655 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1656 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1657 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1658 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1659 #define GRC_MODE_PCIE_DL_SEL 0x20000000 1660 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1661 #define GRC_MODE_PCIE_HI_1K_EN 0x80000000 1662 #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \ 1663 GRC_MODE_PCIE_PL_SEL | \ 1664 GRC_MODE_PCIE_DL_SEL | \ 1665 GRC_MODE_PCIE_HI_1K_EN) 1666 #define GRC_MISC_CFG 0x00006804 1667 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1668 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1669 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1670 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1671 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1672 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1673 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1674 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1675 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1676 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1677 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1678 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1679 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1680 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1681 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1682 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 1683 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1684 #define GRC_LOCAL_CTRL 0x00006808 1685 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1686 #define GRC_LCLCTRL_CLEARINT 0x00000002 1687 #define GRC_LCLCTRL_SETINT 0x00000004 1688 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1689 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1690 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1691 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1692 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 1693 #define GRC_LCLCTRL_GPIO_OE3 0x00000040 1694 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 1695 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1696 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1697 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1698 #define GRC_LCLCTRL_GPIO_OE0 0x00000800 1699 #define GRC_LCLCTRL_GPIO_OE1 0x00001000 1700 #define GRC_LCLCTRL_GPIO_OE2 0x00002000 1701 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1702 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1703 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1704 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1705 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1706 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1707 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1708 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1709 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1710 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1711 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1712 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1713 #define GRC_LCLCTRL_BANK_SELECT 0x00200000 1714 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1715 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1716 #define GRC_TIMER 0x0000680c 1717 #define GRC_RX_CPU_EVENT 0x00006810 1718 #define GRC_RX_CPU_DRIVER_EVENT 0x00004000 1719 #define GRC_RX_TIMER_REF 0x00006814 1720 #define GRC_RX_CPU_SEM 0x00006818 1721 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1722 #define GRC_TX_CPU_EVENT 0x00006820 1723 #define GRC_TX_TIMER_REF 0x00006824 1724 #define GRC_TX_CPU_SEM 0x00006828 1725 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1726 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1727 #define GRC_EEPROM_ADDR 0x00006838 1728 #define EEPROM_ADDR_WRITE 0x00000000 1729 #define EEPROM_ADDR_READ 0x80000000 1730 #define EEPROM_ADDR_COMPLETE 0x40000000 1731 #define EEPROM_ADDR_FSM_RESET 0x20000000 1732 #define EEPROM_ADDR_DEVID_MASK 0x1c000000 1733 #define EEPROM_ADDR_DEVID_SHIFT 26 1734 #define EEPROM_ADDR_START 0x02000000 1735 #define EEPROM_ADDR_CLKPERD_SHIFT 16 1736 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1737 #define EEPROM_ADDR_ADDR_SHIFT 0 1738 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1739 #define EEPROM_CHIP_SIZE (64 * 1024) 1740 #define GRC_EEPROM_DATA 0x0000683c 1741 #define GRC_EEPROM_CTRL 0x00006840 1742 #define GRC_MDI_CTRL 0x00006844 1743 #define GRC_SEEPROM_DELAY 0x00006848 1744 /* 0x684c --> 0x6890 unused */ 1745 #define GRC_VCPU_EXT_CTRL 0x00006890 1746 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1747 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1748 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ 1749 1750 /* 0x6c00 --> 0x7000 unused */ 1751 1752 /* NVRAM Control registers */ 1753 #define NVRAM_CMD 0x00007000 1754 #define NVRAM_CMD_RESET 0x00000001 1755 #define NVRAM_CMD_DONE 0x00000008 1756 #define NVRAM_CMD_GO 0x00000010 1757 #define NVRAM_CMD_WR 0x00000020 1758 #define NVRAM_CMD_RD 0x00000000 1759 #define NVRAM_CMD_ERASE 0x00000040 1760 #define NVRAM_CMD_FIRST 0x00000080 1761 #define NVRAM_CMD_LAST 0x00000100 1762 #define NVRAM_CMD_WREN 0x00010000 1763 #define NVRAM_CMD_WRDI 0x00020000 1764 #define NVRAM_STAT 0x00007004 1765 #define NVRAM_WRDATA 0x00007008 1766 #define NVRAM_ADDR 0x0000700c 1767 #define NVRAM_ADDR_MSK 0x00ffffff 1768 #define NVRAM_RDDATA 0x00007010 1769 #define NVRAM_CFG1 0x00007014 1770 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1771 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1772 #define NVRAM_CFG1_PASS_THRU 0x00000004 1773 #define NVRAM_CFG1_STATUS_BITS 0x00000070 1774 #define NVRAM_CFG1_BIT_BANG 0x00000008 1775 #define NVRAM_CFG1_FLASH_SIZE 0x02000000 1776 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1777 #define NVRAM_CFG1_VENDOR_MASK 0x03000003 1778 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 1779 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1780 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 1781 #define FLASH_VENDOR_ST 0x03000001 1782 #define FLASH_VENDOR_SAIFUN 0x01000003 1783 #define FLASH_VENDOR_SST_SMALL 0x00000001 1784 #define FLASH_VENDOR_SST_LARGE 0x02000001 1785 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 1786 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 1787 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 1788 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1789 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 1790 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 1791 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 1792 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 1793 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 1794 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 1795 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 1796 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 1797 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 1798 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 1799 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 1800 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1801 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1802 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1803 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 1804 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 1805 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 1806 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 1807 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 1808 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 1809 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 1810 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 1811 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 1812 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 1813 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 1814 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 1815 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 1816 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1817 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1818 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1819 #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 1820 #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 1821 #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 1822 #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 1823 #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 1824 #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 1825 #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 1826 #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 1827 #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 1828 #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 1829 #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 1830 #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 1831 #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 1832 #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 1833 #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 1834 #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 1835 #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 1836 #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 1837 #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 1838 #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 1839 #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 1840 #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 1841 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 1842 #define FLASH_5717VENDOR_ST_25USPT 0x03400002 1843 #define FLASH_5717VENDOR_ST_45USPT 0x03400001 1844 #define FLASH_5720_EEPROM_HD 0x00000001 1845 #define FLASH_5720_EEPROM_LD 0x00000003 1846 #define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000 1847 #define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002 1848 #define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001 1849 #define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003 1850 #define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000 1851 #define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002 1852 #define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001 1853 #define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003 1854 #define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000 1855 #define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002 1856 #define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001 1857 #define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003 1858 #define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000 1859 #define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002 1860 #define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001 1861 #define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000 1862 #define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002 1863 #define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001 1864 #define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003 1865 #define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000 1866 #define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002 1867 #define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001 1868 #define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003 1869 #define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000 1870 #define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002 1871 #define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001 1872 #define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003 1873 #define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000 1874 #define FLASH_5720VENDOR_ST_25USPT 0x03c00002 1875 #define FLASH_5720VENDOR_ST_45USPT 0x03c00001 1876 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1877 #define FLASH_5752PAGE_SIZE_256 0x00000000 1878 #define FLASH_5752PAGE_SIZE_512 0x10000000 1879 #define FLASH_5752PAGE_SIZE_1K 0x20000000 1880 #define FLASH_5752PAGE_SIZE_2K 0x30000000 1881 #define FLASH_5752PAGE_SIZE_4K 0x40000000 1882 #define FLASH_5752PAGE_SIZE_264 0x50000000 1883 #define FLASH_5752PAGE_SIZE_528 0x60000000 1884 #define NVRAM_CFG2 0x00007018 1885 #define NVRAM_CFG3 0x0000701c 1886 #define NVRAM_SWARB 0x00007020 1887 #define SWARB_REQ_SET0 0x00000001 1888 #define SWARB_REQ_SET1 0x00000002 1889 #define SWARB_REQ_SET2 0x00000004 1890 #define SWARB_REQ_SET3 0x00000008 1891 #define SWARB_REQ_CLR0 0x00000010 1892 #define SWARB_REQ_CLR1 0x00000020 1893 #define SWARB_REQ_CLR2 0x00000040 1894 #define SWARB_REQ_CLR3 0x00000080 1895 #define SWARB_GNT0 0x00000100 1896 #define SWARB_GNT1 0x00000200 1897 #define SWARB_GNT2 0x00000400 1898 #define SWARB_GNT3 0x00000800 1899 #define SWARB_REQ0 0x00001000 1900 #define SWARB_REQ1 0x00002000 1901 #define SWARB_REQ2 0x00004000 1902 #define SWARB_REQ3 0x00008000 1903 #define NVRAM_ACCESS 0x00007024 1904 #define ACCESS_ENABLE 0x00000001 1905 #define ACCESS_WR_ENABLE 0x00000002 1906 #define NVRAM_WRITE1 0x00007028 1907 /* 0x702c unused */ 1908 1909 #define NVRAM_ADDR_LOCKOUT 0x00007030 1910 /* 0x7034 --> 0x7500 unused */ 1911 1912 #define OTP_MODE 0x00007500 1913 #define OTP_MODE_OTP_THRU_GRC 0x00000001 1914 #define OTP_CTRL 0x00007504 1915 #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 1916 #define OTP_CTRL_OTP_CMD_READ 0x00000000 1917 #define OTP_CTRL_OTP_CMD_INIT 0x00000008 1918 #define OTP_CTRL_OTP_CMD_START 0x00000001 1919 #define OTP_STATUS 0x00007508 1920 #define OTP_STATUS_CMD_DONE 0x00000001 1921 #define OTP_ADDRESS 0x0000750c 1922 #define OTP_ADDRESS_MAGIC1 0x000000a0 1923 #define OTP_ADDRESS_MAGIC2 0x00000080 1924 /* 0x7510 unused */ 1925 1926 #define OTP_READ_DATA 0x00007514 1927 /* 0x7518 --> 0x7c04 unused */ 1928 1929 #define PCIE_TRANSACTION_CFG 0x00007c04 1930 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 1931 #define PCIE_TRANS_CFG_LOM 0x00000020 1932 /* 0x7c08 --> 0x7d28 unused */ 1933 1934 #define PCIE_PWR_MGMT_THRESH 0x00007d28 1935 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 1936 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 1937 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 1938 /* 0x7d2c --> 0x7d54 unused */ 1939 1940 #define TG3_PCIE_LNKCTL 0x00007d54 1941 #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 1942 #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 1943 /* 0x7d58 --> 0x7e70 unused */ 1944 1945 #define TG3_PCIE_PHY_TSTCTL 0x00007e2c 1946 #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040 1947 #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 1948 1949 #define TG3_PCIE_EIDLE_DELAY 0x00007e70 1950 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f 1951 #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c 1952 /* 0x7e74 --> 0x8000 unused */ 1953 1954 1955 /* Alternate PCIE definitions */ 1956 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 1957 #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c 1958 #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff 1959 #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c 1960 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 1961 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 1962 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 1963 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 1964 1965 #define TG3_REG_BLK_SIZE 0x00008000 1966 1967 /* OTP bit definitions */ 1968 #define TG3_OTP_AGCTGT_MASK 0x000000e0 1969 #define TG3_OTP_AGCTGT_SHIFT 1 1970 #define TG3_OTP_HPFFLTR_MASK 0x00000300 1971 #define TG3_OTP_HPFFLTR_SHIFT 1 1972 #define TG3_OTP_HPFOVER_MASK 0x00000400 1973 #define TG3_OTP_HPFOVER_SHIFT 1 1974 #define TG3_OTP_LPFDIS_MASK 0x00000800 1975 #define TG3_OTP_LPFDIS_SHIFT 11 1976 #define TG3_OTP_VDAC_MASK 0xff000000 1977 #define TG3_OTP_VDAC_SHIFT 24 1978 #define TG3_OTP_10BTAMP_MASK 0x0000f000 1979 #define TG3_OTP_10BTAMP_SHIFT 8 1980 #define TG3_OTP_ROFF_MASK 0x00e00000 1981 #define TG3_OTP_ROFF_SHIFT 11 1982 #define TG3_OTP_RCOFF_MASK 0x001c0000 1983 #define TG3_OTP_RCOFF_SHIFT 16 1984 1985 #define TG3_OTP_DEFAULT 0x286c1640 1986 1987 1988 /* Hardware Legacy NVRAM layout */ 1989 #define TG3_NVM_VPD_OFF 0x100 1990 #define TG3_NVM_VPD_LEN 256 1991 1992 /* Hardware Selfboot NVRAM layout */ 1993 #define TG3_NVM_HWSB_CFG1 0x00000004 1994 #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 1995 #define TG3_NVM_HWSB_CFG1_MAJSFT 27 1996 #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 1997 #define TG3_NVM_HWSB_CFG1_MINSFT 22 1998 1999 #define TG3_EEPROM_MAGIC 0x669955aa 2000 #define TG3_EEPROM_MAGIC_FW 0xa5000000 2001 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 2002 #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 2003 #define TG3_EEPROM_SB_FORMAT_1 0x00200000 2004 #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 2005 #define TG3_EEPROM_SB_REVISION_0 0x00000000 2006 #define TG3_EEPROM_SB_REVISION_2 0x00020000 2007 #define TG3_EEPROM_SB_REVISION_3 0x00030000 2008 #define TG3_EEPROM_SB_REVISION_4 0x00040000 2009 #define TG3_EEPROM_SB_REVISION_5 0x00050000 2010 #define TG3_EEPROM_SB_REVISION_6 0x00060000 2011 #define TG3_EEPROM_MAGIC_HW 0xabcd 2012 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff 2013 2014 #define TG3_NVM_DIR_START 0x18 2015 #define TG3_NVM_DIR_END 0x78 2016 #define TG3_NVM_DIRENT_SIZE 0xc 2017 #define TG3_NVM_DIRTYPE_SHIFT 24 2018 #define TG3_NVM_DIRTYPE_LENMSK 0x003fffff 2019 #define TG3_NVM_DIRTYPE_ASFINI 1 2020 #define TG3_NVM_DIRTYPE_EXTVPD 20 2021 #define TG3_NVM_PTREV_BCVER 0x94 2022 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00 2023 #define TG3_NVM_BCVER_MAJSFT 8 2024 #define TG3_NVM_BCVER_MINMSK 0x000000ff 2025 2026 #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 2027 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 2028 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2029 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 2030 #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c 2031 #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 2032 #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c 2033 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 2034 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 2035 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff 2036 #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 2037 #define TG3_EEPROM_SB_EDH_BLD_SHFT 11 2038 2039 2040 /* 32K Window into NIC internal memory */ 2041 #define NIC_SRAM_WIN_BASE 0x00008000 2042 2043 /* Offsets into first 32k of NIC internal memory. */ 2044 #define NIC_SRAM_PAGE_ZERO 0x00000000 2045 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 2046 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 2047 #define NIC_SRAM_STATS_BLK 0x00000300 2048 #define NIC_SRAM_STATUS_BLK 0x00000b00 2049 2050 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 2051 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 2052 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 2053 2054 #define NIC_SRAM_DATA_SIG 0x00000b54 2055 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 2056 2057 #define NIC_SRAM_DATA_CFG 0x00000b58 2058 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 2059 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 2060 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 2061 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 2062 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 2063 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 2064 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 2065 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 2066 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 2067 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 2068 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 2069 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 2070 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 2071 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 2072 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 2073 2074 #define NIC_SRAM_DATA_VER 0x00000b5c 2075 #define NIC_SRAM_DATA_VER_SHIFT 16 2076 2077 #define NIC_SRAM_DATA_PHY_ID 0x00000b74 2078 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 2079 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 2080 2081 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 2082 #define FWCMD_NICDRV_ALIVE 0x00000001 2083 #define FWCMD_NICDRV_PAUSE_FW 0x00000002 2084 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 2085 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 2086 #define FWCMD_NICDRV_FIX_DMAR 0x00000005 2087 #define FWCMD_NICDRV_FIX_DMAW 0x00000006 2088 #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c 2089 #define FWCMD_NICDRV_ALIVE2 0x0000000d 2090 #define FWCMD_NICDRV_ALIVE3 0x0000000e 2091 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 2092 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 2093 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 2094 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 2095 #define DRV_STATE_START 0x00000001 2096 #define DRV_STATE_START_DONE 0x80000001 2097 #define DRV_STATE_UNLOAD 0x00000002 2098 #define DRV_STATE_UNLOAD_DONE 0x80000002 2099 #define DRV_STATE_WOL 0x00000003 2100 #define DRV_STATE_SUSPEND 0x00000004 2101 2102 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 2103 2104 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 2105 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 2106 2107 #define NIC_SRAM_WOL_MBOX 0x00000d30 2108 #define WOL_SIGNATURE 0x474c0000 2109 #define WOL_DRV_STATE_SHUTDOWN 0x00000001 2110 #define WOL_DRV_WOL 0x00000002 2111 #define WOL_SET_MAGIC_PKT 0x00000004 2112 2113 #define NIC_SRAM_DATA_CFG_2 0x00000d38 2114 2115 #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400 2116 #define SHASTA_EXT_LED_MODE_MASK 0x00018000 2117 #define SHASTA_EXT_LED_LEGACY 0x00000000 2118 #define SHASTA_EXT_LED_SHARED 0x00008000 2119 #define SHASTA_EXT_LED_MAC 0x00010000 2120 #define SHASTA_EXT_LED_COMBO 0x00018000 2121 2122 #define NIC_SRAM_DATA_CFG_3 0x00000d3c 2123 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 2124 2125 #define NIC_SRAM_DATA_CFG_4 0x00000d60 2126 #define NIC_SRAM_GMII_MODE 0x00000002 2127 #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004 2128 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 2129 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 2130 2131 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 2132 2133 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 2134 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 2135 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 2136 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 2137 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 2138 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 2139 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 2140 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 2141 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 2142 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 2143 2144 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 2145 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 2146 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 2147 2148 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64 2149 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16 2150 2151 2152 /* Currently this is fixed. */ 2153 #define TG3_PHY_MII_ADDR 0x01 2154 2155 2156 /*** Tigon3 specific PHY MII registers. ***/ 2157 #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ 2158 #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 2159 #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ 2160 2161 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 2162 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 2163 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 2164 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 2165 #define MII_TG3_EXT_CTRL_TBI 0x8000 2166 2167 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2168 #define MII_TG3_EXT_STAT_LPASS 0x0100 2169 2170 #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ 2171 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 2172 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ 2173 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 2174 2175 #define MII_TG3_DSP_TAP1 0x0001 2176 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 2177 #define MII_TG3_DSP_TAP26 0x001a 2178 #define MII_TG3_DSP_TAP26_ALNOKO 0x0001 2179 #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002 2180 #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004 2181 #define MII_TG3_DSP_AADJ1CH0 0x001f 2182 #define MII_TG3_DSP_CH34TP2 0x4022 2183 #define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff 2184 #define MII_TG3_DSP_AADJ1CH3 0x601f 2185 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 2186 #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01 2187 #define MII_TG3_DSP_EXP8 0x0f08 2188 #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 2189 #define MII_TG3_DSP_EXP8_AEDW 0x0200 2190 #define MII_TG3_DSP_EXP75 0x0f75 2191 #define MII_TG3_DSP_EXP96 0x0f96 2192 #define MII_TG3_DSP_EXP97 0x0f97 2193 2194 #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */ 2195 2196 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 2197 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 2198 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 2199 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000 2200 #define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000 2201 2202 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 2203 #define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008 2204 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 2205 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 2206 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040 2207 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 2208 2209 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004 2210 2211 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 2212 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010 2213 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 2214 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12 2215 #define MII_TG3_AUXCTL_MISC_WREN 0x8000 2216 2217 2218 #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */ 2219 #define MII_TG3_AUX_STAT_LPASS 0x0004 2220 #define MII_TG3_AUX_STAT_SPDMASK 0x0700 2221 #define MII_TG3_AUX_STAT_10HALF 0x0100 2222 #define MII_TG3_AUX_STAT_10FULL 0x0200 2223 #define MII_TG3_AUX_STAT_100HALF 0x0300 2224 #define MII_TG3_AUX_STAT_100_4 0x0400 2225 #define MII_TG3_AUX_STAT_100FULL 0x0500 2226 #define MII_TG3_AUX_STAT_1000HALF 0x0600 2227 #define MII_TG3_AUX_STAT_1000FULL 0x0700 2228 #define MII_TG3_AUX_STAT_100 0x0008 2229 #define MII_TG3_AUX_STAT_FULL 0x0001 2230 2231 #define MII_TG3_ISTAT 0x1a /* IRQ status register */ 2232 #define MII_TG3_IMASK 0x1b /* IRQ mask register */ 2233 2234 /* ISTAT/IMASK event bits */ 2235 #define MII_TG3_INT_LINKCHG 0x0002 2236 #define MII_TG3_INT_SPEEDCHG 0x0004 2237 #define MII_TG3_INT_DUPLEXCHG 0x0008 2238 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 2239 2240 #define MII_TG3_MISC_SHDW 0x1c 2241 #define MII_TG3_MISC_SHDW_WREN 0x8000 2242 2243 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 2244 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 2245 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 2246 2247 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 2248 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 2249 #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 2250 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 2251 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 2252 #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 2253 2254 #define MII_TG3_TEST1 0x1e 2255 #define MII_TG3_TEST1_TRIM_EN 0x0010 2256 #define MII_TG3_TEST1_CRC_EN 0x8000 2257 2258 /* Clause 45 expansion registers */ 2259 #define TG3_CL45_D7_EEERES_STAT 0x803e 2260 #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 2261 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 2262 2263 2264 /* Fast Ethernet Tranceiver definitions */ 2265 #define MII_TG3_FET_PTEST 0x17 2266 #define MII_TG3_FET_PTEST_TRIM_SEL 0x0010 2267 #define MII_TG3_FET_PTEST_TRIM_2 0x0002 2268 #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 2269 #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 2270 2271 #define MII_TG3_FET_TEST 0x1f 2272 #define MII_TG3_FET_SHADOW_EN 0x0080 2273 2274 #define MII_TG3_FET_SHDW_MISCCTRL 0x10 2275 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 2276 2277 #define MII_TG3_FET_SHDW_AUXMODE4 0x1a 2278 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 2279 2280 #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b 2281 #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 2282 2283 2284 /* APE registers. Accessible through BAR1 */ 2285 #define TG3_APE_GPIO_MSG 0x0008 2286 #define TG3_APE_GPIO_MSG_SHIFT 4 2287 #define TG3_APE_EVENT 0x000c 2288 #define APE_EVENT_1 0x00000001 2289 #define TG3_APE_LOCK_REQ 0x002c 2290 #define APE_LOCK_REQ_DRIVER 0x00001000 2291 #define TG3_APE_LOCK_GRANT 0x004c 2292 #define APE_LOCK_GRANT_DRIVER 0x00001000 2293 #define TG3_APE_SEG_SIG 0x4000 2294 #define APE_SEG_SIG_MAGIC 0x41504521 2295 2296 /* APE shared memory. Accessible through BAR1 */ 2297 #define TG3_APE_FW_STATUS 0x400c 2298 #define APE_FW_STATUS_READY 0x00000100 2299 #define TG3_APE_FW_FEATURES 0x4010 2300 #define TG3_APE_FW_FEATURE_NCSI 0x00000002 2301 #define TG3_APE_FW_VERSION 0x4018 2302 #define APE_FW_VERSION_MAJMSK 0xff000000 2303 #define APE_FW_VERSION_MAJSFT 24 2304 #define APE_FW_VERSION_MINMSK 0x00ff0000 2305 #define APE_FW_VERSION_MINSFT 16 2306 #define APE_FW_VERSION_REVMSK 0x0000ff00 2307 #define APE_FW_VERSION_REVSFT 8 2308 #define APE_FW_VERSION_BLDMSK 0x000000ff 2309 #define TG3_APE_HOST_SEG_SIG 0x4200 2310 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2311 #define TG3_APE_HOST_SEG_LEN 0x4204 2312 #define APE_HOST_SEG_LEN_MAGIC 0x00000020 2313 #define TG3_APE_HOST_INIT_COUNT 0x4208 2314 #define TG3_APE_HOST_DRIVER_ID 0x420c 2315 #define APE_HOST_DRIVER_ID_LINUX 0xf0000000 2316 #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2317 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8) 2318 #define TG3_APE_HOST_BEHAVIOR 0x4210 2319 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2320 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 2321 #define APE_HOST_HEARTBEAT_INT_DISABLE 0 2322 #define APE_HOST_HEARTBEAT_INT_5SEC 5000 2323 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 2324 #define TG3_APE_HOST_DRVR_STATE 0x421c 2325 #define TG3_APE_HOST_DRVR_STATE_START 0x00000001 2326 #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2327 #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003 2328 #define TG3_APE_HOST_WOL_SPEED 0x4224 2329 #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000 2330 2331 #define TG3_APE_EVENT_STATUS 0x4300 2332 2333 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2334 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2335 #define APE_EVENT_STATUS_STATE_START 0x00010000 2336 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2337 #define APE_EVENT_STATUS_STATE_WOL 0x00030000 2338 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2339 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2340 2341 #define TG3_APE_PER_LOCK_REQ 0x8400 2342 #define APE_LOCK_PER_REQ_DRIVER 0x00001000 2343 #define TG3_APE_PER_LOCK_GRANT 0x8420 2344 #define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2345 2346 /* APE convenience enumerations. */ 2347 #define TG3_APE_LOCK_GRC 1 2348 #define TG3_APE_LOCK_MEM 4 2349 #define TG3_APE_LOCK_GPIO 7 2350 2351 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2352 2353 2354 /* There are two ways to manage the TX descriptors on the tigon3. 2355 * Either the descriptors are in host DMA'able memory, or they 2356 * exist only in the cards on-chip SRAM. All 16 send bds are under 2357 * the same mode, they may not be configured individually. 2358 * 2359 * This driver always uses host memory TX descriptors. 2360 * 2361 * To use host memory TX descriptors: 2362 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 2363 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 2364 * 2) Allocate DMA'able memory. 2365 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2366 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 2367 * obtained in step 2 2368 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 2369 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 2370 * of TX descriptors. Leave flags field clear. 2371 * 4) Access TX descriptors via host memory. The chip 2372 * will refetch into local SRAM as needed when producer 2373 * index mailboxes are updated. 2374 * 2375 * To use on-chip TX descriptors: 2376 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 2377 * Make sure GRC_MODE_HOST_SENDBDS is clear. 2378 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2379 * a) Set TG3_BDINFO_HOST_ADDR to zero. 2380 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 2381 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 2382 * 3) Access TX descriptors directly in on-chip SRAM 2383 * using normal {read,write}l(). (and not using 2384 * pointer dereferencing of ioremap()'d memory like 2385 * the broken Broadcom driver does) 2386 * 2387 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 2388 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 2389 */ 2390 struct tg3_tx_buffer_desc { 2391 u32 addr_hi; 2392 u32 addr_lo; 2393 2394 u32 len_flags; 2395 #define TXD_FLAG_TCPUDP_CSUM 0x0001 2396 #define TXD_FLAG_IP_CSUM 0x0002 2397 #define TXD_FLAG_END 0x0004 2398 #define TXD_FLAG_IP_FRAG 0x0008 2399 #define TXD_FLAG_JMB_PKT 0x0008 2400 #define TXD_FLAG_IP_FRAG_END 0x0010 2401 #define TXD_FLAG_VLAN 0x0040 2402 #define TXD_FLAG_COAL_NOW 0x0080 2403 #define TXD_FLAG_CPU_PRE_DMA 0x0100 2404 #define TXD_FLAG_CPU_POST_DMA 0x0200 2405 #define TXD_FLAG_ADD_SRC_ADDR 0x1000 2406 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 2407 #define TXD_FLAG_NO_CRC 0x8000 2408 #define TXD_LEN_SHIFT 16 2409 2410 u32 vlan_tag; 2411 #define TXD_VLAN_TAG_SHIFT 0 2412 #define TXD_MSS_SHIFT 16 2413 }; 2414 2415 #define TXD_ADDR 0x00UL /* 64-bit */ 2416 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 2417 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 2418 #define TXD_SIZE 0x10UL 2419 2420 struct tg3_rx_buffer_desc { 2421 u32 addr_hi; 2422 u32 addr_lo; 2423 2424 u32 idx_len; 2425 #define RXD_IDX_MASK 0xffff0000 2426 #define RXD_IDX_SHIFT 16 2427 #define RXD_LEN_MASK 0x0000ffff 2428 #define RXD_LEN_SHIFT 0 2429 2430 u32 type_flags; 2431 #define RXD_TYPE_SHIFT 16 2432 #define RXD_FLAGS_SHIFT 0 2433 2434 #define RXD_FLAG_END 0x0004 2435 #define RXD_FLAG_MINI 0x0800 2436 #define RXD_FLAG_JUMBO 0x0020 2437 #define RXD_FLAG_VLAN 0x0040 2438 #define RXD_FLAG_ERROR 0x0400 2439 #define RXD_FLAG_IP_CSUM 0x1000 2440 #define RXD_FLAG_TCPUDP_CSUM 0x2000 2441 #define RXD_FLAG_IS_TCP 0x4000 2442 2443 u32 ip_tcp_csum; 2444 #define RXD_IPCSUM_MASK 0xffff0000 2445 #define RXD_IPCSUM_SHIFT 16 2446 #define RXD_TCPCSUM_MASK 0x0000ffff 2447 #define RXD_TCPCSUM_SHIFT 0 2448 2449 u32 err_vlan; 2450 2451 #define RXD_VLAN_MASK 0x0000ffff 2452 2453 #define RXD_ERR_BAD_CRC 0x00010000 2454 #define RXD_ERR_COLLISION 0x00020000 2455 #define RXD_ERR_LINK_LOST 0x00040000 2456 #define RXD_ERR_PHY_DECODE 0x00080000 2457 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 2458 #define RXD_ERR_MAC_ABRT 0x00200000 2459 #define RXD_ERR_TOO_SMALL 0x00400000 2460 #define RXD_ERR_NO_RESOURCES 0x00800000 2461 #define RXD_ERR_HUGE_FRAME 0x01000000 2462 #define RXD_ERR_MASK 0xffff0000 2463 2464 u32 reserved; 2465 u32 opaque; 2466 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff 2467 #define RXD_OPAQUE_INDEX_SHIFT 0 2468 #define RXD_OPAQUE_RING_STD 0x00010000 2469 #define RXD_OPAQUE_RING_JUMBO 0x00020000 2470 #define RXD_OPAQUE_RING_MINI 0x00040000 2471 #define RXD_OPAQUE_RING_MASK 0x00070000 2472 }; 2473 2474 struct tg3_ext_rx_buffer_desc { 2475 struct { 2476 u32 addr_hi; 2477 u32 addr_lo; 2478 } addrlist[3]; 2479 u32 len2_len1; 2480 u32 resv_len3; 2481 struct tg3_rx_buffer_desc std; 2482 }; 2483 2484 /* We only use this when testing out the DMA engine 2485 * at probe time. This is the internal format of buffer 2486 * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 2487 */ 2488 struct tg3_internal_buffer_desc { 2489 u32 addr_hi; 2490 u32 addr_lo; 2491 u32 nic_mbuf; 2492 /* XXX FIX THIS */ 2493 #ifdef __BIG_ENDIAN 2494 u16 cqid_sqid; 2495 u16 len; 2496 #else 2497 u16 len; 2498 u16 cqid_sqid; 2499 #endif 2500 u32 flags; 2501 u32 __cookie1; 2502 u32 __cookie2; 2503 u32 __cookie3; 2504 }; 2505 2506 #define TG3_HW_STATUS_SIZE 0x50 2507 struct tg3_hw_status { 2508 u32 status; 2509 #define SD_STATUS_UPDATED 0x00000001 2510 #define SD_STATUS_LINK_CHG 0x00000002 2511 #define SD_STATUS_ERROR 0x00000004 2512 2513 u32 status_tag; 2514 2515 #ifdef __BIG_ENDIAN 2516 u16 rx_consumer; 2517 u16 rx_jumbo_consumer; 2518 #else 2519 u16 rx_jumbo_consumer; 2520 u16 rx_consumer; 2521 #endif 2522 2523 #ifdef __BIG_ENDIAN 2524 u16 reserved; 2525 u16 rx_mini_consumer; 2526 #else 2527 u16 rx_mini_consumer; 2528 u16 reserved; 2529 #endif 2530 struct { 2531 #ifdef __BIG_ENDIAN 2532 u16 tx_consumer; 2533 u16 rx_producer; 2534 #else 2535 u16 rx_producer; 2536 u16 tx_consumer; 2537 #endif 2538 } idx[16]; 2539 }; 2540 2541 typedef struct { 2542 u32 high, low; 2543 } tg3_stat64_t; 2544 2545 struct tg3_hw_stats { 2546 u8 __reserved0[0x400-0x300]; 2547 2548 /* Statistics maintained by Receive MAC. */ 2549 tg3_stat64_t rx_octets; 2550 u64 __reserved1; 2551 tg3_stat64_t rx_fragments; 2552 tg3_stat64_t rx_ucast_packets; 2553 tg3_stat64_t rx_mcast_packets; 2554 tg3_stat64_t rx_bcast_packets; 2555 tg3_stat64_t rx_fcs_errors; 2556 tg3_stat64_t rx_align_errors; 2557 tg3_stat64_t rx_xon_pause_rcvd; 2558 tg3_stat64_t rx_xoff_pause_rcvd; 2559 tg3_stat64_t rx_mac_ctrl_rcvd; 2560 tg3_stat64_t rx_xoff_entered; 2561 tg3_stat64_t rx_frame_too_long_errors; 2562 tg3_stat64_t rx_jabbers; 2563 tg3_stat64_t rx_undersize_packets; 2564 tg3_stat64_t rx_in_length_errors; 2565 tg3_stat64_t rx_out_length_errors; 2566 tg3_stat64_t rx_64_or_less_octet_packets; 2567 tg3_stat64_t rx_65_to_127_octet_packets; 2568 tg3_stat64_t rx_128_to_255_octet_packets; 2569 tg3_stat64_t rx_256_to_511_octet_packets; 2570 tg3_stat64_t rx_512_to_1023_octet_packets; 2571 tg3_stat64_t rx_1024_to_1522_octet_packets; 2572 tg3_stat64_t rx_1523_to_2047_octet_packets; 2573 tg3_stat64_t rx_2048_to_4095_octet_packets; 2574 tg3_stat64_t rx_4096_to_8191_octet_packets; 2575 tg3_stat64_t rx_8192_to_9022_octet_packets; 2576 2577 u64 __unused0[37]; 2578 2579 /* Statistics maintained by Transmit MAC. */ 2580 tg3_stat64_t tx_octets; 2581 u64 __reserved2; 2582 tg3_stat64_t tx_collisions; 2583 tg3_stat64_t tx_xon_sent; 2584 tg3_stat64_t tx_xoff_sent; 2585 tg3_stat64_t tx_flow_control; 2586 tg3_stat64_t tx_mac_errors; 2587 tg3_stat64_t tx_single_collisions; 2588 tg3_stat64_t tx_mult_collisions; 2589 tg3_stat64_t tx_deferred; 2590 u64 __reserved3; 2591 tg3_stat64_t tx_excessive_collisions; 2592 tg3_stat64_t tx_late_collisions; 2593 tg3_stat64_t tx_collide_2times; 2594 tg3_stat64_t tx_collide_3times; 2595 tg3_stat64_t tx_collide_4times; 2596 tg3_stat64_t tx_collide_5times; 2597 tg3_stat64_t tx_collide_6times; 2598 tg3_stat64_t tx_collide_7times; 2599 tg3_stat64_t tx_collide_8times; 2600 tg3_stat64_t tx_collide_9times; 2601 tg3_stat64_t tx_collide_10times; 2602 tg3_stat64_t tx_collide_11times; 2603 tg3_stat64_t tx_collide_12times; 2604 tg3_stat64_t tx_collide_13times; 2605 tg3_stat64_t tx_collide_14times; 2606 tg3_stat64_t tx_collide_15times; 2607 tg3_stat64_t tx_ucast_packets; 2608 tg3_stat64_t tx_mcast_packets; 2609 tg3_stat64_t tx_bcast_packets; 2610 tg3_stat64_t tx_carrier_sense_errors; 2611 tg3_stat64_t tx_discards; 2612 tg3_stat64_t tx_errors; 2613 2614 u64 __unused1[31]; 2615 2616 /* Statistics maintained by Receive List Placement. */ 2617 tg3_stat64_t COS_rx_packets[16]; 2618 tg3_stat64_t COS_rx_filter_dropped; 2619 tg3_stat64_t dma_writeq_full; 2620 tg3_stat64_t dma_write_prioq_full; 2621 tg3_stat64_t rxbds_empty; 2622 tg3_stat64_t rx_discards; 2623 tg3_stat64_t rx_errors; 2624 tg3_stat64_t rx_threshold_hit; 2625 2626 u64 __unused2[9]; 2627 2628 /* Statistics maintained by Send Data Initiator. */ 2629 tg3_stat64_t COS_out_packets[16]; 2630 tg3_stat64_t dma_readq_full; 2631 tg3_stat64_t dma_read_prioq_full; 2632 tg3_stat64_t tx_comp_queue_full; 2633 2634 /* Statistics maintained by Host Coalescing. */ 2635 tg3_stat64_t ring_set_send_prod_index; 2636 tg3_stat64_t ring_status_update; 2637 tg3_stat64_t nic_irqs; 2638 tg3_stat64_t nic_avoided_irqs; 2639 tg3_stat64_t nic_tx_threshold_hit; 2640 2641 /* NOT a part of the hardware statistics block format. 2642 * These stats are here as storage for tg3_periodic_fetch_stats(). 2643 */ 2644 tg3_stat64_t mbuf_lwm_thresh_hit; 2645 2646 u8 __reserved4[0xb00-0x9c8]; 2647 }; 2648 2649 /* 'mapping' is superfluous as the chip does not write into 2650 * the tx/rx post rings so we could just fetch it from there. 2651 * But the cache behavior is better how we are doing it now. 2652 */ 2653 struct ring_info { 2654 struct sk_buff *skb; 2655 DEFINE_DMA_UNMAP_ADDR(mapping); 2656 }; 2657 2658 struct tg3_tx_ring_info { 2659 struct sk_buff *skb; 2660 DEFINE_DMA_UNMAP_ADDR(mapping); 2661 bool fragmented; 2662 }; 2663 2664 struct tg3_link_config { 2665 /* Describes what we're trying to get. */ 2666 u32 advertising; 2667 u16 speed; 2668 u8 duplex; 2669 u8 autoneg; 2670 u8 flowctrl; 2671 2672 /* Describes what we actually have. */ 2673 u8 active_flowctrl; 2674 2675 u8 active_duplex; 2676 #define SPEED_INVALID 0xffff 2677 #define DUPLEX_INVALID 0xff 2678 #define AUTONEG_INVALID 0xff 2679 u16 active_speed; 2680 2681 /* When we go in and out of low power mode we need 2682 * to swap with this state. 2683 */ 2684 u16 orig_speed; 2685 u8 orig_duplex; 2686 u8 orig_autoneg; 2687 u32 orig_advertising; 2688 }; 2689 2690 struct tg3_bufmgr_config { 2691 u32 mbuf_read_dma_low_water; 2692 u32 mbuf_mac_rx_low_water; 2693 u32 mbuf_high_water; 2694 2695 u32 mbuf_read_dma_low_water_jumbo; 2696 u32 mbuf_mac_rx_low_water_jumbo; 2697 u32 mbuf_high_water_jumbo; 2698 2699 u32 dma_low_water; 2700 u32 dma_high_water; 2701 }; 2702 2703 struct tg3_ethtool_stats { 2704 /* Statistics maintained by Receive MAC. */ 2705 u64 rx_octets; 2706 u64 rx_fragments; 2707 u64 rx_ucast_packets; 2708 u64 rx_mcast_packets; 2709 u64 rx_bcast_packets; 2710 u64 rx_fcs_errors; 2711 u64 rx_align_errors; 2712 u64 rx_xon_pause_rcvd; 2713 u64 rx_xoff_pause_rcvd; 2714 u64 rx_mac_ctrl_rcvd; 2715 u64 rx_xoff_entered; 2716 u64 rx_frame_too_long_errors; 2717 u64 rx_jabbers; 2718 u64 rx_undersize_packets; 2719 u64 rx_in_length_errors; 2720 u64 rx_out_length_errors; 2721 u64 rx_64_or_less_octet_packets; 2722 u64 rx_65_to_127_octet_packets; 2723 u64 rx_128_to_255_octet_packets; 2724 u64 rx_256_to_511_octet_packets; 2725 u64 rx_512_to_1023_octet_packets; 2726 u64 rx_1024_to_1522_octet_packets; 2727 u64 rx_1523_to_2047_octet_packets; 2728 u64 rx_2048_to_4095_octet_packets; 2729 u64 rx_4096_to_8191_octet_packets; 2730 u64 rx_8192_to_9022_octet_packets; 2731 2732 /* Statistics maintained by Transmit MAC. */ 2733 u64 tx_octets; 2734 u64 tx_collisions; 2735 u64 tx_xon_sent; 2736 u64 tx_xoff_sent; 2737 u64 tx_flow_control; 2738 u64 tx_mac_errors; 2739 u64 tx_single_collisions; 2740 u64 tx_mult_collisions; 2741 u64 tx_deferred; 2742 u64 tx_excessive_collisions; 2743 u64 tx_late_collisions; 2744 u64 tx_collide_2times; 2745 u64 tx_collide_3times; 2746 u64 tx_collide_4times; 2747 u64 tx_collide_5times; 2748 u64 tx_collide_6times; 2749 u64 tx_collide_7times; 2750 u64 tx_collide_8times; 2751 u64 tx_collide_9times; 2752 u64 tx_collide_10times; 2753 u64 tx_collide_11times; 2754 u64 tx_collide_12times; 2755 u64 tx_collide_13times; 2756 u64 tx_collide_14times; 2757 u64 tx_collide_15times; 2758 u64 tx_ucast_packets; 2759 u64 tx_mcast_packets; 2760 u64 tx_bcast_packets; 2761 u64 tx_carrier_sense_errors; 2762 u64 tx_discards; 2763 u64 tx_errors; 2764 2765 /* Statistics maintained by Receive List Placement. */ 2766 u64 dma_writeq_full; 2767 u64 dma_write_prioq_full; 2768 u64 rxbds_empty; 2769 u64 rx_discards; 2770 u64 rx_errors; 2771 u64 rx_threshold_hit; 2772 2773 /* Statistics maintained by Send Data Initiator. */ 2774 u64 dma_readq_full; 2775 u64 dma_read_prioq_full; 2776 u64 tx_comp_queue_full; 2777 2778 /* Statistics maintained by Host Coalescing. */ 2779 u64 ring_set_send_prod_index; 2780 u64 ring_status_update; 2781 u64 nic_irqs; 2782 u64 nic_avoided_irqs; 2783 u64 nic_tx_threshold_hit; 2784 2785 u64 mbuf_lwm_thresh_hit; 2786 }; 2787 2788 struct tg3_rx_prodring_set { 2789 u32 rx_std_prod_idx; 2790 u32 rx_std_cons_idx; 2791 u32 rx_jmb_prod_idx; 2792 u32 rx_jmb_cons_idx; 2793 struct tg3_rx_buffer_desc *rx_std; 2794 struct tg3_ext_rx_buffer_desc *rx_jmb; 2795 struct ring_info *rx_std_buffers; 2796 struct ring_info *rx_jmb_buffers; 2797 dma_addr_t rx_std_mapping; 2798 dma_addr_t rx_jmb_mapping; 2799 }; 2800 2801 #define TG3_IRQ_MAX_VECS_RSS 5 2802 #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS 2803 2804 struct tg3_napi { 2805 struct napi_struct napi ____cacheline_aligned; 2806 struct tg3 *tp; 2807 struct tg3_hw_status *hw_status; 2808 2809 u32 chk_msi_cnt; 2810 u32 last_tag; 2811 u32 last_irq_tag; 2812 u32 int_mbox; 2813 u32 coal_now; 2814 2815 u32 consmbox ____cacheline_aligned; 2816 u32 rx_rcb_ptr; 2817 u32 last_rx_cons; 2818 u16 *rx_rcb_prod_idx; 2819 struct tg3_rx_prodring_set prodring; 2820 struct tg3_rx_buffer_desc *rx_rcb; 2821 2822 u32 tx_prod ____cacheline_aligned; 2823 u32 tx_cons; 2824 u32 tx_pending; 2825 u32 last_tx_cons; 2826 u32 prodmbox; 2827 struct tg3_tx_buffer_desc *tx_ring; 2828 struct tg3_tx_ring_info *tx_buffers; 2829 2830 dma_addr_t status_mapping; 2831 dma_addr_t rx_rcb_mapping; 2832 dma_addr_t tx_desc_mapping; 2833 2834 char irq_lbl[IFNAMSIZ]; 2835 unsigned int irq_vec; 2836 }; 2837 2838 enum TG3_FLAGS { 2839 TG3_FLAG_TAGGED_STATUS = 0, 2840 TG3_FLAG_TXD_MBOX_HWBUG, 2841 TG3_FLAG_USE_LINKCHG_REG, 2842 TG3_FLAG_ERROR_PROCESSED, 2843 TG3_FLAG_ENABLE_ASF, 2844 TG3_FLAG_ASPM_WORKAROUND, 2845 TG3_FLAG_POLL_SERDES, 2846 TG3_FLAG_MBOX_WRITE_REORDER, 2847 TG3_FLAG_PCIX_TARGET_HWBUG, 2848 TG3_FLAG_WOL_SPEED_100MB, 2849 TG3_FLAG_WOL_ENABLE, 2850 TG3_FLAG_EEPROM_WRITE_PROT, 2851 TG3_FLAG_NVRAM, 2852 TG3_FLAG_NVRAM_BUFFERED, 2853 TG3_FLAG_SUPPORT_MSI, 2854 TG3_FLAG_SUPPORT_MSIX, 2855 TG3_FLAG_PCIX_MODE, 2856 TG3_FLAG_PCI_HIGH_SPEED, 2857 TG3_FLAG_PCI_32BIT, 2858 TG3_FLAG_SRAM_USE_CONFIG, 2859 TG3_FLAG_TX_RECOVERY_PENDING, 2860 TG3_FLAG_WOL_CAP, 2861 TG3_FLAG_JUMBO_RING_ENABLE, 2862 TG3_FLAG_PAUSE_AUTONEG, 2863 TG3_FLAG_CPMU_PRESENT, 2864 TG3_FLAG_40BIT_DMA_BUG, 2865 TG3_FLAG_BROKEN_CHECKSUMS, 2866 TG3_FLAG_JUMBO_CAPABLE, 2867 TG3_FLAG_CHIP_RESETTING, 2868 TG3_FLAG_INIT_COMPLETE, 2869 TG3_FLAG_RESTART_TIMER, 2870 TG3_FLAG_TSO_BUG, 2871 TG3_FLAG_IS_5788, 2872 TG3_FLAG_MAX_RXPEND_64, 2873 TG3_FLAG_TSO_CAPABLE, 2874 TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ 2875 TG3_FLAG_ASF_NEW_HANDSHAKE, 2876 TG3_FLAG_HW_AUTONEG, 2877 TG3_FLAG_IS_NIC, 2878 TG3_FLAG_FLASH, 2879 TG3_FLAG_HW_TSO_1, 2880 TG3_FLAG_5705_PLUS, 2881 TG3_FLAG_5750_PLUS, 2882 TG3_FLAG_HW_TSO_3, 2883 TG3_FLAG_USING_MSI, 2884 TG3_FLAG_USING_MSIX, 2885 TG3_FLAG_ICH_WORKAROUND, 2886 TG3_FLAG_5780_CLASS, 2887 TG3_FLAG_HW_TSO_2, 2888 TG3_FLAG_1SHOT_MSI, 2889 TG3_FLAG_NO_FWARE_REPORTED, 2890 TG3_FLAG_NO_NVRAM_ADDR_TRANS, 2891 TG3_FLAG_ENABLE_APE, 2892 TG3_FLAG_PROTECTED_NVRAM, 2893 TG3_FLAG_5701_DMA_BUG, 2894 TG3_FLAG_USE_PHYLIB, 2895 TG3_FLAG_MDIOBUS_INITED, 2896 TG3_FLAG_LRG_PROD_RING_CAP, 2897 TG3_FLAG_RGMII_INBAND_DISABLE, 2898 TG3_FLAG_RGMII_EXT_IBND_RX_EN, 2899 TG3_FLAG_RGMII_EXT_IBND_TX_EN, 2900 TG3_FLAG_CLKREQ_BUG, 2901 TG3_FLAG_5755_PLUS, 2902 TG3_FLAG_NO_NVRAM, 2903 TG3_FLAG_ENABLE_RSS, 2904 TG3_FLAG_ENABLE_TSS, 2905 TG3_FLAG_SHORT_DMA_BUG, 2906 TG3_FLAG_USE_JUMBO_BDFLAG, 2907 TG3_FLAG_L1PLLPD_EN, 2908 TG3_FLAG_57765_PLUS, 2909 TG3_FLAG_APE_HAS_NCSI, 2910 TG3_FLAG_5717_PLUS, 2911 TG3_FLAG_4K_FIFO_LIMIT, 2912 2913 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */ 2914 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ 2915 }; 2916 2917 struct tg3 { 2918 /* begin "general, frequently-used members" cacheline section */ 2919 2920 /* If the IRQ handler (which runs lockless) needs to be 2921 * quiesced, the following bitmask state is used. The 2922 * SYNC flag is set by non-IRQ context code to initiate 2923 * the quiescence. 2924 * 2925 * When the IRQ handler notices that SYNC is set, it 2926 * disables interrupts and returns. 2927 * 2928 * When all outstanding IRQ handlers have returned after 2929 * the SYNC flag has been set, the setter can be assured 2930 * that interrupts will no longer get run. 2931 * 2932 * In this way all SMP driver locks are never acquired 2933 * in hw IRQ context, only sw IRQ context or lower. 2934 */ 2935 unsigned int irq_sync; 2936 2937 /* SMP locking strategy: 2938 * 2939 * lock: Held during reset, PHY access, timer, and when 2940 * updating tg3_flags. 2941 * 2942 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 2943 * netif_tx_lock when it needs to call 2944 * netif_wake_queue. 2945 * 2946 * Both of these locks are to be held with BH safety. 2947 * 2948 * Because the IRQ handler, tg3_poll, and tg3_start_xmit 2949 * are running lockless, it is necessary to completely 2950 * quiesce the chip with tg3_netif_stop and tg3_full_lock 2951 * before reconfiguring the device. 2952 * 2953 * indirect_lock: Held when accessing registers indirectly 2954 * with IRQ disabling. 2955 */ 2956 spinlock_t lock; 2957 spinlock_t indirect_lock; 2958 2959 u32 (*read32) (struct tg3 *, u32); 2960 void (*write32) (struct tg3 *, u32, u32); 2961 u32 (*read32_mbox) (struct tg3 *, u32); 2962 void (*write32_mbox) (struct tg3 *, u32, 2963 u32); 2964 void __iomem *regs; 2965 void __iomem *aperegs; 2966 struct net_device *dev; 2967 struct pci_dev *pdev; 2968 2969 u32 coal_now; 2970 u32 msg_enable; 2971 2972 /* begin "tx thread" cacheline section */ 2973 void (*write32_tx_mbox) (struct tg3 *, u32, 2974 u32); 2975 2976 /* begin "rx thread" cacheline section */ 2977 struct tg3_napi napi[TG3_IRQ_MAX_VECS]; 2978 void (*write32_rx_mbox) (struct tg3 *, u32, 2979 u32); 2980 u32 rx_copy_thresh; 2981 u32 rx_std_ring_mask; 2982 u32 rx_jmb_ring_mask; 2983 u32 rx_ret_ring_mask; 2984 u32 rx_pending; 2985 u32 rx_jumbo_pending; 2986 u32 rx_std_max_post; 2987 u32 rx_offset; 2988 u32 rx_pkt_map_sz; 2989 2990 2991 /* begin "everything else" cacheline(s) section */ 2992 unsigned long rx_dropped; 2993 unsigned long tx_dropped; 2994 struct rtnl_link_stats64 net_stats_prev; 2995 struct tg3_ethtool_stats estats; 2996 struct tg3_ethtool_stats estats_prev; 2997 2998 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS); 2999 3000 union { 3001 unsigned long phy_crc_errors; 3002 unsigned long last_event_jiffies; 3003 }; 3004 3005 struct timer_list timer; 3006 u16 timer_counter; 3007 u16 timer_multiplier; 3008 u32 timer_offset; 3009 u16 asf_counter; 3010 u16 asf_multiplier; 3011 3012 /* 1 second counter for transient serdes link events */ 3013 u32 serdes_counter; 3014 #define SERDES_AN_TIMEOUT_5704S 2 3015 #define SERDES_PARALLEL_DET_TIMEOUT 1 3016 #define SERDES_AN_TIMEOUT_5714S 1 3017 3018 struct tg3_link_config link_config; 3019 struct tg3_bufmgr_config bufmgr_config; 3020 3021 /* cache h/w values, often passed straight to h/w */ 3022 u32 rx_mode; 3023 u32 tx_mode; 3024 u32 mac_mode; 3025 u32 mi_mode; 3026 u32 misc_host_ctrl; 3027 u32 grc_mode; 3028 u32 grc_local_ctrl; 3029 u32 dma_rwctrl; 3030 u32 coalesce_mode; 3031 u32 pwrmgmt_thresh; 3032 3033 /* PCI block */ 3034 u32 pci_chip_rev_id; 3035 u16 pci_cmd; 3036 u8 pci_cacheline_sz; 3037 u8 pci_lat_timer; 3038 3039 int pci_fn; 3040 int pm_cap; 3041 int msi_cap; 3042 int pcix_cap; 3043 int pcie_readrq; 3044 3045 struct mii_bus *mdio_bus; 3046 int mdio_irq[PHY_MAX_ADDR]; 3047 3048 u8 phy_addr; 3049 3050 /* PHY info */ 3051 u32 phy_id; 3052 #define TG3_PHY_ID_MASK 0xfffffff0 3053 #define TG3_PHY_ID_BCM5400 0x60008040 3054 #define TG3_PHY_ID_BCM5401 0x60008050 3055 #define TG3_PHY_ID_BCM5411 0x60008070 3056 #define TG3_PHY_ID_BCM5701 0x60008110 3057 #define TG3_PHY_ID_BCM5703 0x60008160 3058 #define TG3_PHY_ID_BCM5704 0x60008190 3059 #define TG3_PHY_ID_BCM5705 0x600081a0 3060 #define TG3_PHY_ID_BCM5750 0x60008180 3061 #define TG3_PHY_ID_BCM5752 0x60008100 3062 #define TG3_PHY_ID_BCM5714 0x60008340 3063 #define TG3_PHY_ID_BCM5780 0x60008350 3064 #define TG3_PHY_ID_BCM5755 0xbc050cc0 3065 #define TG3_PHY_ID_BCM5787 0xbc050ce0 3066 #define TG3_PHY_ID_BCM5756 0xbc050ed0 3067 #define TG3_PHY_ID_BCM5784 0xbc050fa0 3068 #define TG3_PHY_ID_BCM5761 0xbc050fd0 3069 #define TG3_PHY_ID_BCM5718C 0x5c0d8a00 3070 #define TG3_PHY_ID_BCM5718S 0xbc050ff0 3071 #define TG3_PHY_ID_BCM57765 0x5c0d8a40 3072 #define TG3_PHY_ID_BCM5719C 0x5c0d8a20 3073 #define TG3_PHY_ID_BCM5720C 0x5c0d8b60 3074 #define TG3_PHY_ID_BCM5906 0xdc00ac40 3075 #define TG3_PHY_ID_BCM8002 0x60010140 3076 #define TG3_PHY_ID_INVALID 0xffffffff 3077 3078 #define PHY_ID_RTL8211C 0x001cc910 3079 #define PHY_ID_RTL8201E 0x00008200 3080 3081 #define TG3_PHY_ID_REV_MASK 0x0000000f 3082 #define TG3_PHY_REV_BCM5401_B0 0x1 3083 3084 /* This macro assumes the passed PHY ID is 3085 * already masked with TG3_PHY_ID_MASK. 3086 */ 3087 #define TG3_KNOWN_PHY_ID(X) \ 3088 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \ 3089 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \ 3090 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \ 3091 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \ 3092 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \ 3093 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \ 3094 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \ 3095 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ 3096 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ 3097 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ 3098 (X) == TG3_PHY_ID_BCM8002) 3099 3100 u32 phy_flags; 3101 #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 3102 #define TG3_PHYFLG_IS_CONNECTED 0x00000002 3103 #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 3104 #define TG3_PHYFLG_PHY_SERDES 0x00000010 3105 #define TG3_PHYFLG_MII_SERDES 0x00000020 3106 #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ 3107 TG3_PHYFLG_MII_SERDES) 3108 #define TG3_PHYFLG_IS_FET 0x00000040 3109 #define TG3_PHYFLG_10_100_ONLY 0x00000080 3110 #define TG3_PHYFLG_ENABLE_APD 0x00000100 3111 #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200 3112 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400 3113 #define TG3_PHYFLG_JITTER_BUG 0x00000800 3114 #define TG3_PHYFLG_ADJUST_TRIM 0x00001000 3115 #define TG3_PHYFLG_ADC_BUG 0x00002000 3116 #define TG3_PHYFLG_5704_A0_BUG 0x00004000 3117 #define TG3_PHYFLG_BER_BUG 0x00008000 3118 #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 3119 #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 3120 #define TG3_PHYFLG_EEE_CAP 0x00040000 3121 3122 u32 led_ctrl; 3123 u32 phy_otp; 3124 u32 setlpicnt; 3125 3126 #define TG3_BPN_SIZE 24 3127 char board_part_number[TG3_BPN_SIZE]; 3128 #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN 3129 char fw_ver[TG3_VER_SIZE]; 3130 u32 nic_sram_data_cfg; 3131 u32 pci_clock_ctrl; 3132 struct pci_dev *pdev_peer; 3133 3134 struct tg3_hw_stats *hw_stats; 3135 dma_addr_t stats_mapping; 3136 struct work_struct reset_task; 3137 3138 int nvram_lock_cnt; 3139 u32 nvram_size; 3140 #define TG3_NVRAM_SIZE_2KB 0x00000800 3141 #define TG3_NVRAM_SIZE_64KB 0x00010000 3142 #define TG3_NVRAM_SIZE_128KB 0x00020000 3143 #define TG3_NVRAM_SIZE_256KB 0x00040000 3144 #define TG3_NVRAM_SIZE_512KB 0x00080000 3145 #define TG3_NVRAM_SIZE_1MB 0x00100000 3146 #define TG3_NVRAM_SIZE_2MB 0x00200000 3147 3148 u32 nvram_pagesize; 3149 u32 nvram_jedecnum; 3150 3151 #define JEDEC_ATMEL 0x1f 3152 #define JEDEC_ST 0x20 3153 #define JEDEC_SAIFUN 0x4f 3154 #define JEDEC_SST 0xbf 3155 3156 #define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB 3157 #define ATMEL_AT24C02_PAGE_SIZE (8) 3158 3159 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB 3160 #define ATMEL_AT24C64_PAGE_SIZE (32) 3161 3162 #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB 3163 #define ATMEL_AT24C512_PAGE_SIZE (128) 3164 3165 #define ATMEL_AT45DB0X1B_PAGE_POS 9 3166 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264 3167 3168 #define ATMEL_AT25F512_PAGE_SIZE 256 3169 3170 #define ST_M45PEX0_PAGE_SIZE 256 3171 3172 #define SAIFUN_SA25F0XX_PAGE_SIZE 256 3173 3174 #define SST_25VF0X0_PAGE_SIZE 4098 3175 3176 unsigned int irq_max; 3177 unsigned int irq_cnt; 3178 3179 struct ethtool_coalesce coal; 3180 3181 /* firmware info */ 3182 const char *fw_needed; 3183 const struct firmware *fw; 3184 u32 fw_len; /* includes BSS */ 3185 }; 3186 3187 #endif /* !(_T3_H) */ 3188