1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ 2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 6 * Copyright (C) 2004 Sun Microsystems Inc. 7 * Copyright (C) 2007-2013 Broadcom Corporation. 8 */ 9 10 #ifndef _T3_H 11 #define _T3_H 12 13 #define TG3_64BIT_REG_HIGH 0x00UL 14 #define TG3_64BIT_REG_LOW 0x04UL 15 16 /* Descriptor block info. */ 17 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 18 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 19 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 20 #define BDINFO_FLAGS_DISABLED 0x00000002 21 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 22 #define BDINFO_FLAGS_MAXLEN_SHIFT 16 23 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 24 #define TG3_BDINFO_SIZE 0x10UL 25 26 #define TG3_RX_STD_MAX_SIZE_5700 512 27 #define TG3_RX_STD_MAX_SIZE_5717 2048 28 #define TG3_RX_JMB_MAX_SIZE_5700 256 29 #define TG3_RX_JMB_MAX_SIZE_5717 1024 30 #define TG3_RX_RET_MAX_SIZE_5700 1024 31 #define TG3_RX_RET_MAX_SIZE_5705 512 32 #define TG3_RX_RET_MAX_SIZE_5717 4096 33 34 #define TG3_RSS_INDIR_TBL_SIZE 128 35 36 /* First 256 bytes are a mirror of PCI config space. */ 37 #define TG3PCI_VENDOR 0x00000000 38 #define TG3PCI_VENDOR_BROADCOM 0x14e4 39 #define TG3PCI_DEVICE 0x00000002 40 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 41 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 42 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 43 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 44 #define TG3PCI_DEVICE_TIGON3_5761S 0x1688 45 #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 46 #define TG3PCI_DEVICE_TIGON3_57780 0x1692 47 #define TG3PCI_DEVICE_TIGON3_5787M 0x1693 48 #define TG3PCI_DEVICE_TIGON3_57760 0x1690 49 #define TG3PCI_DEVICE_TIGON3_57790 0x1694 50 #define TG3PCI_DEVICE_TIGON3_57788 0x1691 51 #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ 52 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ 53 #define TG3PCI_DEVICE_TIGON3_5717 0x1655 54 #define TG3PCI_DEVICE_TIGON3_5717_C 0x1665 55 #define TG3PCI_DEVICE_TIGON3_5718 0x1656 56 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1 57 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5 58 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0 59 #define TG3PCI_DEVICE_TIGON3_57765 0x16b4 60 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2 61 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6 62 #define TG3PCI_DEVICE_TIGON3_5719 0x1657 63 #define TG3PCI_DEVICE_TIGON3_5720 0x165f 64 #define TG3PCI_DEVICE_TIGON3_57762 0x1682 65 #define TG3PCI_DEVICE_TIGON3_57766 0x1686 66 #define TG3PCI_DEVICE_TIGON3_57786 0x16b3 67 #define TG3PCI_DEVICE_TIGON3_57782 0x16b7 68 #define TG3PCI_DEVICE_TIGON3_5762 0x1687 69 #define TG3PCI_DEVICE_TIGON3_5725 0x1643 70 #define TG3PCI_DEVICE_TIGON3_5727 0x16f3 71 /* 0x04 --> 0x2c unused */ 72 #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM 73 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 74 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 75 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 76 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 77 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 78 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 79 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 80 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 81 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 82 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 83 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 84 #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM 85 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 86 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 87 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 88 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 89 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 90 #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL 91 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 92 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 93 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 94 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a 95 #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ 96 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c 97 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a 98 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d 99 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 100 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 101 #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM 102 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 103 #define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601 104 #define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612 105 #define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056 106 107 /* 0x30 --> 0x64 unused */ 108 #define TG3PCI_MSI_DATA 0x00000064 109 /* 0x66 --> 0x68 unused */ 110 #define TG3PCI_MISC_HOST_CTRL 0x00000068 111 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 112 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 113 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 114 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 115 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 116 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 117 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 118 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 119 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 120 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 121 #define MISC_HOST_CTRL_CHIPREV 0xffff0000 122 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 123 124 #define CHIPREV_ID_5700_A0 0x7000 125 #define CHIPREV_ID_5700_A1 0x7001 126 #define CHIPREV_ID_5700_B0 0x7100 127 #define CHIPREV_ID_5700_B1 0x7101 128 #define CHIPREV_ID_5700_B3 0x7102 129 #define CHIPREV_ID_5700_ALTIMA 0x7104 130 #define CHIPREV_ID_5700_C0 0x7200 131 #define CHIPREV_ID_5701_A0 0x0000 132 #define CHIPREV_ID_5701_B0 0x0100 133 #define CHIPREV_ID_5701_B2 0x0102 134 #define CHIPREV_ID_5701_B5 0x0105 135 #define CHIPREV_ID_5703_A0 0x1000 136 #define CHIPREV_ID_5703_A1 0x1001 137 #define CHIPREV_ID_5703_A2 0x1002 138 #define CHIPREV_ID_5703_A3 0x1003 139 #define CHIPREV_ID_5704_A0 0x2000 140 #define CHIPREV_ID_5704_A1 0x2001 141 #define CHIPREV_ID_5704_A2 0x2002 142 #define CHIPREV_ID_5704_A3 0x2003 143 #define CHIPREV_ID_5705_A0 0x3000 144 #define CHIPREV_ID_5705_A1 0x3001 145 #define CHIPREV_ID_5705_A2 0x3002 146 #define CHIPREV_ID_5705_A3 0x3003 147 #define CHIPREV_ID_5750_A0 0x4000 148 #define CHIPREV_ID_5750_A1 0x4001 149 #define CHIPREV_ID_5750_A3 0x4003 150 #define CHIPREV_ID_5750_C2 0x4202 151 #define CHIPREV_ID_5752_A0_HW 0x5000 152 #define CHIPREV_ID_5752_A0 0x6000 153 #define CHIPREV_ID_5752_A1 0x6001 154 #define CHIPREV_ID_5714_A2 0x9002 155 #define CHIPREV_ID_5906_A1 0xc001 156 #define CHIPREV_ID_57780_A0 0x57780000 157 #define CHIPREV_ID_57780_A1 0x57780001 158 #define CHIPREV_ID_5717_A0 0x05717000 159 #define CHIPREV_ID_5717_C0 0x05717200 160 #define CHIPREV_ID_57765_A0 0x57785000 161 #define CHIPREV_ID_5719_A0 0x05719000 162 #define CHIPREV_ID_5720_A0 0x05720000 163 #define CHIPREV_ID_5762_A0 0x05762000 164 165 #define ASIC_REV_5700 0x07 166 #define ASIC_REV_5701 0x00 167 #define ASIC_REV_5703 0x01 168 #define ASIC_REV_5704 0x02 169 #define ASIC_REV_5705 0x03 170 #define ASIC_REV_5750 0x04 171 #define ASIC_REV_5752 0x06 172 #define ASIC_REV_5780 0x08 173 #define ASIC_REV_5714 0x09 174 #define ASIC_REV_5755 0x0a 175 #define ASIC_REV_5787 0x0b 176 #define ASIC_REV_5906 0x0c 177 #define ASIC_REV_USE_PROD_ID_REG 0x0f 178 #define ASIC_REV_5784 0x5784 179 #define ASIC_REV_5761 0x5761 180 #define ASIC_REV_5785 0x5785 181 #define ASIC_REV_57780 0x57780 182 #define ASIC_REV_5717 0x5717 183 #define ASIC_REV_57765 0x57785 184 #define ASIC_REV_5719 0x5719 185 #define ASIC_REV_5720 0x5720 186 #define ASIC_REV_57766 0x57766 187 #define ASIC_REV_5762 0x5762 188 #define CHIPREV_5700_AX 0x70 189 #define CHIPREV_5700_BX 0x71 190 #define CHIPREV_5700_CX 0x72 191 #define CHIPREV_5701_AX 0x00 192 #define CHIPREV_5703_AX 0x10 193 #define CHIPREV_5704_AX 0x20 194 #define CHIPREV_5704_BX 0x21 195 #define CHIPREV_5750_AX 0x40 196 #define CHIPREV_5750_BX 0x41 197 #define CHIPREV_5784_AX 0x57840 198 #define CHIPREV_5761_AX 0x57610 199 #define CHIPREV_57765_AX 0x577650 200 #define METAL_REV_A0 0x00 201 #define METAL_REV_A1 0x01 202 #define METAL_REV_B0 0x00 203 #define METAL_REV_B1 0x01 204 #define METAL_REV_B2 0x02 205 #define TG3PCI_DMA_RW_CTRL 0x0000006c 206 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 207 #define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 208 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 209 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 210 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 211 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 212 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 213 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 214 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 215 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 216 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 217 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 218 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 219 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 220 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 221 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 222 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 223 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 224 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 225 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 226 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 227 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 228 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 229 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 230 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 231 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 232 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 233 #define DMA_RWCTRL_ONE_DMA 0x00004000 234 #define DMA_RWCTRL_READ_WATER 0x00070000 235 #define DMA_RWCTRL_READ_WATER_SHIFT 16 236 #define DMA_RWCTRL_WRITE_WATER 0x00380000 237 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 238 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 239 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 240 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 241 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 242 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 243 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 244 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 245 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 246 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 247 #define TG3PCI_PCISTATE 0x00000070 248 #define PCISTATE_FORCE_RESET 0x00000001 249 #define PCISTATE_INT_NOT_ACTIVE 0x00000002 250 #define PCISTATE_CONV_PCI_MODE 0x00000004 251 #define PCISTATE_BUS_SPEED_HIGH 0x00000008 252 #define PCISTATE_BUS_32BIT 0x00000010 253 #define PCISTATE_ROM_ENABLE 0x00000020 254 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 255 #define PCISTATE_FLAT_VIEW 0x00000100 256 #define PCISTATE_RETRY_SAME_DMA 0x00002000 257 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 258 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 259 #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 260 #define TG3PCI_CLOCK_CTRL 0x00000074 261 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 262 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 263 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 264 #define CLOCK_CTRL_ALTCLK 0x00001000 265 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 266 #define CLOCK_CTRL_44MHZ_CORE 0x00040000 267 #define CLOCK_CTRL_625_CORE 0x00100000 268 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 269 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 270 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 271 #define TG3PCI_REG_BASE_ADDR 0x00000078 272 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 273 #define TG3PCI_REG_DATA 0x00000080 274 #define TG3PCI_MEM_WIN_DATA 0x00000084 275 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 276 /* 0x94 --> 0x98 unused */ 277 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 278 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 279 /* 0xa8 --> 0xb8 unused */ 280 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8 281 #define DUAL_MAC_CTRL_CH_MASK 0x00000003 282 #define DUAL_MAC_CTRL_ID 0x00000004 283 #define TG3PCI_PRODID_ASICREV 0x000000bc 284 #define PROD_ID_ASIC_REV_MASK 0x0fffffff 285 /* 0xc0 --> 0xf4 unused */ 286 287 #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 288 #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc 289 /* 0xf8 --> 0x200 unused */ 290 291 #define TG3_CORR_ERR_STAT 0x00000110 292 #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff 293 /* 0x114 --> 0x200 unused */ 294 295 /* Mailbox registers */ 296 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 297 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 298 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 299 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 300 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 301 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 302 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 303 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 304 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 305 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 306 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 307 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 308 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 309 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 310 #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ 311 TG3_64BIT_REG_LOW) 312 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 313 #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ 314 TG3_64BIT_REG_LOW) 315 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 316 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 317 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 318 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 319 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 320 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 321 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 322 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 323 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 324 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 325 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 326 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 327 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 328 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 329 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 330 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 331 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 332 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 333 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 334 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 335 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 336 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 337 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 338 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 339 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 340 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 341 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 342 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 343 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 344 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 345 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 346 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 347 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 348 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 349 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 350 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 351 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 352 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 353 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 354 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 355 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 356 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 357 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 358 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 359 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 360 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 361 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 362 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 363 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 364 365 /* MAC control registers */ 366 #define MAC_MODE 0x00000400 367 #define MAC_MODE_RESET 0x00000001 368 #define MAC_MODE_HALF_DUPLEX 0x00000002 369 #define MAC_MODE_PORT_MODE_MASK 0x0000000c 370 #define MAC_MODE_PORT_MODE_TBI 0x0000000c 371 #define MAC_MODE_PORT_MODE_GMII 0x00000008 372 #define MAC_MODE_PORT_MODE_MII 0x00000004 373 #define MAC_MODE_PORT_MODE_NONE 0x00000000 374 #define MAC_MODE_PORT_INT_LPBACK 0x00000010 375 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 376 #define MAC_MODE_TX_BURSTING 0x00000100 377 #define MAC_MODE_MAX_DEFER 0x00000200 378 #define MAC_MODE_LINK_POLARITY 0x00000400 379 #define MAC_MODE_RXSTAT_ENABLE 0x00000800 380 #define MAC_MODE_RXSTAT_CLEAR 0x00001000 381 #define MAC_MODE_RXSTAT_FLUSH 0x00002000 382 #define MAC_MODE_TXSTAT_ENABLE 0x00004000 383 #define MAC_MODE_TXSTAT_CLEAR 0x00008000 384 #define MAC_MODE_TXSTAT_FLUSH 0x00010000 385 #define MAC_MODE_SEND_CONFIGS 0x00020000 386 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 387 #define MAC_MODE_ACPI_ENABLE 0x00080000 388 #define MAC_MODE_MIP_ENABLE 0x00100000 389 #define MAC_MODE_TDE_ENABLE 0x00200000 390 #define MAC_MODE_RDE_ENABLE 0x00400000 391 #define MAC_MODE_FHDE_ENABLE 0x00800000 392 #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 393 #define MAC_MODE_APE_RX_EN 0x08000000 394 #define MAC_MODE_APE_TX_EN 0x10000000 395 #define MAC_STATUS 0x00000404 396 #define MAC_STATUS_PCS_SYNCED 0x00000001 397 #define MAC_STATUS_SIGNAL_DET 0x00000002 398 #define MAC_STATUS_RCVD_CFG 0x00000004 399 #define MAC_STATUS_CFG_CHANGED 0x00000008 400 #define MAC_STATUS_SYNC_CHANGED 0x00000010 401 #define MAC_STATUS_PORT_DEC_ERR 0x00000400 402 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 403 #define MAC_STATUS_MI_COMPLETION 0x00400000 404 #define MAC_STATUS_MI_INTERRUPT 0x00800000 405 #define MAC_STATUS_AP_ERROR 0x01000000 406 #define MAC_STATUS_ODI_ERROR 0x02000000 407 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 408 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 409 #define MAC_EVENT 0x00000408 410 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 411 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 412 #define MAC_EVENT_MI_COMPLETION 0x00400000 413 #define MAC_EVENT_MI_INTERRUPT 0x00800000 414 #define MAC_EVENT_AP_ERROR 0x01000000 415 #define MAC_EVENT_ODI_ERROR 0x02000000 416 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 417 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 418 #define MAC_LED_CTRL 0x0000040c 419 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 420 #define LED_CTRL_1000MBPS_ON 0x00000002 421 #define LED_CTRL_100MBPS_ON 0x00000004 422 #define LED_CTRL_10MBPS_ON 0x00000008 423 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 424 #define LED_CTRL_TRAFFIC_BLINK 0x00000020 425 #define LED_CTRL_TRAFFIC_LED 0x00000040 426 #define LED_CTRL_1000MBPS_STATUS 0x00000080 427 #define LED_CTRL_100MBPS_STATUS 0x00000100 428 #define LED_CTRL_10MBPS_STATUS 0x00000200 429 #define LED_CTRL_TRAFFIC_STATUS 0x00000400 430 #define LED_CTRL_MODE_MAC 0x00000000 431 #define LED_CTRL_MODE_PHY_1 0x00000800 432 #define LED_CTRL_MODE_PHY_2 0x00001000 433 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000 434 #define LED_CTRL_MODE_SHARED 0x00004000 435 #define LED_CTRL_MODE_COMBO 0x00008000 436 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 437 #define LED_CTRL_BLINK_RATE_SHIFT 19 438 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 439 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 440 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 441 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 442 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 443 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 444 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 445 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 446 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 447 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 448 #define MAC_ACPI_MBUF_PTR 0x00000430 449 #define MAC_ACPI_LEN_OFFSET 0x00000434 450 #define ACPI_LENOFF_LEN_MASK 0x0000ffff 451 #define ACPI_LENOFF_LEN_SHIFT 0 452 #define ACPI_LENOFF_OFF_MASK 0x0fff0000 453 #define ACPI_LENOFF_OFF_SHIFT 16 454 #define MAC_TX_BACKOFF_SEED 0x00000438 455 #define TX_BACKOFF_SEED_MASK 0x000003ff 456 #define MAC_RX_MTU_SIZE 0x0000043c 457 #define RX_MTU_SIZE_MASK 0x0000ffff 458 #define MAC_PCS_TEST 0x00000440 459 #define PCS_TEST_PATTERN_MASK 0x000fffff 460 #define PCS_TEST_PATTERN_SHIFT 0 461 #define PCS_TEST_ENABLE 0x00100000 462 #define MAC_TX_AUTO_NEG 0x00000444 463 #define TX_AUTO_NEG_MASK 0x0000ffff 464 #define TX_AUTO_NEG_SHIFT 0 465 #define MAC_RX_AUTO_NEG 0x00000448 466 #define RX_AUTO_NEG_MASK 0x0000ffff 467 #define RX_AUTO_NEG_SHIFT 0 468 #define MAC_MI_COM 0x0000044c 469 #define MI_COM_CMD_MASK 0x0c000000 470 #define MI_COM_CMD_WRITE 0x04000000 471 #define MI_COM_CMD_READ 0x08000000 472 #define MI_COM_READ_FAILED 0x10000000 473 #define MI_COM_START 0x20000000 474 #define MI_COM_BUSY 0x20000000 475 #define MI_COM_PHY_ADDR_MASK 0x03e00000 476 #define MI_COM_PHY_ADDR_SHIFT 21 477 #define MI_COM_REG_ADDR_MASK 0x001f0000 478 #define MI_COM_REG_ADDR_SHIFT 16 479 #define MI_COM_DATA_MASK 0x0000ffff 480 #define MAC_MI_STAT 0x00000450 481 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 482 #define MAC_MI_STAT_10MBPS_MODE 0x00000002 483 #define MAC_MI_MODE 0x00000454 484 #define MAC_MI_MODE_CLK_10MHZ 0x00000001 485 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 486 #define MAC_MI_MODE_AUTO_POLL 0x00000010 487 #define MAC_MI_MODE_500KHZ_CONST 0x00008000 488 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 489 #define MAC_AUTO_POLL_STATUS 0x00000458 490 #define MAC_AUTO_POLL_ERROR 0x00000001 491 #define MAC_TX_MODE 0x0000045c 492 #define TX_MODE_RESET 0x00000001 493 #define TX_MODE_ENABLE 0x00000002 494 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 495 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 496 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 497 #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 498 #define TX_MODE_JMB_FRM_LEN 0x00400000 499 #define TX_MODE_CNT_DN_MODE 0x00800000 500 #define MAC_TX_STATUS 0x00000460 501 #define TX_STATUS_XOFFED 0x00000001 502 #define TX_STATUS_SENT_XOFF 0x00000002 503 #define TX_STATUS_SENT_XON 0x00000004 504 #define TX_STATUS_LINK_UP 0x00000008 505 #define TX_STATUS_ODI_UNDERRUN 0x00000010 506 #define TX_STATUS_ODI_OVERRUN 0x00000020 507 #define MAC_TX_LENGTHS 0x00000464 508 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 509 #define TX_LENGTHS_SLOT_TIME_SHIFT 0 510 #define TX_LENGTHS_IPG_MASK 0x00000f00 511 #define TX_LENGTHS_IPG_SHIFT 8 512 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 513 #define TX_LENGTHS_IPG_CRS_SHIFT 12 514 #define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000 515 #define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000 516 #define MAC_RX_MODE 0x00000468 517 #define RX_MODE_RESET 0x00000001 518 #define RX_MODE_ENABLE 0x00000002 519 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 520 #define RX_MODE_KEEP_MAC_CTRL 0x00000008 521 #define RX_MODE_KEEP_PAUSE 0x00000010 522 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 523 #define RX_MODE_ACCEPT_RUNTS 0x00000040 524 #define RX_MODE_LEN_CHECK 0x00000080 525 #define RX_MODE_PROMISC 0x00000100 526 #define RX_MODE_NO_CRC_CHECK 0x00000200 527 #define RX_MODE_KEEP_VLAN_TAG 0x00000400 528 #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 529 #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 530 #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 531 #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 532 #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 533 #define RX_MODE_RSS_ENABLE 0x00800000 534 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 535 #define RX_MODE_IPV4_FRAG_FIX 0x02000000 536 #define MAC_RX_STATUS 0x0000046c 537 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 538 #define RX_STATUS_XOFF_RCVD 0x00000002 539 #define RX_STATUS_XON_RCVD 0x00000004 540 #define MAC_HASH_REG_0 0x00000470 541 #define MAC_HASH_REG_1 0x00000474 542 #define MAC_HASH_REG_2 0x00000478 543 #define MAC_HASH_REG_3 0x0000047c 544 #define MAC_RCV_RULE_0 0x00000480 545 #define MAC_RCV_VALUE_0 0x00000484 546 #define MAC_RCV_RULE_1 0x00000488 547 #define MAC_RCV_VALUE_1 0x0000048c 548 #define MAC_RCV_RULE_2 0x00000490 549 #define MAC_RCV_VALUE_2 0x00000494 550 #define MAC_RCV_RULE_3 0x00000498 551 #define MAC_RCV_VALUE_3 0x0000049c 552 #define MAC_RCV_RULE_4 0x000004a0 553 #define MAC_RCV_VALUE_4 0x000004a4 554 #define MAC_RCV_RULE_5 0x000004a8 555 #define MAC_RCV_VALUE_5 0x000004ac 556 #define MAC_RCV_RULE_6 0x000004b0 557 #define MAC_RCV_VALUE_6 0x000004b4 558 #define MAC_RCV_RULE_7 0x000004b8 559 #define MAC_RCV_VALUE_7 0x000004bc 560 #define MAC_RCV_RULE_8 0x000004c0 561 #define MAC_RCV_VALUE_8 0x000004c4 562 #define MAC_RCV_RULE_9 0x000004c8 563 #define MAC_RCV_VALUE_9 0x000004cc 564 #define MAC_RCV_RULE_10 0x000004d0 565 #define MAC_RCV_VALUE_10 0x000004d4 566 #define MAC_RCV_RULE_11 0x000004d8 567 #define MAC_RCV_VALUE_11 0x000004dc 568 #define MAC_RCV_RULE_12 0x000004e0 569 #define MAC_RCV_VALUE_12 0x000004e4 570 #define MAC_RCV_RULE_13 0x000004e8 571 #define MAC_RCV_VALUE_13 0x000004ec 572 #define MAC_RCV_RULE_14 0x000004f0 573 #define MAC_RCV_VALUE_14 0x000004f4 574 #define MAC_RCV_RULE_15 0x000004f8 575 #define MAC_RCV_VALUE_15 0x000004fc 576 #define RCV_RULE_DISABLE_MASK 0x7fffffff 577 #define MAC_RCV_RULE_CFG 0x00000500 578 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 579 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 580 /* 0x508 --> 0x520 unused */ 581 #define MAC_HASHREGU_0 0x00000520 582 #define MAC_HASHREGU_1 0x00000524 583 #define MAC_HASHREGU_2 0x00000528 584 #define MAC_HASHREGU_3 0x0000052c 585 #define MAC_EXTADDR_0_HIGH 0x00000530 586 #define MAC_EXTADDR_0_LOW 0x00000534 587 #define MAC_EXTADDR_1_HIGH 0x00000538 588 #define MAC_EXTADDR_1_LOW 0x0000053c 589 #define MAC_EXTADDR_2_HIGH 0x00000540 590 #define MAC_EXTADDR_2_LOW 0x00000544 591 #define MAC_EXTADDR_3_HIGH 0x00000548 592 #define MAC_EXTADDR_3_LOW 0x0000054c 593 #define MAC_EXTADDR_4_HIGH 0x00000550 594 #define MAC_EXTADDR_4_LOW 0x00000554 595 #define MAC_EXTADDR_5_HIGH 0x00000558 596 #define MAC_EXTADDR_5_LOW 0x0000055c 597 #define MAC_EXTADDR_6_HIGH 0x00000560 598 #define MAC_EXTADDR_6_LOW 0x00000564 599 #define MAC_EXTADDR_7_HIGH 0x00000568 600 #define MAC_EXTADDR_7_LOW 0x0000056c 601 #define MAC_EXTADDR_8_HIGH 0x00000570 602 #define MAC_EXTADDR_8_LOW 0x00000574 603 #define MAC_EXTADDR_9_HIGH 0x00000578 604 #define MAC_EXTADDR_9_LOW 0x0000057c 605 #define MAC_EXTADDR_10_HIGH 0x00000580 606 #define MAC_EXTADDR_10_LOW 0x00000584 607 #define MAC_EXTADDR_11_HIGH 0x00000588 608 #define MAC_EXTADDR_11_LOW 0x0000058c 609 #define MAC_SERDES_CFG 0x00000590 610 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 611 #define MAC_SERDES_STAT 0x00000594 612 /* 0x598 --> 0x5a0 unused */ 613 #define MAC_PHYCFG1 0x000005a0 614 #define MAC_PHYCFG1_RGMII_INT 0x00000001 615 #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 616 #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 617 #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 618 #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 619 #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 620 #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 621 #define MAC_PHYCFG1_TXC_DRV 0x20000000 622 #define MAC_PHYCFG2 0x000005a4 623 #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 624 #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 625 #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 626 #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 627 #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 628 #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 629 #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 630 #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 631 #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 632 #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 633 #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 634 #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 635 #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 636 #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 637 #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 638 #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 639 #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 640 #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 641 #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 642 #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 643 #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 644 #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 645 #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 646 #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 647 #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 648 #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 649 #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 650 #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 651 #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 652 #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 653 #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 654 #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 655 #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 656 #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 657 #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 658 #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 659 #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 660 #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 661 #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 662 #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 663 #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 664 #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 665 #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 666 #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 667 #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 668 #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 669 #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 670 #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 671 #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 672 #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 673 #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 674 #define MAC_PHYCFG2_50610_LED_MODES \ 675 (MAC_PHYCFG2_EMODE_MASK_50610 | \ 676 MAC_PHYCFG2_EMODE_COMP_50610 | \ 677 MAC_PHYCFG2_FMODE_MASK_50610 | \ 678 MAC_PHYCFG2_FMODE_COMP_50610 | \ 679 MAC_PHYCFG2_GMODE_MASK_50610 | \ 680 MAC_PHYCFG2_GMODE_COMP_50610 | \ 681 MAC_PHYCFG2_ACT_MASK_50610 | \ 682 MAC_PHYCFG2_ACT_COMP_50610 | \ 683 MAC_PHYCFG2_QUAL_MASK_50610 | \ 684 MAC_PHYCFG2_QUAL_COMP_50610) 685 #define MAC_PHYCFG2_AC131_LED_MODES \ 686 (MAC_PHYCFG2_EMODE_MASK_AC131 | \ 687 MAC_PHYCFG2_EMODE_COMP_AC131 | \ 688 MAC_PHYCFG2_FMODE_MASK_AC131 | \ 689 MAC_PHYCFG2_FMODE_COMP_AC131 | \ 690 MAC_PHYCFG2_GMODE_MASK_AC131 | \ 691 MAC_PHYCFG2_GMODE_COMP_AC131 | \ 692 MAC_PHYCFG2_ACT_MASK_AC131 | \ 693 MAC_PHYCFG2_ACT_COMP_AC131 | \ 694 MAC_PHYCFG2_QUAL_MASK_AC131 | \ 695 MAC_PHYCFG2_QUAL_COMP_AC131) 696 #define MAC_PHYCFG2_RTL8211C_LED_MODES \ 697 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ 698 MAC_PHYCFG2_EMODE_COMP_RT8211 | \ 699 MAC_PHYCFG2_FMODE_MASK_RT8211 | \ 700 MAC_PHYCFG2_FMODE_COMP_RT8211 | \ 701 MAC_PHYCFG2_GMODE_MASK_RT8211 | \ 702 MAC_PHYCFG2_GMODE_COMP_RT8211 | \ 703 MAC_PHYCFG2_ACT_MASK_RT8211 | \ 704 MAC_PHYCFG2_ACT_COMP_RT8211 | \ 705 MAC_PHYCFG2_QUAL_MASK_RT8211 | \ 706 MAC_PHYCFG2_QUAL_COMP_RT8211) 707 #define MAC_PHYCFG2_RTL8201E_LED_MODES \ 708 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ 709 MAC_PHYCFG2_EMODE_COMP_RT8201 | \ 710 MAC_PHYCFG2_FMODE_MASK_RT8201 | \ 711 MAC_PHYCFG2_FMODE_COMP_RT8201 | \ 712 MAC_PHYCFG2_GMODE_MASK_RT8201 | \ 713 MAC_PHYCFG2_GMODE_COMP_RT8201 | \ 714 MAC_PHYCFG2_ACT_MASK_RT8201 | \ 715 MAC_PHYCFG2_ACT_COMP_RT8201 | \ 716 MAC_PHYCFG2_QUAL_MASK_RT8201 | \ 717 MAC_PHYCFG2_QUAL_COMP_RT8201) 718 #define MAC_EXT_RGMII_MODE 0x000005a8 719 #define MAC_RGMII_MODE_TX_ENABLE 0x00000001 720 #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 721 #define MAC_RGMII_MODE_TX_RESET 0x00000004 722 #define MAC_RGMII_MODE_RX_INT_B 0x00000100 723 #define MAC_RGMII_MODE_RX_QUALITY 0x00000200 724 #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 725 #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 726 /* 0x5ac --> 0x5b0 unused */ 727 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 728 #define SERDES_RX_SIG_DETECT 0x00000400 729 #define SG_DIG_CTRL 0x000005b0 730 #define SG_DIG_USING_HW_AUTONEG 0x80000000 731 #define SG_DIG_SOFT_RESET 0x40000000 732 #define SG_DIG_DISABLE_LINKRDY 0x20000000 733 #define SG_DIG_CRC16_CLEAR_N 0x01000000 734 #define SG_DIG_EN10B 0x00800000 735 #define SG_DIG_CLEAR_STATUS 0x00400000 736 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 737 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000 738 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000 739 #define SG_DIG_SPEED_STATUS_SHIFT 18 740 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 741 #define SG_DIG_RESTART_AUTONEG 0x00010000 742 #define SG_DIG_FIBER_MODE 0x00008000 743 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000 744 #define SG_DIG_PAUSE_MASK 0x00001800 745 #define SG_DIG_PAUSE_CAP 0x00000800 746 #define SG_DIG_ASYM_PAUSE 0x00001000 747 #define SG_DIG_GBIC_ENABLE 0x00000400 748 #define SG_DIG_CHECK_END_ENABLE 0x00000200 749 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 750 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 751 #define SG_DIG_GMII_INPUT_SELECT 0x00000040 752 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020 753 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 754 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 755 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 756 #define SG_DIG_REMOTE_LOOPBACK 0x00000002 757 #define SG_DIG_LOOPBACK 0x00000001 758 #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ 759 SG_DIG_LOCAL_DUPLEX_STATUS | \ 760 SG_DIG_LOCAL_LINK_STATUS | \ 761 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ 762 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) 763 #define SG_DIG_STATUS 0x000005b4 764 #define SG_DIG_CRC16_BUS_MASK 0xffff0000 765 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 766 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 767 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 768 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 769 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 770 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 771 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 772 #define SG_DIG_IS_SERDES 0x00000100 773 #define SG_DIG_COMMA_DETECTOR 0x00000008 774 #define SG_DIG_MAC_ACK_STATUS 0x00000004 775 #define SG_DIG_AUTONEG_COMPLETE 0x00000002 776 #define SG_DIG_AUTONEG_ERROR 0x00000001 777 #define TG3_TX_TSTAMP_LSB 0x000005c0 778 #define TG3_TX_TSTAMP_MSB 0x000005c4 779 #define TG3_TSTAMP_MASK 0x7fffffffffffffffLL 780 /* 0x5c8 --> 0x600 unused */ 781 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 782 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 783 /* 0x624 --> 0x670 unused */ 784 785 #define MAC_RSS_INDIR_TBL_0 0x00000630 786 787 #define MAC_RSS_HASH_KEY_0 0x00000670 788 #define MAC_RSS_HASH_KEY_1 0x00000674 789 #define MAC_RSS_HASH_KEY_2 0x00000678 790 #define MAC_RSS_HASH_KEY_3 0x0000067c 791 #define MAC_RSS_HASH_KEY_4 0x00000680 792 #define MAC_RSS_HASH_KEY_5 0x00000684 793 #define MAC_RSS_HASH_KEY_6 0x00000688 794 #define MAC_RSS_HASH_KEY_7 0x0000068c 795 #define MAC_RSS_HASH_KEY_8 0x00000690 796 #define MAC_RSS_HASH_KEY_9 0x00000694 797 /* 0x698 --> 0x6b0 unused */ 798 799 #define TG3_RX_TSTAMP_LSB 0x000006b0 800 #define TG3_RX_TSTAMP_MSB 0x000006b4 801 /* 0x6b8 --> 0x6c8 unused */ 802 803 #define TG3_RX_PTP_CTL 0x000006c8 804 #define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001 805 #define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002 806 #define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004 807 #define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008 808 #define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 809 TG3_RX_PTP_CTL_DELAY_REQ) 810 #define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 811 TG3_RX_PTP_CTL_DELAY_REQ | \ 812 TG3_RX_PTP_CTL_PDLAY_REQ | \ 813 TG3_RX_PTP_CTL_PDLAY_RES) 814 #define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100 815 #define TG3_RX_PTP_CTL_DELAY_RES 0x00000200 816 #define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400 817 #define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800 818 #define TG3_RX_PTP_CTL_SIGNALING 0x00001000 819 #define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000 820 #define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000 821 #define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000 822 #define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \ 823 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN) 824 #define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000 825 #define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000 826 /* 0x6cc --> 0x800 unused */ 827 828 #define MAC_TX_STATS_OCTETS 0x00000800 829 #define MAC_TX_STATS_RESV1 0x00000804 830 #define MAC_TX_STATS_COLLISIONS 0x00000808 831 #define MAC_TX_STATS_XON_SENT 0x0000080c 832 #define MAC_TX_STATS_XOFF_SENT 0x00000810 833 #define MAC_TX_STATS_RESV2 0x00000814 834 #define MAC_TX_STATS_MAC_ERRORS 0x00000818 835 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 836 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 837 #define MAC_TX_STATS_DEFERRED 0x00000824 838 #define MAC_TX_STATS_RESV3 0x00000828 839 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 840 #define MAC_TX_STATS_LATE_COL 0x00000830 841 #define MAC_TX_STATS_RESV4_1 0x00000834 842 #define MAC_TX_STATS_RESV4_2 0x00000838 843 #define MAC_TX_STATS_RESV4_3 0x0000083c 844 #define MAC_TX_STATS_RESV4_4 0x00000840 845 #define MAC_TX_STATS_RESV4_5 0x00000844 846 #define MAC_TX_STATS_RESV4_6 0x00000848 847 #define MAC_TX_STATS_RESV4_7 0x0000084c 848 #define MAC_TX_STATS_RESV4_8 0x00000850 849 #define MAC_TX_STATS_RESV4_9 0x00000854 850 #define MAC_TX_STATS_RESV4_10 0x00000858 851 #define MAC_TX_STATS_RESV4_11 0x0000085c 852 #define MAC_TX_STATS_RESV4_12 0x00000860 853 #define MAC_TX_STATS_RESV4_13 0x00000864 854 #define MAC_TX_STATS_RESV4_14 0x00000868 855 #define MAC_TX_STATS_UCAST 0x0000086c 856 #define MAC_TX_STATS_MCAST 0x00000870 857 #define MAC_TX_STATS_BCAST 0x00000874 858 #define MAC_TX_STATS_RESV5_1 0x00000878 859 #define MAC_TX_STATS_RESV5_2 0x0000087c 860 #define MAC_RX_STATS_OCTETS 0x00000880 861 #define MAC_RX_STATS_RESV1 0x00000884 862 #define MAC_RX_STATS_FRAGMENTS 0x00000888 863 #define MAC_RX_STATS_UCAST 0x0000088c 864 #define MAC_RX_STATS_MCAST 0x00000890 865 #define MAC_RX_STATS_BCAST 0x00000894 866 #define MAC_RX_STATS_FCS_ERRORS 0x00000898 867 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 868 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 869 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 870 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 871 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 872 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 873 #define MAC_RX_STATS_JABBERS 0x000008b4 874 #define MAC_RX_STATS_UNDERSIZE 0x000008b8 875 /* 0x8bc --> 0xc00 unused */ 876 877 /* Send data initiator control registers */ 878 #define SNDDATAI_MODE 0x00000c00 879 #define SNDDATAI_MODE_RESET 0x00000001 880 #define SNDDATAI_MODE_ENABLE 0x00000002 881 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 882 #define SNDDATAI_STATUS 0x00000c04 883 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 884 #define SNDDATAI_STATSCTRL 0x00000c08 885 #define SNDDATAI_SCTRL_ENABLE 0x00000001 886 #define SNDDATAI_SCTRL_FASTUPD 0x00000002 887 #define SNDDATAI_SCTRL_CLEAR 0x00000004 888 #define SNDDATAI_SCTRL_FLUSH 0x00000008 889 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 890 #define SNDDATAI_STATSENAB 0x00000c0c 891 #define SNDDATAI_STATSINCMASK 0x00000c10 892 #define ISO_PKT_TX 0x00000c20 893 /* 0xc24 --> 0xc80 unused */ 894 #define SNDDATAI_COS_CNT_0 0x00000c80 895 #define SNDDATAI_COS_CNT_1 0x00000c84 896 #define SNDDATAI_COS_CNT_2 0x00000c88 897 #define SNDDATAI_COS_CNT_3 0x00000c8c 898 #define SNDDATAI_COS_CNT_4 0x00000c90 899 #define SNDDATAI_COS_CNT_5 0x00000c94 900 #define SNDDATAI_COS_CNT_6 0x00000c98 901 #define SNDDATAI_COS_CNT_7 0x00000c9c 902 #define SNDDATAI_COS_CNT_8 0x00000ca0 903 #define SNDDATAI_COS_CNT_9 0x00000ca4 904 #define SNDDATAI_COS_CNT_10 0x00000ca8 905 #define SNDDATAI_COS_CNT_11 0x00000cac 906 #define SNDDATAI_COS_CNT_12 0x00000cb0 907 #define SNDDATAI_COS_CNT_13 0x00000cb4 908 #define SNDDATAI_COS_CNT_14 0x00000cb8 909 #define SNDDATAI_COS_CNT_15 0x00000cbc 910 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 911 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 912 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 913 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 914 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 915 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 916 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 917 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 918 /* 0xce0 --> 0x1000 unused */ 919 920 /* Send data completion control registers */ 921 #define SNDDATAC_MODE 0x00001000 922 #define SNDDATAC_MODE_RESET 0x00000001 923 #define SNDDATAC_MODE_ENABLE 0x00000002 924 #define SNDDATAC_MODE_CDELAY 0x00000010 925 /* 0x1004 --> 0x1400 unused */ 926 927 /* Send BD ring selector */ 928 #define SNDBDS_MODE 0x00001400 929 #define SNDBDS_MODE_RESET 0x00000001 930 #define SNDBDS_MODE_ENABLE 0x00000002 931 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 932 #define SNDBDS_STATUS 0x00001404 933 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 934 #define SNDBDS_HWDIAG 0x00001408 935 /* 0x140c --> 0x1440 */ 936 #define SNDBDS_SEL_CON_IDX_0 0x00001440 937 #define SNDBDS_SEL_CON_IDX_1 0x00001444 938 #define SNDBDS_SEL_CON_IDX_2 0x00001448 939 #define SNDBDS_SEL_CON_IDX_3 0x0000144c 940 #define SNDBDS_SEL_CON_IDX_4 0x00001450 941 #define SNDBDS_SEL_CON_IDX_5 0x00001454 942 #define SNDBDS_SEL_CON_IDX_6 0x00001458 943 #define SNDBDS_SEL_CON_IDX_7 0x0000145c 944 #define SNDBDS_SEL_CON_IDX_8 0x00001460 945 #define SNDBDS_SEL_CON_IDX_9 0x00001464 946 #define SNDBDS_SEL_CON_IDX_10 0x00001468 947 #define SNDBDS_SEL_CON_IDX_11 0x0000146c 948 #define SNDBDS_SEL_CON_IDX_12 0x00001470 949 #define SNDBDS_SEL_CON_IDX_13 0x00001474 950 #define SNDBDS_SEL_CON_IDX_14 0x00001478 951 #define SNDBDS_SEL_CON_IDX_15 0x0000147c 952 /* 0x1480 --> 0x1800 unused */ 953 954 /* Send BD initiator control registers */ 955 #define SNDBDI_MODE 0x00001800 956 #define SNDBDI_MODE_RESET 0x00000001 957 #define SNDBDI_MODE_ENABLE 0x00000002 958 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 959 #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 960 #define SNDBDI_STATUS 0x00001804 961 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 962 #define SNDBDI_IN_PROD_IDX_0 0x00001808 963 #define SNDBDI_IN_PROD_IDX_1 0x0000180c 964 #define SNDBDI_IN_PROD_IDX_2 0x00001810 965 #define SNDBDI_IN_PROD_IDX_3 0x00001814 966 #define SNDBDI_IN_PROD_IDX_4 0x00001818 967 #define SNDBDI_IN_PROD_IDX_5 0x0000181c 968 #define SNDBDI_IN_PROD_IDX_6 0x00001820 969 #define SNDBDI_IN_PROD_IDX_7 0x00001824 970 #define SNDBDI_IN_PROD_IDX_8 0x00001828 971 #define SNDBDI_IN_PROD_IDX_9 0x0000182c 972 #define SNDBDI_IN_PROD_IDX_10 0x00001830 973 #define SNDBDI_IN_PROD_IDX_11 0x00001834 974 #define SNDBDI_IN_PROD_IDX_12 0x00001838 975 #define SNDBDI_IN_PROD_IDX_13 0x0000183c 976 #define SNDBDI_IN_PROD_IDX_14 0x00001840 977 #define SNDBDI_IN_PROD_IDX_15 0x00001844 978 /* 0x1848 --> 0x1c00 unused */ 979 980 /* Send BD completion control registers */ 981 #define SNDBDC_MODE 0x00001c00 982 #define SNDBDC_MODE_RESET 0x00000001 983 #define SNDBDC_MODE_ENABLE 0x00000002 984 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 985 /* 0x1c04 --> 0x2000 unused */ 986 987 /* Receive list placement control registers */ 988 #define RCVLPC_MODE 0x00002000 989 #define RCVLPC_MODE_RESET 0x00000001 990 #define RCVLPC_MODE_ENABLE 0x00000002 991 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 992 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 993 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 994 #define RCVLPC_STATUS 0x00002004 995 #define RCVLPC_STATUS_CLASS0 0x00000004 996 #define RCVLPC_STATUS_MAPOOR 0x00000008 997 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 998 #define RCVLPC_LOCK 0x00002008 999 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff 1000 #define RCVLPC_LOCK_REQ_SHIFT 0 1001 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 1002 #define RCVLPC_LOCK_GRANT_SHIFT 16 1003 #define RCVLPC_NON_EMPTY_BITS 0x0000200c 1004 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 1005 #define RCVLPC_CONFIG 0x00002010 1006 #define RCVLPC_STATSCTRL 0x00002014 1007 #define RCVLPC_STATSCTRL_ENABLE 0x00000001 1008 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 1009 #define RCVLPC_STATS_ENABLE 0x00002018 1010 #define RCVLPC_STATSENAB_ASF_FIX 0x00000002 1011 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 1012 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 1013 #define RCVLPC_STATS_INCMASK 0x0000201c 1014 /* 0x2020 --> 0x2100 unused */ 1015 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 1016 #define SELLST_TAIL 0x00000004 1017 #define SELLST_CONT 0x00000008 1018 #define SELLST_UNUSED 0x0000000c 1019 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 1020 #define RCVLPC_DROP_FILTER_CNT 0x00002240 1021 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 1022 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 1023 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c 1024 #define RCVLPC_IN_DISCARDS_CNT 0x00002250 1025 #define RCVLPC_IN_ERRORS_CNT 0x00002254 1026 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 1027 /* 0x225c --> 0x2400 unused */ 1028 1029 /* Receive Data and Receive BD Initiator Control */ 1030 #define RCVDBDI_MODE 0x00002400 1031 #define RCVDBDI_MODE_RESET 0x00000001 1032 #define RCVDBDI_MODE_ENABLE 0x00000002 1033 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 1034 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 1035 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 1036 #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000 1037 #define RCVDBDI_STATUS 0x00002404 1038 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 1039 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 1040 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 1041 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 1042 /* 0x240c --> 0x2440 unused */ 1043 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 1044 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 1045 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 1046 #define RCVDBDI_JUMBO_CON_IDX 0x00002470 1047 #define RCVDBDI_STD_CON_IDX 0x00002474 1048 #define RCVDBDI_MINI_CON_IDX 0x00002478 1049 /* 0x247c --> 0x2480 unused */ 1050 #define RCVDBDI_BD_PROD_IDX_0 0x00002480 1051 #define RCVDBDI_BD_PROD_IDX_1 0x00002484 1052 #define RCVDBDI_BD_PROD_IDX_2 0x00002488 1053 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c 1054 #define RCVDBDI_BD_PROD_IDX_4 0x00002490 1055 #define RCVDBDI_BD_PROD_IDX_5 0x00002494 1056 #define RCVDBDI_BD_PROD_IDX_6 0x00002498 1057 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c 1058 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 1059 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 1060 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 1061 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac 1062 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 1063 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 1064 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 1065 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc 1066 #define RCVDBDI_HWDIAG 0x000024c0 1067 /* 0x24c4 --> 0x2800 unused */ 1068 1069 /* Receive Data Completion Control */ 1070 #define RCVDCC_MODE 0x00002800 1071 #define RCVDCC_MODE_RESET 0x00000001 1072 #define RCVDCC_MODE_ENABLE 0x00000002 1073 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 1074 /* 0x2804 --> 0x2c00 unused */ 1075 1076 /* Receive BD Initiator Control Registers */ 1077 #define RCVBDI_MODE 0x00002c00 1078 #define RCVBDI_MODE_RESET 0x00000001 1079 #define RCVBDI_MODE_ENABLE 0x00000002 1080 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 1081 #define RCVBDI_STATUS 0x00002c04 1082 #define RCVBDI_STATUS_RCB_ATTN 0x00000004 1083 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 1084 #define RCVBDI_STD_PROD_IDX 0x00002c0c 1085 #define RCVBDI_MINI_PROD_IDX 0x00002c10 1086 #define RCVBDI_MINI_THRESH 0x00002c14 1087 #define RCVBDI_STD_THRESH 0x00002c18 1088 #define RCVBDI_JUMBO_THRESH 0x00002c1c 1089 /* 0x2c20 --> 0x2d00 unused */ 1090 1091 #define STD_REPLENISH_LWM 0x00002d00 1092 #define JMB_REPLENISH_LWM 0x00002d04 1093 /* 0x2d08 --> 0x3000 unused */ 1094 1095 /* Receive BD Completion Control Registers */ 1096 #define RCVCC_MODE 0x00003000 1097 #define RCVCC_MODE_RESET 0x00000001 1098 #define RCVCC_MODE_ENABLE 0x00000002 1099 #define RCVCC_MODE_ATTN_ENABLE 0x00000004 1100 #define RCVCC_STATUS 0x00003004 1101 #define RCVCC_STATUS_ERROR_ATTN 0x00000004 1102 #define RCVCC_JUMP_PROD_IDX 0x00003008 1103 #define RCVCC_STD_PROD_IDX 0x0000300c 1104 #define RCVCC_MINI_PROD_IDX 0x00003010 1105 /* 0x3014 --> 0x3400 unused */ 1106 1107 /* Receive list selector control registers */ 1108 #define RCVLSC_MODE 0x00003400 1109 #define RCVLSC_MODE_RESET 0x00000001 1110 #define RCVLSC_MODE_ENABLE 0x00000002 1111 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 1112 #define RCVLSC_STATUS 0x00003404 1113 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 1114 /* 0x3408 --> 0x3600 unused */ 1115 1116 #define TG3_CPMU_DRV_STATUS 0x0000344c 1117 1118 /* CPMU registers */ 1119 #define TG3_CPMU_CTRL 0x00003600 1120 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1121 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1122 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1123 #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1124 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604 1125 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 1126 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1127 /* 0x3608 --> 0x360c unused */ 1128 1129 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c 1130 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1131 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1132 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 1133 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 1134 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 1135 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1136 /* 0x3614 --> 0x361c unused */ 1137 1138 #define TG3_CPMU_HST_ACC 0x0000361c 1139 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 1140 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 1141 /* 0x3620 --> 0x3630 unused */ 1142 1143 #define TG3_CPMU_CLCK_ORIDE 0x00003624 1144 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1145 1146 #define TG3_CPMU_STATUS 0x0000362c 1147 #define TG3_CPMU_STATUS_FMSK_5717 0x20000000 1148 #define TG3_CPMU_STATUS_FMSK_5719 0xc0000000 1149 #define TG3_CPMU_STATUS_FSHFT_5719 30 1150 1151 #define TG3_CPMU_CLCK_STAT 0x00003630 1152 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1153 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1154 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1155 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1156 /* 0x3634 --> 0x365c unused */ 1157 1158 #define TG3_CPMU_MUTEX_REQ 0x0000365c 1159 #define CPMU_MUTEX_REQ_DRIVER 0x00001000 1160 #define TG3_CPMU_MUTEX_GNT 0x00003660 1161 #define CPMU_MUTEX_GNT_DRIVER 0x00001000 1162 #define TG3_CPMU_PHY_STRAP 0x00003664 1163 #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1164 #define TG3_CPMU_PADRNG_CTL 0x00003668 1165 #define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000 1166 /* 0x3664 --> 0x36b0 unused */ 1167 1168 #define TG3_CPMU_EEE_MODE 0x000036b0 1169 #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 1170 #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 1171 #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 1172 #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 1173 #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 1174 #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 1175 #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 1176 #define TG3_CPMU_EEE_DBTMR1 0x000036b4 1177 #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 1178 #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff 1179 #define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff 1180 #define TG3_CPMU_EEE_DBTMR2 0x000036b8 1181 #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000 1182 #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff 1183 #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc 1184 #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 1185 #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 1186 #define TG3_CPMU_EEE_LNKIDL_APE_TX_MT 0x00000002 1187 /* 0x36c0 --> 0x36d0 unused */ 1188 1189 #define TG3_CPMU_EEE_CTRL 0x000036d0 1190 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d 1191 #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384 1192 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8 1193 /* 0x36d4 --> 0x3800 unused */ 1194 1195 /* Mbuf cluster free registers */ 1196 #define MBFREE_MODE 0x00003800 1197 #define MBFREE_MODE_RESET 0x00000001 1198 #define MBFREE_MODE_ENABLE 0x00000002 1199 #define MBFREE_STATUS 0x00003804 1200 /* 0x3808 --> 0x3c00 unused */ 1201 1202 /* Host coalescing control registers */ 1203 #define HOSTCC_MODE 0x00003c00 1204 #define HOSTCC_MODE_RESET 0x00000001 1205 #define HOSTCC_MODE_ENABLE 0x00000002 1206 #define HOSTCC_MODE_ATTN 0x00000004 1207 #define HOSTCC_MODE_NOW 0x00000008 1208 #define HOSTCC_MODE_FULL_STATUS 0x00000000 1209 #define HOSTCC_MODE_64BYTE 0x00000080 1210 #define HOSTCC_MODE_32BYTE 0x00000100 1211 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 1212 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 1213 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 1214 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 1215 #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 1216 #define HOSTCC_STATUS 0x00003c04 1217 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 1218 #define HOSTCC_RXCOL_TICKS 0x00003c08 1219 #define LOW_RXCOL_TICKS 0x00000032 1220 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 1221 #define DEFAULT_RXCOL_TICKS 0x00000048 1222 #define HIGH_RXCOL_TICKS 0x00000096 1223 #define MAX_RXCOL_TICKS 0x000003ff 1224 #define HOSTCC_TXCOL_TICKS 0x00003c0c 1225 #define LOW_TXCOL_TICKS 0x00000096 1226 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 1227 #define DEFAULT_TXCOL_TICKS 0x0000012c 1228 #define HIGH_TXCOL_TICKS 0x00000145 1229 #define MAX_TXCOL_TICKS 0x000003ff 1230 #define HOSTCC_RXMAX_FRAMES 0x00003c10 1231 #define LOW_RXMAX_FRAMES 0x00000005 1232 #define DEFAULT_RXMAX_FRAMES 0x00000008 1233 #define HIGH_RXMAX_FRAMES 0x00000012 1234 #define MAX_RXMAX_FRAMES 0x000000ff 1235 #define HOSTCC_TXMAX_FRAMES 0x00003c14 1236 #define LOW_TXMAX_FRAMES 0x00000035 1237 #define DEFAULT_TXMAX_FRAMES 0x0000004b 1238 #define HIGH_TXMAX_FRAMES 0x00000052 1239 #define MAX_TXMAX_FRAMES 0x000000ff 1240 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 1241 #define DEFAULT_RXCOAL_TICK_INT 0x00000019 1242 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 1243 #define MAX_RXCOAL_TICK_INT 0x000003ff 1244 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 1245 #define DEFAULT_TXCOAL_TICK_INT 0x00000019 1246 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 1247 #define MAX_TXCOAL_TICK_INT 0x000003ff 1248 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 1249 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 1250 #define MAX_RXCOAL_MAXF_INT 0x000000ff 1251 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 1252 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 1253 #define MAX_TXCOAL_MAXF_INT 0x000000ff 1254 #define HOSTCC_STAT_COAL_TICKS 0x00003c28 1255 #define DEFAULT_STAT_COAL_TICKS 0x000f4240 1256 #define MAX_STAT_COAL_TICKS 0xd693d400 1257 #define MIN_STAT_COAL_TICKS 0x00000064 1258 /* 0x3c2c --> 0x3c30 unused */ 1259 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 1260 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 1261 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 1262 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 1263 #define HOSTCC_FLOW_ATTN 0x00003c48 1264 #define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040 1265 /* 0x3c4c --> 0x3c50 unused */ 1266 #define HOSTCC_JUMBO_CON_IDX 0x00003c50 1267 #define HOSTCC_STD_CON_IDX 0x00003c54 1268 #define HOSTCC_MINI_CON_IDX 0x00003c58 1269 /* 0x3c5c --> 0x3c80 unused */ 1270 #define HOSTCC_RET_PROD_IDX_0 0x00003c80 1271 #define HOSTCC_RET_PROD_IDX_1 0x00003c84 1272 #define HOSTCC_RET_PROD_IDX_2 0x00003c88 1273 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c 1274 #define HOSTCC_RET_PROD_IDX_4 0x00003c90 1275 #define HOSTCC_RET_PROD_IDX_5 0x00003c94 1276 #define HOSTCC_RET_PROD_IDX_6 0x00003c98 1277 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c 1278 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 1279 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 1280 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 1281 #define HOSTCC_RET_PROD_IDX_11 0x00003cac 1282 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 1283 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 1284 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 1285 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc 1286 #define HOSTCC_SND_CON_IDX_0 0x00003cc0 1287 #define HOSTCC_SND_CON_IDX_1 0x00003cc4 1288 #define HOSTCC_SND_CON_IDX_2 0x00003cc8 1289 #define HOSTCC_SND_CON_IDX_3 0x00003ccc 1290 #define HOSTCC_SND_CON_IDX_4 0x00003cd0 1291 #define HOSTCC_SND_CON_IDX_5 0x00003cd4 1292 #define HOSTCC_SND_CON_IDX_6 0x00003cd8 1293 #define HOSTCC_SND_CON_IDX_7 0x00003cdc 1294 #define HOSTCC_SND_CON_IDX_8 0x00003ce0 1295 #define HOSTCC_SND_CON_IDX_9 0x00003ce4 1296 #define HOSTCC_SND_CON_IDX_10 0x00003ce8 1297 #define HOSTCC_SND_CON_IDX_11 0x00003cec 1298 #define HOSTCC_SND_CON_IDX_12 0x00003cf0 1299 #define HOSTCC_SND_CON_IDX_13 0x00003cf4 1300 #define HOSTCC_SND_CON_IDX_14 0x00003cf8 1301 #define HOSTCC_SND_CON_IDX_15 0x00003cfc 1302 #define HOSTCC_STATBLCK_RING1 0x00003d00 1303 /* 0x3d00 --> 0x3d80 unused */ 1304 1305 #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80 1306 #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84 1307 #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88 1308 #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c 1309 #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90 1310 #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94 1311 /* 0x3d98 --> 0x4000 unused */ 1312 1313 /* Memory arbiter control registers */ 1314 #define MEMARB_MODE 0x00004000 1315 #define MEMARB_MODE_RESET 0x00000001 1316 #define MEMARB_MODE_ENABLE 0x00000002 1317 #define MEMARB_STATUS 0x00004004 1318 #define MEMARB_TRAP_ADDR_LOW 0x00004008 1319 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c 1320 /* 0x4010 --> 0x4400 unused */ 1321 1322 /* Buffer manager control registers */ 1323 #define BUFMGR_MODE 0x00004400 1324 #define BUFMGR_MODE_RESET 0x00000001 1325 #define BUFMGR_MODE_ENABLE 0x00000002 1326 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 1327 #define BUFMGR_MODE_BM_TEST 0x00000008 1328 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 1329 #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000 1330 #define BUFMGR_STATUS 0x00004404 1331 #define BUFMGR_STATUS_ERROR 0x00000004 1332 #define BUFMGR_STATUS_MBLOW 0x00000010 1333 #define BUFMGR_MB_POOL_ADDR 0x00004408 1334 #define BUFMGR_MB_POOL_SIZE 0x0000440c 1335 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 1336 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1337 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1338 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1339 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 1340 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1341 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1342 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1343 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 1344 #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a 1345 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1346 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b 1347 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e 1348 #define BUFMGR_MB_HIGH_WATER 0x00004418 1349 #define DEFAULT_MB_HIGH_WATER 0x00000060 1350 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1351 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010 1352 #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0 1353 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1354 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 1355 #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea 1356 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1357 #define BUFMGR_MB_ALLOC_BIT 0x10000000 1358 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1359 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1360 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1361 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1362 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1363 #define BUFMGR_DMA_LOW_WATER 0x00004434 1364 #define DEFAULT_DMA_LOW_WATER 0x00000005 1365 #define BUFMGR_DMA_HIGH_WATER 0x00004438 1366 #define DEFAULT_DMA_HIGH_WATER 0x0000000a 1367 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1368 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1369 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1370 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1371 #define BUFMGR_HWDIAG_0 0x0000444c 1372 #define BUFMGR_HWDIAG_1 0x00004450 1373 #define BUFMGR_HWDIAG_2 0x00004454 1374 /* 0x4458 --> 0x4800 unused */ 1375 1376 /* Read DMA control registers */ 1377 #define RDMAC_MODE 0x00004800 1378 #define RDMAC_MODE_RESET 0x00000001 1379 #define RDMAC_MODE_ENABLE 0x00000002 1380 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1381 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1382 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1383 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1384 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1385 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1386 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1387 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1388 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1389 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 1390 #define RDMAC_MODE_SPLIT_RESET 0x00001000 1391 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 1392 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 1393 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1394 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 1395 #define RDMAC_MODE_JMB_2K_MMRR 0x00800000 1396 #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000 1397 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000 1398 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000 1399 #define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000 1400 #define RDMAC_STATUS 0x00004804 1401 #define RDMAC_STATUS_TGTABORT 0x00000004 1402 #define RDMAC_STATUS_MSTABORT 0x00000008 1403 #define RDMAC_STATUS_PARITYERR 0x00000010 1404 #define RDMAC_STATUS_ADDROFLOW 0x00000020 1405 #define RDMAC_STATUS_FIFOOFLOW 0x00000040 1406 #define RDMAC_STATUS_FIFOURUN 0x00000080 1407 #define RDMAC_STATUS_FIFOOREAD 0x00000100 1408 #define RDMAC_STATUS_LNGREAD 0x00000200 1409 /* 0x4808 --> 0x4890 unused */ 1410 1411 #define TG3_RDMA_RSRVCTRL_REG2 0x00004890 1412 #define TG3_LSO_RD_DMA_CRPTEN_CTRL2 0x000048a0 1413 1414 #define TG3_RDMA_RSRVCTRL_REG 0x00004900 1415 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1416 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00 1417 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0 1418 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000 1419 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000 1420 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1421 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 1422 /* 0x4904 --> 0x4910 unused */ 1423 1424 #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 1425 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1426 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 1427 #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 0x02000000 1428 #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 0x00200000 1429 /* 0x4914 --> 0x4be0 unused */ 1430 1431 #define TG3_NUM_RDMA_CHANNELS 4 1432 #define TG3_RDMA_LENGTH 0x00004be0 1433 1434 /* Write DMA control registers */ 1435 #define WDMAC_MODE 0x00004c00 1436 #define WDMAC_MODE_RESET 0x00000001 1437 #define WDMAC_MODE_ENABLE 0x00000002 1438 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1439 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1440 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1441 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1442 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1443 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1444 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1445 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1446 #define WDMAC_MODE_RX_ACCEL 0x00000400 1447 #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 1448 #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 1449 #define WDMAC_STATUS 0x00004c04 1450 #define WDMAC_STATUS_TGTABORT 0x00000004 1451 #define WDMAC_STATUS_MSTABORT 0x00000008 1452 #define WDMAC_STATUS_PARITYERR 0x00000010 1453 #define WDMAC_STATUS_ADDROFLOW 0x00000020 1454 #define WDMAC_STATUS_FIFOOFLOW 0x00000040 1455 #define WDMAC_STATUS_FIFOURUN 0x00000080 1456 #define WDMAC_STATUS_FIFOOREAD 0x00000100 1457 #define WDMAC_STATUS_LNGREAD 0x00000200 1458 /* 0x4c08 --> 0x5000 unused */ 1459 1460 /* Per-cpu register offsets (arm9) */ 1461 #define CPU_MODE 0x00000000 1462 #define CPU_MODE_RESET 0x00000001 1463 #define CPU_MODE_HALT 0x00000400 1464 #define CPU_STATE 0x00000004 1465 #define CPU_EVTMASK 0x00000008 1466 /* 0xc --> 0x1c reserved */ 1467 #define CPU_PC 0x0000001c 1468 #define CPU_INSN 0x00000020 1469 #define CPU_SPAD_UFLOW 0x00000024 1470 #define CPU_WDOG_CLEAR 0x00000028 1471 #define CPU_WDOG_VECTOR 0x0000002c 1472 #define CPU_WDOG_PC 0x00000030 1473 #define CPU_HW_BP 0x00000034 1474 /* 0x38 --> 0x44 unused */ 1475 #define CPU_WDOG_SAVED_STATE 0x00000044 1476 #define CPU_LAST_BRANCH_ADDR 0x00000048 1477 #define CPU_SPAD_UFLOW_SET 0x0000004c 1478 /* 0x50 --> 0x200 unused */ 1479 #define CPU_R0 0x00000200 1480 #define CPU_R1 0x00000204 1481 #define CPU_R2 0x00000208 1482 #define CPU_R3 0x0000020c 1483 #define CPU_R4 0x00000210 1484 #define CPU_R5 0x00000214 1485 #define CPU_R6 0x00000218 1486 #define CPU_R7 0x0000021c 1487 #define CPU_R8 0x00000220 1488 #define CPU_R9 0x00000224 1489 #define CPU_R10 0x00000228 1490 #define CPU_R11 0x0000022c 1491 #define CPU_R12 0x00000230 1492 #define CPU_R13 0x00000234 1493 #define CPU_R14 0x00000238 1494 #define CPU_R15 0x0000023c 1495 #define CPU_R16 0x00000240 1496 #define CPU_R17 0x00000244 1497 #define CPU_R18 0x00000248 1498 #define CPU_R19 0x0000024c 1499 #define CPU_R20 0x00000250 1500 #define CPU_R21 0x00000254 1501 #define CPU_R22 0x00000258 1502 #define CPU_R23 0x0000025c 1503 #define CPU_R24 0x00000260 1504 #define CPU_R25 0x00000264 1505 #define CPU_R26 0x00000268 1506 #define CPU_R27 0x0000026c 1507 #define CPU_R28 0x00000270 1508 #define CPU_R29 0x00000274 1509 #define CPU_R30 0x00000278 1510 #define CPU_R31 0x0000027c 1511 /* 0x280 --> 0x400 unused */ 1512 1513 #define RX_CPU_BASE 0x00005000 1514 #define RX_CPU_MODE 0x00005000 1515 #define RX_CPU_STATE 0x00005004 1516 #define RX_CPU_PGMCTR 0x0000501c 1517 #define RX_CPU_HWBKPT 0x00005034 1518 #define TX_CPU_BASE 0x00005400 1519 #define TX_CPU_MODE 0x00005400 1520 #define TX_CPU_STATE 0x00005404 1521 #define TX_CPU_PGMCTR 0x0000541c 1522 1523 #define VCPU_STATUS 0x00005100 1524 #define VCPU_STATUS_INIT_DONE 0x04000000 1525 #define VCPU_STATUS_DRV_RESET 0x08000000 1526 1527 #define VCPU_CFGSHDW 0x00005104 1528 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 1529 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 1530 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 1531 1532 /* Mailboxes */ 1533 #define GRCMBOX_BASE 0x00005600 1534 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1535 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1536 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1537 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1538 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1539 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1540 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1541 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1542 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1543 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1544 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1545 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1546 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1547 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1548 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1549 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1550 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1551 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1552 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1553 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1554 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1555 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1556 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1557 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1558 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1559 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1560 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1561 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1562 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1563 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1564 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1565 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1566 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1567 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1568 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1569 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1570 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1571 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1572 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1573 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1574 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1575 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1576 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1577 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1578 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1579 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1580 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1581 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1582 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1583 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1584 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1585 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1586 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1587 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1588 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1589 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1590 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1591 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1592 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1593 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1594 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1595 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1596 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1597 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1598 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1599 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1600 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1601 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1602 /* 0x5a10 --> 0x5c00 */ 1603 1604 /* Flow Through queues */ 1605 #define FTQ_RESET 0x00005c00 1606 /* 0x5c04 --> 0x5c10 unused */ 1607 #define FTQ_DMA_NORM_READ_CTL 0x00005c10 1608 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1609 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1610 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1611 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1612 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1613 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1614 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1615 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1616 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1617 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1618 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1619 #define FTQ_SEND_BD_COMP_CTL 0x00005c40 1620 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1621 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1622 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1623 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1624 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1625 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1626 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1627 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1628 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1629 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1630 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1631 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1632 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1633 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1634 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1635 #define FTQ_SWTYPE1_CTL 0x00005c80 1636 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1637 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1638 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1639 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1640 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1641 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1642 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1643 #define FTQ_HOST_COAL_CTL 0x00005ca0 1644 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1645 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1646 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1647 #define FTQ_MAC_TX_CTL 0x00005cb0 1648 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1649 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1650 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1651 #define FTQ_MB_FREE_CTL 0x00005cc0 1652 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1653 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1654 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1655 #define FTQ_RCVBD_COMP_CTL 0x00005cd0 1656 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1657 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1658 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1659 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1660 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1661 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1662 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1663 #define FTQ_RCVDATA_INI_CTL 0x00005cf0 1664 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1665 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1666 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1667 #define FTQ_RCVDATA_COMP_CTL 0x00005d00 1668 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1669 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1670 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1671 #define FTQ_SWTYPE2_CTL 0x00005d10 1672 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1673 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1674 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1675 /* 0x5d20 --> 0x6000 unused */ 1676 1677 /* Message signaled interrupt registers */ 1678 #define MSGINT_MODE 0x00006000 1679 #define MSGINT_MODE_RESET 0x00000001 1680 #define MSGINT_MODE_ENABLE 0x00000002 1681 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020 1682 #define MSGINT_MODE_MULTIVEC_EN 0x00000080 1683 #define MSGINT_STATUS 0x00006004 1684 #define MSGINT_STATUS_MSI_REQ 0x00000001 1685 #define MSGINT_FIFO 0x00006008 1686 /* 0x600c --> 0x6400 unused */ 1687 1688 /* DMA completion registers */ 1689 #define DMAC_MODE 0x00006400 1690 #define DMAC_MODE_RESET 0x00000001 1691 #define DMAC_MODE_ENABLE 0x00000002 1692 /* 0x6404 --> 0x6800 unused */ 1693 1694 /* GRC registers */ 1695 #define GRC_MODE 0x00006800 1696 #define GRC_MODE_UPD_ON_COAL 0x00000001 1697 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1698 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1699 #define GRC_MODE_BSWAP_DATA 0x00000010 1700 #define GRC_MODE_WSWAP_DATA 0x00000020 1701 #define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040 1702 #define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080 1703 #define GRC_MODE_SPLITHDR 0x00000100 1704 #define GRC_MODE_NOFRM_CRACKING 0x00000200 1705 #define GRC_MODE_INCL_CRC 0x00000400 1706 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1707 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1708 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1709 #define GRC_MODE_FORCE_PCI32BIT 0x00008000 1710 #define GRC_MODE_B2HRX_ENABLE 0x00008000 1711 #define GRC_MODE_HOST_STACKUP 0x00010000 1712 #define GRC_MODE_HOST_SENDBDS 0x00020000 1713 #define GRC_MODE_HTX2B_ENABLE 0x00040000 1714 #define GRC_MODE_TIME_SYNC_ENABLE 0x00080000 1715 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1716 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1717 #define GRC_MODE_PCIE_TL_SEL 0x00000000 1718 #define GRC_MODE_PCIE_PL_SEL 0x00400000 1719 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1720 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1721 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1722 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1723 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1724 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1725 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1726 #define GRC_MODE_PCIE_DL_SEL 0x20000000 1727 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1728 #define GRC_MODE_PCIE_HI_1K_EN 0x80000000 1729 #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \ 1730 GRC_MODE_PCIE_PL_SEL | \ 1731 GRC_MODE_PCIE_DL_SEL | \ 1732 GRC_MODE_PCIE_HI_1K_EN) 1733 #define GRC_MISC_CFG 0x00006804 1734 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1735 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1736 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1737 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1738 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1739 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1740 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1741 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1742 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1743 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1744 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1745 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1746 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1747 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1748 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1749 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 1750 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1751 #define GRC_LOCAL_CTRL 0x00006808 1752 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1753 #define GRC_LCLCTRL_CLEARINT 0x00000002 1754 #define GRC_LCLCTRL_SETINT 0x00000004 1755 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1756 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1757 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1758 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1759 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 1760 #define GRC_LCLCTRL_GPIO_OE3 0x00000040 1761 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 1762 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1763 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1764 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1765 #define GRC_LCLCTRL_GPIO_OE0 0x00000800 1766 #define GRC_LCLCTRL_GPIO_OE1 0x00001000 1767 #define GRC_LCLCTRL_GPIO_OE2 0x00002000 1768 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1769 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1770 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1771 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1772 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1773 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1774 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1775 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1776 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1777 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1778 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1779 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1780 #define GRC_LCLCTRL_BANK_SELECT 0x00200000 1781 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1782 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1783 #define GRC_TIMER 0x0000680c 1784 #define GRC_RX_CPU_EVENT 0x00006810 1785 #define GRC_RX_CPU_DRIVER_EVENT 0x00004000 1786 #define GRC_RX_TIMER_REF 0x00006814 1787 #define GRC_RX_CPU_SEM 0x00006818 1788 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1789 #define GRC_TX_CPU_EVENT 0x00006820 1790 #define GRC_TX_TIMER_REF 0x00006824 1791 #define GRC_TX_CPU_SEM 0x00006828 1792 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1793 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1794 #define GRC_EEPROM_ADDR 0x00006838 1795 #define EEPROM_ADDR_WRITE 0x00000000 1796 #define EEPROM_ADDR_READ 0x80000000 1797 #define EEPROM_ADDR_COMPLETE 0x40000000 1798 #define EEPROM_ADDR_FSM_RESET 0x20000000 1799 #define EEPROM_ADDR_DEVID_MASK 0x1c000000 1800 #define EEPROM_ADDR_DEVID_SHIFT 26 1801 #define EEPROM_ADDR_START 0x02000000 1802 #define EEPROM_ADDR_CLKPERD_SHIFT 16 1803 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1804 #define EEPROM_ADDR_ADDR_SHIFT 0 1805 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1806 #define EEPROM_CHIP_SIZE (64 * 1024) 1807 #define GRC_EEPROM_DATA 0x0000683c 1808 #define GRC_EEPROM_CTRL 0x00006840 1809 #define GRC_MDI_CTRL 0x00006844 1810 #define GRC_SEEPROM_DELAY 0x00006848 1811 /* 0x684c --> 0x6890 unused */ 1812 #define GRC_VCPU_EXT_CTRL 0x00006890 1813 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1814 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1815 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ 1816 1817 #define TG3_EAV_REF_CLCK_LSB 0x00006900 1818 #define TG3_EAV_REF_CLCK_MSB 0x00006904 1819 #define TG3_EAV_REF_CLCK_CTL 0x00006908 1820 #define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002 1821 #define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004 1822 #define TG3_EAV_CTL_TSYNC_GPIO_MASK (0x3 << 16) 1823 #define TG3_EAV_CTL_TSYNC_WDOG0 (1 << 17) 1824 1825 #define TG3_EAV_WATCHDOG0_LSB 0x00006918 1826 #define TG3_EAV_WATCHDOG0_MSB 0x0000691c 1827 #define TG3_EAV_WATCHDOG0_EN (1 << 31) 1828 #define TG3_EAV_WATCHDOG_MSB_MASK 0x7fffffff 1829 1830 #define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928 1831 #define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31) 1832 #define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30) 1833 1834 #define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff 1835 1836 /* 0x692c --> 0x7000 unused */ 1837 1838 /* NVRAM Control registers */ 1839 #define NVRAM_CMD 0x00007000 1840 #define NVRAM_CMD_RESET 0x00000001 1841 #define NVRAM_CMD_DONE 0x00000008 1842 #define NVRAM_CMD_GO 0x00000010 1843 #define NVRAM_CMD_WR 0x00000020 1844 #define NVRAM_CMD_RD 0x00000000 1845 #define NVRAM_CMD_ERASE 0x00000040 1846 #define NVRAM_CMD_FIRST 0x00000080 1847 #define NVRAM_CMD_LAST 0x00000100 1848 #define NVRAM_CMD_WREN 0x00010000 1849 #define NVRAM_CMD_WRDI 0x00020000 1850 #define NVRAM_STAT 0x00007004 1851 #define NVRAM_WRDATA 0x00007008 1852 #define NVRAM_ADDR 0x0000700c 1853 #define NVRAM_ADDR_MSK 0x00ffffff 1854 #define NVRAM_RDDATA 0x00007010 1855 #define NVRAM_CFG1 0x00007014 1856 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1857 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1858 #define NVRAM_CFG1_PASS_THRU 0x00000004 1859 #define NVRAM_CFG1_STATUS_BITS 0x00000070 1860 #define NVRAM_CFG1_BIT_BANG 0x00000008 1861 #define NVRAM_CFG1_FLASH_SIZE 0x02000000 1862 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1863 #define NVRAM_CFG1_VENDOR_MASK 0x03000003 1864 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 1865 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1866 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 1867 #define FLASH_VENDOR_ST 0x03000001 1868 #define FLASH_VENDOR_SAIFUN 0x01000003 1869 #define FLASH_VENDOR_SST_SMALL 0x00000001 1870 #define FLASH_VENDOR_SST_LARGE 0x02000001 1871 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 1872 #define NVRAM_CFG1_5762VENDOR_MASK 0x03e00003 1873 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 1874 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 1875 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1876 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 1877 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 1878 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 1879 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 1880 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 1881 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 1882 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 1883 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 1884 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 1885 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 1886 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 1887 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1888 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1889 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1890 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 1891 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 1892 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 1893 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 1894 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 1895 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 1896 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 1897 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 1898 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 1899 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 1900 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 1901 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 1902 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 1903 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1904 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1905 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1906 #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 1907 #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 1908 #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 1909 #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 1910 #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 1911 #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 1912 #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 1913 #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 1914 #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 1915 #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 1916 #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 1917 #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 1918 #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 1919 #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 1920 #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 1921 #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 1922 #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 1923 #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 1924 #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 1925 #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 1926 #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 1927 #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 1928 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 1929 #define FLASH_5717VENDOR_ST_25USPT 0x03400002 1930 #define FLASH_5717VENDOR_ST_45USPT 0x03400001 1931 #define FLASH_5720_EEPROM_HD 0x00000001 1932 #define FLASH_5720_EEPROM_LD 0x00000003 1933 #define FLASH_5762_EEPROM_HD 0x02000001 1934 #define FLASH_5762_EEPROM_LD 0x02000003 1935 #define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000 1936 #define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002 1937 #define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001 1938 #define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003 1939 #define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000 1940 #define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002 1941 #define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001 1942 #define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003 1943 #define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000 1944 #define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002 1945 #define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001 1946 #define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003 1947 #define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000 1948 #define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002 1949 #define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001 1950 #define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000 1951 #define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002 1952 #define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001 1953 #define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003 1954 #define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000 1955 #define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002 1956 #define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001 1957 #define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003 1958 #define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000 1959 #define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002 1960 #define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001 1961 #define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003 1962 #define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000 1963 #define FLASH_5720VENDOR_ST_25USPT 0x03c00002 1964 #define FLASH_5720VENDOR_ST_45USPT 0x03c00001 1965 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1966 #define FLASH_5752PAGE_SIZE_256 0x00000000 1967 #define FLASH_5752PAGE_SIZE_512 0x10000000 1968 #define FLASH_5752PAGE_SIZE_1K 0x20000000 1969 #define FLASH_5752PAGE_SIZE_2K 0x30000000 1970 #define FLASH_5752PAGE_SIZE_4K 0x40000000 1971 #define FLASH_5752PAGE_SIZE_264 0x50000000 1972 #define FLASH_5752PAGE_SIZE_528 0x60000000 1973 #define NVRAM_CFG2 0x00007018 1974 #define NVRAM_CFG3 0x0000701c 1975 #define NVRAM_SWARB 0x00007020 1976 #define SWARB_REQ_SET0 0x00000001 1977 #define SWARB_REQ_SET1 0x00000002 1978 #define SWARB_REQ_SET2 0x00000004 1979 #define SWARB_REQ_SET3 0x00000008 1980 #define SWARB_REQ_CLR0 0x00000010 1981 #define SWARB_REQ_CLR1 0x00000020 1982 #define SWARB_REQ_CLR2 0x00000040 1983 #define SWARB_REQ_CLR3 0x00000080 1984 #define SWARB_GNT0 0x00000100 1985 #define SWARB_GNT1 0x00000200 1986 #define SWARB_GNT2 0x00000400 1987 #define SWARB_GNT3 0x00000800 1988 #define SWARB_REQ0 0x00001000 1989 #define SWARB_REQ1 0x00002000 1990 #define SWARB_REQ2 0x00004000 1991 #define SWARB_REQ3 0x00008000 1992 #define NVRAM_ACCESS 0x00007024 1993 #define ACCESS_ENABLE 0x00000001 1994 #define ACCESS_WR_ENABLE 0x00000002 1995 #define NVRAM_WRITE1 0x00007028 1996 /* 0x702c unused */ 1997 1998 #define NVRAM_ADDR_LOCKOUT 0x00007030 1999 /* 0x7034 --> 0x7500 unused */ 2000 2001 #define OTP_MODE 0x00007500 2002 #define OTP_MODE_OTP_THRU_GRC 0x00000001 2003 #define OTP_CTRL 0x00007504 2004 #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 2005 #define OTP_CTRL_OTP_CMD_READ 0x00000000 2006 #define OTP_CTRL_OTP_CMD_INIT 0x00000008 2007 #define OTP_CTRL_OTP_CMD_START 0x00000001 2008 #define OTP_STATUS 0x00007508 2009 #define OTP_STATUS_CMD_DONE 0x00000001 2010 #define OTP_ADDRESS 0x0000750c 2011 #define OTP_ADDRESS_MAGIC1 0x000000a0 2012 #define OTP_ADDRESS_MAGIC2 0x00000080 2013 /* 0x7510 unused */ 2014 2015 #define OTP_READ_DATA 0x00007514 2016 /* 0x7518 --> 0x7c04 unused */ 2017 2018 #define PCIE_TRANSACTION_CFG 0x00007c04 2019 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 2020 #define PCIE_TRANS_CFG_LOM 0x00000020 2021 /* 0x7c08 --> 0x7d28 unused */ 2022 2023 #define PCIE_PWR_MGMT_THRESH 0x00007d28 2024 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 2025 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 2026 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 2027 /* 0x7d2c --> 0x7d54 unused */ 2028 2029 #define TG3_PCIE_LNKCTL 0x00007d54 2030 #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 2031 #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 2032 /* 0x7d58 --> 0x7e70 unused */ 2033 2034 #define TG3_PCIE_PHY_TSTCTL 0x00007e2c 2035 #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040 2036 #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 2037 2038 #define TG3_PCIE_EIDLE_DELAY 0x00007e70 2039 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f 2040 #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c 2041 /* 0x7e74 --> 0x8000 unused */ 2042 2043 2044 /* Alternate PCIE definitions */ 2045 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 2046 #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c 2047 #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff 2048 #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c 2049 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 2050 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 2051 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 2052 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 2053 2054 #define TG3_REG_BLK_SIZE 0x00008000 2055 2056 /* OTP bit definitions */ 2057 #define TG3_OTP_AGCTGT_MASK 0x000000e0 2058 #define TG3_OTP_AGCTGT_SHIFT 1 2059 #define TG3_OTP_HPFFLTR_MASK 0x00000300 2060 #define TG3_OTP_HPFFLTR_SHIFT 1 2061 #define TG3_OTP_HPFOVER_MASK 0x00000400 2062 #define TG3_OTP_HPFOVER_SHIFT 1 2063 #define TG3_OTP_LPFDIS_MASK 0x00000800 2064 #define TG3_OTP_LPFDIS_SHIFT 11 2065 #define TG3_OTP_VDAC_MASK 0xff000000 2066 #define TG3_OTP_VDAC_SHIFT 24 2067 #define TG3_OTP_10BTAMP_MASK 0x0000f000 2068 #define TG3_OTP_10BTAMP_SHIFT 8 2069 #define TG3_OTP_ROFF_MASK 0x00e00000 2070 #define TG3_OTP_ROFF_SHIFT 11 2071 #define TG3_OTP_RCOFF_MASK 0x001c0000 2072 #define TG3_OTP_RCOFF_SHIFT 16 2073 2074 #define TG3_OTP_DEFAULT 0x286c1640 2075 2076 2077 /* Hardware Legacy NVRAM layout */ 2078 #define TG3_NVM_VPD_OFF 0x100 2079 #define TG3_NVM_VPD_LEN 256 2080 2081 /* Hardware Selfboot NVRAM layout */ 2082 #define TG3_NVM_HWSB_CFG1 0x00000004 2083 #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 2084 #define TG3_NVM_HWSB_CFG1_MAJSFT 27 2085 #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 2086 #define TG3_NVM_HWSB_CFG1_MINSFT 22 2087 2088 #define TG3_EEPROM_MAGIC 0x669955aa 2089 #define TG3_EEPROM_MAGIC_FW 0xa5000000 2090 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 2091 #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 2092 #define TG3_EEPROM_SB_FORMAT_1 0x00200000 2093 #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 2094 #define TG3_EEPROM_SB_REVISION_0 0x00000000 2095 #define TG3_EEPROM_SB_REVISION_2 0x00020000 2096 #define TG3_EEPROM_SB_REVISION_3 0x00030000 2097 #define TG3_EEPROM_SB_REVISION_4 0x00040000 2098 #define TG3_EEPROM_SB_REVISION_5 0x00050000 2099 #define TG3_EEPROM_SB_REVISION_6 0x00060000 2100 #define TG3_EEPROM_MAGIC_HW 0xabcd 2101 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff 2102 2103 #define TG3_NVM_DIR_START 0x18 2104 #define TG3_NVM_DIR_END 0x78 2105 #define TG3_NVM_DIRENT_SIZE 0xc 2106 #define TG3_NVM_DIRTYPE_SHIFT 24 2107 #define TG3_NVM_DIRTYPE_LENMSK 0x003fffff 2108 #define TG3_NVM_DIRTYPE_ASFINI 1 2109 #define TG3_NVM_DIRTYPE_EXTVPD 20 2110 #define TG3_NVM_PTREV_BCVER 0x94 2111 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00 2112 #define TG3_NVM_BCVER_MAJSFT 8 2113 #define TG3_NVM_BCVER_MINMSK 0x000000ff 2114 2115 #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 2116 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 2117 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2118 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 2119 #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c 2120 #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 2121 #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c 2122 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 2123 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 2124 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff 2125 #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 2126 #define TG3_EEPROM_SB_EDH_BLD_SHFT 11 2127 2128 2129 /* 32K Window into NIC internal memory */ 2130 #define NIC_SRAM_WIN_BASE 0x00008000 2131 2132 /* Offsets into first 32k of NIC internal memory. */ 2133 #define NIC_SRAM_PAGE_ZERO 0x00000000 2134 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 2135 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 2136 #define NIC_SRAM_STATS_BLK 0x00000300 2137 #define NIC_SRAM_STATUS_BLK 0x00000b00 2138 2139 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 2140 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 2141 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 2142 2143 #define NIC_SRAM_DATA_SIG 0x00000b54 2144 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 2145 2146 #define NIC_SRAM_DATA_CFG 0x00000b58 2147 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 2148 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 2149 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 2150 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 2151 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 2152 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 2153 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 2154 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 2155 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 2156 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 2157 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 2158 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 2159 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 2160 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 2161 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 2162 2163 #define NIC_SRAM_DATA_VER 0x00000b5c 2164 #define NIC_SRAM_DATA_VER_SHIFT 16 2165 2166 #define NIC_SRAM_DATA_PHY_ID 0x00000b74 2167 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 2168 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 2169 2170 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 2171 #define FWCMD_NICDRV_ALIVE 0x00000001 2172 #define FWCMD_NICDRV_PAUSE_FW 0x00000002 2173 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 2174 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 2175 #define FWCMD_NICDRV_FIX_DMAR 0x00000005 2176 #define FWCMD_NICDRV_FIX_DMAW 0x00000006 2177 #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c 2178 #define FWCMD_NICDRV_ALIVE2 0x0000000d 2179 #define FWCMD_NICDRV_ALIVE3 0x0000000e 2180 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 2181 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 2182 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 2183 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 2184 #define DRV_STATE_START 0x00000001 2185 #define DRV_STATE_START_DONE 0x80000001 2186 #define DRV_STATE_UNLOAD 0x00000002 2187 #define DRV_STATE_UNLOAD_DONE 0x80000002 2188 #define DRV_STATE_WOL 0x00000003 2189 #define DRV_STATE_SUSPEND 0x00000004 2190 2191 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 2192 2193 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 2194 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 2195 2196 #define NIC_SRAM_WOL_MBOX 0x00000d30 2197 #define WOL_SIGNATURE 0x474c0000 2198 #define WOL_DRV_STATE_SHUTDOWN 0x00000001 2199 #define WOL_DRV_WOL 0x00000002 2200 #define WOL_SET_MAGIC_PKT 0x00000004 2201 2202 #define NIC_SRAM_DATA_CFG_2 0x00000d38 2203 2204 #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400 2205 #define SHASTA_EXT_LED_MODE_MASK 0x00018000 2206 #define SHASTA_EXT_LED_LEGACY 0x00000000 2207 #define SHASTA_EXT_LED_SHARED 0x00008000 2208 #define SHASTA_EXT_LED_MAC 0x00010000 2209 #define SHASTA_EXT_LED_COMBO 0x00018000 2210 2211 #define NIC_SRAM_DATA_CFG_3 0x00000d3c 2212 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 2213 #define NIC_SRAM_LNK_FLAP_AVOID 0x00400000 2214 #define NIC_SRAM_1G_ON_VAUX_OK 0x00800000 2215 2216 #define NIC_SRAM_DATA_CFG_4 0x00000d60 2217 #define NIC_SRAM_GMII_MODE 0x00000002 2218 #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004 2219 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 2220 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 2221 2222 #define NIC_SRAM_CPMU_STATUS 0x00000e00 2223 #define NIC_SRAM_CPMUSTAT_SIG 0x0000362c 2224 #define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff 2225 2226 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 2227 2228 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 2229 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 2230 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 2231 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 2232 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 2233 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 2234 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 2235 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 2236 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 2237 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 2238 2239 #define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000 2240 #define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000 2241 #define TG3_57766_FW_BASE_ADDR 0x00030000 2242 #define TG3_57766_FW_HANDSHAKE 0x0003fccc 2243 #define TG3_SBROM_IN_SERVICE_LOOP 0x51 2244 2245 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 2246 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 2247 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 2248 2249 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64 2250 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16 2251 2252 2253 /* Currently this is fixed. */ 2254 #define TG3_PHY_MII_ADDR 0x01 2255 2256 2257 /*** Tigon3 specific PHY MII registers. ***/ 2258 #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ 2259 #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 2260 #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ 2261 2262 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 2263 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 2264 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 2265 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 2266 #define MII_TG3_EXT_CTRL_TBI 0x8000 2267 2268 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2269 #define MII_TG3_EXT_STAT_MDIX 0x2000 2270 #define MII_TG3_EXT_STAT_LPASS 0x0100 2271 2272 #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ 2273 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 2274 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ 2275 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 2276 2277 #define MII_TG3_DSP_TAP1 0x0001 2278 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 2279 #define MII_TG3_DSP_TAP26 0x001a 2280 #define MII_TG3_DSP_TAP26_ALNOKO 0x0001 2281 #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002 2282 #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004 2283 #define MII_TG3_DSP_AADJ1CH0 0x001f 2284 #define MII_TG3_DSP_CH34TP2 0x4022 2285 #define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff 2286 #define MII_TG3_DSP_AADJ1CH3 0x601f 2287 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 2288 #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01 2289 #define MII_TG3_DSP_EXP8 0x0f08 2290 #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 2291 #define MII_TG3_DSP_EXP8_AEDW 0x0200 2292 #define MII_TG3_DSP_EXP75 0x0f75 2293 #define MII_TG3_DSP_EXP96 0x0f96 2294 #define MII_TG3_DSP_EXP97 0x0f97 2295 2296 #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */ 2297 2298 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 2299 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 2300 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 2301 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000 2302 #define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000 2303 2304 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 2305 #define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008 2306 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 2307 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 2308 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040 2309 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 2310 2311 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004 2312 2313 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 2314 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010 2315 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 2316 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12 2317 #define MII_TG3_AUXCTL_MISC_WREN 0x8000 2318 2319 2320 #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */ 2321 #define MII_TG3_AUX_STAT_LPASS 0x0004 2322 #define MII_TG3_AUX_STAT_SPDMASK 0x0700 2323 #define MII_TG3_AUX_STAT_10HALF 0x0100 2324 #define MII_TG3_AUX_STAT_10FULL 0x0200 2325 #define MII_TG3_AUX_STAT_100HALF 0x0300 2326 #define MII_TG3_AUX_STAT_100_4 0x0400 2327 #define MII_TG3_AUX_STAT_100FULL 0x0500 2328 #define MII_TG3_AUX_STAT_1000HALF 0x0600 2329 #define MII_TG3_AUX_STAT_1000FULL 0x0700 2330 #define MII_TG3_AUX_STAT_100 0x0008 2331 #define MII_TG3_AUX_STAT_FULL 0x0001 2332 2333 #define MII_TG3_ISTAT 0x1a /* IRQ status register */ 2334 #define MII_TG3_IMASK 0x1b /* IRQ mask register */ 2335 2336 /* ISTAT/IMASK event bits */ 2337 #define MII_TG3_INT_LINKCHG 0x0002 2338 #define MII_TG3_INT_SPEEDCHG 0x0004 2339 #define MII_TG3_INT_DUPLEXCHG 0x0008 2340 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 2341 2342 #define MII_TG3_MISC_SHDW 0x1c 2343 #define MII_TG3_MISC_SHDW_WREN 0x8000 2344 2345 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 2346 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 2347 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 2348 2349 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 2350 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 2351 #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 2352 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 2353 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 2354 #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 2355 2356 #define MII_TG3_TEST1 0x1e 2357 #define MII_TG3_TEST1_TRIM_EN 0x0010 2358 #define MII_TG3_TEST1_CRC_EN 0x8000 2359 2360 /* Clause 45 expansion registers */ 2361 #define TG3_CL45_D7_EEERES_STAT 0x803e 2362 #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 2363 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 2364 2365 2366 /* Fast Ethernet Tranceiver definitions */ 2367 #define MII_TG3_FET_PTEST 0x17 2368 #define MII_TG3_FET_PTEST_TRIM_SEL 0x0010 2369 #define MII_TG3_FET_PTEST_TRIM_2 0x0002 2370 #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 2371 #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 2372 2373 #define MII_TG3_FET_GEN_STAT 0x1c 2374 #define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000 2375 2376 #define MII_TG3_FET_TEST 0x1f 2377 #define MII_TG3_FET_SHADOW_EN 0x0080 2378 2379 #define MII_TG3_FET_SHDW_MISCCTRL 0x10 2380 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 2381 2382 #define MII_TG3_FET_SHDW_AUXMODE4 0x1a 2383 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 2384 2385 #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b 2386 #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 2387 2388 /* Serdes PHY Register Definitions */ 2389 #define SERDES_TG3_1000X_STATUS 0x14 2390 #define SERDES_TG3_SGMII_MODE 0x0001 2391 #define SERDES_TG3_LINK_UP 0x0002 2392 #define SERDES_TG3_FULL_DUPLEX 0x0004 2393 #define SERDES_TG3_SPEED_100 0x0008 2394 #define SERDES_TG3_SPEED_1000 0x0010 2395 2396 /* APE registers. Accessible through BAR1 */ 2397 #define TG3_APE_GPIO_MSG 0x0008 2398 #define TG3_APE_GPIO_MSG_SHIFT 4 2399 #define TG3_APE_EVENT 0x000c 2400 #define APE_EVENT_1 0x00000001 2401 #define TG3_APE_LOCK_REQ 0x002c 2402 #define APE_LOCK_REQ_DRIVER 0x00001000 2403 #define TG3_APE_LOCK_GRANT 0x004c 2404 #define APE_LOCK_GRANT_DRIVER 0x00001000 2405 #define TG3_APE_OTP_CTRL 0x00e8 2406 #define APE_OTP_CTRL_PROG_EN 0x200000 2407 #define APE_OTP_CTRL_CMD_RD 0x000000 2408 #define APE_OTP_CTRL_START 0x000001 2409 #define TG3_APE_OTP_STATUS 0x00ec 2410 #define APE_OTP_STATUS_CMD_DONE 0x000001 2411 #define TG3_APE_OTP_ADDR 0x00f0 2412 #define APE_OTP_ADDR_CPU_ENABLE 0x80000000 2413 #define TG3_APE_OTP_RD_DATA 0x00f8 2414 2415 #define OTP_ADDRESS_MAGIC0 0x00000050 2416 #define TG3_OTP_MAGIC0_VALID(val) \ 2417 ((((val) & 0xf0000000) == 0xa0000000) ||\ 2418 (((val) & 0x0f000000) == 0x0a000000)) 2419 2420 /* APE shared memory. Accessible through BAR1 */ 2421 #define TG3_APE_SHMEM_BASE 0x4000 2422 #define TG3_APE_SEG_SIG 0x4000 2423 #define APE_SEG_SIG_MAGIC 0x41504521 2424 #define TG3_APE_FW_STATUS 0x400c 2425 #define APE_FW_STATUS_READY 0x00000100 2426 #define TG3_APE_FW_FEATURES 0x4010 2427 #define TG3_APE_FW_FEATURE_NCSI 0x00000002 2428 #define TG3_APE_FW_VERSION 0x4018 2429 #define APE_FW_VERSION_MAJMSK 0xff000000 2430 #define APE_FW_VERSION_MAJSFT 24 2431 #define APE_FW_VERSION_MINMSK 0x00ff0000 2432 #define APE_FW_VERSION_MINSFT 16 2433 #define APE_FW_VERSION_REVMSK 0x0000ff00 2434 #define APE_FW_VERSION_REVSFT 8 2435 #define APE_FW_VERSION_BLDMSK 0x000000ff 2436 #define TG3_APE_SEG_MSG_BUF_OFF 0x401c 2437 #define TG3_APE_SEG_MSG_BUF_LEN 0x4020 2438 #define TG3_APE_HOST_SEG_SIG 0x4200 2439 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2440 #define TG3_APE_HOST_SEG_LEN 0x4204 2441 #define APE_HOST_SEG_LEN_MAGIC 0x00000020 2442 #define TG3_APE_HOST_INIT_COUNT 0x4208 2443 #define TG3_APE_HOST_DRIVER_ID 0x420c 2444 #define APE_HOST_DRIVER_ID_LINUX 0xf0000000 2445 #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2446 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8) 2447 #define TG3_APE_HOST_BEHAVIOR 0x4210 2448 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2449 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 2450 #define APE_HOST_HEARTBEAT_INT_DISABLE 0 2451 #define APE_HOST_HEARTBEAT_INT_5SEC 5000 2452 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 2453 #define TG3_APE_HOST_DRVR_STATE 0x421c 2454 #define TG3_APE_HOST_DRVR_STATE_START 0x00000001 2455 #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2456 #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003 2457 #define TG3_APE_HOST_WOL_SPEED 0x4224 2458 #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000 2459 2460 #define TG3_APE_EVENT_STATUS 0x4300 2461 2462 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2463 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2464 #define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600 2465 #define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700 2466 #define APE_EVENT_STATUS_STATE_START 0x00010000 2467 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2468 #define APE_EVENT_STATUS_STATE_WOL 0x00030000 2469 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2470 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2471 2472 #define TG3_APE_PER_LOCK_REQ 0x8400 2473 #define APE_LOCK_PER_REQ_DRIVER 0x00001000 2474 #define TG3_APE_PER_LOCK_GRANT 0x8420 2475 #define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2476 2477 /* APE convenience enumerations. */ 2478 #define TG3_APE_LOCK_PHY0 0 2479 #define TG3_APE_LOCK_GRC 1 2480 #define TG3_APE_LOCK_PHY1 2 2481 #define TG3_APE_LOCK_PHY2 3 2482 #define TG3_APE_LOCK_MEM 4 2483 #define TG3_APE_LOCK_PHY3 5 2484 #define TG3_APE_LOCK_GPIO 7 2485 2486 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2487 2488 2489 /* There are two ways to manage the TX descriptors on the tigon3. 2490 * Either the descriptors are in host DMA'able memory, or they 2491 * exist only in the cards on-chip SRAM. All 16 send bds are under 2492 * the same mode, they may not be configured individually. 2493 * 2494 * This driver always uses host memory TX descriptors. 2495 * 2496 * To use host memory TX descriptors: 2497 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 2498 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 2499 * 2) Allocate DMA'able memory. 2500 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2501 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 2502 * obtained in step 2 2503 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 2504 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 2505 * of TX descriptors. Leave flags field clear. 2506 * 4) Access TX descriptors via host memory. The chip 2507 * will refetch into local SRAM as needed when producer 2508 * index mailboxes are updated. 2509 * 2510 * To use on-chip TX descriptors: 2511 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 2512 * Make sure GRC_MODE_HOST_SENDBDS is clear. 2513 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2514 * a) Set TG3_BDINFO_HOST_ADDR to zero. 2515 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 2516 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 2517 * 3) Access TX descriptors directly in on-chip SRAM 2518 * using normal {read,write}l(). (and not using 2519 * pointer dereferencing of ioremap()'d memory like 2520 * the broken Broadcom driver does) 2521 * 2522 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 2523 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 2524 */ 2525 struct tg3_tx_buffer_desc { 2526 u32 addr_hi; 2527 u32 addr_lo; 2528 2529 u32 len_flags; 2530 #define TXD_FLAG_TCPUDP_CSUM 0x0001 2531 #define TXD_FLAG_IP_CSUM 0x0002 2532 #define TXD_FLAG_END 0x0004 2533 #define TXD_FLAG_IP_FRAG 0x0008 2534 #define TXD_FLAG_JMB_PKT 0x0008 2535 #define TXD_FLAG_IP_FRAG_END 0x0010 2536 #define TXD_FLAG_HWTSTAMP 0x0020 2537 #define TXD_FLAG_VLAN 0x0040 2538 #define TXD_FLAG_COAL_NOW 0x0080 2539 #define TXD_FLAG_CPU_PRE_DMA 0x0100 2540 #define TXD_FLAG_CPU_POST_DMA 0x0200 2541 #define TXD_FLAG_ADD_SRC_ADDR 0x1000 2542 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 2543 #define TXD_FLAG_NO_CRC 0x8000 2544 #define TXD_LEN_SHIFT 16 2545 2546 u32 vlan_tag; 2547 #define TXD_VLAN_TAG_SHIFT 0 2548 #define TXD_MSS_SHIFT 16 2549 }; 2550 2551 #define TXD_ADDR 0x00UL /* 64-bit */ 2552 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 2553 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 2554 #define TXD_SIZE 0x10UL 2555 2556 struct tg3_rx_buffer_desc { 2557 u32 addr_hi; 2558 u32 addr_lo; 2559 2560 u32 idx_len; 2561 #define RXD_IDX_MASK 0xffff0000 2562 #define RXD_IDX_SHIFT 16 2563 #define RXD_LEN_MASK 0x0000ffff 2564 #define RXD_LEN_SHIFT 0 2565 2566 u32 type_flags; 2567 #define RXD_TYPE_SHIFT 16 2568 #define RXD_FLAGS_SHIFT 0 2569 2570 #define RXD_FLAG_END 0x0004 2571 #define RXD_FLAG_MINI 0x0800 2572 #define RXD_FLAG_JUMBO 0x0020 2573 #define RXD_FLAG_VLAN 0x0040 2574 #define RXD_FLAG_ERROR 0x0400 2575 #define RXD_FLAG_IP_CSUM 0x1000 2576 #define RXD_FLAG_TCPUDP_CSUM 0x2000 2577 #define RXD_FLAG_IS_TCP 0x4000 2578 #define RXD_FLAG_PTPSTAT_MASK 0x0210 2579 #define RXD_FLAG_PTPSTAT_PTPV1 0x0010 2580 #define RXD_FLAG_PTPSTAT_PTPV2 0x0200 2581 2582 u32 ip_tcp_csum; 2583 #define RXD_IPCSUM_MASK 0xffff0000 2584 #define RXD_IPCSUM_SHIFT 16 2585 #define RXD_TCPCSUM_MASK 0x0000ffff 2586 #define RXD_TCPCSUM_SHIFT 0 2587 2588 u32 err_vlan; 2589 2590 #define RXD_VLAN_MASK 0x0000ffff 2591 2592 #define RXD_ERR_BAD_CRC 0x00010000 2593 #define RXD_ERR_COLLISION 0x00020000 2594 #define RXD_ERR_LINK_LOST 0x00040000 2595 #define RXD_ERR_PHY_DECODE 0x00080000 2596 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 2597 #define RXD_ERR_MAC_ABRT 0x00200000 2598 #define RXD_ERR_TOO_SMALL 0x00400000 2599 #define RXD_ERR_NO_RESOURCES 0x00800000 2600 #define RXD_ERR_HUGE_FRAME 0x01000000 2601 #define RXD_ERR_MASK 0xffff0000 2602 2603 u32 reserved; 2604 u32 opaque; 2605 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff 2606 #define RXD_OPAQUE_INDEX_SHIFT 0 2607 #define RXD_OPAQUE_RING_STD 0x00010000 2608 #define RXD_OPAQUE_RING_JUMBO 0x00020000 2609 #define RXD_OPAQUE_RING_MINI 0x00040000 2610 #define RXD_OPAQUE_RING_MASK 0x00070000 2611 }; 2612 2613 struct tg3_ext_rx_buffer_desc { 2614 struct { 2615 u32 addr_hi; 2616 u32 addr_lo; 2617 } addrlist[3]; 2618 u32 len2_len1; 2619 u32 resv_len3; 2620 struct tg3_rx_buffer_desc std; 2621 }; 2622 2623 /* We only use this when testing out the DMA engine 2624 * at probe time. This is the internal format of buffer 2625 * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 2626 */ 2627 struct tg3_internal_buffer_desc { 2628 u32 addr_hi; 2629 u32 addr_lo; 2630 u32 nic_mbuf; 2631 /* XXX FIX THIS */ 2632 #ifdef __BIG_ENDIAN 2633 u16 cqid_sqid; 2634 u16 len; 2635 #else 2636 u16 len; 2637 u16 cqid_sqid; 2638 #endif 2639 u32 flags; 2640 u32 __cookie1; 2641 u32 __cookie2; 2642 u32 __cookie3; 2643 }; 2644 2645 #define TG3_HW_STATUS_SIZE 0x50 2646 struct tg3_hw_status { 2647 u32 status; 2648 #define SD_STATUS_UPDATED 0x00000001 2649 #define SD_STATUS_LINK_CHG 0x00000002 2650 #define SD_STATUS_ERROR 0x00000004 2651 2652 u32 status_tag; 2653 2654 #ifdef __BIG_ENDIAN 2655 u16 rx_consumer; 2656 u16 rx_jumbo_consumer; 2657 #else 2658 u16 rx_jumbo_consumer; 2659 u16 rx_consumer; 2660 #endif 2661 2662 #ifdef __BIG_ENDIAN 2663 u16 reserved; 2664 u16 rx_mini_consumer; 2665 #else 2666 u16 rx_mini_consumer; 2667 u16 reserved; 2668 #endif 2669 struct { 2670 #ifdef __BIG_ENDIAN 2671 u16 tx_consumer; 2672 u16 rx_producer; 2673 #else 2674 u16 rx_producer; 2675 u16 tx_consumer; 2676 #endif 2677 } idx[16]; 2678 }; 2679 2680 typedef struct { 2681 u32 high, low; 2682 } tg3_stat64_t; 2683 2684 struct tg3_hw_stats { 2685 u8 __reserved0[0x400-0x300]; 2686 2687 /* Statistics maintained by Receive MAC. */ 2688 tg3_stat64_t rx_octets; 2689 u64 __reserved1; 2690 tg3_stat64_t rx_fragments; 2691 tg3_stat64_t rx_ucast_packets; 2692 tg3_stat64_t rx_mcast_packets; 2693 tg3_stat64_t rx_bcast_packets; 2694 tg3_stat64_t rx_fcs_errors; 2695 tg3_stat64_t rx_align_errors; 2696 tg3_stat64_t rx_xon_pause_rcvd; 2697 tg3_stat64_t rx_xoff_pause_rcvd; 2698 tg3_stat64_t rx_mac_ctrl_rcvd; 2699 tg3_stat64_t rx_xoff_entered; 2700 tg3_stat64_t rx_frame_too_long_errors; 2701 tg3_stat64_t rx_jabbers; 2702 tg3_stat64_t rx_undersize_packets; 2703 tg3_stat64_t rx_in_length_errors; 2704 tg3_stat64_t rx_out_length_errors; 2705 tg3_stat64_t rx_64_or_less_octet_packets; 2706 tg3_stat64_t rx_65_to_127_octet_packets; 2707 tg3_stat64_t rx_128_to_255_octet_packets; 2708 tg3_stat64_t rx_256_to_511_octet_packets; 2709 tg3_stat64_t rx_512_to_1023_octet_packets; 2710 tg3_stat64_t rx_1024_to_1522_octet_packets; 2711 tg3_stat64_t rx_1523_to_2047_octet_packets; 2712 tg3_stat64_t rx_2048_to_4095_octet_packets; 2713 tg3_stat64_t rx_4096_to_8191_octet_packets; 2714 tg3_stat64_t rx_8192_to_9022_octet_packets; 2715 2716 u64 __unused0[37]; 2717 2718 /* Statistics maintained by Transmit MAC. */ 2719 tg3_stat64_t tx_octets; 2720 u64 __reserved2; 2721 tg3_stat64_t tx_collisions; 2722 tg3_stat64_t tx_xon_sent; 2723 tg3_stat64_t tx_xoff_sent; 2724 tg3_stat64_t tx_flow_control; 2725 tg3_stat64_t tx_mac_errors; 2726 tg3_stat64_t tx_single_collisions; 2727 tg3_stat64_t tx_mult_collisions; 2728 tg3_stat64_t tx_deferred; 2729 u64 __reserved3; 2730 tg3_stat64_t tx_excessive_collisions; 2731 tg3_stat64_t tx_late_collisions; 2732 tg3_stat64_t tx_collide_2times; 2733 tg3_stat64_t tx_collide_3times; 2734 tg3_stat64_t tx_collide_4times; 2735 tg3_stat64_t tx_collide_5times; 2736 tg3_stat64_t tx_collide_6times; 2737 tg3_stat64_t tx_collide_7times; 2738 tg3_stat64_t tx_collide_8times; 2739 tg3_stat64_t tx_collide_9times; 2740 tg3_stat64_t tx_collide_10times; 2741 tg3_stat64_t tx_collide_11times; 2742 tg3_stat64_t tx_collide_12times; 2743 tg3_stat64_t tx_collide_13times; 2744 tg3_stat64_t tx_collide_14times; 2745 tg3_stat64_t tx_collide_15times; 2746 tg3_stat64_t tx_ucast_packets; 2747 tg3_stat64_t tx_mcast_packets; 2748 tg3_stat64_t tx_bcast_packets; 2749 tg3_stat64_t tx_carrier_sense_errors; 2750 tg3_stat64_t tx_discards; 2751 tg3_stat64_t tx_errors; 2752 2753 u64 __unused1[31]; 2754 2755 /* Statistics maintained by Receive List Placement. */ 2756 tg3_stat64_t COS_rx_packets[16]; 2757 tg3_stat64_t COS_rx_filter_dropped; 2758 tg3_stat64_t dma_writeq_full; 2759 tg3_stat64_t dma_write_prioq_full; 2760 tg3_stat64_t rxbds_empty; 2761 tg3_stat64_t rx_discards; 2762 tg3_stat64_t rx_errors; 2763 tg3_stat64_t rx_threshold_hit; 2764 2765 u64 __unused2[9]; 2766 2767 /* Statistics maintained by Send Data Initiator. */ 2768 tg3_stat64_t COS_out_packets[16]; 2769 tg3_stat64_t dma_readq_full; 2770 tg3_stat64_t dma_read_prioq_full; 2771 tg3_stat64_t tx_comp_queue_full; 2772 2773 /* Statistics maintained by Host Coalescing. */ 2774 tg3_stat64_t ring_set_send_prod_index; 2775 tg3_stat64_t ring_status_update; 2776 tg3_stat64_t nic_irqs; 2777 tg3_stat64_t nic_avoided_irqs; 2778 tg3_stat64_t nic_tx_threshold_hit; 2779 2780 /* NOT a part of the hardware statistics block format. 2781 * These stats are here as storage for tg3_periodic_fetch_stats(). 2782 */ 2783 tg3_stat64_t mbuf_lwm_thresh_hit; 2784 2785 u8 __reserved4[0xb00-0x9c8]; 2786 }; 2787 2788 #define TG3_SD_NUM_RECS 3 2789 #define TG3_OCIR_LEN (sizeof(struct tg3_ocir)) 2790 #define TG3_OCIR_SIG_MAGIC 0x5253434f 2791 #define TG3_OCIR_FLAG_ACTIVE 0x00000001 2792 2793 #define TG3_TEMP_CAUTION_OFFSET 0xc8 2794 #define TG3_TEMP_MAX_OFFSET 0xcc 2795 #define TG3_TEMP_SENSOR_OFFSET 0xd4 2796 2797 2798 struct tg3_ocir { 2799 u32 signature; 2800 u16 version_flags; 2801 u16 refresh_int; 2802 u32 refresh_tmr; 2803 u32 update_tmr; 2804 u32 dst_base_addr; 2805 u16 src_hdr_offset; 2806 u16 src_hdr_length; 2807 u16 src_data_offset; 2808 u16 src_data_length; 2809 u16 dst_hdr_offset; 2810 u16 dst_data_offset; 2811 u16 dst_reg_upd_offset; 2812 u16 dst_sem_offset; 2813 u32 reserved1[2]; 2814 u32 port0_flags; 2815 u32 port1_flags; 2816 u32 port2_flags; 2817 u32 port3_flags; 2818 u32 reserved2[1]; 2819 }; 2820 2821 2822 /* 'mapping' is superfluous as the chip does not write into 2823 * the tx/rx post rings so we could just fetch it from there. 2824 * But the cache behavior is better how we are doing it now. 2825 * 2826 * This driver uses new build_skb() API : 2827 * RX ring buffer contains pointer to kmalloc() data only, 2828 * skb are built only after Hardware filled the frame. 2829 */ 2830 struct ring_info { 2831 u8 *data; 2832 DEFINE_DMA_UNMAP_ADDR(mapping); 2833 }; 2834 2835 struct tg3_tx_ring_info { 2836 struct sk_buff *skb; 2837 DEFINE_DMA_UNMAP_ADDR(mapping); 2838 bool fragmented; 2839 }; 2840 2841 struct tg3_link_config { 2842 /* Describes what we're trying to get. */ 2843 u32 advertising; 2844 u16 speed; 2845 u8 duplex; 2846 u8 autoneg; 2847 u8 flowctrl; 2848 2849 /* Describes what we actually have. */ 2850 u8 active_flowctrl; 2851 2852 u8 active_duplex; 2853 u16 active_speed; 2854 u32 rmt_adv; 2855 }; 2856 2857 struct tg3_bufmgr_config { 2858 u32 mbuf_read_dma_low_water; 2859 u32 mbuf_mac_rx_low_water; 2860 u32 mbuf_high_water; 2861 2862 u32 mbuf_read_dma_low_water_jumbo; 2863 u32 mbuf_mac_rx_low_water_jumbo; 2864 u32 mbuf_high_water_jumbo; 2865 2866 u32 dma_low_water; 2867 u32 dma_high_water; 2868 }; 2869 2870 struct tg3_ethtool_stats { 2871 /* Statistics maintained by Receive MAC. */ 2872 u64 rx_octets; 2873 u64 rx_fragments; 2874 u64 rx_ucast_packets; 2875 u64 rx_mcast_packets; 2876 u64 rx_bcast_packets; 2877 u64 rx_fcs_errors; 2878 u64 rx_align_errors; 2879 u64 rx_xon_pause_rcvd; 2880 u64 rx_xoff_pause_rcvd; 2881 u64 rx_mac_ctrl_rcvd; 2882 u64 rx_xoff_entered; 2883 u64 rx_frame_too_long_errors; 2884 u64 rx_jabbers; 2885 u64 rx_undersize_packets; 2886 u64 rx_in_length_errors; 2887 u64 rx_out_length_errors; 2888 u64 rx_64_or_less_octet_packets; 2889 u64 rx_65_to_127_octet_packets; 2890 u64 rx_128_to_255_octet_packets; 2891 u64 rx_256_to_511_octet_packets; 2892 u64 rx_512_to_1023_octet_packets; 2893 u64 rx_1024_to_1522_octet_packets; 2894 u64 rx_1523_to_2047_octet_packets; 2895 u64 rx_2048_to_4095_octet_packets; 2896 u64 rx_4096_to_8191_octet_packets; 2897 u64 rx_8192_to_9022_octet_packets; 2898 2899 /* Statistics maintained by Transmit MAC. */ 2900 u64 tx_octets; 2901 u64 tx_collisions; 2902 u64 tx_xon_sent; 2903 u64 tx_xoff_sent; 2904 u64 tx_flow_control; 2905 u64 tx_mac_errors; 2906 u64 tx_single_collisions; 2907 u64 tx_mult_collisions; 2908 u64 tx_deferred; 2909 u64 tx_excessive_collisions; 2910 u64 tx_late_collisions; 2911 u64 tx_collide_2times; 2912 u64 tx_collide_3times; 2913 u64 tx_collide_4times; 2914 u64 tx_collide_5times; 2915 u64 tx_collide_6times; 2916 u64 tx_collide_7times; 2917 u64 tx_collide_8times; 2918 u64 tx_collide_9times; 2919 u64 tx_collide_10times; 2920 u64 tx_collide_11times; 2921 u64 tx_collide_12times; 2922 u64 tx_collide_13times; 2923 u64 tx_collide_14times; 2924 u64 tx_collide_15times; 2925 u64 tx_ucast_packets; 2926 u64 tx_mcast_packets; 2927 u64 tx_bcast_packets; 2928 u64 tx_carrier_sense_errors; 2929 u64 tx_discards; 2930 u64 tx_errors; 2931 2932 /* Statistics maintained by Receive List Placement. */ 2933 u64 dma_writeq_full; 2934 u64 dma_write_prioq_full; 2935 u64 rxbds_empty; 2936 u64 rx_discards; 2937 u64 rx_errors; 2938 u64 rx_threshold_hit; 2939 2940 /* Statistics maintained by Send Data Initiator. */ 2941 u64 dma_readq_full; 2942 u64 dma_read_prioq_full; 2943 u64 tx_comp_queue_full; 2944 2945 /* Statistics maintained by Host Coalescing. */ 2946 u64 ring_set_send_prod_index; 2947 u64 ring_status_update; 2948 u64 nic_irqs; 2949 u64 nic_avoided_irqs; 2950 u64 nic_tx_threshold_hit; 2951 2952 u64 mbuf_lwm_thresh_hit; 2953 }; 2954 2955 struct tg3_rx_prodring_set { 2956 u32 rx_std_prod_idx; 2957 u32 rx_std_cons_idx; 2958 u32 rx_jmb_prod_idx; 2959 u32 rx_jmb_cons_idx; 2960 struct tg3_rx_buffer_desc *rx_std; 2961 struct tg3_ext_rx_buffer_desc *rx_jmb; 2962 struct ring_info *rx_std_buffers; 2963 struct ring_info *rx_jmb_buffers; 2964 dma_addr_t rx_std_mapping; 2965 dma_addr_t rx_jmb_mapping; 2966 }; 2967 2968 #define TG3_RSS_MAX_NUM_QS 4 2969 #define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1) 2970 #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS 2971 2972 struct tg3_napi { 2973 struct napi_struct napi ____cacheline_aligned; 2974 struct tg3 *tp; 2975 struct tg3_hw_status *hw_status; 2976 2977 u32 chk_msi_cnt; 2978 u32 last_tag; 2979 u32 last_irq_tag; 2980 u32 int_mbox; 2981 u32 coal_now; 2982 2983 u32 consmbox ____cacheline_aligned; 2984 u32 rx_rcb_ptr; 2985 u32 last_rx_cons; 2986 u16 *rx_rcb_prod_idx; 2987 struct tg3_rx_prodring_set prodring; 2988 struct tg3_rx_buffer_desc *rx_rcb; 2989 2990 u32 tx_prod ____cacheline_aligned; 2991 u32 tx_cons; 2992 u32 tx_pending; 2993 u32 last_tx_cons; 2994 u32 prodmbox; 2995 struct tg3_tx_buffer_desc *tx_ring; 2996 struct tg3_tx_ring_info *tx_buffers; 2997 2998 dma_addr_t status_mapping; 2999 dma_addr_t rx_rcb_mapping; 3000 dma_addr_t tx_desc_mapping; 3001 3002 char irq_lbl[IFNAMSIZ]; 3003 unsigned int irq_vec; 3004 }; 3005 3006 enum TG3_FLAGS { 3007 TG3_FLAG_TAGGED_STATUS = 0, 3008 TG3_FLAG_TXD_MBOX_HWBUG, 3009 TG3_FLAG_USE_LINKCHG_REG, 3010 TG3_FLAG_ERROR_PROCESSED, 3011 TG3_FLAG_ENABLE_ASF, 3012 TG3_FLAG_ASPM_WORKAROUND, 3013 TG3_FLAG_POLL_SERDES, 3014 TG3_FLAG_MBOX_WRITE_REORDER, 3015 TG3_FLAG_PCIX_TARGET_HWBUG, 3016 TG3_FLAG_WOL_SPEED_100MB, 3017 TG3_FLAG_WOL_ENABLE, 3018 TG3_FLAG_EEPROM_WRITE_PROT, 3019 TG3_FLAG_NVRAM, 3020 TG3_FLAG_NVRAM_BUFFERED, 3021 TG3_FLAG_SUPPORT_MSI, 3022 TG3_FLAG_SUPPORT_MSIX, 3023 TG3_FLAG_USING_MSI, 3024 TG3_FLAG_USING_MSIX, 3025 TG3_FLAG_PCIX_MODE, 3026 TG3_FLAG_PCI_HIGH_SPEED, 3027 TG3_FLAG_PCI_32BIT, 3028 TG3_FLAG_SRAM_USE_CONFIG, 3029 TG3_FLAG_TX_RECOVERY_PENDING, 3030 TG3_FLAG_WOL_CAP, 3031 TG3_FLAG_JUMBO_RING_ENABLE, 3032 TG3_FLAG_PAUSE_AUTONEG, 3033 TG3_FLAG_CPMU_PRESENT, 3034 TG3_FLAG_40BIT_DMA_BUG, 3035 TG3_FLAG_BROKEN_CHECKSUMS, 3036 TG3_FLAG_JUMBO_CAPABLE, 3037 TG3_FLAG_CHIP_RESETTING, 3038 TG3_FLAG_INIT_COMPLETE, 3039 TG3_FLAG_MAX_RXPEND_64, 3040 TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ 3041 TG3_FLAG_ASF_NEW_HANDSHAKE, 3042 TG3_FLAG_HW_AUTONEG, 3043 TG3_FLAG_IS_NIC, 3044 TG3_FLAG_FLASH, 3045 TG3_FLAG_FW_TSO, 3046 TG3_FLAG_HW_TSO_1, 3047 TG3_FLAG_HW_TSO_2, 3048 TG3_FLAG_HW_TSO_3, 3049 TG3_FLAG_TSO_CAPABLE, 3050 TG3_FLAG_TSO_BUG, 3051 TG3_FLAG_ICH_WORKAROUND, 3052 TG3_FLAG_1SHOT_MSI, 3053 TG3_FLAG_NO_FWARE_REPORTED, 3054 TG3_FLAG_NO_NVRAM_ADDR_TRANS, 3055 TG3_FLAG_ENABLE_APE, 3056 TG3_FLAG_PROTECTED_NVRAM, 3057 TG3_FLAG_5701_DMA_BUG, 3058 TG3_FLAG_USE_PHYLIB, 3059 TG3_FLAG_MDIOBUS_INITED, 3060 TG3_FLAG_LRG_PROD_RING_CAP, 3061 TG3_FLAG_RGMII_INBAND_DISABLE, 3062 TG3_FLAG_RGMII_EXT_IBND_RX_EN, 3063 TG3_FLAG_RGMII_EXT_IBND_TX_EN, 3064 TG3_FLAG_CLKREQ_BUG, 3065 TG3_FLAG_NO_NVRAM, 3066 TG3_FLAG_ENABLE_RSS, 3067 TG3_FLAG_ENABLE_TSS, 3068 TG3_FLAG_SHORT_DMA_BUG, 3069 TG3_FLAG_USE_JUMBO_BDFLAG, 3070 TG3_FLAG_L1PLLPD_EN, 3071 TG3_FLAG_APE_HAS_NCSI, 3072 TG3_FLAG_TX_TSTAMP_EN, 3073 TG3_FLAG_4K_FIFO_LIMIT, 3074 TG3_FLAG_5719_5720_RDMA_BUG, 3075 TG3_FLAG_RESET_TASK_PENDING, 3076 TG3_FLAG_PTP_CAPABLE, 3077 TG3_FLAG_5705_PLUS, 3078 TG3_FLAG_IS_5788, 3079 TG3_FLAG_5750_PLUS, 3080 TG3_FLAG_5780_CLASS, 3081 TG3_FLAG_5755_PLUS, 3082 TG3_FLAG_57765_PLUS, 3083 TG3_FLAG_57765_CLASS, 3084 TG3_FLAG_5717_PLUS, 3085 TG3_FLAG_IS_SSB_CORE, 3086 TG3_FLAG_FLUSH_POSTED_WRITES, 3087 TG3_FLAG_ROBOSWITCH, 3088 TG3_FLAG_ONE_DMA_AT_ONCE, 3089 TG3_FLAG_RGMII_MODE, 3090 3091 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */ 3092 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ 3093 }; 3094 3095 struct tg3_firmware_hdr { 3096 __be32 version; /* unused for fragments */ 3097 __be32 base_addr; 3098 __be32 len; 3099 }; 3100 #define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr)) 3101 3102 struct tg3 { 3103 /* begin "general, frequently-used members" cacheline section */ 3104 3105 /* If the IRQ handler (which runs lockless) needs to be 3106 * quiesced, the following bitmask state is used. The 3107 * SYNC flag is set by non-IRQ context code to initiate 3108 * the quiescence. 3109 * 3110 * When the IRQ handler notices that SYNC is set, it 3111 * disables interrupts and returns. 3112 * 3113 * When all outstanding IRQ handlers have returned after 3114 * the SYNC flag has been set, the setter can be assured 3115 * that interrupts will no longer get run. 3116 * 3117 * In this way all SMP driver locks are never acquired 3118 * in hw IRQ context, only sw IRQ context or lower. 3119 */ 3120 unsigned int irq_sync; 3121 3122 /* SMP locking strategy: 3123 * 3124 * lock: Held during reset, PHY access, timer, and when 3125 * updating tg3_flags. 3126 * 3127 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 3128 * netif_tx_lock when it needs to call 3129 * netif_wake_queue. 3130 * 3131 * Both of these locks are to be held with BH safety. 3132 * 3133 * Because the IRQ handler, tg3_poll, and tg3_start_xmit 3134 * are running lockless, it is necessary to completely 3135 * quiesce the chip with tg3_netif_stop and tg3_full_lock 3136 * before reconfiguring the device. 3137 * 3138 * indirect_lock: Held when accessing registers indirectly 3139 * with IRQ disabling. 3140 */ 3141 spinlock_t lock; 3142 spinlock_t indirect_lock; 3143 3144 u32 (*read32) (struct tg3 *, u32); 3145 void (*write32) (struct tg3 *, u32, u32); 3146 u32 (*read32_mbox) (struct tg3 *, u32); 3147 void (*write32_mbox) (struct tg3 *, u32, 3148 u32); 3149 void __iomem *regs; 3150 void __iomem *aperegs; 3151 struct net_device *dev; 3152 struct pci_dev *pdev; 3153 3154 u32 coal_now; 3155 u32 msg_enable; 3156 3157 struct ptp_clock_info ptp_info; 3158 struct ptp_clock *ptp_clock; 3159 s64 ptp_adjust; 3160 3161 /* begin "tx thread" cacheline section */ 3162 void (*write32_tx_mbox) (struct tg3 *, u32, 3163 u32); 3164 u32 dma_limit; 3165 u32 txq_req; 3166 u32 txq_cnt; 3167 u32 txq_max; 3168 3169 /* begin "rx thread" cacheline section */ 3170 struct tg3_napi napi[TG3_IRQ_MAX_VECS]; 3171 void (*write32_rx_mbox) (struct tg3 *, u32, 3172 u32); 3173 u32 rx_copy_thresh; 3174 u32 rx_std_ring_mask; 3175 u32 rx_jmb_ring_mask; 3176 u32 rx_ret_ring_mask; 3177 u32 rx_pending; 3178 u32 rx_jumbo_pending; 3179 u32 rx_std_max_post; 3180 u32 rx_offset; 3181 u32 rx_pkt_map_sz; 3182 u32 rxq_req; 3183 u32 rxq_cnt; 3184 u32 rxq_max; 3185 bool rx_refill; 3186 3187 3188 /* begin "everything else" cacheline(s) section */ 3189 unsigned long rx_dropped; 3190 unsigned long tx_dropped; 3191 struct rtnl_link_stats64 net_stats_prev; 3192 struct tg3_ethtool_stats estats_prev; 3193 3194 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS); 3195 3196 union { 3197 unsigned long phy_crc_errors; 3198 unsigned long last_event_jiffies; 3199 }; 3200 3201 struct timer_list timer; 3202 u16 timer_counter; 3203 u16 timer_multiplier; 3204 u32 timer_offset; 3205 u16 asf_counter; 3206 u16 asf_multiplier; 3207 3208 /* 1 second counter for transient serdes link events */ 3209 u32 serdes_counter; 3210 #define SERDES_AN_TIMEOUT_5704S 2 3211 #define SERDES_PARALLEL_DET_TIMEOUT 1 3212 #define SERDES_AN_TIMEOUT_5714S 1 3213 3214 struct tg3_link_config link_config; 3215 struct tg3_bufmgr_config bufmgr_config; 3216 3217 /* cache h/w values, often passed straight to h/w */ 3218 u32 rx_mode; 3219 u32 tx_mode; 3220 u32 mac_mode; 3221 u32 mi_mode; 3222 u32 misc_host_ctrl; 3223 u32 grc_mode; 3224 u32 grc_local_ctrl; 3225 u32 dma_rwctrl; 3226 u32 coalesce_mode; 3227 u32 pwrmgmt_thresh; 3228 u32 rxptpctl; 3229 3230 /* PCI block */ 3231 u32 pci_chip_rev_id; 3232 u16 pci_cmd; 3233 u8 pci_cacheline_sz; 3234 u8 pci_lat_timer; 3235 3236 int pci_fn; 3237 int msi_cap; 3238 int pcix_cap; 3239 int pcie_readrq; 3240 3241 struct mii_bus *mdio_bus; 3242 int mdio_irq[PHY_MAX_ADDR]; 3243 int old_link; 3244 3245 u8 phy_addr; 3246 u8 phy_ape_lock; 3247 3248 /* PHY info */ 3249 u32 phy_id; 3250 #define TG3_PHY_ID_MASK 0xfffffff0 3251 #define TG3_PHY_ID_BCM5400 0x60008040 3252 #define TG3_PHY_ID_BCM5401 0x60008050 3253 #define TG3_PHY_ID_BCM5411 0x60008070 3254 #define TG3_PHY_ID_BCM5701 0x60008110 3255 #define TG3_PHY_ID_BCM5703 0x60008160 3256 #define TG3_PHY_ID_BCM5704 0x60008190 3257 #define TG3_PHY_ID_BCM5705 0x600081a0 3258 #define TG3_PHY_ID_BCM5750 0x60008180 3259 #define TG3_PHY_ID_BCM5752 0x60008100 3260 #define TG3_PHY_ID_BCM5714 0x60008340 3261 #define TG3_PHY_ID_BCM5780 0x60008350 3262 #define TG3_PHY_ID_BCM5755 0xbc050cc0 3263 #define TG3_PHY_ID_BCM5787 0xbc050ce0 3264 #define TG3_PHY_ID_BCM5756 0xbc050ed0 3265 #define TG3_PHY_ID_BCM5784 0xbc050fa0 3266 #define TG3_PHY_ID_BCM5761 0xbc050fd0 3267 #define TG3_PHY_ID_BCM5718C 0x5c0d8a00 3268 #define TG3_PHY_ID_BCM5718S 0xbc050ff0 3269 #define TG3_PHY_ID_BCM57765 0x5c0d8a40 3270 #define TG3_PHY_ID_BCM5719C 0x5c0d8a20 3271 #define TG3_PHY_ID_BCM5720C 0x5c0d8b60 3272 #define TG3_PHY_ID_BCM5762 0x85803780 3273 #define TG3_PHY_ID_BCM5906 0xdc00ac40 3274 #define TG3_PHY_ID_BCM8002 0x60010140 3275 #define TG3_PHY_ID_INVALID 0xffffffff 3276 3277 #define PHY_ID_RTL8211C 0x001cc910 3278 #define PHY_ID_RTL8201E 0x00008200 3279 3280 #define TG3_PHY_ID_REV_MASK 0x0000000f 3281 #define TG3_PHY_REV_BCM5401_B0 0x1 3282 3283 /* This macro assumes the passed PHY ID is 3284 * already masked with TG3_PHY_ID_MASK. 3285 */ 3286 #define TG3_KNOWN_PHY_ID(X) \ 3287 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \ 3288 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \ 3289 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \ 3290 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \ 3291 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \ 3292 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \ 3293 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \ 3294 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ 3295 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ 3296 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ 3297 (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \ 3298 (X) == TG3_PHY_ID_BCM8002) 3299 3300 u32 phy_flags; 3301 #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 3302 #define TG3_PHYFLG_IS_CONNECTED 0x00000002 3303 #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 3304 #define TG3_PHYFLG_USER_CONFIGURED 0x00000008 3305 #define TG3_PHYFLG_PHY_SERDES 0x00000010 3306 #define TG3_PHYFLG_MII_SERDES 0x00000020 3307 #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ 3308 TG3_PHYFLG_MII_SERDES) 3309 #define TG3_PHYFLG_IS_FET 0x00000040 3310 #define TG3_PHYFLG_10_100_ONLY 0x00000080 3311 #define TG3_PHYFLG_ENABLE_APD 0x00000100 3312 #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200 3313 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400 3314 #define TG3_PHYFLG_JITTER_BUG 0x00000800 3315 #define TG3_PHYFLG_ADJUST_TRIM 0x00001000 3316 #define TG3_PHYFLG_ADC_BUG 0x00002000 3317 #define TG3_PHYFLG_5704_A0_BUG 0x00004000 3318 #define TG3_PHYFLG_BER_BUG 0x00008000 3319 #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 3320 #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 3321 #define TG3_PHYFLG_EEE_CAP 0x00040000 3322 #define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000 3323 #define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000 3324 #define TG3_PHYFLG_MDIX_STATE 0x00200000 3325 3326 u32 led_ctrl; 3327 u32 phy_otp; 3328 u32 setlpicnt; 3329 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE]; 3330 3331 #define TG3_BPN_SIZE 24 3332 char board_part_number[TG3_BPN_SIZE]; 3333 #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN 3334 char fw_ver[TG3_VER_SIZE]; 3335 u32 nic_sram_data_cfg; 3336 u32 pci_clock_ctrl; 3337 struct pci_dev *pdev_peer; 3338 3339 struct tg3_hw_stats *hw_stats; 3340 dma_addr_t stats_mapping; 3341 struct work_struct reset_task; 3342 3343 int nvram_lock_cnt; 3344 u32 nvram_size; 3345 #define TG3_NVRAM_SIZE_2KB 0x00000800 3346 #define TG3_NVRAM_SIZE_64KB 0x00010000 3347 #define TG3_NVRAM_SIZE_128KB 0x00020000 3348 #define TG3_NVRAM_SIZE_256KB 0x00040000 3349 #define TG3_NVRAM_SIZE_512KB 0x00080000 3350 #define TG3_NVRAM_SIZE_1MB 0x00100000 3351 #define TG3_NVRAM_SIZE_2MB 0x00200000 3352 3353 u32 nvram_pagesize; 3354 u32 nvram_jedecnum; 3355 3356 #define JEDEC_ATMEL 0x1f 3357 #define JEDEC_ST 0x20 3358 #define JEDEC_SAIFUN 0x4f 3359 #define JEDEC_SST 0xbf 3360 3361 #define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB 3362 #define ATMEL_AT24C02_PAGE_SIZE (8) 3363 3364 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB 3365 #define ATMEL_AT24C64_PAGE_SIZE (32) 3366 3367 #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB 3368 #define ATMEL_AT24C512_PAGE_SIZE (128) 3369 3370 #define ATMEL_AT45DB0X1B_PAGE_POS 9 3371 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264 3372 3373 #define ATMEL_AT25F512_PAGE_SIZE 256 3374 3375 #define ST_M45PEX0_PAGE_SIZE 256 3376 3377 #define SAIFUN_SA25F0XX_PAGE_SIZE 256 3378 3379 #define SST_25VF0X0_PAGE_SIZE 4098 3380 3381 unsigned int irq_max; 3382 unsigned int irq_cnt; 3383 3384 struct ethtool_coalesce coal; 3385 struct ethtool_eee eee; 3386 3387 /* firmware info */ 3388 const char *fw_needed; 3389 const struct firmware *fw; 3390 u32 fw_len; /* includes BSS */ 3391 3392 struct device *hwmon_dev; 3393 bool link_up; 3394 }; 3395 3396 /* Accessor macros for chip and asic attributes 3397 * 3398 * nb: Using static inlines equivalent to the accessor macros generates 3399 * larger object code with gcc 4.7. 3400 * Using statement expression macros to check tp with 3401 * typecheck(struct tg3 *, tp) also creates larger objects. 3402 */ 3403 #define tg3_chip_rev_id(tp) \ 3404 ((tp)->pci_chip_rev_id) 3405 #define tg3_asic_rev(tp) \ 3406 ((tp)->pci_chip_rev_id >> 12) 3407 #define tg3_chip_rev(tp) \ 3408 ((tp)->pci_chip_rev_id >> 8) 3409 3410 #endif /* !(_T3_H) */ 3411