1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/wait.h> 12 #include <linux/mii.h> 13 #include <linux/ethtool.h> 14 #include <linux/bitops.h> 15 #include <linux/netdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/brcmphy.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/platform_data/bcmgenet.h> 24 #include <linux/platform_data/mdio-bcm-unimac.h> 25 26 #include "bcmgenet.h" 27 28 /* setup netdev link state when PHY link status change and 29 * update UMAC and RGMII block when link up 30 */ 31 void bcmgenet_mii_setup(struct net_device *dev) 32 { 33 struct bcmgenet_priv *priv = netdev_priv(dev); 34 struct phy_device *phydev = dev->phydev; 35 u32 reg, cmd_bits = 0; 36 bool status_changed = false; 37 38 if (priv->old_link != phydev->link) { 39 status_changed = true; 40 priv->old_link = phydev->link; 41 } 42 43 if (phydev->link) { 44 /* check speed/duplex/pause changes */ 45 if (priv->old_speed != phydev->speed) { 46 status_changed = true; 47 priv->old_speed = phydev->speed; 48 } 49 50 if (priv->old_duplex != phydev->duplex) { 51 status_changed = true; 52 priv->old_duplex = phydev->duplex; 53 } 54 55 if (priv->old_pause != phydev->pause) { 56 status_changed = true; 57 priv->old_pause = phydev->pause; 58 } 59 60 /* done if nothing has changed */ 61 if (!status_changed) 62 return; 63 64 /* speed */ 65 if (phydev->speed == SPEED_1000) 66 cmd_bits = UMAC_SPEED_1000; 67 else if (phydev->speed == SPEED_100) 68 cmd_bits = UMAC_SPEED_100; 69 else 70 cmd_bits = UMAC_SPEED_10; 71 cmd_bits <<= CMD_SPEED_SHIFT; 72 73 /* duplex */ 74 if (phydev->duplex != DUPLEX_FULL) 75 cmd_bits |= CMD_HD_EN; 76 77 /* pause capability */ 78 if (!phydev->pause) 79 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 80 81 /* 82 * Program UMAC and RGMII block based on established 83 * link speed, duplex, and pause. The speed set in 84 * umac->cmd tell RGMII block which clock to use for 85 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 86 * Receive clock is provided by the PHY. 87 */ 88 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 89 reg &= ~OOB_DISABLE; 90 reg |= RGMII_LINK; 91 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 92 93 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 94 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 95 CMD_HD_EN | 96 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 97 reg |= cmd_bits; 98 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 99 } else { 100 /* done if nothing has changed */ 101 if (!status_changed) 102 return; 103 104 /* needed for MoCA fixed PHY to reflect correct link status */ 105 netif_carrier_off(dev); 106 } 107 108 phy_print_status(phydev); 109 } 110 111 112 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 113 struct fixed_phy_status *status) 114 { 115 struct bcmgenet_priv *priv; 116 u32 reg; 117 118 if (dev && dev->phydev && status) { 119 priv = netdev_priv(dev); 120 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 121 status->link = !!(reg & MODE_LINK_STATUS); 122 } 123 124 return 0; 125 } 126 127 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 128 { 129 struct bcmgenet_priv *priv = netdev_priv(dev); 130 u32 reg = 0; 131 132 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 133 if (GENET_IS_V4(priv)) { 134 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 135 if (enable) { 136 reg &= ~EXT_CK25_DIS; 137 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 138 mdelay(1); 139 140 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 141 reg |= EXT_GPHY_RESET; 142 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 143 mdelay(1); 144 145 reg &= ~EXT_GPHY_RESET; 146 } else { 147 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 148 EXT_GPHY_RESET; 149 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 150 mdelay(1); 151 reg |= EXT_CK25_DIS; 152 } 153 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 154 udelay(60); 155 } else { 156 mdelay(1); 157 } 158 } 159 160 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 161 { 162 u32 reg; 163 164 if (!GENET_IS_V5(priv)) { 165 /* Speed settings are set in bcmgenet_mii_setup() */ 166 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 167 reg |= LED_ACT_SOURCE_MAC; 168 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 169 } 170 171 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 172 fixed_phy_set_link_update(priv->dev->phydev, 173 bcmgenet_fixed_phy_link_update); 174 } 175 176 int bcmgenet_mii_connect(struct net_device *dev) 177 { 178 struct bcmgenet_priv *priv = netdev_priv(dev); 179 struct device_node *dn = priv->pdev->dev.of_node; 180 struct phy_device *phydev; 181 u32 phy_flags = 0; 182 int ret; 183 184 /* Communicate the integrated PHY revision */ 185 if (priv->internal_phy) 186 phy_flags = priv->gphy_rev; 187 188 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 189 priv->old_link = -1; 190 priv->old_speed = -1; 191 priv->old_duplex = -1; 192 priv->old_pause = -1; 193 194 if (dn) { 195 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 196 phy_flags, priv->phy_interface); 197 if (!phydev) { 198 pr_err("could not attach to PHY\n"); 199 return -ENODEV; 200 } 201 } else { 202 phydev = dev->phydev; 203 phydev->dev_flags = phy_flags; 204 205 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 206 priv->phy_interface); 207 if (ret) { 208 pr_err("could not attach to PHY\n"); 209 return -ENODEV; 210 } 211 } 212 213 return 0; 214 } 215 216 int bcmgenet_mii_config(struct net_device *dev, bool init) 217 { 218 struct bcmgenet_priv *priv = netdev_priv(dev); 219 struct phy_device *phydev = dev->phydev; 220 struct device *kdev = &priv->pdev->dev; 221 const char *phy_name = NULL; 222 u32 id_mode_dis = 0; 223 u32 port_ctrl; 224 u32 reg; 225 226 priv->ext_phy = !priv->internal_phy && 227 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 228 229 switch (priv->phy_interface) { 230 case PHY_INTERFACE_MODE_INTERNAL: 231 case PHY_INTERFACE_MODE_MOCA: 232 /* Irrespective of the actually configured PHY speed (100 or 233 * 1000) GENETv4 only has an internal GPHY so we will just end 234 * up masking the Gigabit features from what we support, not 235 * switching to the EPHY 236 */ 237 if (GENET_IS_V4(priv)) 238 port_ctrl = PORT_MODE_INT_GPHY; 239 else 240 port_ctrl = PORT_MODE_INT_EPHY; 241 242 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 243 244 if (priv->internal_phy) { 245 phy_name = "internal PHY"; 246 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 247 phy_name = "MoCA"; 248 bcmgenet_moca_phy_setup(priv); 249 } 250 break; 251 252 case PHY_INTERFACE_MODE_MII: 253 phy_name = "external MII"; 254 phy_set_max_speed(phydev, SPEED_100); 255 bcmgenet_sys_writel(priv, 256 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 257 break; 258 259 case PHY_INTERFACE_MODE_REVMII: 260 phy_name = "external RvMII"; 261 /* of_mdiobus_register took care of reading the 'max-speed' 262 * PHY property for us, effectively limiting the PHY supported 263 * capabilities, use that knowledge to also configure the 264 * Reverse MII interface correctly. 265 */ 266 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 267 dev->phydev->supported)) 268 port_ctrl = PORT_MODE_EXT_RVMII_50; 269 else 270 port_ctrl = PORT_MODE_EXT_RVMII_25; 271 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 272 break; 273 274 case PHY_INTERFACE_MODE_RGMII: 275 /* RGMII_NO_ID: TXC transitions at the same time as TXD 276 * (requires PCB or receiver-side delay) 277 * RGMII: Add 2ns delay on TXC (90 degree shift) 278 * 279 * ID is implicitly disabled for 100Mbps (RG)MII operation. 280 */ 281 id_mode_dis = BIT(16); 282 /* fall through */ 283 case PHY_INTERFACE_MODE_RGMII_TXID: 284 if (id_mode_dis) 285 phy_name = "external RGMII (no delay)"; 286 else 287 phy_name = "external RGMII (TX delay)"; 288 bcmgenet_sys_writel(priv, 289 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 290 break; 291 default: 292 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 293 return -EINVAL; 294 } 295 296 /* This is an external PHY (xMII), so we need to enable the RGMII 297 * block for the interface to work 298 */ 299 if (priv->ext_phy) { 300 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 301 reg |= id_mode_dis; 302 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 303 reg |= RGMII_MODE_EN_V123; 304 else 305 reg |= RGMII_MODE_EN; 306 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 307 } 308 309 if (init) { 310 linkmode_copy(phydev->advertising, phydev->supported); 311 312 /* The internal PHY has its link interrupts routed to the 313 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 314 * that prevents the signaling of link UP interrupts when 315 * the link operates at 10Mbps, so fallback to polling for 316 * those versions of GENET. 317 */ 318 if (priv->internal_phy && !GENET_IS_V5(priv)) 319 phydev->irq = PHY_IGNORE_INTERRUPT; 320 321 dev_info(kdev, "configuring instance for %s\n", phy_name); 322 } 323 324 return 0; 325 } 326 327 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 328 { 329 struct device_node *dn = priv->pdev->dev.of_node; 330 struct device *kdev = &priv->pdev->dev; 331 char *compat; 332 333 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 334 if (!compat) 335 return NULL; 336 337 priv->mdio_dn = of_get_compatible_child(dn, compat); 338 kfree(compat); 339 if (!priv->mdio_dn) { 340 dev_err(kdev, "unable to find MDIO bus node\n"); 341 return NULL; 342 } 343 344 return priv->mdio_dn; 345 } 346 347 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 348 struct unimac_mdio_pdata *ppd) 349 { 350 struct device *kdev = &priv->pdev->dev; 351 struct bcmgenet_platform_data *pd = kdev->platform_data; 352 353 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 354 /* 355 * Internal or external PHY with MDIO access 356 */ 357 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 358 ppd->phy_mask = 1 << pd->phy_address; 359 else 360 ppd->phy_mask = 0; 361 } 362 } 363 364 static int bcmgenet_mii_wait(void *wait_func_data) 365 { 366 struct bcmgenet_priv *priv = wait_func_data; 367 368 wait_event_timeout(priv->wq, 369 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 370 & MDIO_START_BUSY), 371 HZ / 100); 372 return 0; 373 } 374 375 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 376 { 377 struct platform_device *pdev = priv->pdev; 378 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 379 struct device_node *dn = pdev->dev.of_node; 380 struct unimac_mdio_pdata ppd; 381 struct platform_device *ppdev; 382 struct resource *pres, res; 383 int id, ret; 384 385 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 386 memset(&res, 0, sizeof(res)); 387 memset(&ppd, 0, sizeof(ppd)); 388 389 ppd.wait_func = bcmgenet_mii_wait; 390 ppd.wait_func_data = priv; 391 ppd.bus_name = "bcmgenet MII bus"; 392 393 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 394 * and is 2 * 32-bits word long, 8 bytes total. 395 */ 396 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 397 res.end = res.start + 8; 398 res.flags = IORESOURCE_MEM; 399 400 if (dn) 401 id = of_alias_get_id(dn, "eth"); 402 else 403 id = pdev->id; 404 405 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 406 if (!ppdev) 407 return -ENOMEM; 408 409 /* Retain this platform_device pointer for later cleanup */ 410 priv->mii_pdev = ppdev; 411 ppdev->dev.parent = &pdev->dev; 412 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 413 if (pdata) 414 bcmgenet_mii_pdata_init(priv, &ppd); 415 416 ret = platform_device_add_resources(ppdev, &res, 1); 417 if (ret) 418 goto out; 419 420 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 421 if (ret) 422 goto out; 423 424 ret = platform_device_add(ppdev); 425 if (ret) 426 goto out; 427 428 return 0; 429 out: 430 platform_device_put(ppdev); 431 return ret; 432 } 433 434 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 435 { 436 struct device_node *dn = priv->pdev->dev.of_node; 437 struct device *kdev = &priv->pdev->dev; 438 struct phy_device *phydev; 439 int phy_mode; 440 int ret; 441 442 /* Fetch the PHY phandle */ 443 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 444 445 /* In the case of a fixed PHY, the DT node associated 446 * to the PHY is the Ethernet MAC DT node. 447 */ 448 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 449 ret = of_phy_register_fixed_link(dn); 450 if (ret) 451 return ret; 452 453 priv->phy_dn = of_node_get(dn); 454 } 455 456 /* Get the link mode */ 457 phy_mode = of_get_phy_mode(dn); 458 if (phy_mode < 0) { 459 dev_err(kdev, "invalid PHY mode property\n"); 460 return phy_mode; 461 } 462 463 priv->phy_interface = phy_mode; 464 465 /* We need to specifically look up whether this PHY interface is internal 466 * or not *before* we even try to probe the PHY driver over MDIO as we 467 * may have shut down the internal PHY for power saving purposes. 468 */ 469 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 470 priv->internal_phy = true; 471 472 /* Make sure we initialize MoCA PHYs with a link down */ 473 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 474 phydev = of_phy_find_device(dn); 475 if (phydev) { 476 phydev->link = 0; 477 put_device(&phydev->mdio.dev); 478 } 479 } 480 481 return 0; 482 } 483 484 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 485 { 486 struct device *kdev = &priv->pdev->dev; 487 struct bcmgenet_platform_data *pd = kdev->platform_data; 488 char phy_name[MII_BUS_ID_SIZE + 3]; 489 char mdio_bus_id[MII_BUS_ID_SIZE]; 490 struct phy_device *phydev; 491 492 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 493 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 494 495 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 496 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 497 mdio_bus_id, pd->phy_address); 498 499 /* 500 * Internal or external PHY with MDIO access 501 */ 502 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 503 if (!phydev) { 504 dev_err(kdev, "failed to register PHY device\n"); 505 return -ENODEV; 506 } 507 } else { 508 /* 509 * MoCA port or no MDIO access. 510 * Use fixed PHY to represent the link layer. 511 */ 512 struct fixed_phy_status fphy_status = { 513 .link = 1, 514 .speed = pd->phy_speed, 515 .duplex = pd->phy_duplex, 516 .pause = 0, 517 .asym_pause = 0, 518 }; 519 520 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 521 if (!phydev || IS_ERR(phydev)) { 522 dev_err(kdev, "failed to register fixed PHY device\n"); 523 return -ENODEV; 524 } 525 526 /* Make sure we initialize MoCA PHYs with a link down */ 527 phydev->link = 0; 528 529 } 530 531 priv->phy_interface = pd->phy_interface; 532 533 return 0; 534 } 535 536 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 537 { 538 struct device_node *dn = priv->pdev->dev.of_node; 539 540 if (dn) 541 return bcmgenet_mii_of_init(priv); 542 else 543 return bcmgenet_mii_pd_init(priv); 544 } 545 546 int bcmgenet_mii_init(struct net_device *dev) 547 { 548 struct bcmgenet_priv *priv = netdev_priv(dev); 549 int ret; 550 551 ret = bcmgenet_mii_register(priv); 552 if (ret) 553 return ret; 554 555 ret = bcmgenet_mii_bus_init(priv); 556 if (ret) 557 goto out; 558 559 return 0; 560 561 out: 562 bcmgenet_mii_exit(dev); 563 return ret; 564 } 565 566 void bcmgenet_mii_exit(struct net_device *dev) 567 { 568 struct bcmgenet_priv *priv = netdev_priv(dev); 569 struct device_node *dn = priv->pdev->dev.of_node; 570 571 if (of_phy_is_fixed_link(dn)) 572 of_phy_deregister_fixed_link(dn); 573 of_node_put(priv->phy_dn); 574 platform_device_unregister(priv->mii_pdev); 575 } 576