1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET MDIO routines 4 * 5 * Copyright (c) 2014-2017 Broadcom 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/wait.h> 12 #include <linux/mii.h> 13 #include <linux/ethtool.h> 14 #include <linux/bitops.h> 15 #include <linux/netdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy.h> 18 #include <linux/phy_fixed.h> 19 #include <linux/brcmphy.h> 20 #include <linux/of.h> 21 #include <linux/of_net.h> 22 #include <linux/of_mdio.h> 23 #include <linux/platform_data/bcmgenet.h> 24 #include <linux/platform_data/mdio-bcm-unimac.h> 25 26 #include "bcmgenet.h" 27 28 static void bcmgenet_mac_config(struct net_device *dev) 29 { 30 struct bcmgenet_priv *priv = netdev_priv(dev); 31 struct phy_device *phydev = dev->phydev; 32 u32 reg, cmd_bits = 0; 33 34 /* speed */ 35 if (phydev->speed == SPEED_1000) 36 cmd_bits = CMD_SPEED_1000; 37 else if (phydev->speed == SPEED_100) 38 cmd_bits = CMD_SPEED_100; 39 else 40 cmd_bits = CMD_SPEED_10; 41 cmd_bits <<= CMD_SPEED_SHIFT; 42 43 /* duplex */ 44 if (phydev->duplex != DUPLEX_FULL) { 45 cmd_bits |= CMD_HD_EN | 46 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 47 } else { 48 /* pause capability defaults to Symmetric */ 49 if (priv->autoneg_pause) { 50 bool tx_pause = 0, rx_pause = 0; 51 52 if (phydev->autoneg) 53 phy_get_pause(phydev, &tx_pause, &rx_pause); 54 55 if (!tx_pause) 56 cmd_bits |= CMD_TX_PAUSE_IGNORE; 57 if (!rx_pause) 58 cmd_bits |= CMD_RX_PAUSE_IGNORE; 59 } 60 61 /* Manual override */ 62 if (!priv->rx_pause) 63 cmd_bits |= CMD_RX_PAUSE_IGNORE; 64 if (!priv->tx_pause) 65 cmd_bits |= CMD_TX_PAUSE_IGNORE; 66 } 67 68 /* Program UMAC and RGMII block based on established 69 * link speed, duplex, and pause. The speed set in 70 * umac->cmd tell RGMII block which clock to use for 71 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 72 * Receive clock is provided by the PHY. 73 */ 74 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 75 reg |= RGMII_LINK; 76 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 77 78 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 79 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 80 CMD_HD_EN | 81 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 82 reg |= cmd_bits; 83 if (reg & CMD_SW_RESET) { 84 reg &= ~CMD_SW_RESET; 85 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 86 udelay(2); 87 reg |= CMD_TX_EN | CMD_RX_EN; 88 } 89 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 90 } 91 92 /* setup netdev link state when PHY link status change and 93 * update UMAC and RGMII block when link up 94 */ 95 void bcmgenet_mii_setup(struct net_device *dev) 96 { 97 struct bcmgenet_priv *priv = netdev_priv(dev); 98 struct phy_device *phydev = dev->phydev; 99 u32 reg; 100 101 if (phydev->link) { 102 bcmgenet_mac_config(dev); 103 } else { 104 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 105 reg &= ~RGMII_LINK; 106 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 107 } 108 109 phy_print_status(phydev); 110 } 111 112 113 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 114 struct fixed_phy_status *status) 115 { 116 struct bcmgenet_priv *priv; 117 u32 reg; 118 119 if (dev && dev->phydev && status) { 120 priv = netdev_priv(dev); 121 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 122 status->link = !!(reg & MODE_LINK_STATUS); 123 } 124 125 return 0; 126 } 127 128 void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx) 129 { 130 struct phy_device *phydev = dev->phydev; 131 132 linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->advertising, rx); 133 linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->advertising, 134 rx | tx); 135 phy_start_aneg(phydev); 136 137 mutex_lock(&phydev->lock); 138 if (phydev->link) 139 bcmgenet_mac_config(dev); 140 mutex_unlock(&phydev->lock); 141 } 142 143 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 144 { 145 struct bcmgenet_priv *priv = netdev_priv(dev); 146 u32 reg = 0; 147 148 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 149 if (GENET_IS_V4(priv) || priv->ephy_16nm) { 150 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 151 if (enable) { 152 reg &= ~EXT_CK25_DIS; 153 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 154 mdelay(1); 155 156 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 157 EXT_CFG_IDDQ_GLOBAL_PWR); 158 reg |= EXT_GPHY_RESET; 159 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 160 mdelay(1); 161 162 reg &= ~EXT_GPHY_RESET; 163 } else { 164 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 165 EXT_GPHY_RESET | EXT_CFG_IDDQ_GLOBAL_PWR; 166 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 167 mdelay(1); 168 reg |= EXT_CK25_DIS; 169 } 170 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 171 udelay(60); 172 } else { 173 mdelay(1); 174 } 175 } 176 177 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 178 { 179 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 180 fixed_phy_set_link_update(priv->dev->phydev, 181 bcmgenet_fixed_phy_link_update); 182 } 183 184 int bcmgenet_mii_config(struct net_device *dev, bool init) 185 { 186 struct bcmgenet_priv *priv = netdev_priv(dev); 187 struct phy_device *phydev = dev->phydev; 188 struct device *kdev = &priv->pdev->dev; 189 const char *phy_name = NULL; 190 u32 id_mode_dis = 0; 191 u32 port_ctrl; 192 u32 reg; 193 194 switch (priv->phy_interface) { 195 case PHY_INTERFACE_MODE_INTERNAL: 196 phy_name = "internal PHY"; 197 fallthrough; 198 case PHY_INTERFACE_MODE_MOCA: 199 /* Irrespective of the actually configured PHY speed (100 or 200 * 1000) GENETv4 only has an internal GPHY so we will just end 201 * up masking the Gigabit features from what we support, not 202 * switching to the EPHY 203 */ 204 if (GENET_IS_V4(priv)) 205 port_ctrl = PORT_MODE_INT_GPHY; 206 else 207 port_ctrl = PORT_MODE_INT_EPHY; 208 209 if (!phy_name) { 210 phy_name = "MoCA"; 211 if (!GENET_IS_V5(priv)) 212 port_ctrl |= LED_ACT_SOURCE_MAC; 213 bcmgenet_moca_phy_setup(priv); 214 } 215 break; 216 217 case PHY_INTERFACE_MODE_MII: 218 phy_name = "external MII"; 219 phy_set_max_speed(phydev, SPEED_100); 220 port_ctrl = PORT_MODE_EXT_EPHY; 221 break; 222 223 case PHY_INTERFACE_MODE_REVMII: 224 phy_name = "external RvMII"; 225 /* of_mdiobus_register took care of reading the 'max-speed' 226 * PHY property for us, effectively limiting the PHY supported 227 * capabilities, use that knowledge to also configure the 228 * Reverse MII interface correctly. 229 */ 230 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 231 dev->phydev->supported)) 232 port_ctrl = PORT_MODE_EXT_RVMII_50; 233 else 234 port_ctrl = PORT_MODE_EXT_RVMII_25; 235 break; 236 237 case PHY_INTERFACE_MODE_RGMII: 238 /* RGMII_NO_ID: TXC transitions at the same time as TXD 239 * (requires PCB or receiver-side delay) 240 * 241 * ID is implicitly disabled for 100Mbps (RG)MII operation. 242 */ 243 phy_name = "external RGMII (no delay)"; 244 id_mode_dis = BIT(16); 245 port_ctrl = PORT_MODE_EXT_GPHY; 246 break; 247 248 case PHY_INTERFACE_MODE_RGMII_TXID: 249 /* RGMII_TXID: Add 2ns delay on TXC (90 degree shift) */ 250 phy_name = "external RGMII (TX delay)"; 251 port_ctrl = PORT_MODE_EXT_GPHY; 252 break; 253 254 case PHY_INTERFACE_MODE_RGMII_RXID: 255 phy_name = "external RGMII (RX delay)"; 256 port_ctrl = PORT_MODE_EXT_GPHY; 257 break; 258 default: 259 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 260 return -EINVAL; 261 } 262 263 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 264 265 priv->ext_phy = !priv->internal_phy && 266 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 267 268 /* This is an external PHY (xMII), so we need to enable the RGMII 269 * block for the interface to work, unconditionally clear the 270 * Out-of-band disable since we do not need it. 271 */ 272 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 273 reg &= ~OOB_DISABLE; 274 if (priv->ext_phy) { 275 reg &= ~ID_MODE_DIS; 276 reg |= id_mode_dis; 277 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 278 reg |= RGMII_MODE_EN_V123; 279 else 280 reg |= RGMII_MODE_EN; 281 } 282 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 283 284 if (init) 285 dev_info(kdev, "configuring instance for %s\n", phy_name); 286 287 return 0; 288 } 289 290 int bcmgenet_mii_probe(struct net_device *dev) 291 { 292 struct bcmgenet_priv *priv = netdev_priv(dev); 293 struct device *kdev = &priv->pdev->dev; 294 struct device_node *dn = kdev->of_node; 295 phy_interface_t phy_iface = priv->phy_interface; 296 struct phy_device *phydev; 297 u32 phy_flags = PHY_BRCM_AUTO_PWRDWN_ENABLE | 298 PHY_BRCM_DIS_TXCRXC_NOENRGY | 299 PHY_BRCM_IDDQ_SUSPEND; 300 int ret; 301 302 /* Communicate the integrated PHY revision */ 303 if (priv->internal_phy) 304 phy_flags = priv->gphy_rev; 305 306 /* This is an ugly quirk but we have not been correctly interpreting 307 * the phy_interface values and we have done that across different 308 * drivers, so at least we are consistent in our mistakes. 309 * 310 * When the Generic PHY driver is in use either the PHY has been 311 * strapped or programmed correctly by the boot loader so we should 312 * stick to our incorrect interpretation since we have validated it. 313 * 314 * Now when a dedicated PHY driver is in use, we need to reverse the 315 * meaning of the phy_interface_mode values to something that the PHY 316 * driver will interpret and act on such that we have two mistakes 317 * canceling themselves so to speak. We only do this for the two 318 * modes that GENET driver officially supports on Broadcom STB chips: 319 * PHY_INTERFACE_MODE_RGMII and PHY_INTERFACE_MODE_RGMII_TXID. Other 320 * modes are not *officially* supported with the boot loader and the 321 * scripted environment generating Device Tree blobs for those 322 * platforms. 323 * 324 * Note that internal PHY, MoCA and fixed-link configurations are not 325 * affected because they use different phy_interface_t values or the 326 * Generic PHY driver. 327 */ 328 switch (priv->phy_interface) { 329 case PHY_INTERFACE_MODE_RGMII: 330 phy_iface = PHY_INTERFACE_MODE_RGMII_ID; 331 break; 332 case PHY_INTERFACE_MODE_RGMII_TXID: 333 phy_iface = PHY_INTERFACE_MODE_RGMII_RXID; 334 break; 335 default: 336 break; 337 } 338 339 if (dn) { 340 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 341 phy_flags, phy_iface); 342 if (!phydev) { 343 pr_err("could not attach to PHY\n"); 344 return -ENODEV; 345 } 346 } else { 347 if (has_acpi_companion(kdev)) { 348 char mdio_bus_id[MII_BUS_ID_SIZE]; 349 struct mii_bus *unimacbus; 350 351 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 352 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 353 354 unimacbus = mdio_find_bus(mdio_bus_id); 355 if (!unimacbus) { 356 pr_err("Unable to find mii\n"); 357 return -ENODEV; 358 } 359 phydev = phy_find_first(unimacbus); 360 put_device(&unimacbus->dev); 361 if (!phydev) { 362 pr_err("Unable to find PHY\n"); 363 return -ENODEV; 364 } 365 } else { 366 phydev = dev->phydev; 367 } 368 phydev->dev_flags = phy_flags; 369 370 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 371 phy_iface); 372 if (ret) { 373 pr_err("could not attach to PHY\n"); 374 return -ENODEV; 375 } 376 } 377 378 /* Configure port multiplexer based on what the probed PHY device since 379 * reading the 'max-speed' property determines the maximum supported 380 * PHY speed which is needed for bcmgenet_mii_config() to configure 381 * things appropriately. 382 */ 383 ret = bcmgenet_mii_config(dev, true); 384 if (ret) { 385 phy_disconnect(dev->phydev); 386 return ret; 387 } 388 389 /* The internal PHY has its link interrupts routed to the 390 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 391 * that prevents the signaling of link UP interrupts when 392 * the link operates at 10Mbps, so fallback to polling for 393 * those versions of GENET. 394 */ 395 if (priv->internal_phy && !GENET_IS_V5(priv)) 396 dev->phydev->irq = PHY_MAC_INTERRUPT; 397 398 /* Indicate that the MAC is responsible for PHY PM */ 399 dev->phydev->mac_managed_pm = true; 400 401 return 0; 402 } 403 404 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 405 { 406 struct device_node *dn = priv->pdev->dev.of_node; 407 struct device *kdev = &priv->pdev->dev; 408 char *compat; 409 410 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 411 if (!compat) 412 return NULL; 413 414 priv->mdio_dn = of_get_compatible_child(dn, compat); 415 kfree(compat); 416 if (!priv->mdio_dn) { 417 dev_err(kdev, "unable to find MDIO bus node\n"); 418 return NULL; 419 } 420 421 return priv->mdio_dn; 422 } 423 424 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 425 struct unimac_mdio_pdata *ppd) 426 { 427 struct device *kdev = &priv->pdev->dev; 428 struct bcmgenet_platform_data *pd = kdev->platform_data; 429 430 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 431 /* 432 * Internal or external PHY with MDIO access 433 */ 434 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 435 ppd->phy_mask = 1 << pd->phy_address; 436 else 437 ppd->phy_mask = 0; 438 } 439 } 440 441 static int bcmgenet_mii_wait(void *wait_func_data) 442 { 443 struct bcmgenet_priv *priv = wait_func_data; 444 445 wait_event_timeout(priv->wq, 446 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 447 & MDIO_START_BUSY), 448 HZ / 100); 449 return 0; 450 } 451 452 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 453 { 454 struct platform_device *pdev = priv->pdev; 455 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 456 struct device_node *dn = pdev->dev.of_node; 457 struct unimac_mdio_pdata ppd; 458 struct platform_device *ppdev; 459 struct resource *pres, res; 460 int id, ret; 461 462 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 463 if (!pres) { 464 dev_err(&pdev->dev, "Invalid resource\n"); 465 return -EINVAL; 466 } 467 memset(&res, 0, sizeof(res)); 468 memset(&ppd, 0, sizeof(ppd)); 469 470 ppd.wait_func = bcmgenet_mii_wait; 471 ppd.wait_func_data = priv; 472 ppd.bus_name = "bcmgenet MII bus"; 473 474 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 475 * and is 2 * 32-bits word long, 8 bytes total. 476 */ 477 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 478 res.end = res.start + 8; 479 res.flags = IORESOURCE_MEM; 480 481 if (dn) 482 id = of_alias_get_id(dn, "eth"); 483 else 484 id = pdev->id; 485 486 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 487 if (!ppdev) 488 return -ENOMEM; 489 490 /* Retain this platform_device pointer for later cleanup */ 491 priv->mii_pdev = ppdev; 492 ppdev->dev.parent = &pdev->dev; 493 if (dn) 494 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 495 else if (pdata) 496 bcmgenet_mii_pdata_init(priv, &ppd); 497 else 498 ppd.phy_mask = ~0; 499 500 ret = platform_device_add_resources(ppdev, &res, 1); 501 if (ret) 502 goto out; 503 504 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 505 if (ret) 506 goto out; 507 508 ret = platform_device_add(ppdev); 509 if (ret) 510 goto out; 511 512 return 0; 513 out: 514 platform_device_put(ppdev); 515 return ret; 516 } 517 518 static int bcmgenet_phy_interface_init(struct bcmgenet_priv *priv) 519 { 520 struct device *kdev = &priv->pdev->dev; 521 int phy_mode = device_get_phy_mode(kdev); 522 523 if (phy_mode < 0) { 524 dev_err(kdev, "invalid PHY mode property\n"); 525 return phy_mode; 526 } 527 528 priv->phy_interface = phy_mode; 529 530 /* We need to specifically look up whether this PHY interface is 531 * internal or not *before* we even try to probe the PHY driver 532 * over MDIO as we may have shut down the internal PHY for power 533 * saving purposes. 534 */ 535 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 536 priv->internal_phy = true; 537 538 return 0; 539 } 540 541 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 542 { 543 struct device_node *dn = priv->pdev->dev.of_node; 544 struct phy_device *phydev; 545 int ret; 546 547 /* Fetch the PHY phandle */ 548 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 549 550 /* In the case of a fixed PHY, the DT node associated 551 * to the PHY is the Ethernet MAC DT node. 552 */ 553 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 554 ret = of_phy_register_fixed_link(dn); 555 if (ret) 556 return ret; 557 558 priv->phy_dn = of_node_get(dn); 559 } 560 561 /* Get the link mode */ 562 ret = bcmgenet_phy_interface_init(priv); 563 if (ret) 564 return ret; 565 566 /* Make sure we initialize MoCA PHYs with a link down */ 567 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 568 phydev = of_phy_find_device(dn); 569 if (phydev) { 570 phydev->link = 0; 571 put_device(&phydev->mdio.dev); 572 } 573 } 574 575 return 0; 576 } 577 578 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 579 { 580 struct device *kdev = &priv->pdev->dev; 581 struct bcmgenet_platform_data *pd = kdev->platform_data; 582 char phy_name[MII_BUS_ID_SIZE + 3]; 583 char mdio_bus_id[MII_BUS_ID_SIZE]; 584 struct phy_device *phydev; 585 586 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 587 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 588 589 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 590 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 591 mdio_bus_id, pd->phy_address); 592 593 /* 594 * Internal or external PHY with MDIO access 595 */ 596 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 597 if (IS_ERR(phydev)) { 598 dev_err(kdev, "failed to register PHY device\n"); 599 return PTR_ERR(phydev); 600 } 601 } else { 602 /* 603 * MoCA port or no MDIO access. 604 * Use fixed PHY to represent the link layer. 605 */ 606 struct fixed_phy_status fphy_status = { 607 .link = 1, 608 .speed = pd->phy_speed, 609 .duplex = pd->phy_duplex, 610 .pause = 0, 611 .asym_pause = 0, 612 }; 613 614 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 615 if (!phydev || IS_ERR(phydev)) { 616 dev_err(kdev, "failed to register fixed PHY device\n"); 617 return -ENODEV; 618 } 619 620 /* Make sure we initialize MoCA PHYs with a link down */ 621 phydev->link = 0; 622 623 } 624 625 priv->phy_interface = pd->phy_interface; 626 627 return 0; 628 } 629 630 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 631 { 632 struct device *kdev = &priv->pdev->dev; 633 struct device_node *dn = kdev->of_node; 634 635 if (dn) 636 return bcmgenet_mii_of_init(priv); 637 else if (has_acpi_companion(kdev)) 638 return bcmgenet_phy_interface_init(priv); 639 else 640 return bcmgenet_mii_pd_init(priv); 641 } 642 643 int bcmgenet_mii_init(struct net_device *dev) 644 { 645 struct bcmgenet_priv *priv = netdev_priv(dev); 646 int ret; 647 648 ret = bcmgenet_mii_register(priv); 649 if (ret) 650 return ret; 651 652 ret = bcmgenet_mii_bus_init(priv); 653 if (ret) 654 goto out; 655 656 return 0; 657 658 out: 659 bcmgenet_mii_exit(dev); 660 return ret; 661 } 662 663 void bcmgenet_mii_exit(struct net_device *dev) 664 { 665 struct bcmgenet_priv *priv = netdev_priv(dev); 666 struct device_node *dn = priv->pdev->dev.of_node; 667 668 if (of_phy_is_fixed_link(dn)) 669 of_phy_deregister_fixed_link(dn); 670 of_node_put(priv->phy_dn); 671 platform_device_unregister(priv->mii_pdev); 672 } 673