1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 28 #include "bcmgenet.h" 29 30 /* read a value from the MII */ 31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) 32 { 33 int ret; 34 struct net_device *dev = bus->priv; 35 struct bcmgenet_priv *priv = netdev_priv(dev); 36 u32 reg; 37 38 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | 39 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); 40 /* Start MDIO transaction*/ 41 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 42 reg |= MDIO_START_BUSY; 43 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 44 wait_event_timeout(priv->wq, 45 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 46 & MDIO_START_BUSY), 47 HZ / 100); 48 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 49 50 /* Some broken devices are known not to release the line during 51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for 52 * that condition here and ignore the MDIO controller read failure 53 * indication. 54 */ 55 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL)) 56 return -EIO; 57 58 return ret & 0xffff; 59 } 60 61 /* write a value to the MII */ 62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, 63 int location, u16 val) 64 { 65 struct net_device *dev = bus->priv; 66 struct bcmgenet_priv *priv = netdev_priv(dev); 67 u32 reg; 68 69 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | 70 (location << MDIO_REG_SHIFT) | (0xffff & val)), 71 UMAC_MDIO_CMD); 72 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 73 reg |= MDIO_START_BUSY; 74 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 75 wait_event_timeout(priv->wq, 76 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & 77 MDIO_START_BUSY), 78 HZ / 100); 79 80 return 0; 81 } 82 83 /* setup netdev link state when PHY link status change and 84 * update UMAC and RGMII block when link up 85 */ 86 void bcmgenet_mii_setup(struct net_device *dev) 87 { 88 struct bcmgenet_priv *priv = netdev_priv(dev); 89 struct phy_device *phydev = priv->phydev; 90 u32 reg, cmd_bits = 0; 91 bool status_changed = false; 92 93 if (priv->old_link != phydev->link) { 94 status_changed = true; 95 priv->old_link = phydev->link; 96 } 97 98 if (phydev->link) { 99 /* check speed/duplex/pause changes */ 100 if (priv->old_speed != phydev->speed) { 101 status_changed = true; 102 priv->old_speed = phydev->speed; 103 } 104 105 if (priv->old_duplex != phydev->duplex) { 106 status_changed = true; 107 priv->old_duplex = phydev->duplex; 108 } 109 110 if (priv->old_pause != phydev->pause) { 111 status_changed = true; 112 priv->old_pause = phydev->pause; 113 } 114 115 /* done if nothing has changed */ 116 if (!status_changed) 117 return; 118 119 /* speed */ 120 if (phydev->speed == SPEED_1000) 121 cmd_bits = UMAC_SPEED_1000; 122 else if (phydev->speed == SPEED_100) 123 cmd_bits = UMAC_SPEED_100; 124 else 125 cmd_bits = UMAC_SPEED_10; 126 cmd_bits <<= CMD_SPEED_SHIFT; 127 128 /* duplex */ 129 if (phydev->duplex != DUPLEX_FULL) 130 cmd_bits |= CMD_HD_EN; 131 132 /* pause capability */ 133 if (!phydev->pause) 134 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 135 136 /* 137 * Program UMAC and RGMII block based on established 138 * link speed, duplex, and pause. The speed set in 139 * umac->cmd tell RGMII block which clock to use for 140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 141 * Receive clock is provided by the PHY. 142 */ 143 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 144 reg &= ~OOB_DISABLE; 145 reg |= RGMII_LINK; 146 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 147 148 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 149 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 150 CMD_HD_EN | 151 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 152 reg |= cmd_bits; 153 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 154 } else { 155 /* done if nothing has changed */ 156 if (!status_changed) 157 return; 158 159 /* needed for MoCA fixed PHY to reflect correct link status */ 160 netif_carrier_off(dev); 161 } 162 163 phy_print_status(phydev); 164 } 165 166 167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 168 struct fixed_phy_status *status) 169 { 170 if (dev && dev->phydev && status) 171 status->link = dev->phydev->link; 172 173 return 0; 174 } 175 176 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about 177 * not doing it and will start corrupting packets 178 */ 179 void bcmgenet_mii_reset(struct net_device *dev) 180 { 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 183 if (GENET_IS_V4(priv)) 184 return; 185 186 if (priv->phydev) { 187 phy_init_hw(priv->phydev); 188 phy_start_aneg(priv->phydev); 189 } 190 } 191 192 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 193 { 194 struct bcmgenet_priv *priv = netdev_priv(dev); 195 u32 reg = 0; 196 197 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 198 if (!GENET_IS_V4(priv)) 199 return; 200 201 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 202 if (enable) { 203 reg &= ~EXT_CK25_DIS; 204 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 205 mdelay(1); 206 207 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 208 reg |= EXT_GPHY_RESET; 209 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 210 mdelay(1); 211 212 reg &= ~EXT_GPHY_RESET; 213 } else { 214 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET; 215 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 216 mdelay(1); 217 reg |= EXT_CK25_DIS; 218 } 219 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 220 udelay(60); 221 } 222 223 static void bcmgenet_internal_phy_setup(struct net_device *dev) 224 { 225 struct bcmgenet_priv *priv = netdev_priv(dev); 226 u32 reg; 227 228 /* Power up PHY */ 229 bcmgenet_phy_power_set(dev, true); 230 /* enable APD */ 231 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 232 reg |= EXT_PWR_DN_EN_LD; 233 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 234 bcmgenet_mii_reset(dev); 235 } 236 237 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 238 { 239 u32 reg; 240 241 /* Speed settings are set in bcmgenet_mii_setup() */ 242 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 243 reg |= LED_ACT_SOURCE_MAC; 244 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 245 246 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 247 fixed_phy_set_link_update(priv->phydev, 248 bcmgenet_fixed_phy_link_update); 249 } 250 251 int bcmgenet_mii_config(struct net_device *dev) 252 { 253 struct bcmgenet_priv *priv = netdev_priv(dev); 254 struct phy_device *phydev = priv->phydev; 255 struct device *kdev = &priv->pdev->dev; 256 const char *phy_name = NULL; 257 u32 id_mode_dis = 0; 258 u32 port_ctrl; 259 u32 reg; 260 261 priv->ext_phy = !priv->internal_phy && 262 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 263 264 if (priv->internal_phy) 265 priv->phy_interface = PHY_INTERFACE_MODE_NA; 266 267 switch (priv->phy_interface) { 268 case PHY_INTERFACE_MODE_NA: 269 case PHY_INTERFACE_MODE_MOCA: 270 /* Irrespective of the actually configured PHY speed (100 or 271 * 1000) GENETv4 only has an internal GPHY so we will just end 272 * up masking the Gigabit features from what we support, not 273 * switching to the EPHY 274 */ 275 if (GENET_IS_V4(priv)) 276 port_ctrl = PORT_MODE_INT_GPHY; 277 else 278 port_ctrl = PORT_MODE_INT_EPHY; 279 280 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 281 282 if (priv->internal_phy) { 283 phy_name = "internal PHY"; 284 bcmgenet_internal_phy_setup(dev); 285 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 286 phy_name = "MoCA"; 287 bcmgenet_moca_phy_setup(priv); 288 } 289 break; 290 291 case PHY_INTERFACE_MODE_MII: 292 phy_name = "external MII"; 293 phydev->supported &= PHY_BASIC_FEATURES; 294 bcmgenet_sys_writel(priv, 295 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 296 break; 297 298 case PHY_INTERFACE_MODE_REVMII: 299 phy_name = "external RvMII"; 300 /* of_mdiobus_register took care of reading the 'max-speed' 301 * PHY property for us, effectively limiting the PHY supported 302 * capabilities, use that knowledge to also configure the 303 * Reverse MII interface correctly. 304 */ 305 if ((priv->phydev->supported & PHY_BASIC_FEATURES) == 306 PHY_BASIC_FEATURES) 307 port_ctrl = PORT_MODE_EXT_RVMII_25; 308 else 309 port_ctrl = PORT_MODE_EXT_RVMII_50; 310 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 311 break; 312 313 case PHY_INTERFACE_MODE_RGMII: 314 /* RGMII_NO_ID: TXC transitions at the same time as TXD 315 * (requires PCB or receiver-side delay) 316 * RGMII: Add 2ns delay on TXC (90 degree shift) 317 * 318 * ID is implicitly disabled for 100Mbps (RG)MII operation. 319 */ 320 id_mode_dis = BIT(16); 321 /* fall through */ 322 case PHY_INTERFACE_MODE_RGMII_TXID: 323 if (id_mode_dis) 324 phy_name = "external RGMII (no delay)"; 325 else 326 phy_name = "external RGMII (TX delay)"; 327 bcmgenet_sys_writel(priv, 328 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 329 break; 330 default: 331 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 332 return -EINVAL; 333 } 334 335 /* This is an external PHY (xMII), so we need to enable the RGMII 336 * block for the interface to work 337 */ 338 if (priv->ext_phy) { 339 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 340 reg |= RGMII_MODE_EN | id_mode_dis; 341 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 342 } 343 344 dev_info_once(kdev, "configuring instance for %s\n", phy_name); 345 346 return 0; 347 } 348 349 int bcmgenet_mii_probe(struct net_device *dev) 350 { 351 struct bcmgenet_priv *priv = netdev_priv(dev); 352 struct device_node *dn = priv->pdev->dev.of_node; 353 struct phy_device *phydev; 354 u32 phy_flags; 355 int ret; 356 357 /* Communicate the integrated PHY revision */ 358 phy_flags = priv->gphy_rev; 359 360 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 361 priv->old_link = -1; 362 priv->old_speed = -1; 363 priv->old_duplex = -1; 364 priv->old_pause = -1; 365 366 if (dn) { 367 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 368 phy_flags, priv->phy_interface); 369 if (!phydev) { 370 pr_err("could not attach to PHY\n"); 371 return -ENODEV; 372 } 373 } else { 374 phydev = priv->phydev; 375 phydev->dev_flags = phy_flags; 376 377 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 378 priv->phy_interface); 379 if (ret) { 380 pr_err("could not attach to PHY\n"); 381 return -ENODEV; 382 } 383 } 384 385 priv->phydev = phydev; 386 387 /* Configure port multiplexer based on what the probed PHY device since 388 * reading the 'max-speed' property determines the maximum supported 389 * PHY speed which is needed for bcmgenet_mii_config() to configure 390 * things appropriately. 391 */ 392 ret = bcmgenet_mii_config(dev); 393 if (ret) { 394 phy_disconnect(priv->phydev); 395 return ret; 396 } 397 398 phydev->advertising = phydev->supported; 399 400 /* The internal PHY has its link interrupts routed to the 401 * Ethernet MAC ISRs 402 */ 403 if (priv->internal_phy) 404 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT; 405 else 406 priv->mii_bus->irq[phydev->addr] = PHY_POLL; 407 408 return 0; 409 } 410 411 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with 412 * their internal MDIO management controller making them fail to successfully 413 * be read from or written to for the first transaction. We insert a dummy 414 * BMSR read here to make sure that phy_get_device() and get_phy_id() can 415 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a 416 * PHY device for this peripheral. 417 * 418 * Once the PHY driver is registered, we can workaround subsequent reads from 419 * there (e.g: during system-wide power management). 420 * 421 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is 422 * therefore the right location to stick that workaround. Since we do not want 423 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual 424 * Device Tree scan to limit the search area. 425 */ 426 static int bcmgenet_mii_bus_reset(struct mii_bus *bus) 427 { 428 struct net_device *dev = bus->priv; 429 struct bcmgenet_priv *priv = netdev_priv(dev); 430 struct device_node *np = priv->mdio_dn; 431 struct device_node *child = NULL; 432 u32 read_mask = 0; 433 int addr = 0; 434 435 if (!np) { 436 read_mask = 1 << priv->phy_addr; 437 } else { 438 for_each_available_child_of_node(np, child) { 439 addr = of_mdio_parse_addr(&dev->dev, child); 440 if (addr < 0) 441 continue; 442 443 read_mask |= 1 << addr; 444 } 445 } 446 447 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 448 if (read_mask & 1 << addr) { 449 dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr); 450 mdiobus_read(bus, addr, MII_BMSR); 451 } 452 } 453 454 return 0; 455 } 456 457 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) 458 { 459 struct mii_bus *bus; 460 461 if (priv->mii_bus) 462 return 0; 463 464 priv->mii_bus = mdiobus_alloc(); 465 if (!priv->mii_bus) { 466 pr_err("failed to allocate\n"); 467 return -ENOMEM; 468 } 469 470 bus = priv->mii_bus; 471 bus->priv = priv->dev; 472 bus->name = "bcmgenet MII bus"; 473 bus->parent = &priv->pdev->dev; 474 bus->read = bcmgenet_mii_read; 475 bus->write = bcmgenet_mii_write; 476 bus->reset = bcmgenet_mii_bus_reset; 477 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", 478 priv->pdev->name, priv->pdev->id); 479 480 bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL); 481 if (!bus->irq) { 482 mdiobus_free(priv->mii_bus); 483 return -ENOMEM; 484 } 485 486 return 0; 487 } 488 489 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 490 { 491 struct device_node *dn = priv->pdev->dev.of_node; 492 struct device *kdev = &priv->pdev->dev; 493 const char *phy_mode_str = NULL; 494 struct phy_device *phydev = NULL; 495 char *compat; 496 int phy_mode; 497 int ret; 498 499 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 500 if (!compat) 501 return -ENOMEM; 502 503 priv->mdio_dn = of_find_compatible_node(dn, NULL, compat); 504 kfree(compat); 505 if (!priv->mdio_dn) { 506 dev_err(kdev, "unable to find MDIO bus node\n"); 507 return -ENODEV; 508 } 509 510 ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn); 511 if (ret) { 512 dev_err(kdev, "failed to register MDIO bus\n"); 513 return ret; 514 } 515 516 /* Fetch the PHY phandle */ 517 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 518 519 /* In the case of a fixed PHY, the DT node associated 520 * to the PHY is the Ethernet MAC DT node. 521 */ 522 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 523 ret = of_phy_register_fixed_link(dn); 524 if (ret) 525 return ret; 526 527 priv->phy_dn = of_node_get(dn); 528 } 529 530 /* Get the link mode */ 531 phy_mode = of_get_phy_mode(dn); 532 priv->phy_interface = phy_mode; 533 534 /* We need to specifically look up whether this PHY interface is internal 535 * or not *before* we even try to probe the PHY driver over MDIO as we 536 * may have shut down the internal PHY for power saving purposes. 537 */ 538 if (phy_mode < 0) { 539 ret = of_property_read_string(dn, "phy-mode", &phy_mode_str); 540 if (ret < 0) { 541 dev_err(kdev, "invalid PHY mode property\n"); 542 return ret; 543 } 544 545 priv->phy_interface = PHY_INTERFACE_MODE_NA; 546 if (!strcasecmp(phy_mode_str, "internal")) 547 priv->internal_phy = true; 548 } 549 550 /* Make sure we initialize MoCA PHYs with a link down */ 551 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 552 phydev = of_phy_find_device(dn); 553 if (phydev) 554 phydev->link = 0; 555 } 556 557 return 0; 558 } 559 560 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 561 { 562 struct device *kdev = &priv->pdev->dev; 563 struct bcmgenet_platform_data *pd = kdev->platform_data; 564 struct mii_bus *mdio = priv->mii_bus; 565 struct phy_device *phydev; 566 int ret; 567 568 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 569 /* 570 * Internal or external PHY with MDIO access 571 */ 572 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 573 mdio->phy_mask = ~(1 << pd->phy_address); 574 else 575 mdio->phy_mask = 0; 576 577 ret = mdiobus_register(mdio); 578 if (ret) { 579 dev_err(kdev, "failed to register MDIO bus\n"); 580 return ret; 581 } 582 583 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 584 phydev = mdio->phy_map[pd->phy_address]; 585 else 586 phydev = phy_find_first(mdio); 587 588 if (!phydev) { 589 dev_err(kdev, "failed to register PHY device\n"); 590 mdiobus_unregister(mdio); 591 return -ENODEV; 592 } 593 } else { 594 /* 595 * MoCA port or no MDIO access. 596 * Use fixed PHY to represent the link layer. 597 */ 598 struct fixed_phy_status fphy_status = { 599 .link = 1, 600 .speed = pd->phy_speed, 601 .duplex = pd->phy_duplex, 602 .pause = 0, 603 .asym_pause = 0, 604 }; 605 606 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 607 if (!phydev || IS_ERR(phydev)) { 608 dev_err(kdev, "failed to register fixed PHY device\n"); 609 return -ENODEV; 610 } 611 612 /* Make sure we initialize MoCA PHYs with a link down */ 613 phydev->link = 0; 614 615 } 616 617 priv->phydev = phydev; 618 priv->phy_interface = pd->phy_interface; 619 620 return 0; 621 } 622 623 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 624 { 625 struct device_node *dn = priv->pdev->dev.of_node; 626 627 if (dn) 628 return bcmgenet_mii_of_init(priv); 629 else 630 return bcmgenet_mii_pd_init(priv); 631 } 632 633 int bcmgenet_mii_init(struct net_device *dev) 634 { 635 struct bcmgenet_priv *priv = netdev_priv(dev); 636 int ret; 637 638 ret = bcmgenet_mii_alloc(priv); 639 if (ret) 640 return ret; 641 642 ret = bcmgenet_mii_bus_init(priv); 643 if (ret) 644 goto out; 645 646 return 0; 647 648 out: 649 of_node_put(priv->phy_dn); 650 mdiobus_unregister(priv->mii_bus); 651 kfree(priv->mii_bus->irq); 652 mdiobus_free(priv->mii_bus); 653 return ret; 654 } 655 656 void bcmgenet_mii_exit(struct net_device *dev) 657 { 658 struct bcmgenet_priv *priv = netdev_priv(dev); 659 660 of_node_put(priv->phy_dn); 661 mdiobus_unregister(priv->mii_bus); 662 kfree(priv->mii_bus->irq); 663 mdiobus_free(priv->mii_bus); 664 } 665