1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 28 #include "bcmgenet.h" 29 30 /* read a value from the MII */ 31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) 32 { 33 int ret; 34 struct net_device *dev = bus->priv; 35 struct bcmgenet_priv *priv = netdev_priv(dev); 36 u32 reg; 37 38 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | 39 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); 40 /* Start MDIO transaction*/ 41 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 42 reg |= MDIO_START_BUSY; 43 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 44 wait_event_timeout(priv->wq, 45 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 46 & MDIO_START_BUSY), 47 HZ / 100); 48 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 49 50 /* Some broken devices are known not to release the line during 51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for 52 * that condition here and ignore the MDIO controller read failure 53 * indication. 54 */ 55 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL)) 56 return -EIO; 57 58 return ret & 0xffff; 59 } 60 61 /* write a value to the MII */ 62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, 63 int location, u16 val) 64 { 65 struct net_device *dev = bus->priv; 66 struct bcmgenet_priv *priv = netdev_priv(dev); 67 u32 reg; 68 69 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | 70 (location << MDIO_REG_SHIFT) | (0xffff & val)), 71 UMAC_MDIO_CMD); 72 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 73 reg |= MDIO_START_BUSY; 74 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 75 wait_event_timeout(priv->wq, 76 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & 77 MDIO_START_BUSY), 78 HZ / 100); 79 80 return 0; 81 } 82 83 /* setup netdev link state when PHY link status change and 84 * update UMAC and RGMII block when link up 85 */ 86 void bcmgenet_mii_setup(struct net_device *dev) 87 { 88 struct bcmgenet_priv *priv = netdev_priv(dev); 89 struct phy_device *phydev = dev->phydev; 90 u32 reg, cmd_bits = 0; 91 bool status_changed = false; 92 93 if (priv->old_link != phydev->link) { 94 status_changed = true; 95 priv->old_link = phydev->link; 96 } 97 98 if (phydev->link) { 99 /* check speed/duplex/pause changes */ 100 if (priv->old_speed != phydev->speed) { 101 status_changed = true; 102 priv->old_speed = phydev->speed; 103 } 104 105 if (priv->old_duplex != phydev->duplex) { 106 status_changed = true; 107 priv->old_duplex = phydev->duplex; 108 } 109 110 if (priv->old_pause != phydev->pause) { 111 status_changed = true; 112 priv->old_pause = phydev->pause; 113 } 114 115 /* done if nothing has changed */ 116 if (!status_changed) 117 return; 118 119 /* speed */ 120 if (phydev->speed == SPEED_1000) 121 cmd_bits = UMAC_SPEED_1000; 122 else if (phydev->speed == SPEED_100) 123 cmd_bits = UMAC_SPEED_100; 124 else 125 cmd_bits = UMAC_SPEED_10; 126 cmd_bits <<= CMD_SPEED_SHIFT; 127 128 /* duplex */ 129 if (phydev->duplex != DUPLEX_FULL) 130 cmd_bits |= CMD_HD_EN; 131 132 /* pause capability */ 133 if (!phydev->pause) 134 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 135 136 /* 137 * Program UMAC and RGMII block based on established 138 * link speed, duplex, and pause. The speed set in 139 * umac->cmd tell RGMII block which clock to use for 140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 141 * Receive clock is provided by the PHY. 142 */ 143 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 144 reg &= ~OOB_DISABLE; 145 reg |= RGMII_LINK; 146 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 147 148 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 149 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 150 CMD_HD_EN | 151 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 152 reg |= cmd_bits; 153 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 154 } else { 155 /* done if nothing has changed */ 156 if (!status_changed) 157 return; 158 159 /* needed for MoCA fixed PHY to reflect correct link status */ 160 netif_carrier_off(dev); 161 } 162 163 phy_print_status(phydev); 164 } 165 166 167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 168 struct fixed_phy_status *status) 169 { 170 if (dev && dev->phydev && status) 171 status->link = dev->phydev->link; 172 173 return 0; 174 } 175 176 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about 177 * not doing it and will start corrupting packets 178 */ 179 void bcmgenet_mii_reset(struct net_device *dev) 180 { 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 183 if (GENET_IS_V4(priv)) 184 return; 185 186 if (dev->phydev) { 187 phy_init_hw(dev->phydev); 188 phy_start_aneg(dev->phydev); 189 } 190 } 191 192 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 193 { 194 struct bcmgenet_priv *priv = netdev_priv(dev); 195 u32 reg = 0; 196 197 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 198 if (!GENET_IS_V4(priv)) 199 return; 200 201 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 202 if (enable) { 203 reg &= ~EXT_CK25_DIS; 204 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 205 mdelay(1); 206 207 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 208 reg |= EXT_GPHY_RESET; 209 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 210 mdelay(1); 211 212 reg &= ~EXT_GPHY_RESET; 213 } else { 214 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_GPHY_RESET; 215 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 216 mdelay(1); 217 reg |= EXT_CK25_DIS; 218 } 219 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 220 udelay(60); 221 } 222 223 static void bcmgenet_internal_phy_setup(struct net_device *dev) 224 { 225 struct bcmgenet_priv *priv = netdev_priv(dev); 226 u32 reg; 227 228 /* Power up PHY */ 229 bcmgenet_phy_power_set(dev, true); 230 /* enable APD */ 231 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 232 reg |= EXT_PWR_DN_EN_LD; 233 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 234 bcmgenet_mii_reset(dev); 235 } 236 237 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 238 { 239 struct net_device *ndev = priv->dev; 240 u32 reg; 241 242 /* Speed settings are set in bcmgenet_mii_setup() */ 243 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 244 reg |= LED_ACT_SOURCE_MAC; 245 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 246 247 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 248 fixed_phy_set_link_update(ndev->phydev, 249 bcmgenet_fixed_phy_link_update); 250 } 251 252 int bcmgenet_mii_config(struct net_device *dev) 253 { 254 struct bcmgenet_priv *priv = netdev_priv(dev); 255 struct phy_device *phydev = dev->phydev; 256 struct device *kdev = &priv->pdev->dev; 257 const char *phy_name = NULL; 258 u32 id_mode_dis = 0; 259 u32 port_ctrl; 260 u32 reg; 261 262 priv->ext_phy = !priv->internal_phy && 263 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 264 265 if (priv->internal_phy) 266 priv->phy_interface = PHY_INTERFACE_MODE_NA; 267 268 switch (priv->phy_interface) { 269 case PHY_INTERFACE_MODE_NA: 270 case PHY_INTERFACE_MODE_MOCA: 271 /* Irrespective of the actually configured PHY speed (100 or 272 * 1000) GENETv4 only has an internal GPHY so we will just end 273 * up masking the Gigabit features from what we support, not 274 * switching to the EPHY 275 */ 276 if (GENET_IS_V4(priv)) 277 port_ctrl = PORT_MODE_INT_GPHY; 278 else 279 port_ctrl = PORT_MODE_INT_EPHY; 280 281 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 282 283 if (priv->internal_phy) { 284 phy_name = "internal PHY"; 285 bcmgenet_internal_phy_setup(dev); 286 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 287 phy_name = "MoCA"; 288 bcmgenet_moca_phy_setup(priv); 289 } 290 break; 291 292 case PHY_INTERFACE_MODE_MII: 293 phy_name = "external MII"; 294 phydev->supported &= PHY_BASIC_FEATURES; 295 bcmgenet_sys_writel(priv, 296 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 297 break; 298 299 case PHY_INTERFACE_MODE_REVMII: 300 phy_name = "external RvMII"; 301 /* of_mdiobus_register took care of reading the 'max-speed' 302 * PHY property for us, effectively limiting the PHY supported 303 * capabilities, use that knowledge to also configure the 304 * Reverse MII interface correctly. 305 */ 306 if ((phydev->supported & PHY_BASIC_FEATURES) == 307 PHY_BASIC_FEATURES) 308 port_ctrl = PORT_MODE_EXT_RVMII_25; 309 else 310 port_ctrl = PORT_MODE_EXT_RVMII_50; 311 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 312 break; 313 314 case PHY_INTERFACE_MODE_RGMII: 315 /* RGMII_NO_ID: TXC transitions at the same time as TXD 316 * (requires PCB or receiver-side delay) 317 * RGMII: Add 2ns delay on TXC (90 degree shift) 318 * 319 * ID is implicitly disabled for 100Mbps (RG)MII operation. 320 */ 321 id_mode_dis = BIT(16); 322 /* fall through */ 323 case PHY_INTERFACE_MODE_RGMII_TXID: 324 if (id_mode_dis) 325 phy_name = "external RGMII (no delay)"; 326 else 327 phy_name = "external RGMII (TX delay)"; 328 bcmgenet_sys_writel(priv, 329 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 330 break; 331 default: 332 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 333 return -EINVAL; 334 } 335 336 /* This is an external PHY (xMII), so we need to enable the RGMII 337 * block for the interface to work 338 */ 339 if (priv->ext_phy) { 340 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 341 reg |= RGMII_MODE_EN | id_mode_dis; 342 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 343 } 344 345 dev_info_once(kdev, "configuring instance for %s\n", phy_name); 346 347 return 0; 348 } 349 350 int bcmgenet_mii_probe(struct net_device *dev) 351 { 352 struct bcmgenet_priv *priv = netdev_priv(dev); 353 struct device_node *dn = priv->pdev->dev.of_node; 354 struct phy_device *phydev; 355 u32 phy_flags; 356 int ret; 357 358 /* Communicate the integrated PHY revision */ 359 phy_flags = priv->gphy_rev; 360 361 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 362 priv->old_link = -1; 363 priv->old_speed = -1; 364 priv->old_duplex = -1; 365 priv->old_pause = -1; 366 367 if (dn) { 368 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 369 phy_flags, priv->phy_interface); 370 if (!phydev) { 371 pr_err("could not attach to PHY\n"); 372 return -ENODEV; 373 } 374 } else { 375 phydev = dev->phydev; 376 phydev->dev_flags = phy_flags; 377 378 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 379 priv->phy_interface); 380 if (ret) { 381 pr_err("could not attach to PHY\n"); 382 return -ENODEV; 383 } 384 } 385 386 /* Configure port multiplexer based on what the probed PHY device since 387 * reading the 'max-speed' property determines the maximum supported 388 * PHY speed which is needed for bcmgenet_mii_config() to configure 389 * things appropriately. 390 */ 391 ret = bcmgenet_mii_config(dev); 392 if (ret) { 393 phy_disconnect(phydev); 394 return ret; 395 } 396 397 phydev->advertising = phydev->supported; 398 399 /* The internal PHY has its link interrupts routed to the 400 * Ethernet MAC ISRs 401 */ 402 if (priv->internal_phy) 403 phydev->irq = PHY_IGNORE_INTERRUPT; 404 405 return 0; 406 } 407 408 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with 409 * their internal MDIO management controller making them fail to successfully 410 * be read from or written to for the first transaction. We insert a dummy 411 * BMSR read here to make sure that phy_get_device() and get_phy_id() can 412 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a 413 * PHY device for this peripheral. 414 * 415 * Once the PHY driver is registered, we can workaround subsequent reads from 416 * there (e.g: during system-wide power management). 417 * 418 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is 419 * therefore the right location to stick that workaround. Since we do not want 420 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual 421 * Device Tree scan to limit the search area. 422 */ 423 static int bcmgenet_mii_bus_reset(struct mii_bus *bus) 424 { 425 struct net_device *dev = bus->priv; 426 struct bcmgenet_priv *priv = netdev_priv(dev); 427 struct device_node *np = priv->mdio_dn; 428 struct device_node *child = NULL; 429 u32 read_mask = 0; 430 int addr = 0; 431 432 if (!np) { 433 read_mask = 1 << priv->phy_addr; 434 } else { 435 for_each_available_child_of_node(np, child) { 436 addr = of_mdio_parse_addr(&dev->dev, child); 437 if (addr < 0) 438 continue; 439 440 read_mask |= 1 << addr; 441 } 442 } 443 444 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 445 if (read_mask & 1 << addr) { 446 dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr); 447 mdiobus_read(bus, addr, MII_BMSR); 448 } 449 } 450 451 return 0; 452 } 453 454 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) 455 { 456 struct mii_bus *bus; 457 458 if (priv->mii_bus) 459 return 0; 460 461 priv->mii_bus = mdiobus_alloc(); 462 if (!priv->mii_bus) { 463 pr_err("failed to allocate\n"); 464 return -ENOMEM; 465 } 466 467 bus = priv->mii_bus; 468 bus->priv = priv->dev; 469 bus->name = "bcmgenet MII bus"; 470 bus->parent = &priv->pdev->dev; 471 bus->read = bcmgenet_mii_read; 472 bus->write = bcmgenet_mii_write; 473 bus->reset = bcmgenet_mii_bus_reset; 474 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", 475 priv->pdev->name, priv->pdev->id); 476 477 return 0; 478 } 479 480 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 481 { 482 struct device_node *dn = priv->pdev->dev.of_node; 483 struct device *kdev = &priv->pdev->dev; 484 const char *phy_mode_str = NULL; 485 struct phy_device *phydev = NULL; 486 char *compat; 487 int phy_mode; 488 int ret; 489 490 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 491 if (!compat) 492 return -ENOMEM; 493 494 priv->mdio_dn = of_find_compatible_node(dn, NULL, compat); 495 kfree(compat); 496 if (!priv->mdio_dn) { 497 dev_err(kdev, "unable to find MDIO bus node\n"); 498 return -ENODEV; 499 } 500 501 ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn); 502 if (ret) { 503 dev_err(kdev, "failed to register MDIO bus\n"); 504 return ret; 505 } 506 507 /* Fetch the PHY phandle */ 508 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 509 510 /* In the case of a fixed PHY, the DT node associated 511 * to the PHY is the Ethernet MAC DT node. 512 */ 513 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 514 ret = of_phy_register_fixed_link(dn); 515 if (ret) 516 return ret; 517 518 priv->phy_dn = of_node_get(dn); 519 } 520 521 /* Get the link mode */ 522 phy_mode = of_get_phy_mode(dn); 523 priv->phy_interface = phy_mode; 524 525 /* We need to specifically look up whether this PHY interface is internal 526 * or not *before* we even try to probe the PHY driver over MDIO as we 527 * may have shut down the internal PHY for power saving purposes. 528 */ 529 if (phy_mode < 0) { 530 ret = of_property_read_string(dn, "phy-mode", &phy_mode_str); 531 if (ret < 0) { 532 dev_err(kdev, "invalid PHY mode property\n"); 533 return ret; 534 } 535 536 priv->phy_interface = PHY_INTERFACE_MODE_NA; 537 if (!strcasecmp(phy_mode_str, "internal")) 538 priv->internal_phy = true; 539 } 540 541 /* Make sure we initialize MoCA PHYs with a link down */ 542 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 543 phydev = of_phy_find_device(dn); 544 if (phydev) 545 phydev->link = 0; 546 } 547 548 return 0; 549 } 550 551 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 552 { 553 struct device *kdev = &priv->pdev->dev; 554 struct bcmgenet_platform_data *pd = kdev->platform_data; 555 struct mii_bus *mdio = priv->mii_bus; 556 struct phy_device *phydev; 557 int ret; 558 559 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 560 /* 561 * Internal or external PHY with MDIO access 562 */ 563 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 564 mdio->phy_mask = ~(1 << pd->phy_address); 565 else 566 mdio->phy_mask = 0; 567 568 ret = mdiobus_register(mdio); 569 if (ret) { 570 dev_err(kdev, "failed to register MDIO bus\n"); 571 return ret; 572 } 573 574 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 575 phydev = mdiobus_get_phy(mdio, pd->phy_address); 576 else 577 phydev = phy_find_first(mdio); 578 579 if (!phydev) { 580 dev_err(kdev, "failed to register PHY device\n"); 581 mdiobus_unregister(mdio); 582 return -ENODEV; 583 } 584 } else { 585 /* 586 * MoCA port or no MDIO access. 587 * Use fixed PHY to represent the link layer. 588 */ 589 struct fixed_phy_status fphy_status = { 590 .link = 1, 591 .speed = pd->phy_speed, 592 .duplex = pd->phy_duplex, 593 .pause = 0, 594 .asym_pause = 0, 595 }; 596 597 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 598 if (!phydev || IS_ERR(phydev)) { 599 dev_err(kdev, "failed to register fixed PHY device\n"); 600 return -ENODEV; 601 } 602 603 /* Make sure we initialize MoCA PHYs with a link down */ 604 phydev->link = 0; 605 606 } 607 608 priv->phy_interface = pd->phy_interface; 609 610 return 0; 611 } 612 613 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 614 { 615 struct device_node *dn = priv->pdev->dev.of_node; 616 617 if (dn) 618 return bcmgenet_mii_of_init(priv); 619 else 620 return bcmgenet_mii_pd_init(priv); 621 } 622 623 int bcmgenet_mii_init(struct net_device *dev) 624 { 625 struct bcmgenet_priv *priv = netdev_priv(dev); 626 int ret; 627 628 ret = bcmgenet_mii_alloc(priv); 629 if (ret) 630 return ret; 631 632 ret = bcmgenet_mii_bus_init(priv); 633 if (ret) 634 goto out; 635 636 return 0; 637 638 out: 639 of_node_put(priv->phy_dn); 640 mdiobus_unregister(priv->mii_bus); 641 mdiobus_free(priv->mii_bus); 642 return ret; 643 } 644 645 void bcmgenet_mii_exit(struct net_device *dev) 646 { 647 struct bcmgenet_priv *priv = netdev_priv(dev); 648 649 of_node_put(priv->phy_dn); 650 mdiobus_unregister(priv->mii_bus); 651 mdiobus_free(priv->mii_bus); 652 } 653